Z16C3220VSC1660TR - Zilog - Datasheet.Directory

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

RELIMINARY

RODUCT

PECIFICATION

Z16C32

IUSC™ INTEGRATED UNIVERSAL

SERIAL CONTROLLER

FEATURES

■Two Full-Capacity 20 MHz DMA Channels, Each with

32-Bit Addressing and 16-Bit Data Transfers.

■DMA Modes Include Single Buffer, Pipelined, Array-

Chained and Linked-Array Chained.

■Ring Buffer Feature Supports Circular Queue of Buffers

in Memory.

■Linked Frame Status Transfer Feature Writes Status

Information for Received Frames and Reads Control

Information for Transmit Frames to the DMA Channel’s

Array or Linked List to Significantly Simplify Processing

Frame Status and Control Information.

■Programmable Throttling of DMA Bus Occupancy in

Burst Mode with Bus Occupancy Time Limitation.

■0 to 20 Mbit/sec, Full-Duplex Channel, with Two Baud

Rate Generators and a Digital Phase-Locked Loop for

Clock Recovery.

■32-Byte Data FIFOs for Receiver and Transmitter

■Up to 12.5 MByte/sec (16-Bit) Data Bus Bandwidth

■Multiprotocol Operation Under Program Control with

Independent Mode Selection for Receiver and

Transmitter.

■Async Mode with One-to-Eight Bits/Character, 1/16 to

Two Stop Bits/Character in 1/16 Bit Increments; 16x,

32x, or 64x Oversampling; Break Detect and

Generation; Odd, Even, Mark, Space or No Parity and

Framing Error Detection. Supports 9-Bit and MIL-STD-

1553B Protocols.

■HDLC/SDLC Mode with 8-Bit Address Compare;

Extended Address Field Option; 16- or 32-Bit CRC;

Programmable Idle Line Condition; Optional Preamble

Transmission and Loop Mode. Selectable Number of

Flags Between Back-to-Back Frames.

■Byte Oriented Synchronous Mode with One-to-Eight

Bits/Character; Programmable Sync and Idle Line

Conditions; Optional Receive Sync Stripping; Optional

Preamble Transmission; 16- or 32-Bit CRC; Transmit-

to-Receive Slaving (for X.21).

■External Character Sync Mode for Receive

■Transparent Bisync Mode with EBCDIC or ASCII

Character Code; Automatic CRC Handling;

Programmable Idle Line Condition; Optional Preamble

Transmission; Automatic Recognition of DLE, SYN,

SOH, ITX, ETX, ETB, EOT, ENQ and ITB.

■Flexible Bus Interface for Direct Connection to Most

Microprocessors; User Programmable for 8 or 16 Bits

Wide. Directly Supports 680X0 Family or 8X86 Family

Bus Interfaces.

■Receive and Transmit Time Slot Assigners for ISDN,

T1 and E1 (CEPT) Applications.

■8-Bit General-Purpose Port with Transition Detection

■Low Power CMOS

■68-Pin PLCC Package

■Electronic Programmer's Manual Support Tool and

Software Drivers are Available.

GENERAL DESCRIPTION

The Z16C32 IUSC™ (Integrated Universal Serial Controller)

is a multiprotocol datacommunications device with on-

chip dual-channel DMA. The integration of a high-speed

serial communications channel with high-performance

DMA facilitates higher data throughput than can be

achieved with discrete serial/DMA chip combinations.

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PS97USC0200

ZILOG

GENERAL DESCRIPTION (Continued)

There are additional reasons for using the Z16C32 IUSC

than just reduced chip count and board space economy.

The DMA and serial channel intercommunication offers

application benefits as well. For example, events such as

the reception of the end of a HDLC frame is internally

communicated from the serial controller to the DMA so that

each frame can be written into a separate memory buffer.

The buffer chaining capabilities, ring buffer support, auto-

mated frame status/control blocks, and buffer termination

at the end of the frame combine to significantly reduce

CPU overhead (Figure 1).

The IUSC is software configurable to satisfy a wide variety

of serial communication applications. The 20 Mbit/second

data rate and multiple protocol support make it ideal for

applications in today’s dynamic environment of changing

specifications and increasing speed. The many program-

mable features allow the user to tune the device response

to meet system requirements and adapt to future require-

ments. The IUSC contains a variety of sophisticated inter-

nal functions including two baud rate generators, a digital

phase-locked loop, character counters, and 32-byte FIFOs

for both the receiver and the transmitter.

The on-chip DMA channels allow high speed data trans-

fers for both the receiver and the transmitter. The IUSC

supports automatic status and control transfer through

DMA and allows initialization of the serial controller under

DMA control. Each DMA channel can do a 16-bit transfer

in as little as three 50 ns clock cycles and can generate

addresses compatible with 32-, 24- or 16-bit memory

ranges. The DMA channels operate in any of four modes:

single buffer, pipelined, array-chained, or linked-list. The

array-chained and linked-list modes provide scatter-read

and gather-write capabilities with minimal software inter-

vention. To prevent the DMA from holding bus mastership

too long, mastership time may be limited by counting the

absolute number of clock cycles, the number of bus

transactions, or both.

The CPU bus interface is designed for use with any

conventional multiplexed or non-multiplexed bus from

manufacturers of CISC and RISC processors including

Intel, Motorola, and Zilog. The bus interface is configurable

for 16-bit data, 8-bit data with separate address or 8-bit

data without separate address to support multiplexed or

non-multiplexed busses.

The IUSC handles asynchronous formats, synchronous

bit-oriented formats such as HDLC and synchronous byte-

oriented formats (e.g., BISYNC and DDCMP). This device

supports virtually any serial data transfer application.

The IUSC can generate and check CRC in any synchro-

nous mode. Complete access to the CRC value allows

system software to resend or manipulate the CRC as

needed in various applications. The IUSC also provides

facilities for modem control signals. In applications where

these controls are not needed, the modem controls can be

used for general-purpose I/O.

Interrupts are supported by a daisy-chain hierarchy within

the serial channel and between the serial channel and the

DMA. Separate interrupt vectors for each type of interrupt

within the serial controller and the DMA facilitate fast

discrimination of the interrupt source. The IUSC supports

Pulsed, Double Pulsed, and Status Interrupt Acknowledge

cycles.

Support tools are available to aid the designer in efficiently

programming the IUSC. The Technical Manual describes

in detail all the features and gives programming sequence

hints. The Electronic Programmer's Manual, DC #8287-02,

is an MS-DOS, disk-based programming initialization tool

that can generate custom sequences. Also, Zilog offers

assorted application notes and development boards to

assist the designer in hardware and software develop-

ment. Contact your nearest Zilog representative for addi-

tional information.

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.:

B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection Circuit Device

Power VCC VDD

Ground GND VSS

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

Bus

Interface

Transmit

DMA

Transmit

FIFO

Host

Processor

Interrupt

Control

Transmitter

Time Slot

Assigner

Receive

DMA

Serial Clock

DPLL

Counters

BRG0, BRG1

Receiver

Time Slot

Assigner

Receive

FIFO

I/O

Port

16-Bit Internal Data Bus

Figure 1. Z16C32 IUSC Block Diagram

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PS97USC0200

ZILOG

GENERAL DESCRIPTION (Continued)

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

/AS

/DS

/RD

/WR

/CS

S//D

D//C

R//W

/INTACK

/WAIT//RDY

GND

Ground

Interrupt

Control

Bus

Timing

Address/

Data Bus

Z16C32

TxD

RxD

/TxC

/RxC

/CTS

/DCD

/RxREQ

/ABORT

/TxREQ

B//W

/INT

IEI

IEO

PORT 0

PORT 1

Serial

Data

Channel

Clocks

Channel

I/O

Channel

DMA

Interface

Device Reset

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

/RESET

VCC

Channel

Interrupt

Interface

I/O Port

Power

CLK System Clock

/BUSREQ

/BIN

/BOUT

/UAS

Figure 2. Z16C32 Pin Functions

ZiLOG Z16C 32 IUSC™

5P R E L I M I N A R Y PS97USC0200

Figure 3. QFP 80-Pin Assignments

/UAS

/INTACK

R/W

/WR

/RD

/DS

/AS

VCC

/RESET

/CS

D//C

S//D

/Wait//RDY

B//W

PORT 6

PORT 5

PORT 4

PORT 3

PORT 2

PORT 1

PORT 0

GND

/CTS

TxD

/TxC

/DCD

RxD

/RxC

/TxREQ

/ABORT

/INT

IEI

IEO

GND

VCC

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

GND

VCC

/RxREQ

/BIN

/BUS REQ

CLK

/BOUT

GND

VCC

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

GND

VCC

PORT 7

5101520

60 55 50 45 4164

QFP 80 - Pin

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

68 61

27 43

B//W

/WAIT//RDY

Reserved

S//D

D//C

/CS

/RESET

VCC

/AS

/DS

/RD

/WR

R//W

/INTACK

/UAS

/ABORT

/INT

IEI

IEO

GND

VCC

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

GND

VCC

/RxREQ

IUSC

/BIN

/BUSREQ

CLK

/BOUT

GND

VCC

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

GND

VCC

PORT 7

/TxREQ

/RxC

RxD

/DCD

/TxC

TxD

/CTS

GND

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PIN DESCRIPTION

Figure 4. Z16C32 68-Pin PLCC Pin Assignments

Figure 2 shows the logical pin groupings of the IUSC’s

pins, and Figure 3-4 shows the physical pin assignments.

Only one strobe pin (/DS, /RD, /WR or Pulsed INTACK)

should ever be active at one time. Any unused input pin (if

an input when the IUSC is bus master or slave) must be

pulled up to its inactive state.

/RESET

Reset

(input, active Low). A Low on this line

places the IUSC in a known, inactive state, and conditions

it so that the data, from the next write operation that asserts

the /CS pin, goes into the Bus Configuration Register

(BCR) regardless of register addressing. /RESET should

be driven Low as soon as possible during power-up, and

as needed when restarting the overall system or the

communications subsystem.

CLK

System Clock

(input). This signal is the timing refer-

ence for the DMA and bus interface logic. (The serial

controller section is clocked by the selected sources of

receive and transmit clocking.)

AD15-0

Address/Data Bus

(inputs/tri-state outputs). After

Reset, these lines carry data between the controlling

microprocessor and the IUSC, and may also carry multi-

plexed addresses of registers within the IUSC. Such op-

eration, between the host processor and the IUSC, is often

called slave mode. Once the software has set up the

device and placed it into operation, these lines also carry

multiplexed addresses and data between the IUSC and

system memory; such operation is called master mode.

AD15-0 can be used in a variety of ways based on whether

the IUSC senses activity on /AS after Reset, and on the

data written to the Bus Configuration Register (BCR).

/CS

Chip Select

(input, active Low). A Low on this line

indicates that the controlling microprocessor’s current bus

cycle refers to a register in the IUSC. The IUSC ignores /CS

when a Low on /INTACK indicates that the current bus

operation is an interrupt acknowledge cycle. On a multi-

plexed bus the IUSC latches the state of this pin at rising

edges on /AS; on a non-multiplexed bus, it latches /CS at

leading/falling edges on /DS, /RD, or /WR.

PRELIMINARY

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ZILOG

PS97USC0200

Reset

Non-

Multiplexed

Bus

Multiplexed

Bus

At Least One /ASNo /AS

Any Transaction

Up To and Including

BCR Write

BCR

Write

Transaction

8-Bit With

Separate

Address

8-Bit Without

Separate

Address 16-Bit 8-Bit With

Separate

Address

8-Bit Without

Separate

Address 16-Bit

BCR[2]=0

BCR[15]=1 BCR[2]=0

BCR[15]=0 BCR[2]=1 BCR[2]=0

BCR[15]=1 BCR[2]=0

BCR[15]=0 BCR[2]=1

Note:

The presence of one transaction with an /AS active between reset, up to

and including the BCR write, chooses a multiplexed type of bus.

Figure 5. BCR Reset Sequence and Bit Assignments

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PS97USC0200

For slave cycles, this is a full time (totem pole) output. The

board designer can combine this signal with similar sig-

nals from other slaves, by means of an external logic gate

or a tri-state or open-collector driver.

/INT

Interrupt Request

(output, active Low). The IUSC

drives this line Low when (1) its IEI pin is High, (2) one or

more of its interrupt condition(s) is (are) enabled and

pending, and (3) the Under Service flag is not set for its

highest priority enabled/pending condition, nor for any

higher-priority internal condition. Software can program

whether the bus interface drives this pin in a totem-pole or

an open-drain fashion.

/INTACK

Interrupt Acknowledge

(input, active Low). A

Low on this line indicates that the host processor is

performing an interrupt acknowledge cycle. In some sys-

tems, a Low on this line may further indicate that external

logic has selected this IUSC as the device to be acknowl-

edged, or as a potential device to be acknowledged. A

field in the Bus Configuration Register selects whether this

line carries a level-sensitive “status” signal that the IUSC

should sample at the leading edge of /AS or /DS, or a

single-pulse or double-pulse protocol. The IUSC responds

to an interrupt acknowledge cycle in a variety of ways

depending on this programming and the state of the /INT

and IEI lines, as described in the text.

IEI

Interrupt Enable In

(input, active High). This signal and

the IEO pin can be part of an interrupt-acknowledge daisy

chain with other devices that may request interrupts. If IEI

is High outside of an interrupt acknowledge cycle, one or

more IUSC interrupt condition(s) is (are) enabled and

pending, and the Under Service flag isn’t set for the highest

priority condition nor for any higher-priority one, then the

IUSC requests an interrupt by driving its /INT pin Low. If the

IEI pin is High during an interrupt acknowledge cycle, one

or more IUSC interrupt condition(s) is (are) enabled and

pending, and the Under Service flag isn’t set for the highest

priority condition nor for any higher-priority, then the IUSC

keeps IEO Low and responds to the cycle.

IEO

Interrupt Enable Out

(output, active High). This signal

and/or IEI can be part of an interrupt acknowledge daisy

chain with other devices that may request interrupts. The

IUSC drives its IEO pin Low whenever its IEI pin is Low,

and/or if the Under Service flag is set for any condition. This

IUSC drives this signal slightly differently during an inter-

rupt acknowledge cycle, in that it also forces IEO Low if it

is (has been) requesting an interrupt.

/RD

Read Strobe

(input/tri-state output, active Low). This

line indicates a read cycle on the bus, for host processors/

buses having this kind of signalling. It is an output when the

IUSC has taken control of the bus and is operating in

master mode, otherwise, it is an input that is qualified by

/CS Low or /INTACK Low. For master read cycles, the IUSC

captures data at the rising (trailing) edge of this line. For

slave read cycles the IUSC provides valid data on the AD

lines within the specified access time after this line goes

Low, and keeps the data valid until after the master

releases this line to High.

/WR

Write Strobe

(input/tri-state output, active Low). This

line indicates write cycles on the bus, for host processors/

buses having this kind of signalling. It is an output when the

IUSC has taken control of the bus and is operating in

master mode, otherwise it is an input that is qualified by

/CS Low. For slave write cycles, the IUSC captures write

data at the rising (trailing) edge of this line. For master write

cycles, the IUSC places valid data on the AD lines before

it drives this signal to Low , and keeps the data valid until

after it drives this line back to High.

B//W

Byte / Word Select

(tri-state output, High indicates

8-bit transfer). When the IUSC takes control of the bus and

operates as a master, a High on this line indicates that a

byte is to be transferred, and a Low indicates that 16 bits

are to be transferred. The IUSC ignores this signal during

slave cycles: it takes the byte/word distinction from an AD

line at the rising edge of /AS, or from a bit in the serial or

DMA Command/Address Register.

/WAIT//RDY

Wait, Ready, or Acknowledge handshaking

(input/tri-state output, active Low). This line is an input

when the IUSC has taken control of the bus and is operat-

ing in master mode. For slave cycles, the IUSC activates

this line as an output. In both directions, the line can carry

wait or acknowledge signalling depending on the state of

the S//D input during the initial BCR write. If S//D is High

when the BCR is written, this line operates as a Ready/Wait

line for Zilog and most Intel processors. In this mode, the

IUSC will not complete a master cycle while this line is Low,

and it asserts this line Low until it’s ready to complete an

interrupt acknowledge cycle; it never asserts this line when

the host accesses one of the IUSC registers.

If S//D is Low when the BCR is written, this line operates

thereafter as an Acknowledge line for Motorola and some

Intel processors. In this mode, the IUSC will not complete

a master cycle until this line is Low. It asserts this line Low

for register read and write cycles, and when it is ready to

complete an interrupt acknowledge cycle.

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ZILOG

PIN DESCRIPTION (Continued)

/BUSREQ

Bus Request

(output, active Low). The DMA

controller section drives this line Low to request control of

the host bus. /BUSREQ can be an open-drain or totem-

pole output depending on a bit in the Bus Configuration

an input and only drives it Low after sampling it high.

/BIN

Bus Acknowledge In

(input, active Low). When the

IUSC receives a falling edge on this input, it samples

whether it has been driving (or has just begun to drive)

/BUSREQ. If so, it keeps /BOUT High and takes control of

the host bus. If not, it passes the bus grant by driving

/BOUT Low. This signal can be used with /BOUT to form a

bus-grant daisy chain for arbitration of bus control. Alter-

natively, it can be connected to a direct, positive grant from

an external arbiter, and the /BOUT pin can be left uncon-

nected.

/BOUT

Bus Acknowledge Out

(output, active Low). As

noted above, this signal can be used with /BIN to form a

bus-grant daisy chain for arbitration of bus control.

/ABORT

Abort Master Cycle

(input, active Low ). A Low on

this line during a master cycle makes the currently active

DMA channel terminate its activity and enter a disabled

state. Note that /ABORT is only effective during a DMA

cycle, so that the IUSC knows which channel should be

aborted. Also note that external logic must set /WAIT//RDY

to the right state for the cycle to complete, before /ABORT

becomes effective.

RxD

Received Data

(input, positive logic). The serial input.

TxD

Transmit Data

(output, positive logic). The serial

output.

/RxC

Receive Clock

(input or output). This signal can be

used as a clock input for any of the functional blocks in the

serial controller. Or, software can program the IUSC so that

this pin is an output carrying any of several receiver or

internal clock signals, a general-purpose input or output,

or an interrupt input.

/TxC

Transmit Clock

(input or output). This signal can be

used as a clock input for any of the functional blocks in the

serial controller. Or, software can program the IUSC so that

this pin is an output carrying any of several transmitter or

internal clock signals, a general purpose input or output, or

an interrupt input.

/RxREQ

Receive DMA Request

(input or output). In device

testing or in applications not using the serial controller and

DMA controller sections together in the usual way, this pin

can carry an active Low DMA Request from the receive

FIFO. On the IUSC this request is internally routed to the

on-chip Receive DMA channel; it is more typical to use the

RxREQ pin as a general-purpose output or as an interrupt

input.

/TxREQ

Transmit DMA Request

(input or output). In device

testing or in applications not using the serial controller and

DMA controller sections together in the usual way, this pin

can carry an active Low DMA Request from the transmit

FIFO. On the IUSC this request is internally routed to the

on-chip Transmit DMA channel, and it’s more typical to use

the RxREQ pin as a general-purpose output or as an

interrupt input.

/DCD

Data Carrier Detect

(input or output, active Low).

Software can program the IUSC so that this signal enables/

disables the receiver. In addition, software can program

the device to request interrupts in response to transitions

on this line. The pin can also be used as a simple input or

output.

/CTS

Clear to Send

(input or output, active Low). Software

can program the IUSC so that this signal enables/disables

the transmitter. In addition, software can program the

device to request interrupts in response to transitions on

this line. The pin can also be used as a simple input or

output.

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PORT 3/RxTSA

General-Purpose I/O or Receive Time Slot

Assigner Gate

(input or output). Software can program the

IUSC so that this pin is a general-purpose input or output,

or so that it carries the Gate output of the Receive Time Slot

Assigner. The IUSC captures transitions on this pin in

internal latches.

PORT 2

General-Purpose I/O

(input or output). Software

can program the IUSC so that this pin is a general-purpose

input or output. The IUSC captures transitions on this pin

in internal latches.

PORT 1-0/CLK 1-0

General-Purpose I/Os or Reference

Clocks

(inputs or outputs). Software can program the IUSC

so that either of these pins is a general-purpose input or

output, or a reference clock that can be divided down to

derive clocking for the Receiver and/or Transmitter. When

one of these pins is a general-purpose I/O, the IUSC

captures transitions on it in internal latches.

VCC, VSS

Power and Ground.

The inclusion of seven pins for

each power rail ensures good signal integrity, prevents

transients on outputs, and improves noise margins on

inputs. The IUSC’s internal power distribution network

requires that all these pins be connected appropriately.

PORT7/TxCOMPLT

General-Purpose I/O or Transmit Com-

plete

(input or output). Software can program the IUSC so

that this pin is a general-purpose input or output, or so that

it carries a Transmit Complete signal from the Transmitter,

that can control an external driver. The IUSC captures

transitions on this pin in internal latches.

PORT6/FSYNC

General-Purpose I/O or Frame Sync

(in-

put or output). Software can program the IUSC so that this

pin is a general-purpose input or output, or a Frame Sync

input for the IUSC’s Time Slot Assigner circuits. The IUSC

captures transitions on this pin in internal latches.

PORT5/RxSYNC

General-Purpose I/O or Receive Sync

(input or output). Software can program the IUSC so that

this pin is a general-purpose input or output, or so that it

carries a Receive Sync output from the Receiver. The IUSC

captures transitions on this pin in internal latches.

PORT4/TxTSA

General-Purpose I/O or Transmit Time Slot

Assigner Gate

(input or output). Software can program the

IUSC so that this pin is a general-purpose input or output,

or so that it carries the Gate output of the Transmit Time Slot

Assigner, that can enable an external TxD driver in time-

slotted ISDN or Fractional T1 applications. The IUSC

captures transitions on this pin in internal latches, as

described in the text.

ARCHITECTURE

The IUSC integrates a fast and efficient dual-channel DMA

with a highly versatile serial communications controller.

The functional capabilities of the IUSC are described from

two different points of view; as a datacommunications

device, it transmits and receives data in a wide variety of

datacommunications protocols; as a microprocessor pe-

ripheral with two DMA channels that offer such features as

four DMA transfer types, a flexible bus interface, and

vectored interrupts. The architecture is described in three

sections, DMA and Bus Interface Capabilities, Communi-

cation between the DMA and Serial Channel, and Serial

Communication Capabilities. The structure of the IUSC is

shown in Figure 1.

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Z16C32 IUSC

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ZILOG

DMA AND BUS INTERFACE CAPABILITIES

The IUSC’s two versatile DMA channels combined with a

flexible bus interface gives it the ability to meet a wide

variety of application requirements. The time required to

move data into and out of the transmitter and receiver is

minimized by the IUSC’s speed (20 MHz clock, three clock

cycles per word, typical); two buffer-chaining modes with

linked-frame status transfer; early buffer termination to

keep received frames in separate memory buffers; and

vectored interrupts. Some of the these features are briefly

described below, however, the user should refer to the

IUSC Technical Manual for additional information.

DMA Modes

The IUSC contains two DMA channels, one for the trans-

mitter and one for the receiver. Each channel supports a

32-bit address and a 16-bit byte count. The channels

operate in one of four modes. In normal mode, the proces-

sor must reload the address and length at the end of each

buffer. In Pipelined mode, the processor can load the

address and length of the next buffer at any time during the

DMA transfer to the first buffer. In Array-Chained mode the

processor creates a table of address/length pairs in memory

for automatic transfer by the channel. In Linked List mode

the processor creates a linked list of address and length

pairs in memory to be automatically transferred by the

channel.

Single Buffer Mode is the most basic of the four data

transfer types. The starting address of each memory buffer

and the maximum number of characters to be transferred

to or from memory are programmed into the IUSC regis-

ters. When the DMA is enabled, it transfers all data be-

tween system memory and the transmit and receive FIFOs.

Pipelined Mode is similar to Single Buffer Mode with the

addition of an extra set of registers into which the proces-

sor can load to reload the DMA with the address and count

of the next memory buffer. Therefore, when a buffer is

complete, the IUSC is pre-programmed with the address

and count of the next buffer so the DMA need not stop

between each buffer as long as software stays one step

ahead of memory buffer usage.

In Array Mode, one of the two chaining modes, software

sets up a table of memory buffer information. The length of

the array is only limited by the amount of system memory

available for buffers. The IUSC is programmed with the

location of the array of buffer addresses and sizes. This

mode has the advantage that a burst of short frames is less

likely to overrun the systems ability to keep up. The use of

receive status block and transmit control block along with

the early buffer termination feature simplifies the segmen-

tation and reassembly of serial messages in memory

buffers. When a DMA channel fetches a buffer count of

zero, it stops and can create an End-Of-Array interrupt.

Linked List Mode is the most versatile of DMA modes. It has

the Array Mode’s ability to switch buffers rapidly without

the requirement for the buffer information to be in a continu-

ous table. Each link entry contains: The starting address to

write or read the data; the size of the buffer; optional status

or control information; and a pointer to the next link.

Memory buffers can easily be added and removed from

the list by changing the links in list entries.

DMA Features

In Linked List Mode, the IUSC has a programmable feature

to facilitate the use of buffers in a ring. When this feature is

enabled, the DMA writes a zero back to the buffer length

field of each array or list entry after it is read. Therefore, if

a linked list wraps around on itself, a DMA channel will not

reuse a buffer until software has processed the buffer, and

indicated that its eligible for reuse by writing a nonzero

value in the count field (fetching a count value of zero

deactivates the DMA channel). This feature can also be

used in array mode to track buffer use.

In both Bus Slave and Master Modes, the IUSC can read

and write data words in either byte order. It supports the

Little Endian convention used by many Intel microproces-

sors and the Big Endian convention used by many Motorola

microprocessors. When the IUSC is bus master, it can be

programmed to generate only the upper 16-bit address

when required and, consequently, save a clock cycle on

each transfer (three clocks per transfer instead of four).

When using the IUSC on a 16-bit bus and the starting

address of the message is on an odd address, the IUSC

automatically reorients itself onto even word boundaries

by first fetching a byte. This is especially valuable when

retransmitting a frame with a different size header than was

received. Two pins are available as status signals of the

type of transfer in progress.

There are a variety of command and status registers to

control and monitor the DMA channels. A DMA channel

can be aborted with either the /ABORT pin or by software

command. A pause command is also available to tempo-

rarily suspend transfers.

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Bus Interface & Utilization

The bus interface module stands between the external bus

pins and an on-chip 16-bit data bus that interconnects the

other functional modules. It includes several flexible bus

interfacing options that are controlled by the contents of

the Bus Configuration Register (BCR). The BCR is auto-

matically the destination of the first write to the IUSC by the

host processor after a reset.

The IUSC is compatible with both multiplexed and non-

multiplexed bus interfaces and can transfer either 8 or 16

bits. It supports data transfers with /RD and /WR or R//W

and /DS strobe pins and either format of byte ordering. The

IUSC generates the Wait or Ready acknowledge hand-

shaking used by Intel or Motorola microprocessors. Also,

three styles of interrupt acknowledge signals are sup-

ported for automated return of an interrupt vector to any

common microprocessor.

There are several options that control how the IUSC uses

the bus. The /BIN and /BOUT pins are available to form a

bus-grant daisy chain. The IUSC has several options on

how it arbitrates requests for bus mastership between

channels and how long it stays off the bus between

requests. The priority of the two DMA channels is program-

mable and can alternate between requests to allow both

channels equal access to the bus. Once one of the

channels has mastership of the bus, control can be passed

to the other channel if it is requesting or the IUSC can be

forced off the bus. A programmable preempt feature

selects whether the higher priority channel can take over

control of the bus if it starts requesting control while the

lower priority channel is using the bus.

The IUSC maximizes the use of its 32-byte FIFOs by

holding /BUSREQ active until the transmit FIFO is full, the

receive FIFO is empty, or both. The programmable dwell

timers can be used to limit how long the IUSC holds bus

mastership by counting either bus transfers, clock cycles

or both. Therefore, the combination of programmable FIFO

request levels, channel arbitration options, and program-

mable dwell timer features provide application software

the flexibility to optimize the IUSCs bus occupancy to meet

system throughput and bus response requirements.

Interrupts

The interrupt subsystem of the IUSC derives from Zilog’s

experience in providing the most advanced interrupt ca-

pabilities in the microprocessor field. These capabilities

are at their best when used with a Zilog microprocessor,

but it is easy to interface the IUSC to work well with other

microprocessors as well. Four pins are dedicated to create

an interrupt daisy-chain hierarchy within the Serial Chan-

nel and between the Serial Channel and the DMA.

When an IUSC responds to an interrupt acknowledge from

the CPU, it places an interrupt vector on the data bus. To

speed interrupt response time, the IUSC modifies three

bits in the vector to indicate which type of interrupt is being

requested. Separate vectors are provided for the serial

channel and DMA to easily discriminate the interrupt

source.

The DMA has four interrupt sources each for the receive

and transmit channels. Each interrupt source is indepen-

dently enabled and there is a master enable for all DMA

interrupts. The four interrupt sources are End Of Array/ End

of Link, End Of Buffer, Hardware Abort, and Software

Abort.

Each of the six types of interrupts in the serial portion IUSC

(Receive Status, Receive Data, Transmit Status, Transmit

Data, I/O Status and Device Status) has three bits associ-

ated with it: Interrupt Pending (IP), Interrupt-Under-Ser-

vice (IUS) and Interrupt Enable (IE). If the IE bit for a given

source is set, then that bit can source request interrupts.

Note that individual sources within the six types also have

their own interrupt arm bits. Finally, there is a Master

Interrupt Enable (MIE) bit which globally enables or dis-

ables all interrupts from the serial channel.

The Interrupt (/INT), Interrupt Acknowledge (/INTACK),

Interrupt Enable In (IEI) and Interrupt Enable Out (IEO)

pins are provided to create an automated mechanism to

place the vector on the bus among the highest priority

pending interrupts from multiple devices. The device with

the highest pending interrupt (/INT Low, IEI High) places a

vector on the bus in response to an interrupt acknowledge

cycle.

In the IUSC, the IP bit signals that an interrupt is pending.

If an IUS bit is set, this interrupt is being serviced and all

interrupt sources of lower priority are prevented from

requesting interrupts. An IUS bit is set during an interrupt

acknowledge cycle if there are no higher priority devices

requesting interrupts.

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DMA AND BUS INTERFACE CAPABILITIES (Continued)

There are six sources of Receive Status interrupt. Each one

is individually armed: Receiver exited hunt, received idle

line, received break/abort, received code violation/end-of-

transmission/end-of-message, parity error/abort and over-

run error. The Receive Data interrupt is generated when-

ever the receive FIFO fills with data beyond the level

programmed in the Receive Interrupt Control Register

(RICR). There are six sources of Transmit Status interrupt.

Each one is individually armed: Preamble sent, idle line

sent, abort sent, end-of-frame/end-of-message sent, CRC

sent and underrun error. The Transmit Data interrupt is

generated whenever the transmit FIFO empties below the

level programmed in the Transmit Interrupt Control Regis-

ter (TICR).

The I/O Status interrupt serves to report transitions on any

of six pins. Interrupts are generated on either or both

edges with individual edge selection and arming for each

pin. The pins that can be programmed to generate I/O

Status interrupts are /RxC, /TxC, /RxREQ, /TxREQ, /DCD

and /CTS. These interrupts are independent of the pro-

grammed function of the pins.

The Device Status interrupt has four individually enabled

sources: Receive character counter underflow, DPLL sync

acquired, BRG1 zero count and BRGO zero count. Refer

to the IUSC Technical Manual for more details.

COMMUNICATION BETWEEN THE DMA AND SERIAL CHANNELS

The IUSC’s intra-chip communication between the DMA

and serial communications controller gives it the power to

achieve higher efficiency than is possible with a separate

DMA controller. The Linked Frame Status Transfer feature

writes the status and byte count of each received frame to

memory as part of an array or linked list. This provides a

simple and easy to use mechanism for storing the results

of a received message without arbitrary restrictions on how

quickly the host software must examine the results. Simi-

larly, control information for transmit frames can be auto-

matically read by the DMA from the array or link and

transferred into registers in the serial logic.

In all modes, the DMA can accept a signal from the serial

channel for early buffer termination. When the end of a

message is received, the data is transferred to the buffer

and the status is written to memory. The status is written

after the data in single buffer and pipelined modes or to the

array/link in array and linked-list modes if Linked-Frame

Status Transfer is enabled. This early buffer termination is

treated identically to the terminal count condition in the

DMA. Therefore, the receipt of the end of a message is a

seamless transition from one memory buffer to the next.

An example of using these intercommunication features

using linked list mode is shown in Figure 5. This example

shows the format of a ring of memory buffers with the linked

frame status transfer and ring buffer features enabled. Any

protocol that sets the “RxBound” bit (RCSR4 = 1), like

HDLC or 802.3, is appropriate to this example. The linked

list is shown in Figure 5 with three links for simplicity and

may be as large as memory allows. The sixth word in each

list entry is reserved and should not be used (it keeps the

list entries on 32-bit boundaries). If the end of the buffer is

reached and it is not the end of the frame, the IUSC writes

zeros as the status and count. Also, if the transmit channel

needs to start a new memory buffer other than at the

beginning of a frame, the DMA ignores the transmit control

block.

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Figure 5. Linked List Mode with Linked Frame Status Transfer and Ring Buffer Features

Another method by which the DMA and serial channel

work together is using the Transmit Character Counter to

break a large block of data into a number of fixed length

frames. For example, it is desired to transmit a large file

which is located in several memory buffers as fixed length

smaller frames. With the IUSC, the serial channel is pro-

grammed to send the end-of-frame sequence each time

the set number of bytes is transmitted. Therefore, DMA

transfers are not interrupted, nor is system response

required to break the large file into frames.

The IUSC provides higher throughput than discrete serial

and DMA chip solutions because discrete chips do not

directly communicate with each other and, therefore, the

status of one device must be read by the CPU and

communicated to the other. This typically requires inter-

rupts and the suspension of activity until status/control

information is updated. This uses precious time and bus

bandwidth, which can limit total throughput.

Buffer 1 Address

Buffer 1 RSBR or 0

Buffer 1 Length

Buffer 1 RSHR or 0

Link Address

of Entry2

Buffer 3 Address

Buffer 3 RSBR or 0

Buffer 3 Length

Buffer 3 RSHR or 0

Link Address

of Entry1

Buffer 2 Address

Buffer 2 RSBR or 0

Buffer 2 Length

Buffer 2 RSHR or 0

Link Address

of Entry3

Ring Buffer Mode

Writes this word

to 0 after it is read.

Integrated Frame Status

Transfer writes the Receive

Status Block (or 0) here.

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DATA COMMUNICATIONS CAPABILITIES

The IUSC provides a full-duplex channel programmable

for use in any common data communication protocol. The

receiver and transmitter are completely independent and

each is supported by a 32-byte deep FIFO and a 16-bit

frame length counter. All modes allow optional even, odd,

mark or space parity. Synchronous modes allow the choice

of either of two 16-bit or a 32-bit CRC polynomials. Char-

acter length of up to 8 bits can be programmed for the

receiver and transmitter independently. Error and status

conditions are carried with the data in the receive FIFO to

greatly reduce the CPU overhead required to send or

receive a message, while key control parameters accom-

pany transmit characters through the Tx FIFO. Interrupts

can be individually armed to signal such conditions as

overrun, parity error, framing error, end-of-frame, idle line

received, sync acquired, transmit underrun, CRC sent,

closing sync/flag sent, abort sent, idle line sent and pre-

amble sent. In addition, several useful internal signals like

receive character boundary, received sync, transmit char-

acter boundary and transmission complete can be sent to

pins for use by external circuitry.

Protocols

Asynchronous Mode. The receiver and transmitter handle

data at a rate of 1/16, 1/32, or 1/64 the clock rate. The

receiver rejects start bits less than one-half a bit time and

includes recovery logic following a framing error. The

transmitter is capable of sending one, two, or anywhere in

the range of 9/16th to two stop bits per character in 1/16 bit

increments.

Nine-Bit Mode. This mode is identical to async except that

the receiver checks for the status of an additional address/

data bit between the parity bit and the stop bit. The value

of this bit is FIFO’ed along with the data. In the transmitter,

this bit is automatically inserted with the value that is

FIFO’ed from the transmit data.

Isochronous Mode. Both transmitter and receiver oper-

ate on start-stop (async) data using a 1x clock. The

transmitter sends one or two stop bits.

Asynchronous With Code Violations. This is similar to

Isochronous mode except that the start bit is replaced by

a three bit-time code violation pattern as in MIL-STD-

1553B. The transmitter sends zero, one or two stop bits.

HDLC Mode. In this mode, the receiver recognizes flags,

performs optional address matching, accommodates ex-

tended address fields, and performs zero deletion and

CRC checking. The receiver is capable of receiving shared-

zero flags, recognizes abort sequences and can receive

arbitrary length frames. The transmitter automatically sends

opening and closing flags, performs zero insertion and

can be programmed to send an abort, an extended abort,

a flag or CRC and a flag on transmit underrun. The

transmitter automatically sends a closing flag with optional

CRC at the end of a programmed message length. Shared-

zero flags are selected in the transmitter and a separate

character length is programmed for the last character in

the frame.

Frames terminated with an ABORT can be marked with a

status bit on the preceding character in addition to the

status interrupt that can be enabled. Abort is only detected

in-frame and, therefore, eliminates false detection due to

an idle line. The IUSC provides four choices (flag, all 1s, all

0s, or alternating 1s and 0s) of line preamble to condition

the line before beginning data transmission. This feature is

valuable to get the receiver DPLL in sync and as a flow

control mechanism to slow down frame transmission with-

out slowing down the clock or disabling the transmitter.

HDLC Loop Mode. This mode is available only in the

transmitter and allows the IUSC to be used in an HDLC

Loop configuration. In this mode, the receiver is pro-

grammed to operate in HDLC mode to allow the transmitter

to echo received messages. Upon receipt of a particular

bit pattern (actually a sequence of seven consecutive

ones) the transmitter stops repeating data and inserts its

own frame(s).

802.3 Mode. This mode implements the data format of

IEEE 802.3 with a 16-bit address compare. In this mode,

/DCD and /CTS are used to implement the carrier sense

and collision detect interactions with the receiver and

transmitter. Back-off timing must be provided externally.

Monosync Mode. In this mode, a single character is used

for synchronization. The sync character can be either eight

bits long or the same length as the data characters. The

receiver can automatically strip sync characters from the

received data stream. The transmitter is programmed to

automatically send CRC on either an underrun or at the end

of a programmed message length.

Slaved Monosync Mode. This mode is available only in

the transmitter and allows the transmitter (operating just as

though it were in monosync mode) to send data with its

byte boundaries synchronized to those of the received

data.

Bisync Mode. This mode is identical to monosync mode

except that character synchronization requires two suc-

cessive characters. The two characters need not be iden-

tical.

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Transparent Bisync Mode. In this mode, the synchroni-

zation pattern is DLE-SYN, programmable selected from

either ASCII or EBCDIC encoding. The receiver recog-

nizes control character sequences and automatically

handles CRC calculations without CPU intervention. The

transmitter is programmed to send either SYN, DLE-SYN,

CRC-SYN, or CRC-DLE-SYN upon underrun and automati-

cally sends the closing DLE-SYN with optional CRC at the

end of a programmed message length.

External Sync Mode. The receiver is synchronized to the

receive data by an externally-supplied signal on a pin for

custom protocol applications.

Data Encoding

The IUSC is programmed to encode and decode the serial

data in any of eight different ways (Figure 6). The transmit-

ter encoding method is selected independently of the

receiver decoding method.

NRZ. In NRZ, a 1 is represented by a High level for the

duration of the bit cell and a 0 is represented by a Low level

for the duration of the bit cell.

NRZB. NRZB is inverted from NRZ.

NRZI-Mark. In NRZI-Mark, a 1 is represented by a transi-

tion at the beginning of a bit cell, i.e., the level present in the

preceding bit cell is reversed. A 0 is represented by the

absence of a transition at the beginning of the bit cell.

NRZI-Space. In NRZI-Space, a 1 is represented by the

absence of a transition at the beginning of a bit cell, i.e., the

level present in the preceding bit cell is maintained. A 0 is

represented by a transition at the beginning of the bit cell.

Biphase-Mark. In Biphase-Mark, a 1 is represented by a

transition at the beginning of the bit cell and another

transition at the center of the bit cell. A 0 is represented by

a transition at the beginning of the bit cell only.

Biphase-Space. In Biphase-Space, a 1 is represented by

a transition at the beginning of the bit cell only. A 0 is

represented by a transition at the beginning of the bit cell

and another transition at the center of the bit cell.

Biphase-Level. In Biphase-Level, a 1 is represented by a

High during the first half of the bit cell and a Low during the

second half of the bit cell. A 0 is represented by a Low

during the first half of the bit cell and a High during the

second half of the bit cell.

Differential Biphase-Level. In Differential Biphase-Level,

a 1 is represented by a transition at the center of the bit cell,

with the opposite polarity from the transition at the center

of the preceding bit cell. A 0 is represented by a transition

at the center of the bit cell with the same polarity as the

transition at the center of the preceding bit cell. In both

cases, there are transitions at the beginning of the bit cell

to set up the level required to make the correct center

transition.

Figure 6. Data Encoding

Data 110010

NRZ

NRZB

NRZI-M

NRZI-S

BI-PHASE-M

BIPHASE-S

BIPHASE-L

DIFFERENTIAL

BIPHASE-L

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DATA COMMUNICATIONS CAPABILITIES (Continued)

Character Counters

The IUSC contains separate 16-bit character counters for

the receiver and transmitter. The receive character counter

is set to a programmable starting value or automatically at

the beginning of each received frame and can be reloaded

under software control during a frame. The counter decre-

ments with each receive character. At the end of the

receive message the current value in the counter is auto-

matically loaded into a four-deep FIFO. With the Receive

Status Block (RSB) feature enabled, the counter value and

the status (RCSR) can be automatically transferred to

memory following the data. In array and linked list modes,

the RSB can be transferred to the array or list entry for easy

software access. This allows DMA transfer of data to

proceed without CPU intervention at the end of a received

frame, as the values in the FIFO allow the CPU to determine

the status and length of each frame.

Similarly, the transmit character counter is loaded auto-

matically at the beginning of each transmit frame and can

be reloaded under software control during a frame. The

counter is decremented with each write to the transmit

FIFO. When the counter reaches zero, and that byte is sent,

the transmitter automatically terminates the message in

the appropriate fashion (usually by sending the CRC and

the closing flag or sync character) without requiring CPU

intervention. In linked list and array modes, the transmit

character count and frame control word can be fetched

from the linked list or array.

Baud Rate Generators

The IUSC contains two Baud Rate Generators. Each gen-

erator consists of a 16-bit time constant register and a 16-

bit down counter. In operation, the counter decrements

with each cycle of its selected input clock, and the time

constant can be automatically reloaded when the count

reaches zero. The output of the Baud Rate Generator

toggles when the counter reaches a count of one-half of the

time constant and again when the counter reaches zero. A

new time constant can be written at any time but the new

value does not take effect until the next load of the counter.

The outputs of both baud rate generators are sent to the

clock multiplexer for use internally or externally. The input

to the Baud Rate Generator can be the /TxC pin, the /RxC

pin, a PORT pin, or the output of either counter. The baud

rate generator output frequency is related to the baud rate

generator input clock frequency by the following formula:

Output frequency = Input frequency/time constant + 1.

Note:This allows an output frequency in the range of 1 to

1/65536 of the input frequency, inclusive.

The output of either Baud Rate Generator can be used as

the transmit or receive clock, the reference clock input to

the DPLL circuit, and/or can be output on the /RxC or /TxC

pin.

Digital Phase-Locked Loop

The IUSC contains a DPLL (Digital Phase-Locked Loop) to

recover clock information from a data stream with NRZI or

Biphase encoding. The DPLL is driven by a clock that is

nominally 8, 16 or 32 times the receive data rate. The DPLL

uses this clock, along with the data stream, to construct a

clock for the data. This clock can be routed to the receiver,

transmitter, or both, or to a pin for use externally. In all

modes, the DPLL counts the input clock to create nominal

bit times. While counting, the DPLL watches the incoming

data stream for transitions. When a transition is detected,

the DPLL may make a count adjustment (during the next

counting cycle) to produce an output clock which tracks

the incoming bit cells. The DPLL provides properly phased

transmit and receive clocks to the clock multiplexer.

Counters

The IUSC contains two 5-bit counters, which are pro-

grammed to divide an input clock by 4, 8, 16 or 32. The

outputs of these two counters are sent to the clock multi-

plexer. The counters can be used as prescalers for the

Baud Rate Generators. They also provide a stable transmit

clock from a common source when the DPLL is providing

the receive clock. The PORT0 and PORT1 pins can be

used as inputs to the counters.

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Clock Multiplexers

The clock multiplexer logic selects the receive and trans-

mit clocks and optional outputs on the /RxC and/or /TxC

pin(s). In the Z16C32, the PORT0 and PORT1 pins can be

used directly as receive and transmit clocks, as well as

being used as inputs to the counters.

Time Slot Assigner

The IUSC is equipped with two Time Slot Assigners to

support ISDN and Fractional T1 communications. There is

one assigner for the receiver. Each time slot assigner

selects one or more time slots within a frame, however, the

selected time slots must be contiguous. The first selected

time slot is programmable from slot 0 (the first slot) to slot

127 of the frame. The number of concatenated slots is

programmable from 1 to 15 (total slots). The time of the first

slot can be offset an integral number of clocks. This offset

is a delay and is programmable from 0 (no offset) to 7

clocks in increments of one clock (one bit cell). This offset

can be used to compensate for delays in frame sync

detection logic.

Test Modes

The IUSC can be programmed for local loopback or auto

echo operation. In local loopback, the output of the trans-

mitter is internally routed to the input of the receiver. This

allows testing of the IUSC data paths without any external

logic. Auto echo connects the RxD pin directly to the TxD

pin. This is useful for testing serial links external to the

IUSC.

I/O Port

The Port pins are general-purpose I/O pins. They are used

as additional modem control lines or other I/O functions.

Each port bit is individually programmable as general-

purpose input, as an output, or for a dedicated input or

output function. This programming is done in the Port

Control Register. Whether used as inputs or outputs, the

port pins can be read at any time.

The dedicated functions of the port pins include Time Slot

Assigner gate outputs, transmit complete output, clock

inputs, receive sync output, or frame sync input.

The port pins capture edge transitions. Programming for

the capture is done using the Port Latched/Unlatch com-

mand bits in the Port Status Register. Each port bit is

individually controlled. The Latched/Unlatch bit is used as

a status signal to indicate that a transition has occurred on

the port pin and as a command to open the latches that

capture this transition. Both rising edge and falling edge

are detected. When a transition is detected, the latch

closes, holding the post transition state of the input.

The Latched/Unlatch bit is held at 0 if no transitions occur

on the port pin; this bit is set to a 1 when a rising edge or

falling edge transition is detected, or immediately after the

latch is opened if one or more transitions occurred while

the latch was closed. Writing a 0 to the Latched/Unlatch bit

has no effect on the latch. Writing a 1 to this bit resets the

status bit and opens the latch. To use the port as an input

without edge detection, a 1 would be written to the Latched/

Unlatch bit to open the latch and then the Port Status

status.

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PROGRAMMING

An Electronic Programmer’s Manual (MS DOS based) and

a Technical Manual are available to provide details about

programming the IUSC. Also included are explanations

and features of all registers in the IUSC.

The registers in the IUSC are programmed by the system

to configure the channel. Before this can occur, the system

must set up the bus interface by writing to the Bus Configu-

ration Register (BCR). The BCR has no specific address

and is only accessible after a hardware reset of the device.

The first write to the IUSC, after a hardware reset, programs

the BCR. From that time on other channel registers can be

accessed. No specific address need be presented to the

IUSC for the BCR write; the IUSC knows that the first write

after a hardware reset is destined for the BCR.

In the multiplexed bus case, all registers are directly

addressable through the address latched by /AS at the

beginning of each bus cycle. The D//C pin is still used to

directly access the receive and send data registers (RDR

and TDR) with a multiplexed bus; if D//C is High, the

address latched by /AS is ignored and an access of RDR

or TDR is performed.

In the non-multiplexed bus case, the channel registers are

accessed indirectly using the address pointer in the Chan-

nel Command/Address Register (CCAR). The address of

the desired register is first written to the CCAR and then the

selected register is accessed; the pointer in the CCAR is

automatically cleared after this access.

Two more points about the IUSC should be noted here.

Channel Reset bit in the CCAR places the channel in the

reset state. To exit this reset state either a word of all zeros

is written to the CCAR (16-bit bus) or a byte of all zeros is

written to the lower byte of the CCAR (8-bit bus). Secondly,

after reset, the transmit and receive clocks are disabled.

The first thing that should be done in any initialization

sequence is a write to the Clock Mode Control Register

(CMCR) to select a clock source for the receiver and

transmitter.

The Serial/DMA (S//D) pin is used to differentiate between

the serial channel and the DMA registers. The DMA regis-

ters fall into three logic groupings; common registers that

apply to both transmit and receive, transmit registers, and

receive registers. The registers for DMA transmit functions

and receive functions are symmetric and therefore, a

single diagram is shown for each in the following pages.

When addressing the DMA registers, the Data/Control (D/

/C) pin selects between the transmit and receive registers.

For example, there is a DMA byte count register for

transmit and receive (TBCR and RBCR) at address 10101

with S//D pin Low. The TBCR is selected with the D//C pin

Low, and the RBCR is selected with the D//C pin High. The

format of these two registers is shown in Figure 21.

The register addressing is shown in Table 2 and the table

assumes that the BCR register bit 0 is set to 1. The A5-A1

column in the Table reflects the state of AD5-AD1, AD13-

AD9, CCAR5-CCAR1 or DCAR5-DCAR1 as applicable.

The bit assignments of the registers are shown in Figures

8 through 81. See the IUSC Technical Manual for details.

The register addressing is shown in Table 2 and the bit

assignments for the registers are shown in Figure 7.

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Reset

Non-

Multiplexed

Bus

Multiplexed

Bus

At Least One /ASNo /AS

Any Transaction

Up To and Including

BCR Write

BCR

Write

Transaction

8-Bit With

Separate

Address

8-Bit Without

Separate

Address 16-Bit 8-Bit With

Separate

Address

8-Bit Without

Separate

Address 16-Bit

BCR[2]=0

BCR[15]=1 BCR[2]=0

BCR[15]=0 BCR[2]=1 BCR[2]=0

BCR[15]=1 BCR[2]=0

BCR[15]=0 BCR[2]=1

Note:

The presence of one transaction with an /AS active between reset, up to

and including the BCR write, chooses a multiplexed type of bus.

Figure 7. BCR Reset Sequence and Bit Assignments

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

PROGRAMMING (Continued)

Table 1. Register Address List

Address

S//D D//C A5-A1 Name Description

1 0 00000 CCAR Channel Command/Address Register

1 0 00001 CMR Channel Mode Register

1 0 00010 CCSR Channel Command/Status Register

1 0 00011 CCR Channel Control Register

1 0 00100 PSR Port Status Register

1 0 00101 PCR Port Control Register

1 0 00110 TMDR Test Mode Data Register

1 0 00111 TMCR Test Mode Control Register

1 0 01000 CMCR Clock Mode Control Register

1 0 01001 HCR Hardware Configuration Register

1 0 01010 IVR Interrupt Vector Register

1 0 01011 IOCR I/O Control Register

1 0 01100 ICR Interrupt Control Register

1 0 01101 DCCR Daisy-Chain Control Register

1 0 01110 MISR Misc. Interrupt Status Register

1 0 01111 SICR Status Interrupt Control Register

1 1 XXXXX RDR Receive Data Register (Read Only)

1 0 1X000 RDR Receive Data Register (Read Only)

1 0 10001 RMR Receive Mode Register

1 0 10010 RCSR Receive Command/Status Register

1 0 10011 RICR Receive Interrupt Control Register

1 0 10100 RSR Receive Sync Register

1 0 10101 RCLR Receive Count Limit Register

1 0 10110 RCCR Receive Character Count Register

1 0 10111 TC0R Time Constant 0 Register

1 1 XXXXX TDR Transmit Data Register (Write Only)

1 0 1X000 TDR Transmit Data Register (Write Only)

1 0 11001 TMR Transmit Mode Register

1 0 11010 TCSR Transmit Command/Status Register

1 0 11011 TICR Transmit Interrupt Control Register

1 0 11100 TSR Transmit Sync Register

1 0 11101 TCLR Transmit Count Limit Register

1 0 11110 TCCR Transmit Character Count Register

1 0 11111 TC1R Time Constant 1 Register

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

Table 1. Register Address List (Continued)

Address

S//D D//C A5-A1 Name Description

X 0 XXXXX BCR Bus Configuration Register

0 X 00000 DCAR DMA Command/Address Register

0 0 00001 TDCMR Transmit DMA Channel Mode Register

0 X 00011 DCR DMA Control Register

0 X 00100 DACR DMA Array Count Register

0 X 01001 BDCR Burst Dwell Control Register

0 X 01010 DIVR DMA Interrupt Vector Register

0 X 01100 DICR DMA Interrupt Control Register

0 X 01101 CDIR Clear DMA Interrupt Register

0 X 01110 SDIR Set DMA Interrupt Register

0 0 01111 TDIAR Transmit DMA Interrupt Arm

0 0 10101 TBCR Transmit Byte Count Register

0 0 10110 TARL Transmit Address Register (Lower)

0 0 10111 TARU Transmit Address Register (Upper)

0 0 11101 NTBCR Next Transmit Byte Count Register

0 0 11110 NTARL Next Transmit Address Register (Lower)

0 0 11111 NTARU Next Transmit Address Register (Upper)

0 1 00001 RDMR Receive DMA Mode Register

0 1 01111 RDIAR Receive DMA Interrupt Arm

0 1 10101 RBCR Receive DMA Byte Count Register

0 1 10110 RARL Receive Address Register (Lower)

0 1 10111 RARU Receive Address Register (Upper)

0 1 11101 NRBCR Next Receive Byte Count Register

0 1 11110 NRARL Next Receive Address Register (Lower)

0 1 11111 NRARU Next Receive Address Register (Upper)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

This section describes the function of the various bits in the

registers of the device. Throughout this section the follow-

ing conventions are discussed:

Control bits are written and read by the CPU and are not

modified by the device. Command bits are written by the

CPU to initiate an action in the device and are read as

zeros. Status bits are controlled by the device and are read

to check device status. Any writes to status bits are ignored

by the device. Command/Status bits are controlled by both

the device and the CPU. They may be written and read by

the CPU and may also be modified by the device.

Reserved bits are not used in this implementation of the

device and may or may not be physically present in the

device. Any reserved bits that are physically present are

readable and writable, but reserved bits that are not

present are always read as zeros. To ensure compatibility

with future versions of the device, reserved bits should

always be written with zeros. Reserved commands should

not be used for the same reason.

First, the DMA registers unique to the IUSC are described

in the following pages (Figures 8-17) and then the serial

channel registers are described (Figures 18-81).

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00000 (Shared)

Upper//Lower Byte Select (WO)

0 0 0 Tx Channel

0 0 1 Rx Channel

0 1 0 Reserved

0 1 1 Reserved

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

Address 0 (WO)

Address 1 (WO)

Address 2 (WO)

Address 3 (WO)

Channel Select (WO)

D15 D14 D13 D12 D11 D10 D9 D8

Address 4 (WO)

Byte//Word Access (WO)

Pointer Channel Select (WO)

Master Bus Request Enable

0 0 0 0 Null Command

0 0 0 1 Reset This Channel

0 0 1 0 Start This Channel

0 0 1 1 Start/Continue This Channel

0 1 0 0 Pause This Channel

0 1 0 1 Abort This Channel

0 1 1 0 Reserved

0 1 1 1 Start/Init This Channel

1 0 0 0 Reset Highest IUS

1 0 0 1 Reset All Channels

1 0 1 0 Start All Channels

1 0 1 1 Start/Continue All Channels

1 1 0 0 Pause All Channels

1 1 0 1 Abort All Channels

1 1 1 0 Reserved

1 1 1 1 Start/Init All Channels

Channel Command

Notes:

(Shared) means, shared between DMA Channels

(WO) means Write Only

Figure 8. DMA Command/Address Register

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Software Abort (RO)

Hardware Abort (RO)

Buffer Termination (RO)

Array Termination (RO)

Busy (RO)

Initializing (RO)

Get Link (RO)

Continue (RO)

0 0 0 0 0 0 0 0 Reset

X X X 1 X X X X Start

1 X X 1 X X X X Start/Continue (Buffered Mode)

X X X 1 X X X X Start/Continue (Other Than Buffered Mode)

X X X 0 X X X X Pause

X X X 0 X X X 1 Abort

X X 1 1 X X X X Start/Init (Array or Linked Array Modes)

X X X 1 X X X X Start/Init (Normal or Buffered Modes)

Command

Notes:

X = Previous Value

(RO) = Read Only

Figure 9. Affect of Commands on Status Bits

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D15

Software Abort (RO)

Hardware Abort (RO)

End of Buffer (RO)

End of Array/Link (RO)

Busy (RO)

Initialization (RO)

Get Link (RO)

Continue (RO)

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 00001

0 0 Increment

0 1 Decrement

1 0 Fixed Address

1 1 Reserved

0 0 Auto Modes Disabled

0 1 Buffered

1 0 Array Chained

1 1 Linked-Array Chained

Address Mode

DMA Mode

8-Bit Operand

Enable Early Termination

Ring Buffer Enable

Linked Frame Status Transfer

Figure 10. Tx/Rx DMA Mode Register (TDMR) (RDMR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4

Busy

Initialization

Get Link

0 0 0 0 Channel Disabled

0 0 1 0 Channel Enabled

X X X 1 Not Possible

X 1 X X Not Possible

1 X X X Not Possible

Normal Mode

0 0 0 0 Channel Disabled, Base Registers Invalid

0 0 1 0 Channel Enabled, Base Registers Invalid

1 0 0 0 Channel Disabled, Base Registers Valid

1 0 1 0 Channel Enabled, Base Registers Valid

X X X 1 Not Possible

X 1 X X Not Possible

Buffered Mode

0 0 0 0 Channel Disabled, Data Transfer Phase

0 0 1 0 Channel Enabled, Data Transfer Phase

0 0 0 1 Channel Disabled, Array Transfer Phase

0 0 1 1 Channel Enabled, Array Transfer Phase

X 1 X X Not Possible

1 X X X Not Possible

Array-Chained Mode

0 0 0 0 Channel Disabled, Data Transfer Phase

0 0 1 0 Channel Enabled, Data Transfer Phase

0 0 0 1 Channel Disabled, Array Transfer Phase

0 0 1 1 Channel Enabled, Array Transfer Phase

0 1 X 0 Not Possible

0 1 0 1 Channel Disabled, Link Transfer Phase

0 1 1 1 Channel Enabled, Link Transfer Phase

1 X X X Not Possible

Linked Array-Chained Mode

Continue

Figure 11. Status Bit Combinations

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D15 D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 00011 (Shared)

0 0 32-bit Linear

0 1 Reserved

1 0 Segmented 16/16

1 1 Segmented 8/24

Addressing

Mode

/UAS Every Transaction

One Wait Every Transaction

Enable Transaction Status

Bus Inactive Time

Reserved

0 0 End of Demand or Burst

0 1 End of Demand Only

1 0 End of Burst Only

1 1 Reserved

DMA Request

Arbitration

Link Array Big End/Little End

Preempt Enable

0 0 Tx Channel

0 1 Rx Channel

1 0 Alternating

1 1 Reserved

Channel

Priority

Figure 12. DMA Control Register (DCR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

31 30 29 28 27 26 25 24

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

23 22 21 20 19 18 17

31 30 29 28 27 26 25 24

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

23 22 21 20 19 18 17

AD15 AD0

Big End Array

(16-Bit bus)

Address n

Address n+2

Little End Array

(16-Bit bus)

Address n

Address n+2

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

15 14 13 12 11 10 09 08

07 06 05 04 03 02 01 00

AD7 AD0

Big End Array

(8-Bit bus)

Address n

Address n+1

Address n+2

Address n+3

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

15 14 13 12 11 10 09 08

07 06 05 04 03 02 01 00

AD7 AD0

Little End Array

(8-Bit bus)

Address n

Address n+1

Address n+2

Address n+3

Figure 13. Array-Chained Bit Ordering

Note:

Bit 12 in DCR is used to control the byte ordering of addresses and counts stored in memory in the

Array and Linked Array Modes. The above figure shows the two cases for both bus bandwidths.

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D15

Tx Channel Array Count (RO)

Reserved

Rx Channel Array Count (RO)

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 00100 (Shared)

Figure 14a. DMA Array Count Register (DACR)

Channel Array Count 2

Channel Array Count 1

Channel Array Count 0

0 0 0 0 Array Operation Not Started

0 0 0 1 Fetched Last Byte of Array

0 0 1 0 Fetched Fifth Byte of Array

0 0 1 1 Fetched Fourth Byte of Array

0 1 0 0 Fetched Third Byte of Array

0 1 0 1 Fetched Second Byte of Array

0 1 1 0 Fetched First Byte of Array

0 1 1 1 Fetched Last Byte of Buffer

0 0 0 0 0 Array Operation Not Started

0 0 0 0 1 Fetched Last Byte of Array

0 0 0 1 0 Fetched Fifth Byte of Array

0 0 0 1 1 Fetched Fourth Byte of Array

0 0 1 0 0 Fetched Third Byte of Array

0 0 1 0 1 Fetched Second Byte of Array

0 0 1 1 0 Fetched First Byte of Array

0 0 1 1 1 Fetched Last Byte of Linked Address

1 0 0 0 0 Invalid

1 0 0 0 1 Invalid

1 0 0 1 0 Invalid

1 0 0 1 1 Invalid

1 0 1 0 0 Fetched Third Byte of Linked Address

1 0 1 0 1 Fetched Second Byte of Linked Address

1 0 1 1 0 Fetched First Byte of Linked Address

1 0 1 1 1 Fetched Last Byte of Buffer

Getlink (in DCMR)

Array-Chained

Linked Array-Chained

Channel Array Count 3

Figure 14b. Channel Array Count Bit Combinations

Note: See the Z16C32 Technical Manual for the appropri-

ate table with Linked Status Transfer feature enabled.

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D15

Clock Cycle Limit (Bit 3)

Clock Cycle Limit (Bit 4)

Clock Cycle Limit (Bit 5)

Clock Cycle Limit (Bit 6)

Clock Cycle Limit (Bit 7)

Clock Cycle Limit (Bit 8)

Clock Cycle Limit (Bit 9)

Clock Cycle Limit (Bit 10)

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 01001 (Shared)

Transaction Limit (Bit 0)

Transaction Limit (Bit 1)

Transaction Limit (Bit 2)

Transaction Limit (Bit 3)

Transaction Limit (Bit 4)

Transaction Limit (Bit 5)

Transaction Limit (Bit 6)

Transaction Limit (Bit 7)

Figure 15. Burst Dwell Control Register (BDCR)

Notes:

BDCR Controls the amount of time that DMA may remain bus master.

Bits 15 through 8 are used to select a limit for the number of DMA transfers on the Bus

while the DMA is bus master. This limit is a binary number, a value of zero disables

the transaction limit function.

Bits 7 through 0 are used to select a limit for the number of clock cycles that the DMA

may remain on the bus as bus master.

Bus transaction will always complete, even if the clock cycle limit is exceeded during

the bus cycle, and even if the cycle is extended by external hardware signalling

through /WAIT//RDY.

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D15

IV <0>

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 01010 (Shared)

0 0 None

0 1 Not Used

1 0 Tx Channel

1 1 Rx Channel

Type Code (RO)

IV <1>

IV <2>

IV <3>

IV <4>

IV <5>

IV <6>

IV <7>

IV <0> (RO)

IV <3> (RO)

IV <4> (RO)

IV <5> (RO)

IV <6> (RO)

IV <7> (RO)

Figure 16. DMA Interrupt Vector Register (DIVR)

Figure 17. DMA Interrupt Control Register (DICR)

D15

Tx IE

Rx IE

Reserved

VIS

DLC

MIE

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 01100 (Shared)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D15

Reset Tx IP (WO)

Reset Rx IP (WO)

Reserved

Reset Tx IUS (WO)

Reset Rx IUS (WO)

Reserved

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 01101 (Shared)

D15

Set Tx IP

Set Rx IP

Reserved

Set Tx IUS

Set Rx IUS

Reserved

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 01110 (Shared)

D15

Software Abort IA

Hardware Abort IA

Buf fer Termination IA

Array Termination IA

Reserved

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 01111

Figure 18. Clear DMA Interrupt Register (CDIR)

Figure 19. Set DMA Interrupt Register (SDIR)

Figure 20. Tx/Rx DMA Interrupt Arm (TDIAR)/(RDIAR)

Notes:

* The format of this register is the same for the receiver and transmitter. The transmit register

is accessed by addressing it with the D//C pin Low (0). The receive register is accessed by

addressing it with the D//C pin High (1). This applies to Figures 20 through 26.

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

Figure 22. Tx/Rx Address Register (lower) (TARL)/(RARL)

D15

TTC <0>

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 10101

TTC <1>

TTC <2>

TTC <3>

TTC <4>

TTC <5>

TTC <6>

TTC <7>

TTC <8>

TTC <9>

TTC <10>

TTC <11>

TTC <12>

TTC <13>

TTC <14>

TTC <15>

D15

TAR <0>

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 10110

TAR <1>

TAR <2>

TAR <3>

TAR <4>

TAR <5>

TAR <6>

TAR <7>

TAR <8>

TAR <9>

TAR <10>

TAR <11>

TAR <12>

TAR <13>

TAR <14>

TAR <15>

Figure 21. Tx/Rx Byte Count Register (TBCR)/(RBCR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

Figure 24. Next Tx/Rx Byte Counter Register (NTBCR)/(RTBCR)

D15

TAR <16>

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 10111

TAR <17>

TAR <18>

TAR <19>

TAR <20>

TAR <21>

TAR <22>

TAR <23>

TAR <24>

TAR <25>

TAR <26>

TAR <27>

TAR <28>

TAR <29>

TAR <30>

TAR <31>

D15

BTC <0>

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 11101

BTC <1>

BTC <2>

BTC <3>

BTC <4>

BTC <5>

BTC <6>

BTC <7>

BTC <8>

BTC <9>

BTC <10>

BTC <11>

BTC <12>

BTC <13>

BTC <14>

BTC <15>

Figure 23. Tx/Rx Address Register (Upper) (TARU)/(RARU)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D15

BAR <0>

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 11110

BAR <1>

BAR <2>

BAR <3>

BAR <4>

BAR <5>

BAR <6>

BAR <7>

BAR <8>

BAR <9>

BAR <10>

BAR <11>

BAR <12>

BAR <13>

BAR <14>

BAR <15>

D15

BAR <16>

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: 11111

BAR <17>

BAR <18>

BAR <19>

BAR <20>

BAR <21>

BAR <22>

BAR <23>

BAR <24>

BAR <25>

BAR <26>

BAR <27>

BAR <28>

BAR <29>

BAR <30>

BAR <31>

Figure 25. Next Tx/Rx Address Register (Lower) (NTARL)/(RTARL)

Figure 26. Next Tx/Rx Address Register (Upper) (NTARU)/(RTARU)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

AD<31-24>

AD<15-8>

CNT<15-8>

AD<31-24>

AD<15-8>

CNT<15-8>

AD<31-24>

AD<15-8>

CNT<15-8>

AD<23-16>

AD<7-0>

CNT<7-0>

AD<23-16>

AD<7-0>

CNT<7-0>

AD<23-16>

AD<7-0>

CNT<7-0>

Ignored

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Buffer #1

Buffer #2

Buffer #3

Dummy

Base Address

Base Address + 2

Base Address + 4

Base Address + 6

Base Address + 8

Base Address + 10

Base Address + 12

Base Address + 14

Base Address + 16

Last Base Address

Last Base Address + 2

Last Base Address + 4

Base Address Register

After Termination

AD15 AD0

Figure 27a. Array-Chained, 16-Bit Bus, Big End Array

Note:

The addition of frame status/control information in the array with Linked Frame

Status Transfer Enabled is similar for Big and Little End Array. See Figure 27b.

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

AD<31-24>

AD<15-8>

CNT <15-8>

RSB/TCB <15-8>

RCHR/TCLR <15-8>

AD<23-16>

AD<7-0>

CNT <7-0>

RSB/TCB <7-0>

RCHR/TCLR <7-0>

Buffer #1

Buffer #2

Buffer #3

AD<31-24>

AD<15-8>

CNT <15-8 >

RSB/TCB <15-8>

RCHR/TCLR <15-8>

AD<23-16>

AD<7-0>

CNT <7-0>

RSB/TCB <7-0>

RCHR/TCLR <7-0>

AD<31-24>

AD<15-8>

CNT <15-8>

RSB/TCB <15-8>

RCHR/TCLR <15-8>

AD<23-16>

AD<7-0>

CNT <7-0>

RSB/TCB <7-0>

RCHR/TCLR <7-0>

AD15 AD0

Base Address

Base Address + 2

Base Address + 4

Base Address + 6

Base Address + 8

Base Address + 10

Base Address + 12

Base Address + 14

Base Address + 16

Base Address + 18

Base Address + 20

Base Address + 22

Base Address + 24

Base Address + 26

Base Address + 28

Base Address + 30

Base Address + 32

Ignored

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Dummy

Last Base Address

Last Base Address + 2

Last Base Address + 4

Base Address Register

After Termination

Base Address + 34

Figure 27b. Array-Chained, 16-Bit Bus, Big End Array

Linked Frame Status Transfer Enabled

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

AD<15-8>

AD<31-24>

CNT<15-8>

AD<15-8>

AD<31-24>

CNT<15-8>

AD<15-8>

AD<31-24>

CNT<15-8>

AD<7-0>

AD<23-16>

CNT<7-0>

AD<7-0>

AD<23-16>

CNT<7-0>

AD<7-0>

AD<23-16>

CNT<7-0>

Ignored

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Buffer #1

Buffer #2

Buffer #3

Dummy

Base Address

Base Address + 2

Base Address + 4

Base Address + 6

Base Address + 8

Base Address + 10

Base Address + 12

Base Address + 14

Base Address + 16

Last Base Address

Last Base Address + 2

Last Base Address + 4

Base Address Register

After Termination

AD15 AD0

Figure 28. Array-Chained, 16-Bit Bus, Little End Array

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

AD<31-24>

AD<23-16>

AD<15-8>

AD<7-0>

CNT<15-8>

CNT<7-0>

AD<31-24>

AD<23-16>

AD<15-8>

Ignored

0 0 0 0 0 0 0 0

Buffer #1

Buffer #2

Dummy

Base Address

Base Address + 1

Base Address + 2

Base Address + 3

Base Address + 4

Base Address + 5

Base Address + 6

Base Address + 7

Base Address + 8

Last Base Address

Last Base Address + 1

Last Base Address + 2

Base Address Register

After Termination

AD7 AD0

AD<7-0>

CNT<15-8>

CNT<7-0>

0 0 0 0 0 0 0 0

Ignored

Base Address + 9

Base Address + 10

Base Address + 11

Last Base Address + 3

Last Base Address + 4

Last Base Address + 5

Figure 29a. Array-Chained, 8-Bit Bus, Big End Array

Note:

The addition of frame status/control information in the array with Linked Frame

Status Transfer Enabled is similar for Big and Little End Array. See Figure 29b.

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

AD<31-24>

AD<23-16>

AD<15-8>

AD<7-0>

CNT<15-8>

CNT<7-0>

RSB/TCB <15-8>

Buffer #1

Buffer #2

Base Address

Base Address + 1

Base Address + 2

Base Address + 3

Base Address + 4

Base Address + 5

Base Address + 6

Base Address + 7

Base Address + 8

AD7 AD0

Base Address + 9

Base Address + 10

Base Address + 12

Ignored

0 0 0 0 0 0 0 0

Dummy

Last Base Address

Last Base Address + 1

Last Base Address + 2

Base Address Register

After Termination

0 0 0 0 0 0 0 0

Ignored

IgnoredLast Base Address + 3

Last Base Address + 4

Last Base Address + 5

RSB/TCB <7-0>

RCHR/TCLR <15-8>

RSHR/TCLR <7-0>

AD<31-24>

AD<23-16>

AD<15-8>

AD<7-0>

CNT<15-8>

CNT<7-0>

RSB/TCB <15-8>

RSB/TCB <7-0>

RCHR/TCLR <15-8>

RSHR/TCLR <7-0>

Base Address + 13

Base Address + 14

Base Address + 15

Base Address + 16

Base Address + 17

Base Address + 18

Base Address + 19

Base Address + 20

Base Address + 21

Base Address + 22

Base Address + 11

Base Address + 23

Figure 29b. Array-Chained, 8-Bit Bus, Big End Array,

Linked Frame Status Transfer Enabled

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

AD<7-0>

AD<15-8>

AD<23-16>

AD<31-24>

CNT<7-0>

CNT<15-8>

AD<7-0>

AD<15-8>

AD<23-16>

Ignored

0 0 0 0 0 0 0 0

Buffer #1

Buffer #2

Dummy

Base Address

Base Address + 1

Base Address + 2

Base Address + 3

Base Address + 4

Base Address + 5

Base Address + 6

Base Address + 7

Base Address + 8

Last Base Address

Last Base Address + 1

Last Base Address + 2

Base Address Register

After Termination

AD7 AD0

AD<31-24>

CNT<7-0>

CNT<15-8>

0 0 0 0 0 0 0 0

Ignored

Base Address + 9

Base Address + 10

Base Address + 11

Last Base Address + 3

Last Base Address + 4

Last Base Address + 5

Figure 30. Array-Chained, 8-Bit Bus, Little End Array

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

AD<31-24>

AD<15-8>

CNT<15-8>

AD<23-16>

AD<7-0>

CNT<7-0>

Ignored

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Buffer #1

Buffer #n

Base Address

Base Address + 2

Base Address + 4

Base Address + 6

Base Address + 8

#2 Base Address

#2 Base Address + 2

#2 Base Address + 4

#n Base Address

#n Base Address + 2

#n Base Address + 4

AD15 AD0

AD<31-24>

AD<15-8>

AD<31-24>

AD<23-16>

AD<7-0>

AD<23-16>

AD<15-8> AD<7-0>

CNT<15-8> CNT<7-0>

AD<31-24>

AD<15-8>

AD<31-24>

AD<23-16>

AD<7-0>

AD<23-16>

AD<15-8> AD<7-0>

CNT<15-8> CNT<7-0>

AD<31-24>

AD<15-8>

AD<23-16>

AD<7-0>

#n - 1 Base Address + 8

#n - 1 Base Address + 6

Base #2

Buffer #2

Base #3

Buffer #3

#2 Base Address + 6

#2 Base Address + 8

#3 Base Address

#3 Base Address + 2

#3 Base Address + 4

Base #n

Figure 31a. Linked Array-Chained, 16-Bit Bus, Big End Array

Note:

The addition of frame status/control information in the array with Linked Frame

Status Transfer Enabled is similar for Big and Little End Array. See Figure 31b.

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

Buffer #1

AD15 AD0

Base #2

Buffer #2

Base #3

Buffer #3

AD<31-24>

AD <15-8>

CNT<15-8>

AD<23-16>

AD<7-0>

CNT<7-0>

RSB/TCB <15-8> RSB/TCB <7-0>

RCHR/TCLR <15-8> RCHR/TCLR <7-0>

AD<31-24>

AD <15-8>

CNT<15-8>

AD<23-16>

AD<7-0>

CNT<7-0>

RSB/TCB <15-8> RSB/TCB <7-0>

RCHR/TCLR <15-8> RCHR/TCLR <7-0>

AD<31-24>

AD <15-8>

AD<23-16>

AD<7-0>

AD<31-24>

AD <15-8>

CNT<15-8>

AD<23-16>

AD<7-0>

CNT<7-0>

RSB/TCB <15-8> RSB/TCB <7-0>

RCHR/TCLR <15-8> RCHR/TCLR <7-0>

AD<31-24>

AD <15-8>

AD<23-16>

AD<7-0>

Base Address

Base Address + 2

Base Address + 4

Base Address + 12

Base Address + 14

#2 Base Address

#2 Base Address + 2

#2 Base Address + 4

#3 Base Address

#3 Base Address + 2

#3 Base Address + 4

#3 Base Address + 6

#3 Base Address + 8

Base Address + 6

Base Address + 8

Base Address + 10

#2 Base Address + 6

#2 Base Address + 8

#2 Base Address + 10

#2 Base Address + 12

#2 Base Address + 14

#3 Base Address + 10

Figure 31b. Linked Array-Chained, 16-Bit Bus, Big End Array

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

AD<15-8>

AD<31-24>

CNT<15-8>

AD<7-0>

AD<23-16>

CNT<7-0>

Ignored

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Buffer #1

Buffer #n

Base Address

Base Address + 2

Base Address + 4

Base Address + 6

Base Address + 8

#2 Base Address

#2 Base Address + 2

#2 Base Address + 4

#n Base Address

#n Base Address + 2

#n Base Address + 4

AD15 AD0

AD<15-8>

AD<31-24>

AD<15-8>

AD<7-0>

AD<23-16>

AD<7-0>

AD<31-24> AD<23-16>

CNT<15-8> CNT<7-0>

AD<15-8>

AD<31-24>

AD<15-8>

AD<7-0>

AD<23-16>

AD<7-0>

AD<31-24> AD<23-16>

CNT<15-8> CNT<7-0>

AD<15-8>

AD<31-24>

AD<7-0>

AD<23-16>

#n - 1 Base Address + 8

#n - 1 Base Address + 6

Base #2

Buffer #2

Base #3

Buffer #3

#2 Base Address + 6

#2 Base Address + 8

#3 Base Address

#3 Base Address + 2

#3 Base Address + 4

Base #n

Figure 32. Linked Array-Chained, 16-Bit Bus, Little End Array

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

AD<7-0>

AD<15-8>

AD<23-16>

Buffer #1Base Address

Base Address + 1

Base Address + 2

Base Address + 4

Base Address + 5

Base Address + 8

Base Address + 6

Base Address + 7

#2 Base Address + 8

#2 Base Address + 9

AD7 AD0

CNT<7-0>

CNT<15-8>

AD<7-0>

AD<15-8>

#2 Base Address + 7

#2 Base Address + 6

Base #2

Buffer #2#2 Base Address

#2 Base Address + 1

#2 Base Address + 2

#2 Base Address + 3

#2 Base Address + 4

AD<31-24>

AD<23-16>

AD<31-24>

AD<7-0>

AD<15-8>

AD<23-16>

AD<31-24>

CNT<7-0>

CNT<15-8>

AD<7-0>

AD<15-8>

AD<23-16>

AD<31-24>

Base #3

Base Address + 3

Base Address + 9

#2 Base Address + 5

Figure 33a. Linked Array-Chained, 8-Bit Bus, Big End Array

Note:

The addition of frame status/control information in the array with Linked

Frame Status Transfer Enabled is similar to Big End Array. See Figure 33b.

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

AD<31-24>

AD<23-16>

AD<15-8>

Buffer #1

Base Address

Base Address + 1

Base Address + 2

Base Address + 4

Base Address + 5

Base Address + 14

Base Address + 12

Base Address + 13

#2 Base Address + 8

#2 Base Address + 9

AD7 AD0

CNT<7-0>

CNT<15-8>

AD<31-24>

AD<23-16>

#2 Base Address + 7

#2 Base Address + 6

Base #2

Buffer #2

#2 Base Address

#2 Base Address + 1

#2 Base Address + 2

#2 Base Address + 3

#2 Base Address + 4

AD<7-0>

AD<15-8>

AD<7-0>

AD<31-24>

AD<23-16>

AD<15-8>

AD<7-0>

CNT<15-8>

CNT<7-0>

RSB/TCB <7-0>

RCHR/TCLR <15-8>

RCHR/TCLR <7-0>

Base Address + 3

Base Address + 15

#2 Base Address + 5

Base Address + 6

Base Address + 7

Base Address + 8

Base Address + 9

Base Address + 10

Base Address + 11

RSB/TCB <15-8>

RSB/TCB <7-0>

RCHR/TCLR <15-8>

RCHR/TCLR <7-0>

RSB/TCB <15-8>

#2 Base Address + 10

#2 Base Address + 11 0

Figure 33b. Linked Frame Status Transfer Enables

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

AD<31-24>

AD<23-16>

AD<15-8>

Buffer #1Base Address

Base Address + 1

Base Address + 2

Base Address + 4

Base Address + 5

Base Address + 8

Base Address + 6

Base Address + 7

#2 Base Address + 8

#2 Base Address + 9

AD7 AD0

CNT<15-8>

CNT<7-0>

AD<31-24>

AD<23-16>

#2 Base Address + 7

#2 Base Address + 6

Base #2

Buffer #2#2 Base Address

#2 Base Address + 1

#2 Base Address + 2

#2 Base Address + 3

#2 Base Address + 4

AD<7-0>

AD<15-8>

AD<7-0>

AD<31-24>

AD<23-16>

AD<15-8>

AD<7-0>

CNT<15-8>

CNT<7-0>

AD<31-24>

AD<23-16>

AD<15-8>

AD<7-0>

Base #3

Base Address + 3

Base Address + 9

#2 Base Address + 5

Figure 34. Linked Array-Chained 8-Bit Bus, Little End Array

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00000

Upper//Lower Byte Select (WO)

0 0 Normal Operation

0 1 Auto Echo

1 0 External Local Loopback

1 1 Internal Local Loopback

Address 0 (WO)

Address 1 (WO)

Address 2 (WO)

Address 3 (WO)

Rx/Tx

Mode

D15 D14 D13 D12 D11 D10 D9 D8

Rx/Tx Reset

0 0 0 0 0 Null Command

0 0 0 0 1 Reserved

0 0 0 1 0 Reset Highest IUS

0 0 0 1 1 Reserved

0 0 1 0 0 Trigger Channel Load DMA

0 0 1 0 1 Trigger Rx DMA

0 0 1 1 0 Trigger Tx DMA

0 0 1 1 1 Trigger Rx & Tx DMA

0 1 0 0 0 Reserved

0 1 0 0 1 Rx FIFO Purge

0 1 0 1 0 Tx FIFO Purge

0 1 0 1 1 Rx & Tx FIFO Purge

0 1 1 0 0 Reserved

0 1 1 0 1 Load Rx Character Count

0 1 1 1 0 Load Tx Character Count

0 1 1 1 1 Load Rx & Tx Character Count

1 0 0 0 0 Reserved

1 0 0 0 1 Load TC0

1 0 0 1 0 Load TC1

1 0 0 1 1 Load TC0 & TC1

1 0 1 0 0 Select Serial Data LSB First

1 0 1 0 1 Select Serial Data MSB First

1 0 1 1 0 Select Straight Memory Data

1 0 1 1 1 Select Swapped Memory Data

1 1 0 0 0 Reserved

1 1 0 0 1 Reserved

1 1 0 1 0 Reserved

1 1 0 1 1 Reserved

1 1 1 0 0 Reserved

1 1 1 0 1 Reserved

1 1 1 1 0 Reserved

1 1 1 1 1 Reserved

Address 4 (WO)

Byte//Word Access (WO)

Channel Load DMA (WO)

Channel

Command

(WO)

Selected

Upon Reset

Figure 35. Channel Command/Address Register (CCAR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

0 0 0 0 Asynchronous

0 0 0 1 External Synchronous

0 0 1 0 Isochronous

0 0 1 1 Asynchronous with CV

0 1 0 0 Monosync

0 1 0 1 Bisync

0 1 1 0 HDLC

0 1 1 1 Transparent Bisync

1 0 0 0 NBIP

1 0 0 1 802.3

1 0 1 0 Reserved

1 0 1 1 Reserved

1 1 0 0 Reserved

1 1 0 1 Reserved

1 1 1 0 Reserved

1 1 1 1 Reserved

Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

Rx Submode 0

Rx Submode 1

Rx Submode 2

Rx Submode 3

0 0 0 0 Asynchronous

0 0 0 1 Reserved

0 0 1 0 Isochronous

0 0 1 1 Asynchronous with CV

0 1 0 0 Monosync

0 1 0 1 Bisync

0 1 1 0 HDLC

0 1 1 1 Transparent Bisync

1 0 0 0 NBIP

1 0 0 1 802.3

1 0 1 0 Reserved

1 0 1 1 Reserved

1 1 0 0 Slaved Monosync

1 1 0 1 Reserved

1 1 1 0 HDLC Loop

1 1 1 1 Reserved

Tx Submode 0

Tx Submode 1

Tx Submode 2

Tx Submode 3

Transmitter

Mode

Figure 36. Channel Mode Register (CMR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

0 0 0 0 Asynchronous Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

Reserved

0 0 16X Data Rate

0 1 32X Data Rate

1 0 64X Data Rate

1 1 Reserved

Rx Clock

Rate

0 0 0 0 Asynchronous Transmitter

Mode

0 0 16X Data Rate

0 1 32X Data Rate

1 0 64X Data Rate

1 1 Reserved

Tx Clock

Rate

0 0 One Stop Bit

0 1 Two Stop Bits

1 0 One Stop Bit, Shaved

1 1 Two Stop Bits, Shaved

Tx Stop

Bits

Figure 37. Channel Mode Register, Asynchronous Mode

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

0 0 0 1 External Sync Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 1 Reserved Transmitter

Mode

Reserved

Figure 38. Channel Mode Register, External Sync Mode

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

0 0 1 0 Isochronous Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

0 0 1 0 Isochronous Transmitter

Mode

Reserved

Tx Two Stop Bits

Reserved

Figure 39. Channel Mode Register, Isochronous Mode

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

0 0 1 1 Asynchronous with CV Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

0 0 1 1 Asynchronous with CV Transmitter

Mode

Rx Extended Word

CV Polarity

Tx Extended Word

Reserved

0 0 One Stop Bit

0 1 Two Stop Bits

1 0 No Stop Bit

1 1 Reserved

Stop Bits

Figure 40. Channel Mode Register, Asynchronous Mode

with Code Violation (MIL STD 1553)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

0 1 0 0 Monosync Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

0 1 0 0 Monosync Transmitter

Mode

Rx Short Sync Character

Tx Short Sync Character

Tx Preamble Enable

Rx Sync Strip

Reserved

Tx CRC on Underrun

Figure 41. Channel Mode Register, Monosync Mode

Figure 42. Channel Mode Register, Bisync Mode

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

0 1 0 1 Bisync Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

0 1 0 1 Bisync Transmitter

Mode

Rx Short Sync Character

Tx Short Sync Character

Rx Sync Strip

0 0 SYN1

0 1 SYN0/SYN1

1 0 CRC/SYN1

1 1 CRC/SYN0/SYN1

Underrun

Condition

Reserved

Tx Preamble Enable

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

0 1 1 0 HDLC Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

0 1 1 0 HDLC Transmitter

Mode

Rx 16-Bit Control

0 0 Abort

0 1 Extended Abort

1 0 Flag

1 1 CRC/Flag

Underrun

Condition

Rx Logical Control Enable

0 0 Disabled

0 1 One Byte, No Control

1 0 One Byte, Plus Control

1 1 Extended, Plus Control

Rx Address

Search Mode

Shared Zero Flags

Tx Preamble Enable

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

0 1 1 1 Transparent Bisync Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

0 1 1 1 Transparent Bisync Transmitter

Mode

0 0 SYN

0 1 DLE/SYN

1 0 CRC/SYN

1 1 CRC/DLE/SYN

Underrun

Condition

Tx Preamble Enable

EBCDIC

Reserved

EBCDIC

Figure 43. Channel Mode Register, HDLC Mode

Figure 44. Channel Mode Register, Transparent Bisync Mode

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

1 0 0 0 NBIP Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

Rx Parity on Data

Reserved

0 0 16X Data Rate

0 1 32X Data Rate

1 0 64X Data Rate

1 1 Reserved

Rx Clock

Rate

1 0 0 0 NBIP Transmitter

Mode

0 0 16X Data Rate

0 1 32X Data Rate

1 0 64X Data Rate

1 1 Reserved

Tx Clock

Rate

Tx Parity on Data

Tx Address Bit

Figure 46. Channel Mode Register, 802.3 Mode

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

1 0 0 1 802.3 Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

1 0 0 1 802.3 Transmitter

Mode

Rx Address Search

Reserved

Tx CRC on Underrun

Reserved

Figure 45. Channel Mode Register, NBIP Mode

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

1 1 0 0 Reserved Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

1 1 0 0 Slaved Monosync Transmitter

Mode

Reserved

Tx Short Sync Character

Tx Active on Received Sync

Reserved

Tx CRC on Underrun

Figure 47. Channel Mode Register, Slaved Monosync Mode

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00001

1 1 1 0 Reserved Receiver

Mode

D15 D14 D13 D12 D11 D10 D9 D8

1 1 1 0 HDLC Loop Transmitter

Mode

Reserved

Shared-Zero Flags

Tx Active on Poll

0 0 Abort

0 1 Extended Abort

1 0 Flag

1 1 CRC/Flag

Tx Underrun

Condition

Figure 48. Channel Mode Register, HDLC Loop Mode

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00010

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 8 Bits

0 0 1 1 Bit

0 1 0 2 Bits

0 1 1 3 Bits

1 0 0 4 Bits

1 0 1 5 Bits

1 1 0 6 Bits

1 1 1 7 Bits

HDLC Tx Last

Character Length

0 0 Both Edges

0 1 Rising Edge Only

1 0 Falling Edge Only

1 1 Adjust/Sync Inhibit

DPLL Adjust/Sync Edge

Reserved

Counter By-pass Enable

Loop Sending (RO)

On Loop (RO)

Clock Missed Latched/Unlatch

2 Clocks Missed Latched/Unlatch

DPLL in Sync/Quick Sync

RCC FIFO Clear (WO)

RCC FIFO Valid (RO)

RCC FIFO Overflow (RO)

Figure 49. Channel Command/Status Register (CCSR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00011

D15 D14 D13 D12 D11 D10 D9 D8

0 0 All Zeros

0 1 All Ones

1 0 Alternating 1 and 0

1 1 Alternating 0 and 1

Tx Preamble

Pattern

Reserved

Wait for Rx DMA Trigger

Tx Flag Preamble

Wait for Tx DMA Trigger

0 0 No Status Block

0 1 One Word Status Block

1 0 Two Word Status Block

1 1 Reserved

Rx Status

Block Transfer

Tx Shaved Bit Length

(Async Only)

0 0 8 Bits

0 1 16 Bits

1 0 32 Bits

1 1 64 Bits

Tx Preamble

Length

0 0 No Status Block

0 1 One Word Status Block

1 0 Two Word Status Block

1 1 Reserved

Tx Control

Block Transfer

(All Sync)

Figure 50. Channel Control Register (CCR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00100

D15 D14 D13 D12 D11 D10 D9 D8

/Port Bit 0 (RO)

Port Bit 0 Latched/Unlatch

/Port Bit 1 (RO)

Port Bit 1 Latched/Unlatch

/Port Bit 2 (RO)

Port Bit 2 Latched/Unlatch

/Port Bit 3 (RO)

Port Bit 3 Latched/Unlatch

/Port Bit 4 (RO)

Port Bit 4 Latched/Unlatch

/Port Bit 5 (RO)

Port Bit 5 Latched/Unlatch

/Port Bit 6 (RO)

Port Bit 6 Latched/Unlatch

/Port Bit 7 (RO)

Port Bit 7 Latched/Unlatch

Figure 51. Port Status Register (PSR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00101

D15 D14 D13 D12 D11 D10 D9 D8

0 0 Tri-State Output

0 1 CLK0 Input

1 0 Output 0

1 1 Output 1

Port Bit 0

Pin Control

0 0 Tri-State Output

0 1 CLK1 Input

1 0 Output 0

1 1 Output 1

Port Bit 1

Pin Control

0 0 Tri-State Output

0 1 Reserved

1 0 Output 0

1 1 Output 1

Port Bit 2

Pin Control

0 0 Tri-State Output

0 1 Rx TSA Gate Output

1 0 Output 0

1 1 Output 1

Port Bit 3

Pin Control

0 0 Tri-State Output

0 1 Tx TSA Gate Output

1 0 Output 0

1 1 Output 1

Port Bit 4

Pin Control

0 0 Tri-State Output

0 1 Rx Sync Output

1 0 Output 0

1 1 Output 1

Port Bit 5

Pin Control

0 0 Tri-State Output

0 1 Frame Sync Input

1 0 Output 0

1 1 Output 1

Port Bit 6

Pin Control

0 0 Tri-State Output

0 1 Tx Complete Output

1 0 Output 0

1 1 Output 1

Port Bit 7

Pin Control

Figure 52. Port Control Register (PCR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00110

D15 D14 D13 D12 D11 D10 D9 D8

Test Data <0>

Test Data <1>

Test Data <2>

Test Data <3>

Test Data <4>

Test Data <5>

Test Data <6>

Test Data <7>

Test Data <8>

Test Data <9>

Test Data <10>

Test Data <11>

Test Data <12>

Test Data <13>

Test Data <14>

Test Data <15>

Figure 53. Test Mode Data Register (TMDR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 00111

0 0 0 0 0 Null Address

0 0 0 0 1 High Byte of Shifters

0 0 0 1 0 CRC Byte 0

0 0 0 1 1 CRC Byte 1

0 0 1 0 0 Rx FIFO (Write)

0 0 1 0 1 Clock Multiplexer Outputs

0 0 1 1 0 CTR0 and CTR1 Counters

0 0 1 1 1 Clock Multiplexer Inputs

0 1 0 0 0 DPLL State

0 1 0 0 1 Low Byte of Shifters

0 1 0 1 0 CRC Byte 2

0 1 0 1 1 CRC Byte 3

0 1 1 0 0 Tx FIFO (Read)

0 1 1 0 1 Reserved

0 1 1 1 0 I/O and Device Status Latches

0 1 1 1 1 Internal Daisy Chain

1 0 0 0 0 Reserved

1 0 0 0 1 Reserved

1 0 0 1 0 Reserved

1 0 0 1 1 Reserved

1 0 1 0 0 Reserved

1 0 1 0 1 Reserved

1 0 1 1 0 Rx Count Holding Register

1 0 1 1 1 Reserved

1 1 0 0 0 Reserved

1 1 0 0 1 Reserved

1 1 0 1 0 Reserved

1 1 0 1 1 4453H

1 1 1 0 0 Reserved

1 1 1 0 1 Reserved

1 1 1 1 0 Reserved

1 1 1 1 1 4453H

Test

Address

D15 D14 D13 D12 D11 D10 D9 D8

Reserved

Figure 54. Test Mode Control Register (TMCR)

Note:

When software writes the value 1F to the LS byte of the Test Mode Control Register (TMCR),

and then reads the Test Mode Data Register (TMDR), current versions of the Z16C32 will return

hex 4453. Future revisions, if any, will return other values.

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 01000

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 Disabled

0 0 1 /RxC Pin

0 1 0 /TxC Pin

0 1 1 DPLL Output

1 0 0 BRG0 Output

1 0 1 BRG1 Output

1 1 0 CTR0 Output

1 1 1 CTR1 Output

Receive Clock

Source

0 0 0 Disabled

0 0 1 /RxC Pin

0 1 0 /TxC Pin

0 1 1 DPLL Output

1 0 0 BRG0 Output

1 0 1 BRG1 Output

1 1 0 CTR0 Output

1 1 1 CTR1 Output

Transmit Clock

Source

0 0 BRG0 Output

0 1 BRG1 Output

1 0 /RxC Pin

1 1 /TxC Pin

DPLL Clock

Source

0 0 CTR0 Output

0 1 CTR1 Output

1 0 /RxC Pin

1 1 /TxC Pin

BRG1 Clock

Source

0 0 Disabled

0 1 Port0 Pin

1 0 /RxC Pin

1 1 /TxC Pin

CTR0 Clock

Source

0 0 Disabled

0 1 Port1 Pin

1 0 /RxC Pin

1 1 /TxC Pin

CTR1 Clock

Source

0 0 CTR0 Output

0 1 CTR1 Output

1 0 /RxC Pin

1 1 /TxC Pin

BRG0 Clock

Source

Figure 55. Clock Mode Control Register (CMCR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 01001

D15 D14 D13 D12 D11 D10 D9 D8

0 0 32x Clock Mode

0 1 16x Clock Mode

1 0 8x Clock Mode

1 1 Reserved

DPLL Clock

Divider

0 0 32x Clock Mode

0 1 16x Clock Mode

1 0 8x Clock Mode

1 1 4x Clock Mode

CTR0 Clock

Divider

0 0 Disabled

0 1 NRZ/NRZI

1 0 Biphase-Mark/Space

1 1 Biphase-Level

DPLL

Divider

BRG0 Enable

BRG0 Single Cycle/Continuous

BRG1 Enable

BRG1 Single Cycle/Continuous

Code Violations OK

CTR1 Rate Match DPLL/CTR0

Reserved

Figure 56. Hardware Configuration Register (HCR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 01010

D15 D14 D13 D12 D11 D10 D9 D8

IV <0>

IV <1>

IV <2>

IV <3>

IV <4>

IV <5>

IV <6>

IV <7>

IV <0> (RO)

IV <4> (RO)

IV <5> (RO)

IV <6> (RO)

IV <7> (RO)

0 0 0 None

0 0 1 Device Status

0 1 0 I/O Status

0 1 1 Transmit Data

1 0 0 Transmit Status

1 0 1 Receive Data

1 1 0 Receive Status

1 1 1 Not Used

Type

Code

Figure 57. Interrupt Vector Register (IVR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 01011

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 Input Pin

0 0 1 Rx Clock Output

0 1 0 Rx Byte Clock Output

0 1 1 SYNC Output

1 0 0 BRG0 Output

1 0 1 BRG1 Output

1 1 0 CTR0 Output

1 1 1 DPLL Rx Output

/RxC Pin

Control

0 0 0 Input PIn

0 0 1 Tx Clock Output

0 1 0 Tx Byte Clock Output

0 1 1 Tx Complete Output

1 0 0 BRG0 Output

1 0 1 BRG1 Output

1 1 0 CTR1 Output

1 1 1 DPLL Tx Output

/TxC

Pin Control

0 0 Tx Data Output

0 1 3-State Output

1 0 Output 0

1 1 Output 1

TxD Pin

Control

0 0 3-State Output

0 1 Tx Request Output

1 0 Output 0

1 1 Output 1

/TxREQ

Pin Control

0 0 /DCD Input

0 1 /DCD//SYNC Input

1 0 Output 0

1 1 Output 1

/DCD

Pin Control

0 0 /CTS Input

0 1 /CTS Input

1 0 Output 0

1 1 Output 1

/CTS

Pin Control

0 0 3-State Output

0 1 Rx Request Output

1 0 Output 0

1 1 Output 1

/RxREQ

Pin Control

Figure 58. I/O Control Register (IOCR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 01100

D15 D14 D13 D12 D11 D10 D9 D8

0 0 Null Command

0 1 Null Command

1 0 Reset IE

1 1 Set IE

IE Command

(WO)

0 0 0 All

0 0 1 All

0 1 0 I/O Status and Above

0 1 1 Transmit Data and Above

1 0 0 Transmit Status and Above

1 0 1 Receive Data and Above

1 1 0 Receive Status Only

1 1 1 None

VIS

Level

Device Status IE

Receive Status IE

VIS

I/O Status IE

Transmit Data IE

Transmit Status IE

Receive Data IE

Reserved

DLC

MIE

Figure 59. Interrupt Control Register (ICR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 01101

D15 D14 D13 D12 D11 D10 D9 D8

0 0 Null Command

0 1 Reset IP and IUS

1 0 Reset IP

1 1 Set IP

IP Command

(WO)

Device Status IP

Receive Status IP

I/O Status IP

Transmit Data IP

Transmit Status IP

Receive Data IP

Device Status IUS

I/O Status IUS

Transmit Data IUS

Transmit Status IUS

Receive Data IUS

Receive Status IUS

0 0 Null Command

0 1 Null Command

1 0 Reset IUS

1 1 Set IUS

IUS Command

(WO)

Figure 60. Daisy-Chain Control Register (DCCR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 01110

D15 D14 D13 D12 D11 D10 D9 D8

BRG0 ZC Latched/Unlatch

BRG1 ZC Latched/Unlatch

DPLL SYNC Latched/Unlatch

RCC Overflow Latched/Unlatch

/CTS (RO)

/CTS Latched/Unlatch

/DCD (RO)

/DCD Latched/Unlatch

/TxREQ (RO)

/RxREQ (RO)

/RxREQ Latched/Unlatch

/TxC (RO)

/TxC Latched/Unlatch

/RxC (RO)

/RxC Latched/Unlatch

/TxREQ Latched/Unlatch

Figure 61. Miscellaneous Interrupt Status Register (MISR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 01111

D15 D14 D13 D12 D11 D10 D9 D8

BRG0 ZC IA

BRG1 ZC IA

DPLL SYNC IA

RCC Overflow IA

0 0 Disabled

0 1 Rising Edge Only

1 0 Falling Edge Only

1 1 Both Edges

/CTS

Interrupt

Arm

0 0 Disabled

0 1 Rising Edge Only

1 0 Falling Edge Only

1 1 Both Edges

/DCD

Interrupt

Arm

0 0 Disabled

0 1 Rising Edge Only

1 0 Falling Edge Only

1 1 Both Edges

/TxREQ

Interrupt

Arm

0 0 Disabled

0 1 Rising Edge Only

1 0 Falling Edge Only

1 1 Both Edges

/RxREQ

Interrupt

Arm

0 0 Disabled

0 1 Rising Edge Only

1 0 Falling Edge Only

1 1 Both Edges

/TxC

Interrupt

Arm

0 0 Disabled

0 1 Rising Edge Only

1 0 Falling Edge Only

1 1 Both Edges

/RxC

Interrupt

Arm

Figure 62. Status Interrupt Control Register (SICR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 1x000

D15 D14 D13 D12 D11 D10 D9 D8

RxDAT <0> (RO)

RxDAT <1> (RO)

RxDAT <2> (RO)

RxDAT <3> (RO)

RxDAT <4> (RO)

RxDAT <5> (RO)

RxDAT <6> (RO)

RxDAT <7> (RO)

RxDAT <8> (RO)

RxDAT <9> (RO)

RxDAT <10> (RO)

RxDAT <11> (RO)

RxDAT <12> (RO)

RxDAT <13> (RO)

RxDAT <14> (RO)

RxDAT <15> (RO)

Figure 63. Receive Data Register (RDR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 10001

D15 D14 D13 D12 D11 D10 D9 D8

0 0 Even

0 1 Odd

1 0 Space

1 1 Mark

Rx Parity

Type

0 0 Disable Immediately

0 1 Disable After Reception

1 0 Enable Without Auto-Enables

1 1 Enable With Auto-Enables

Enable

0 0 0 8 Bits

0 0 1 1 Bit

0 1 0 2 Bits

0 1 1 3 Bits

1 0 0 4 Bits

1 0 1 5 Bits

1 1 0 6 Bits

1 1 1 7 Bits

Rx Character

Length

Rx Parity Enable

Abort Frame Status

Rx CRC Enable

Rx CRC Preset Value

0 0 CRC-CCITT

0 1 CRC-16

1 0 CRC-32

1 1 Reserved

Rx CRC

Polynomial

0 0 0 NRZ

0 0 1 NRZB

0 1 0 NRZI-Mark

0 1 1 NRZI-Space

1 0 0 Biphase-Mark

1 0 1 Biphase-Space

1 1 0 Biphase-Level

1 1 1 Diff. Biphase-Level

Rx Data

Decoding

Figure 64. Receive Mode Register (RMR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 10010

D15 D14 D13 D12 D11 D10 D9 D8

Rx Character Available (RO)

Rx Overrun

Parity Error/Rx Frame Abort

CRC/Framing Error (RO)

Rx CV/EOT/EOF

Rx Break/Abort

Rx Idle

Exited Hunt

Short Frame/CV Polarity (RO)

First Byte in Error (RO)

Second Byte in Error (RO)

0 0 0 0 Null Command

0 0 0 1 Reserved

0 0 1 0 Preset CRC

0 0 1 1 Enter Hunt Mode

0 1 0 0 Select Timeslot Assignment

0 1 0 1 Select FIFO Status

0 1 1 0 Select FIFO Interrupt Level

0 1 1 1 Select FIFO Request Level

1 0 0 0 Reserved

1 0 0 1 Reserved

1 0 1 0 Reserved

0 0 1 1 Reserved

1 1 0 0 Reserved

1 1 0 1 Reserved

1 1 1 1 Reserved

Receive

Command (WO)

Residue Code 0 (RO)

Residue Code 1 (RO)

Residue Code 2 (RO)

Figure 65. Receive Command Status Register (RCSR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

Figure 66a. Receive Interrupt Control Register (RICR)

Figure 66b. Receive Interrupt Control Register (RICR)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 10011

D15 D14 D13 D12 D11 D10 D9 D8

TC0R Read Count/TC

Rx Overrun IA

Parity Error/Frame Abort IA

Status on Words

Rx CV/EOT/EOF IA

Rx Break/Abort IA

Rx Idle IA

Exited Hunt IA

Timeslot (0-127)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 10011

D15 D14 D13 D12 D11 D10 D9 D8

TC0R Read Count/TC

Rx Overrun IA

Parity Error/Frame Abort IA

Status on Words

Rx CV/EOT/EOF IA

Rx Break/Abort IA

Rx Idle IA

Exited Hunt IA

Rx FIFO Control and Status

(Fill/Interrupt/DMA Level)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

Figure 66c. Receive Interrupt Control Register (RICR)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 10011

D15 D14 D13 D12 D11 D10 D9 D8

Rx Overrun IA

Parity Error/Frame Abort IA

Status on Words

Rx CV/EOT/EOF IA

0 0 0 0 No Slot (Disabled)

0 0 0 1 1 Slot

0 0 1 0 2 Slots

0 0 1 1 3 Slots

0 1 0 0 4 Slots

0 1 0 1 5 Slots

0 1 1 0 6 Slots

0 1 1 1 7 Slots

1 0 0 0 8 Slots

1 0 0 1 9 Slots

1 0 1 0 10 Slots

1 0 1 1 11 Slots

1 1 0 0 12 Slots

1 1 0 1 13 Slots

1 1 1 0 14 Slots

1 1 1 1 15 Slots

Concatenated

Slots (WO)

TC0R Read Count/TC

Rx Break/Abort IA

Rx Idle IA

Exited Hunt IA

1 (WO)

0 0 0 No Offset

0 0 1 7 Clocks Offset

0 1 0 6 Clocks Offset

0 1 1 5 Clocks Offset

1 0 0 4 Clocks Offset

1 0 1 3 Clocks Offset

1 1 0 2 Clocks Offset

1 1 1 1 Clock Offset

Slot Offset

(WO)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 10100

D15 D14 D13 D12 D11 D10 D9 D8

RSYN <0>

RSYN <1>

RSYN <2>

RSYN <3>

RSYN <4>

RSYN <5>

RSYN <6>

RSYN <7>

RSYN <8>

RSYN <9>

RSYN <10>

RSYN <11>

RSYN <12>

RSYN <13>

RSYN <14>

RSYN <15>

Figure 67. Receive Sync Register (RSR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 10101

D15 D14 D13 D12 D11 D10 D9 D8

RCL <0>

RCL <1>

RCL <2>

RCL <3>

RCL <4>

RCL <5>

RCL <6>

RCL <7>

RCL <8>

RCL <9>

RCL <10>

RCL <11>

RCL <12>

RCL <13>

RCL <14>

RCL <15>

Figure 68. Receive Count Limit Register (RCLR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 10110

D15 D14 D13 D12 D11 D10 D9 D8

RCC <0> (RO)

RCC <1> (RO)

RCC <2> (RO)

RCC <3> (RO)

RCC <4> (RO)

RCC <5> (RO)

RCC <6> (RO)

RCC <7> (RO)

RCC <8> (RO)

RCC <9> (RO)

RCC <10> (RO)

RCC <11> (RO)

RCC <12> (RO)

RCC <13> (RO)

RCC <14> (RO)

RCC <15> (RO)

Figure 69. Receive Character Count Register (RCCR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 10111

D15 D14 D13 D12 D11 D10 D9 D8

TC0 <0>

TC0 <1>

TC0 <2>

TC0 <3>

TC0 <4>

TC0 <5>

TC0 <6>

TC0 <7>

TC0 <8>

TC0 <9>

TC0 <10>

TC0 <11>

TC0 <12>

TC0 <13>

TC0 <14>

TC0 <15>

Figure 70. Time Constant 0 Register (TC0R)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 1x000

D15 D14 D13 D12 D11 D10 D9 D8

TxDAT <0> (WO)

TxDAT <1> (WO)

TxDAT <2> (WO)

TxDAT <3> (WO)

TxDAT <4> (WO)

TxDAT <5> (WO)

TxDAT <6> (WO)

TxDAT <7> (WO)

TxDAT <8> (WO)

TxDAT <9> (WO)

TxDAT <10> (WO)

TxDAT <11> (WO)

TxDAT <12> (WO)

TxDAT <13> (WO)

TxDAT <14> (WO)

TxDAT <15> (WO)

Figure 71. Transmit Data Register (TDR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 11001

D15 D14 D13 D12 D11 D10 D9 D8

0 0 Even

0 1 Odd

1 0 Space

1 1 Mark

Tx Parity

Sense

0 0 Disable Immediately

0 1 Disable After Transmission

1 0 Enable Without Auto-Enables

1 1 Enable With Auto-Enables

Enable

0 0 0 8 Bits

0 0 1 1 Bit

0 1 0 2 Bits

0 1 1 3 Bits

1 0 0 4 Bits

1 0 1 5 Bits

1 1 0 6 Bits

1 1 1 7 Bits

Tx Character

Length

Tx Parity Enable

Tx CRC on EOF/EOM

Tx CRC Enable

Tx CRC Start Value

0 0 CRC-CCITT

0 1 CRC-16

1 0 CRC-32

1 1 Reserved

Tx CRC

Type

0 0 0 NRZ

0 0 1 NRZB

0 1 0 NRZI-Mark

0 1 1 NRZI-Space

1 0 0 Biphase-Mark

1 0 1 Biphase-Space

1 1 0 Biphase-Level

1 1 1 Diff. Biphase-Level

Tx Data

Encoding

Figure 72. Transmit Mode Register (TMR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 11010

D15 D14 D13 D12 D11 D10 D9 D8

Tx Underrun

All Sent (RO)

Tx CRC Sent

Tx EOF/EOT Sent

0 0 0 0 Null Command

0 0 0 1 Reserved

0 0 1 0 Preset CRC

0 0 1 1 Reserved

0 1 0 0 Select Timeslot Assignment

0 1 0 1 Select FIFO Status

0 1 1 0 Select Interrupt Level

0 1 1 1 Select Request Level

1 0 0 0 Send Frame/Message

1 0 0 1 Send Abort

1 0 1 0 Reserved

1 0 1 1 Reserved

1 1 0 0 Reset DLE Inhibit

1 1 0 1 Set DLE Inhibit

1 1 1 0 Reset EOF/EOM

1 1 1 1 Set EOF/EOM

Transmit

Command (WO)

Tx Buffer Empty (RO)

Tx Abort Sent

Tx Idle Sent

Tx Preamble Sent

0 0 0 SYNC/Flag/Normal

0 0 1 Alternating 1 and 0

0 1 0 All Zeros

0 1 1 All Ones

1 0 0 Reserved

1 0 1 Alternating Mark and Space

1 1 0 Space

1 1 1 Mark

Tx Idle Line

Condition

Reserved

Figure 73. Transmit Command/Status Register (TCSR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 11011

D15 D14 D13 D12 D11 D10 D9 D8

TC1R Read Count/TC

Tx Overrun IA

Wait for Send Command

Tx CRC Sent IA

Tx EOF/EOT Sent IA

Tx Abort Sent IA

Tx Idle Sent IA

Tx Preamble Sent IA

Tx FIFO Control and Status

(Fill/Interrupt/DMA Level)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 11011

D15 D14 D13 D12 D11 D10 D9 D8

TC1R Read Count/TC

Tx Underrun IA

Wait for Send Command

Tx CRC Sent IA

Tx EOF/EOT Sent IA

Tx Abort Sent IA

Tx Idle Sent IA

Tx Preamble Sent IA

Timeslot (0-127)

Figure 74a. Transmit Interrupt Control Register (TICR)

Figure 74b. Transmit Interrupt Control Register (TICR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 11011

D15 D14 D13 D12 D11 D10 D9 D8

Tx Underrun IA

Wait for Send Command

Tx CRC Sent IA

Tx EOF/EOT Sent IA

0 0 0 0 No Slot (Disabled)

0 0 0 1 1 Slot

0 0 1 0 2 Slots

0 0 1 1 3 Slots

0 1 0 0 4 Slots

0 1 0 1 5 Slots

0 1 1 0 6 Slots

0 1 1 1 7 Slots

1 0 0 0 8 Slots

1 0 0 1 9 Slots

1 0 1 0 10 Slots

1 0 1 1 11 Slots

1 1 0 0 12 Slots

1 1 0 1 13 Slots

1 1 1 0 14 Slots

1 1 1 1 15 Slots

Concatenated

Slots (WO)

TC1R Read Count/TC

Tx Abort Sent IA

Tx Idle Sent IA

Tx Preamble Sent IA

1 (WO)

0 0 0 No Offset

0 0 1 7 Clocks Offset

0 1 0 6 Clocks Offset

0 1 1 5 Clocks Offset

1 0 0 4 Clocks Offset

1 0 1 3 Clocks Offset

1 1 0 2 Clocks Offset

1 1 1 1 Clock Offset

Slot Offset

(WO)

Figure 74c. Transmit Interrupt Control Register (TICR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 11100

D15 D14 D13 D12 D11 D10 D9 D8

TSYN <0>

TSYN <1>

TSYN <2>

TSYN <3>

TSYN <4>

TSYN <5>

TSYN <6>

TSYN <7>

TSYN <8>

TSYN <9>

TSYN <10>

TSYN <11>

TSYN <12>

TSYN <13>

TSYN <14>

TSYN <15>

Figure 75. Transmit Sync Register (TSR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 11101

D15 D14 D13 D12 D11 D10 D9 D8

TCL <0>

TCL <1>

TCL <2>

TCL <3>

TCL <4>

TCL <5>

TCL <6>

TCL <7>

TCL <8>

TCL <9>

TCL <10>

TCL <11>

TCL <12>

TCL <13>

TCL <14>

TCL <15>

Figure 76. Transmit Count Limit Register (TCLR)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: 11110

D15 D14 D13 D12 D11 D10 D9 D8

TCC <0> (RO)

TCC <1> (RO)

TCC <2> (RO)

TCC <3> (RO)

TCC <4> (RO)

TCC <5> (RO)

TCC <6> (RO)

TCC <7> (RO)

TCC <8> (RO)

TCC <9> (RO)

TCC <10> (RO)

TCC <11> (RO)

TCC <12> (RO)

TCC <13> (RO)

TCC <14> (RO)

TCC <15> (RO)

Figure 77. Transmit Character Count Register (TCCR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: 11111

D15 D14 D13 D12 D11 D10 D9 D8

TC1 <0>

TC1 <1>

TC1 <2>

TC1 <3>

TC1 <4>

TC1 <5>

TC1 <6>

TC1 <7>

TC1 <8>

TC1 <9>

TC1 <10>

TC1 <11>

TC1 <12>

TC1 <13>

TC1 <14>

TC1 <15>

Figure 78. Time Constant 1 Register (TC1R)

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

D7 D6 D5 D4 D3 D2 D1 D0

Address: None

D15 D14 D13 D12 D11 D10 D9 D8

RCC <0>

Rx Overrun

Parity Error Rx/Frame Abort

CRC Error

Rx Bound

Short Frame/CV Polarity

Residue Code 0

Residue Code 1

Residue Code 2

First Byte in Error

Second Byte in Error

Refer to Figure 22 (Channel Control Register)

Bits 6-7 for Access Method

Figure 79. Receive Status Block Register (RSBR)

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

CONTROL REGISTERS (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Address: None

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 8 Bits

0 0 1 1 Bit

0 1 0 2 Bits

0 1 1 3 Bits

1 0 0 4 Bits

1 0 1 5 Bits

1 1 0 6 Bits

1 1 1 7 Bits

HDLC Tx Last

Character Length

Reserved

Tx Submode 0

Tx Submode 1

Tx Submode 2

Tx Submode 3

Refer to Figure 22 (Channel Control Register)

Bits15-14 for Access Method

Figure 80. Transmit Status Block Register (TSBR)

Figure 81. Bus Configuration Register (BCR)

D15

Shift Right Address

/INT Open-Drain

16-Bit Bus

/BUSREQ Type

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Address: none

0 0 Status Acknowledge

0 1 Single Pulse Acknowledge

1 0 Reserved

1 1 Double Pulse Acknowledge

INTACK Mode

Tri-State All Pins

Separate Address for 8-Bit Bus

Must be programmed as 0.

PRELIMINARY

Z16C32 IUSC

™

ZILOG

PS97USC0200

ABSOLUTE MAXIMUM RATINGS

Symbol Description Min Max Units

VCC Supply Voltage (*) –0.3 +7.0 V

TSTG Storage Temp –65°+150°C

TAOper Ambient Temp † C

Power Dissipation 2.2 W

Notes:

* Voltage on all pins with respect to GND.

† See Ordering Information.

Stresses greater than those listed under Absolute Maxi-

mum Ratings may cause permanent damage to the de-

vice. This is a stress rating only; operation of the device at

any condition above those indicated in the operational

sections of these specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods

may affect device reliability.

STANDARD TEST CONDITIONS

The DC Characteristics and Capacitance Section below

apply for the following standard test conditions, unless

otherwise noted. All voltages are referenced to Ground.

Positive current flows into the referenced pin (Figure 82).

Standard conditions are as follows:

■+4.5 V < VCC < +5.5 V

■GND = 0 V

■TA as specified in Ordering Information

+5V

From Output

Under Test

50 pF 250 μA

1.73 K

Figure 82. Standard Test Load

CAPACITANCE

Symbol Parameter Min Max Unit Condition

CIN Input Capacitance 10 pF *

COUT Output Capacitance 15 pF *

CI/O Bidirectional Capacitance 20 pF

MISCELLANEOUS

Transistor Count - 100,000

TEMPERATURE RANGE

Standard = 0°C to 70°C

Notes:

F = 1 MHz, over specified temperature range.

* Unmeasured pins returned to Ground.

PRELIMINARY

Z16C32 IUSC

™

PS97USC0200

ZILOG

the IUSC will enter a pre-reset state. This state is only

exited by a hardware reset. Do not allow overlap of timing

strobes. The timing diagrams, beginning on the next page,

illustrate the different bus transactions possible with the

necessary setup, hold, and delay times. IUSC Timing

diagrams are shown from Figure 83 through Figure 107.

DC CHARACTERISTICS

Symbol Parameter Min Typ Max Unit Condition

VIH Input High Voltage 2.2 VCC +0.3 V

VIL Input Low Voltage –0.3 0.8 V

VOH1 Output High Voltage 2.4 V IOH = –1.6 mA

VOH2 Output High Voltage VCC –0.8 V IOH = –250 μA

VOL Output Low Voltage 0.4 V IOL = +2.0 mA

IIL Input Leakage +10.00 μA 0.4 < VIN < +2.4V

IOL Output Leakage +10.00 μA 0.4 < VOUT < +2.4V

ICC1 VCC Supply Current 7 50 mA VCC = 5V VIH = 4.8V VIL = 0.2V

IUSC TIMING

The IUSC interface timing is similar to that found on a static

RAM, except that it is much more flexible. Up to four

separate timing strobe signals are present on the inter-

face: /DS, /RD, /WR and /INTACK. Only one of these timing

strobes is active at any time. Should the external logic

activate more than one of these strobes at the same time,

AC CHARACTERISTICS

Timing Diagrams (Figures 83-105)

/RESET

/STB

113 114

115

Note:

/STB is any of the following: /DS, /RD, /WR or Pulsed /INTACK.

Figure 84. Bus Cycle Timing

/STB

112

Figure 83. Reset Timing

Note:

VCC = 5V ± 10% unless otherwise specified, over specified temperature range.

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AC CHARACTERISTICS

Timing Diagrams (Continued)

/CS

12 13

14 15

1716

20 21

4 5

18 19 8

2322

116 79 80

S//D, D//C

/INTACK

(Status)

/AS

R//W

/DS

AD15-AD0

/RxREQ

/WAIT//RDY

(Wait)

/WAIT//RDY

(Ready)

Figure 85. Multiplexed /DS Read Cycle

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AC CHARACTERISTICS

Timing Diagrams (Continued)

/CS

12 13

14 15

1716

20 21

4 5

18 19

2726

116 80

S//D, D//C

/INTACK

(Status)

/AS

R//W

/DS

AD15-AD0

/TxREQ

/WAIT//RDY

(Wait)

/WAIT//RDY

(Ready)

2524

Figure 86. Multiplexed /DS Write Cycle

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/CS

12 13

14 15

1716

230

28 29

18 19 32

3736

119 79 90

S//D, D//C

/INTACK

(Status)

/AS

/RD

AD15-AD0

/RxREQ

/WAIT//RDY

(Wait)

/WAIT//RDY

(Ready)

Figure 87. Multiplexed /RD Read Cycle

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AC CHARACTERISTICS

Timing Diagrams (Continued)

/CS

12 13

14 15

1716

240

38 39

18 19

117 118

S//D, D//C

/INTACK

(Status)

/AS

/WR

AD15-AD0

/TxREQ

/WAIT//RDY

(Wait)

/WAIT//RDY

(Ready)

42 43

Figure 88. Multiplexed /WR Write Cycle

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/CS

46 47

48 49

2120

2322

S//D, D//C

R//W

/DS

AD15-AD0

/RxREQ

/WAIT//RDY

(Wait)

/WAIT//RDY

(Ready)

108

911

116 79

5150

/INTACK

(Status)

Figure 89. Non-Multiplexed /DS Read Cycle

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AC CHARACTERISTICS

Timing Diagrams (Continued)

/CS

46 47

48 49

2120

2726

S//D, D//C

R//W

/DS

AD15-AD0

/TxREQ

/WAIT//RDY

(Wait)

/WAIT//RDY

(Ready)

116

5150

/INTACK

(Status)

24 25

Figure 90. Non-Multiplexed /DS Write Cycle

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/CS

S//D, D//C

/RD

AD15-AD0

/RxREQ

/WAIT//RDY

(Wait)

/WAIT//RDY

(Ready)

119

/INTACK

(Status)

33 35

52 53

5756

Figure 91. Non-Multiplexed /RD Read Cycle

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AC CHARACTERISTICS

Timing Diagrams (Continued)

/CS

118

S//D, D//C

/WR

AD15-AD0

/TxREQ

/WAIT//RDY

(Wait)

/WAIT//RDY

(Ready)

117

/INTACK

(Status)

58 59

6362

38 39

Figure 92. Non-Multiplexed /WR Write Cycle

100

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/AS

/WAIT//RDY

(Ready)

/WAIT//RDY

(Wait)

2 76

87 88

/INTACK

(Status)

/DS

AD15-AD0

IEI

IEO

/INT

83 84

Figure 93. Multiplexed /DS Interrupt Acknowledge Cycle

101

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AC CHARACTERISTICS

Timing Diagrams (Continued)

/AS

/WAIT//RDY

(Ready)

/WAIT//RDY

(Wait)

23130

95 88

/INTACK

(Status)

/RD

AD15-AD0

IEI

IEO

/INT

83 84

Figure 94. Multiplexed /RD Interrupt Acknowledge Cycle

102

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Figure 95. Multiplexed Pulsed Interrupt Acknowledge Cycle

/AS

/WAIT//RDY

(Ready)

/WAIT//RDY

(Wait)

110 88

/INTACK

(Pulsed)

AD15-AD0

IEI

IEO

/INT

101

100

107

103

106

104

109

108

105

102

103

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AC CHARACTERISTICS

Timing Diagrams (Continued)

/INTACK

(Status)

/WAIT//RDY

(Ready)

/WAIT//RDY

(Wait)

87 88

/DS

AD15-AD0

IEI

IEO

/INT

111

Figure 96. Non-Multiplexed /DS Interrupt Acknowledge Cycle

104

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/INTACK

(Status)

/WAIT//RDY

(Ready)

/WAIT//RDY

(Wait)

95 88

/RD

AD15-AD0

IEI

IEO

/INT

111

Figure 97. Non-Multiplexed /RD Pulsed Interrupt Acknowledge Cycle

105

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AC CHARACTERISTICS

Timing Diagrams (Continued)

/WAIT//RDY

(Ready)

/WAIT//RDY

(Wait)

/INTACK

(Pulsed)

AD15-AD0

IEI

IEO

/INT

101100

103

106

104

108

105

102107 79

110

109

Figure 98. Non-Multiplexed Pulsed Interrupt Acknowledge Cycle

106

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/WAIT//RDY

(Ready)

/WAIT//RDY

(Wait)

/INTACK

(2-Pulse)

AD15-AD0

IEI

IEO

/INT

83 105

109

103

108

102

101

104

106

110

107

100

9796

299

1 1

9998

/AS

Figure 99. Multiplexed Double-Pulse Intack Cycle

107

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AC CHARACTERISTICS

Timing Diagrams (Continued)

/WAIT//RDY

(Ready)

/WAIT//RDY

(Wait)

/INTACK

(2-Pulse)

AD15-AD0

IEI

IEO

/INT

83 105

109

103

108

102

101

104

106

110

79107

100

9796

Figure 100. Non-Multiplexed Double-Pulse Intack Cycle

108

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CLK

/UAS

171

/AS

171

/DS

171

R//W

171

/RD

171

/WR

171

S//D, D//C

171

AD15-AD0

148

/BUSREQ

170

/BIN

172 173 172 173

Figure 101. DMA Start-Up

109

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AC CHARACTERISTICS

Timing Diagrams (Continued)

Figure 102. Memory Read

CLK

/UAS

/AS

/DS

R//W

/RD

S//D, D//C

AD15-AD0

/WAIT//RDY

(Wait)

/WAIT//RDY

(Ready)

/BIN

120

125 127

126

128

129

130

131

132

137

138

144

149 150 151 152

148 145 146

147

153

155

172 173

156

154

139 141

140

143142

134

133

135 136

121

122

/ABORT

168 169

123

124

110

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Figure 103. Memory Write

CLK

/UAS

/AS

/DS

R//W

/WR

S//D, D//C

AD15-AD0

/WAIT//RDY

(Ready)

/WAIT//RDY

(Wait)

/BIN

120

125 127

126

128

129

130

137

144

149 150 151

145 145

153

155

172 173

156

154

121

122

159 161

134

160

134

158

163

166 166

164

165

162

152

145 157

123

124

/ABORT

168 169

111

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AC CHARACTERISTICS

Timing Diagrams (Continued)

CLK

/UAS

167

/AS

/DS

R//W

/RD

/WR

S//D, D//C

AD15-AD0

167

147

Figure 104. Bus Release

112

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CLK

/BUSREQ

/BIN

/BOUT

174

175

176

Figure 105. Request Timing

113

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AC CHARACTERISTICS

Timing Table

No Symbol Parameter Min Max Units Note

1 Tcyc Bus Cycle Time 160 ns

2 TwASl /AS Low Width 40 ns

3 TwASh /AS High Width 90 ns

4 TwDSl /DS Low Width 70 ns

5 TwDSh /DS High Width 60 ns

6 TdAS(DS) /AS Rise to /DS Fall Delay Time 5 ns

7 TdDS(AS) /DS Rise to /AS Fall Delay Time 5 ns

8 TdDS(DRa) /DS Fall to Data Active Delay 0 ns

9 TdDS(DRv) /DS Fall to Data Valid Delay 85 ns

10 TdDS(DRn) /DS Rise to Data Not Valid Delay 0 ns

11 TdDS(DRz) /DS Rise to Data Float Delay 20 ns

12 TsCS(AS) /CS to /AS Rise Setup Time 15 ns

13 ThCS(AS) /CS to /AS Rise Hold Time 5 ns

14 TsADD(AS) Direct Address to /AS Rise Setup Time 15 ns [1]

15 ThADD(AS) Direct Address to /AS Rise Hold Time 5 ns [1]

16 TsSIA(AS) Status /INTACK to /AS Rise Setup Time 15 ns

17 ThSIA(AS) Status /INTACK to /AS Rise Hold Time 5 ns

18 TsAD(AS) Address to /AS Rise Setup Time 15 ns

19 ThAD(AS) Address to /AS Rise Hold Time 5 ns

20 TsRW(DS) R//W to /DS Fall Setup Time 0 ns

21 ThRW(DS) R//W to /DS Fall Hold Time 25 ns

22 TsDSf(RRQ) /DS Fall to /RxREQ Inactive Delay 60 ns [4]

23 TdDSr(RRQ) /DS Rise to /RxREQ Active Delay 0 ns

24 TsDW(DS) Write Data to /DS Rise Setup Time 30 ns

25 ThDW(DS) Write Data to DS Rise Hold Time 0 ns

26 TdDSf(TRQ) /DS Fall to /TxREQ Inactive Delay 60 ns [5]

27 TdDSr(TRQ) /DS Rise to /TxREQ Active Delay 0 ns

28 TwRDl /RD Low Width 70 ns

29 TwRDh /RD High Width 60 ns

30 TdAS(RD) /AS Rise to /RD Fall Delay Time 5 ns

31 TdRD(AS) /RD Rise to /AS Fall Delay Time 5 ns

32 TdRD(DRa) /RD Fall to Data Active Delay 0 ns

33 TdRD(DRv) /RD Fall to Data Valid Delay 85 ns

34 TdRD(DRn) /RD Rise to Data Not Valid Delay 0 ns

35 TdRD(DRz) /RD Rise to Data Float Delay 20 ns

36 TdRDf(RRQ) /RD Fall to /RxREQ Inactive Delay 60 ns [4]

37 TdRDr(RRQ) /RD Rise to /RxREQ Active Delay 0 ns

38 TwWRl /WR Low Width 70 ns

39 TwWRh /WR High Width 60 ns

40 TdAS(WR) /AS Rise to /WR Fall Delay Time 5 ns

41 TdWR(AS) /WR Rise to /AS Fall Delay Time 5 ns

42 TsDW(WR) Write Data to /WR Rise Setup Time 30 ns

43 ThDW(WR) Write Data to /WR Rise Hold Time 0 ns

44 TdWRf(TRQ) /WR Fall to /TxREQ Inactive Delay 60 ns [5]

114

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No Symbol Parameter Min Max Units Note

45 TdWRr(TRQ) /WR Rise to /TxREQ Active Delay 0 ns

46 TsCS(DS) /CS to /DS Fall Setup Time 0 ns [2]

47 ThCS(DS) /CS to /DS Fall Hold Time 25 ns [2]

48 TsADD(DS) Direct Address to /DS Fall Setup Time 5 ns [1,2]

49 ThADD(DS) Direct Address to /DS Fall Hold Time 25 ns [1,2]

50 TsSIA(DS) Status /INTACK to /DS Fall Setup time 5 ns [2]

51 ThSIA(DS) Status /INTACK to /DS Fall Hold Time 25 ns [2]

52 TsCS(RD) /CS to /RD Fall Setup Time 0 ns [2]

53 ThCS(RD) /CS to /RD Fall Hold Time 25 ns [2]

54 TsADD(RD) Direct Address to /RD Fall Setup Time 5 ns [1,2]

55 ThADD(RD) Direct Address to /RD Fall Hold Time 25 ns [1,2]

56 TsSIA(RD) Status /INTACK to /RD Fall Setup Time 5 ns [2]

57 ThSIA(RD) Status /INTACK to /RD Fall Hold Time 25 ns [2]

58 TsCS(WR) /CS to /WR Fall Setup Time 0 ns [2]

59 ThCS(WR) /CS to /WR Fall Hold Time 25 ns [2]

60 TsADD(WR) Direct Address to /WR Fall Setup Time 5 ns [1,2]

61 ThADD(WR) Direct Address to /WR Fall Hold Time 25 ns [1,2]

62 TsSIA(WR) Status /INTACK to /WR Fall Setup Time 5 ns [2]

63 ThSIA(WR) Status /INTACK to /WR Fall Hold Time 25 ns [2]

78 TdDSf(RDY) /DS Fall (Intack) to /RDY Fall Delay 200 ns

79 TdRDY(DRv) /RDY Fall to Data Valid Delay 40 ns

80 TdDSr(RDY) /DS Rise to /RDY Rise Delay 40 ns

81 TsIEI(DSI) IEI to /DS Fall (Intack) Setup Time 60 ns

82 ThIEI(DSI) IEI to /DS Rise (Intack) Hold Time 0 ns

83 TdIEI(IEO) IEI to IEO Delay 60 ns

84 TdAS(IEO) /AS Rise (Intack) to IEO Delay 60 ns

85 TdDSI(INT) /DS Fall to /INT Inactive Delay 200 ns

86 TdDSI(Wf) /DS Fall (Intack) to /WAIT Fall Delay 40 ns

87 TdDSI(Wr) /DS Fall (Intack) to /WAIT Rise Delay 200 ns

88 TdW(DRv) /WAIT Rise to Data Valid Delay 40 ns

89 TdRDf(RDY) /RD Fall (Intack) to /RDY Fall Delay 200 ns

90 TdRDr(RDY) /RD Rise to /RDY Rise Delay 40 ns

91 TsIEI(RDI) IEI to /RD Fall (Intack) Setup Time 60 ns

92 ThIEI(RDI) IEI to /RD Rise (Intack) Hold Time 0 ns

93 TdRDI(INT) /RD Fall (Intack) to /INT Inactive Delay 200 ns

94 TdRDI(Wf) /RD Fall (Intack) to /WAIT Fall Delay 40 ns

95 TdRDI(Wr) /RD Fall (Intack) to /WAIT Rise Delay 200 ns

96 TwPIAl Pulsed /INTACK Low Width 70 ns

97 TwPIAh Pulsed /INTACK High Width 60 ns

98 TdAS(PIA) /AS Rise to Pulsed /INTACK Fall Delay Time 5 ns

99 TdPIA(AS) Pulsed /INTACK Rise to /AS Fall Delay Time 5 ns

100 TdPIA(DRa) Pulsed /INTACK Fall to Data Active Delay 0 ns

101 TdPIA(DRn) Pulsed /INTACK Rise to Data Not Valid Delay 0 ns

102 TdPIA(DRz) Pulsed /INTACK Rise to Data Float Delay 20 ns

115

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AC CHARACTERISTICS (Continued)

Timing Table

No Symbol Parameter Min Max Units Note

103 TsIEI(PIA) IEI to Pulsed /INTACK Fall Setup Time 10 ns

104 ThIEI(PIA) IEI to Pulsed /INTACK Rise Hold Time 0 ns

105 TdPIA(IEO) Pulsed /INTACK Fall to IEO Delay 60 ns

106 TdPIA(INT) Pulsed /INTACK Fall to /INT Inactive Delay 200 ns

107 TdPIAf(RDY) Pulsed /INTACK Fall to /RDY Fall Delay 200 ns

108 TdPIAr(RDY) Pulsed /INTACK Rise to /RDY Rise Delay 40 ns

109 TdPIA(Wf) Pulsed /INTACK Fall to /WAIT Fall Delay 40 ns

110 TdPIA(Wr) Pulsed /INTACK Fall to /WAIT Rise Delay 200 ns

111 TdSIA(INT) Status /INTACK Fall to IEO Inactive Delay 200 ns [2]

112 TwSTBh /Strobe High Width 50 ns [3]

113 TwRESl /RESET Low Width 170 ns

114 TwRESh /RESET High Width 60 ns

115 TdRES(STB) /RESET Rise to /STB Fall 60 ns [3]

116 TdDSf(RDY) /DS Fall to /RDY Fall Delay 50 ns

117 TdWRf(RDY) /WR Fall to /RDY Fall Delay 50 ns

118 TdWRr(RDY) /WR Rise to /RDY Rise Delay 40 ns

119 TdRDf(RDY) /RD Fall to /RDY Fall Delay 50 ns

120 TwCLKl CLK Low Width 25 ns

121a TwCLKh CLK High Width 25 ns

121b TwCLKh CLK High Width (Linked List Mode) 35 ns [12]

122a TcCLK CLK Cycle Time 50 ns

122b TcCLK CLK Cycle Time (Linked List Mode) 60 ns [12]

123 TfCLK CLK Fall Time 5 ns

124 TrCLK CLK Rise Time 5 ns

125 TdCLKr (UAS) CLK Rise to /UAS Fall Delay 30 ns [6]

126 TwUASl /UAS Low Width 25 ns [6,7,13]

127 TdCLKf(UAS) CLK Fall to /UAS Rise Delay 30 ns [6]

128 TdCLKr(AS) CLK Rise to /AS Fall Delay 30 ns [6]

129 TwASl /AS Low Width 25 ns [6,7,13]

130 TdCLKf(AS) CLK Fall to /AS Rise Delay 30 ns [6]

131 TdAS(DSr) /AS Rise to /DS Fall (Read) Delay 25 ns [6,8]

132 TdCLKr(DS) CLK Rise to /DS Delay 30 ns [6]

133 TwDSlr /DS (Read) Low Width 75 ns [6,9,13]

134 TdCLKf(DS) CLK Fall to /DS Delay 30 ns [6]

135 TsDR(DS) Read Data to /DS Rise Setup Time 30 ns [6]

136 ThDR(DS) Read Data to /DS Rise Hold Time 0 ns [6]

137 TdCLK(RW) CLK Rise to R//W Delay 30 ns [6]

138 TdAS(RD) /AS Rise to /RD Fall Delay 25 ns [6,8]

139 TdCLKr(RD) CLK Rise to /RD Delay 30 ns [6]

140 TwRDl /RD Low Width 75 ns [6,9]

141 TdCLKf(RD) CLK Fall to /RD Delay 30 ns [6]

142 TsDR(RD) Read Data to /RD Rise Setup Time 30 ns [6]

143 ThDR(RD) Read Data to /RD Rise Hold Time 0 ns [6]

144 TdCLK(ADD) CLK Rise to Direct Address Delay 30 ns [1,6]

145 TdCLK(AD) CLK Rise to Address Delay TdCLKf(DS) 35 ns [6]

146 ThAD(PC) Address to CLK Rise Hold Time 0 ns [6]

116

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No Symbol Parameter Min Max Units Note

147 TdCLK(ADz) CLK Rise to Address Float Delay 35 ns [6]

148 TdCLK(ADa) CLK Rise to Address Active Delay 35 ns [6]

149 TsAD(UAS) Address to /UAS Rise Setup Time 10 ns [6]

150 ThAD(UAS) Address to /UAS Rise Hold Time 10 ns [6]

151 TsAD(AS) Address to /AS Rise Setup Time 10 ns [6]

152 ThAD(AS) Address to /AS Rise Hold Time 10 ns [6]

153 TsW(CLK) /WAIT to CLK Fall Setup Time 10 ns [6]

154 ThW(CLK) /WAIT to CLK Fall Hold Time 15 ns [6]

155 TsRDY(CLK) /READY to CLK Fall Setup Time 10 ns [6]

156 ThRDY(CLK) /READY to CLK Fall Hold Time 15 ns [6]

157 ThDW(CLK) Write Data to CLK Rise Hold Time 0 ns [6]

158 TdAS(DSw) /AS Rise to /DS Fall (Write) Delay 40 ns [6,10,13]

159 TsDW(DS) Write Data to /DS Fall Setup Time 25 ns [6,7,13]

160 TwDSlw /DS (Write) Low Width 45 ns [6,11,13]

161 ThDW(DS) Write Data to /DS Rise Hold Time 25 ns [6,8]

162 TdAS(WR) /AS Rise to /WR Fall Delay 40 ns [6,10,13]

163 TsDW(WR) Write Data to /WR Fall Setup Time 25 ns [6,7,13]

164 TwWRl /WR Low Width 45 ns [6,11,13]

165 ThDW(WR) Write Data to /WR Rise Hold Time 25 ns [6,8]

166 TdCLK(WR) CLK Fall to /WR Delay 30 ns [6]

167 TdCLK(BUSz) CLK Rise to Bus Float Delay 30 ns [6]

168 TsABT(CLK) /ABORT to CLK Rise Setup Time 20 ns [6]

169 ThABT(CLK) /ABORT to CLK Rise Hold Time 15 ns [6]

170 TdCLK(BRQ) CLK Rise to /BUSREQ Delay 30 ns [6]

171 TdCLK(BUSa) CLK Rise to Bus Active Delay 30 ns [6]

172 TsBIN(CLK) /BIN to CLK Rise Setup Time 20 ns [6]

173 ThBIN(CLK) /BIN to CLK Rise Hold Time 15 ns [6]

174 TsBRQ(CLK) /BUSREQ to CLK Rise Setup Time 25 ns [6]

175 ThBRQ(CLK) /BUSREQ to CLK Rise Hold Time 0 ns [6]

176 TdBIN(BOT) /BIN to /BOUT Delay 60 ns

Notes:

AC Test Conditions:

VCC = 5V ±5% unless otherwise specified,

over specified temperature range.

VIH = 2.0V VOH = 2.0V

VIL = 0.8V VOL = 0.8V

Float = +0.5V

[1] Direct Address is any of S//D, D//C or AD15-AD8 used

as an address bus.

[2] The parameter applies only when /AS is not present.

[3] Strobe is any of /DS, /RD, /WR or Pulsed /INTACK.

[4] Parameter applies only if read empties the receive FIFO.

[5] Parameter applies only if write fills the transmit FIFO.

[6] Parameter applies only while the IUSC is bus master.

[7] Parameter is clock-cycle dependent, TwCLKh + TfCLK – 5.

[8] Parameter is clock-cycle dependent, TwCLKl + TrCLK –5

[9] Parameter is clock-cycle dependent,

TcCLK + TwCLKh + TfCLK –5.

[10] Parameter is clock-cycle dependent, TcCLK –10.

[11] Parameter is clock-cycle dependent, TcCLK –5.

[12] Clock cycle parameters TwCLKh and TcCLK have unique

values for Linked List Mode. In Linked List Mode, the system clock

cycle is extended to 60 ns, and the system clock High pulse width

is extended to 35 ns. This is due to the internal timing paths unique

to the Linked List Mode. The transmit and receive bit rates are not

affected.

[13] For Linked List Mode, the minimum for these values should be

calculated using TwCLKh = 35 ns and TcCLK = 60 ns.

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/DCD as

/SYNC

External

/TxC

/RxC, /TxC

Receive

RxD

/TxC, /RxC

Transmit

TxD

/RxC

1 3

5 6

910

1515

1616

/CTS,

/DCD

/DCD as

/SYNC

Input

Figure 106. General Timing

AC CHARACTERISTICS

General Timing Diagram

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AC CHARACTERISTICS

General Timing Table

No Symbol Parameter Min Max Units Note

1 TsRxD(RxCr) RxD to /RxC Rise Setup Time (x1 Mode) 0 ns [1]

2 ThRxD(RxCr) RxD to /RxC Rise Hold Time (x1 Mode) 20 ns [1]

3 TsRxd(RxCf) RxD to /RxC Fall Setup Time (x1 Mode) 0 ns [1,3]

4 ThRxD(RxCf) RxD to /RxC Fall Hold Time (x1 Mode) 20 ns [1,3]

5 TsSy(RxC) /DCD as /SYNC to /RxC Rise Setup Time 0 ns [1]

6 ThSy(RxC) /DCD as /SYNC to /RxC Rise Hold Time (x1 Mode) 20 ns [1]

7 TdTxCf(TxD) /TxC Fall to TxD Delay 25 ns [2]

8 TdTxCr(TxD) /TxC Rise to TxD Delay 25 ns [2,3]

9 TwRxCh /RxC High Width 20 ns

10 TwRxCl /RxC Low Width 20 ns

11 TcRxC /RxC Cycle Time 50 ns

12 TwTxCh /TxC High Width 20 ns

13 TwTxCl /TxC Low Width 20 ns

14 TcTxC /TxC Cycle Time 50 ns

15 TwExT /DCD or /CTS Pulse Width 35 ns

16 TWSY /DCD as /SYNC Input Pulse Width 35 ns

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AC CHARACTERISTICS

System Timing Diagram

/RxC, /TxC

Receive

/RxREQ

Request

/RxC as

Receiver

Output

/INT

/RxC, /TxC

Transmit

/TxREQ

/TxC as

Transmitter

Output

/INT

/CTS, /DCD,

/TxREQ,

/RxREQ

/INT

Figure 107. Z16C32 System Timing

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AC CHARACTERISTICS

System Timing Table

No Symbol Parameter Min Max Units Note

1 TdRxC(REQ) /RxC Rise to /RxREQ Valid Delay 50 ns [2]

2 TdRxC(RxC) /TxC Rise to /RxC as Receiver Output Valid Delay 50 ns [2]

3 TdRxC(INT) /RxC Rise to /INT Valid Delay 50 ns [2]

4 TdTxC(REQ) /TxC Fall to /TxREQ Valid Delay 50 ns [2]

5 TdTxC(TxC) /RxC Fall to /TxC as transmitter Output Valid Delay 50 ns

6 TdTxC(INT) /TxC Fall to /INT Valid Delay 50 ns [2]

7 TdEXT(INT) /CTS, /DCD, /TxREQ, /RxREQ transition

to /INT Valid Delay 50 ns

Notes:

[1] /RxC is /RxC or /TxC, whichever is supplying the receive clock.

[2] /TxC is /TxC or /RxC, whichever is supplying the transmit clock.

[3] Parameter applies only to FM encoding/decoding.

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PACKAGE INFORMATION

68-Pin PLCC Package Diagram

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ORDERING INFORMATION

Z16C32 IUSC

20 MHz

68-Pin PLCC

Z16C3220VSC

For fast results, contact your local Zilog sales office for assistance in ordering the part desired.

Package

V = Plastic Chip Carrier

Temperature

S = 0°C to 70°C

Speed

20 = 20 MHz

Environmental

C = Plastic Standard

Example:

Z 16C32 20 V S C is a Z16C32, 20 MHz, PLCC, 0°C to +70°C, Plastic Standard Flow

Environmental Flow

Temperature

Package

Speed

Product Number

Zilog Prefix

Zilog’s products are not authorized for use as critical compo-

nents in life support devices or systems unless a specific written

agreement pertaining to such intended use is executed between

the customer and Zilog prior to use. Life support devices or

systems are those which are intended for surgical implantation

into the body, or which sustains life whose failure to perform,

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result in

significant injury to the user.

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Campbell, CA 95008-6600

Telephone (408) 370-8000

Telex 910-338-7621

FAX 408 370-8056

Internet: http://www.zilog.com

may be copied or reproduced in any form or by any means

without the prior written consent of Zilog, Inc. The information in

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by Zilog, Inc. are covered by warranty and patent indemnification

provisions appearing in Zilog, Inc. Terms and Conditions of Sale

only. Zilog, Inc. makes no warranty, express, statutory, implied or

by description, regarding the information set forth herein or

regarding the freedom of the described devices from intellectual

property infringement. Zilog, Inc. makes no warranty of mer-

chantability or fitness for any purpose. Zilog, Inc. shall not be

responsible for any errors that may appear in this document.

Zilog, Inc. makes no commitment to update or keep current the

information contained in this document.