TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 Dual Synchronous, Step-Down Controller with 5-V and 3.3-V LDOs Check for Samples: TPS51225, TPS51225B, TPS51225C FEATURES APPLICATIONS 1 * * Input Voltage Range: 5.5 V to 24 V * Notebook Computers Output Voltages: 5 V and 3.3 V (Adjustable * Netbook, Tablet Computers Range 10%) DESCRIPTION Built-in, 100-mA, 5-V and 3.3-V LDOs The TPS51225/B/C is a cost-effective, dualClock Output for Charge-Pump synchronous buck controller targeted for notebook 1% Reference Accuracy system-power supply solutions. It provides 5-V and Adaptive On-time D-CAPTM Mode Control 3.3-V LDOs and requires few external components. The 260-kHz VCLK output can be used to drive an Architecture with 300kHz/355kHz Frequency external charge pump, generating gate drive voltage Setting for the load switches without reducing the main Auto-skip Light Load Operation (TPS51225/C) converter efficiency. The TPS51225/B/C supports OOA Light Load Operation (TPS51225B) high efficiency, fast transient response and provides a combined power-good signal. Adaptive on-time, DInternal 0.8-ms Voltage Servo Soft-Start CAPTM control provides convenient and efficient Low-Side RDS(on) Current Sensing Scheme with operation. The device operates with supply input 4500 ppm/C Temperature Coefficient voltage ranging from 5.5 V to 24 V and supports Built-in Output Discharge Function output voltages of 5.0 V and 3.3 V. The TPS51225/B/C is available in a 20-pin, 3 mm x 3 Separate Enable Input for Switchers mm, QFN package and is specified from -40C to (TPS51225/B/C) 85C. Dedicated OC Setting Terminals Power Good Indicator OVP/UVP/OCP Protection Non-latch UVLO/OTP Protection 20-Pin, 3 mm x 3 mm, QFN (RUK) ORDERING INFORMATION (1) 2 * * * * * * * * * * * * * * * ORDERABLE DEVICE NUMBER TPS51225RUKR TPS51225RUKT TPS51225BRUKR TPS51225BRUKT TPS51225CRUKR TPS51225CRUKT (1) ENABLE FUNCTION SKIP MODE ALWAYS ON-LDO EN1/ EN2 Auto-skip VREG3 EN1/ EN2 OOA VREG3 EN1/ EN2 Auto-skip VREG3 & VREG5 PACKAGE PLASTIC Quad Flat Pack (20 pin QFN) OUTPUT SUPPLY QUANTITY Tape and Reel 3000 Mini reel 250 Tape and Reel 3000 Mini reel 250 Tape and Reel 3000 Mini reel 250 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP, Out-of-Audio are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012, Texas Instruments Incorporated TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL APPLICATION DIAGRAM (TPS51225/TPS51225B) VIN 5.5 V to 24 V TPS51225 TPS51225 B VIN VOUT 5V VBST1 VBST2 DRVH1 DRVH 2 SW1 VOUT 3.3 V SW2 DRVL1 DRVL2 VO1 VFB1 VFB2 CS1 CS2 VCLK VOUT 15 V EN-5V PGOOD EN1 5V PGOOD EN2 VREG5 EN 3.3 V VREG3 3.3-V Always ON 1 mF 1 mF UDG-11182 TYPICAL APPLICATION DIAGRAM (TPS51225C) VIN 5.5 V to 24 V TPS51225C VIN VOUT 5V VBST1 VBST2 DRVH1 DRVH 2 SW1 DRVL1 VOUT 3.3 V SW2 DRVL2 VO1 VFB1 EN 5 V CS1 CS2 EN1 PGOOD VCLK VOUT 15 V 5V Always ON VREG5 1 mF VFB2 PGOOD EN2 EN 3.3 V VREG3 3.3-V Always ON 1 mF UDG-12001 2 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE Input voltage (2) MIN MAX VBST1, VBST2 -0.3 32 VBST1, VBST2 (3) -0.3 6 SW1, SW2 -6.0 26 VIN -0.3 26 EN1, EN2 -0.3 6 VFB1, VFB2 -0.3 3.6 VO1 -0.3 6 DRVH1, DRVH2 -6.0 32 -0.3 6 DRVH1, DRVH2 (3) DRVH1, DRVH2 Output voltage (2) Electrostatic discharge (3) -2.5 6 DRVL1, DRVL2 (pulse width < 20 ns) -0.3 6 DRVL1, DRVL2 (pulse width < 20 ns) -2.5 6 PGOOD, VCLK, VREG5 -0.3 6 VREG3, CS1, CS2 -0.3 3.6 HBM QSS 009-105 (JESD22-A114A) 2 CDM QSS 009-147 (JESD22-C101B.01) 1 Junction temperature, TJ 150 Storage temperature, TST -55 (1) (2) (3) UNIT V V kV C 150 C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted Voltage values are with respect to SW terminals. THERMAL INFORMATION THERMAL METRIC TPS51225 TPS51225B TPS51225C (1) UNITS 20-PIN RUK JA Junction-to-ambient thermal resistance 94.1 JCtop Junction-to-case (top) thermal resistance 58.1 JB Junction-to-board thermal resistance 64.3 JT Junction-to-top characterization parameter 31.8 JB Junction-to-board characterization parameter 58.0 JCbot Junction-to-case (bottom) thermal resistance 5.9 (1) C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 3 TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) Supply voltage Input voltage (1) Output voltage (1) VIN 4 TYP MAX 5.5 24 VBST1, VBST2 -0.1 30 VBST1, VBST2 (2) -0.1 5.5 SW1, SW2 -5.5 24 EN1, EN2 -0.1 5.5 VFB1, VFB2 -0.1 3.5 VO1 -0.1 5.5 DRVH1, DRVH2 -5.5 30 DRVH1, DRVH2 (2) -0.1 5.5 DRVL1, DRVL2 -0.1 5.5 PGOOD, VCLK, VREG5 -0.1 5.5 VREG3, CS1, CS2 -0.1 3.5 -40 85 Operating free-air temperature, TA (1) (2) MIN UNIT V V C All voltage values are with respect to the network ground terminal unless otherwise noted. Voltage values are with respect to the SW terminal. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VVIN= 12 V, VVO1= 5 V, VVFB1= VVFB2= 2 V, VEN1= VEN2= 3.3 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT IVIN1 VIN supply current-1 TA = 25C, No load, VVO1=0 V IVIN2 VIN supply current-2 TA = 25C, No load IVO1 VO1 supply current TA = 25C, No load, VVFB1= VVFB2=2.05 V IVIN(STBY) VIN stand-by current TA = 25C, No load, VVO1= 0 V, VEN1= VEN2= 0 V IVIN(STBY) VIN stand-by current TA = 25C, No load, VVO1=0 V, VEN1=VEN2=0V (TPS51225C) TPS51225 TPS51225B 860 A 30 A 900 A 95 A 180 A INTERNAL REFERENCE VFBx TA = 25C VFB regulation voltage 1.99 2.00 2.01 V 1.98 2.00 2.02 V VREG5 OUTPUT TA = 25C, No load, VVO1= 0 V VVREG5 VREG5 output voltage 4.9 5.0 5.1 VVIN> 7 V , VVO1= 0 V, IVREG5< 100 mA 4.85 5.00 5.10 VVIN > 5.5 V , VVO1= 0 V, IVREG5< 35 mA 4.85 5.00 5.10 100 150 mA 1.8 IVREG5 VREG5 current limit VVO1= 0 V, VVREG5= 4.5 V, VVIN= 7 V RV5SW 5-V switch resistance TA = 25C, VVO1= 5 V, IVREG5= 50 mA V VREG3 OUTPUT VVREG3 VREG3 output voltage IVREG3 VREG3 current limit TA = 25C, No load, VVO1= 0 V 3.267 3.300 3.333 VVIN > 7 V , VVO1= 0 V, IVREG3< 100 mA 3.217 3.300 3.383 5.5 V < VVIN , VVO1= 0 V, IVREG3< 35 mA 3.234 3.300 3.366 0C TA 85C, VVIN > 5.5 V, VVO1= 0 V, IVREG3< 35 mA 3.333 3.267 3.300 VVO1= 0 V, VVREG3= 3.0 V, VVIN= 7 V 100 150 V mA DUTY CYCLE and FREQUENCY CONTROL fsw1 CH1 frequency (1) TA = 25C, VVIN= 20 V 240 300 360 kHz fSW2 CH2 frequency (1) TA = 25C, VVIN= 20 V 280 355 430 kHz TOFF(MIN) Minimum off-time TA = 25C 200 300 500 ns MOSFET DRIVERS Source, (VVBST - VDRVH) = 0.25 V, (VVBST - VSW) = 5 V 3.0 Sink, (VDRVH - VSW) = 0.25 V, (VVBST - VSW) = 5 V 1.9 Source, (VVREG5 - VDRVL) = 0.25 V, VVREG5 = 5 V 3.0 Sink, VDRVL = 0.25 V, VVREG5= 5 V 0.9 DRVH-off to DRVL-on 12 DRVL-off to DRVH-on 20 Boost switch on-resistance TA = 25C, IVBST = 10 mA 13 VBST leakage current TA = 25C RDRVH DRVH resistance RDRVL DRVL resistance tD Dead time ns INTERNAL BOOT STRAP SWITCH RVBST (ON) IVBSTLK 1 A CLOCK OUTPUT RVCLK (PU) VCLK on-resistance (pull-up) TA = 25C 10 RVCLK (PD) VCLK on-resistance (pull-down) TA = 25C 10 Clock frequency TA = 25C 260 fCLK (1) kHz Ensured by design. Not production tested. Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 5 TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VVIN= 12 V, VVO1= 5 V, VVFB1= VVFB2= 2 V, VEN1= VEN2= 3.3 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT OUTPUT DISCHARGE RDIS1 CH1 discharge resistance TA = 25C, VVO1 = 0.5 V VEN1 = VEN2 = 0 V 35 RDIS2 CH2 discharge resistance TA = 25C, VSW2 = 0.5 V VEN1 = VEN2 = 0 V 75 RDIS2 CH2 discharge resistance TA = 25C, VSW2 = 0.5 V, VEN1 = VEN2 = 0 V (TPS51225C) 70 SOFT START OPERATION tSS Soft-start time From ENx="Hi" and VVREG5 > VUVLO5 to VOUT = 95% 0.91 ms tSSRAMP Soft-start time (ramp-up) VOUT= 0% to VOUT = 95%, VVREG5 = 5 V 0.78 ms POWER GOOD Lower (rising edge of PG-in) VPGTH 92.5% Hysteresis PG threshold 95.0% Upper (rising edge of PG-out) 107.5% 110.0% 112.5% Hysteresis 5% 6.5 IPGMAX PG sink current VPGOOD = 0.5 V IPGLK PG leak current VPGOOD = 5.5 V tPGDEL PG delay From PG lower threshold (95%=typ) to PG flag high 97.5% 5% mA 1 0.7 A ms CURRENT SENSING ICS CS source current TA = 25C, VCS= 0.4 V TCCS CS current temperature coefficient (1) On the basis of 25C VCS CS Current limit setting range VZC Zero cross detection offset 9 10 11 4500 0.2 TA = 25C -1 1 A ppm/C 2 V 3 mV LOGIC THRESHOLD VENX(ON) EN threshold high-level SMPS on level VENX(OFF) EN threshold low-level SMPS off level 0.3 1.6 IEN EN input current VENx= 3.3 V -1 V V 1 A OUTPUT OVERVOLTAGE PROTECTION VOVP OVP trip threshold tOVPDLY OVP propagation delay 112.5% 115.0% 117.5% TA = 25C 0.5 s OUTPUT UNDERVOLTAGE PROTECTION VUVP UVP trip Threshold tUVPDLY UVP prop delay tUVPENDLY UVP enable delay 55% 60% 65% 250 s From ENx ="Hi", VVREG5 = 5 V 1.35 ms Wake up 4.58 V 0.5 V 4.38 V 0.4 V Wake up 3.15 V Hysteresis 0.15 V Shutdown temperature 155 UVLO VUVL0VIN VUVLO5 VUVLO3 VIN UVLO Threshold Hysteresis Wake up VREG5 UVLO Threshold Hysteresis VREG3 UVLO Threshold OVER TEMPERATURE PROTECTION TOTP (1) 6 OTP threshold (1) Hysteresis 10 C Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 DEVICE INFORMATION 3 VFB2 4 CS2 5 VCLK SW1 VBST1 DRVH1 16 TPS51225 TPS51225B TPS51225C Thermal Pad 6 7 8 9 10 DRVH2 VREG3 17 VBST2 2 18 SW2 VFB1 19 PGOOD 1 20 EN2 CS1 EN1 RUK PACKAGE 20 PINS (TOP VIEW) 15 DRVL1 14 VO1 13 VREG5 12 VIN 11 DRVL2 PIN FUNCTIONS PIN NO. TPS51225 TPS51225B TPS51225C I/O 1 O Sets the channel 1 OCL trip level. CS2 5 O Sets the channel 2OCL trip level. DRVH1 16 O High-side driver output DRVH2 10 O High-side driver output DRVL1 15 O Low-side driver output DRVL2 11 O Low-side driver output EN1 20 I Channel 1 enable. EN2 6 I Channel 2 enable. PGOOD 7 O Power good output flag. Open drain output. Pull up to external rail via a resistor SW1 18 O Switch-node connection. SW2 8 O Switch-node connection. VBST1 17 I VBST2 9 I Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal. VCLK 19 O Clock output for charge pump. VFB1 2 I VFB2 4 I VIN 12 I Power conversion voltage input. Apply the same voltage as drain voltage of high-side MOSFETs of channel 1 and channel 2. VO1 14 I Output voltage input, 5-V input for switch-over. VREG3 3 O 3.3-V LDO output. VREG5 13 O 5-V LDO output. Thermal pad -- -- GND terminal, solder to the ground plane NAME CS1 DESCRIPTION Voltage feedback Input Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 7 TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM (TPS51225/B/C) TPS51225 TPS51225B TPS51225C VIN + + 155C/145C 4.5 V/4.0 V VO1 + VREG5 + + + 2V + VREG3 Osc VCLK EN1 VBST1 EN2 VDRV VIN VDD VO_OK DRVH 1 SW1 DRVL 1 Switcher Controller (CH1) VFB1 CS1 VDD VDRV EN FAULT FAULT REF REF PGOOD PGND GND VIN Switcher Controller (CH2) PGOOD DCHG DCHG VBST2 DRVH 2 EN SW2 DRVL 2 VFB2 GND PGND CS2 PGOOD GND (Thermal Pad ) 8 Submit Documentation Feedback UDG-12002 Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 SWITCHER CONTROLLER BLOCK DIAGRAM TPS51225 TPS51225B TPS51225C VDD VREF -40% + UV VREF +5%/10% + Control Logic + OV + VREF -5%/10% VREF +15% VFB EN REF SS Ramp Comp + + PWM VO_OK VBST SKIP DRVH HS VIN SW XCON OC CS 10 A VDRV + + LS NOC DRVL PGND One-Shot + Discharge GND + ZC DCHG PGOOD PGOOD FAULT UDG-12007 Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 9 TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com DETAILED DESCRIPTION PWM Operations The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports a proprietary D-CAPTM mode. D-CAPTM mode does not require external conpensation circuit and is suitable for low external component count configuration when used with appropriate amount of ESR at the output capacitor(s). At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or enters the ON state. This MOSFET is turned off, or enters the `OFF state, after the internal, one-shot timer expires. The MOSFET is turned on again when the feedback point voltage, VVFB, decreased to match the internal 2-V reference. The inductor current information is also monitored and should be below the overcurrent threshold to initiate this new cycle. By repeating the operation in this manner, the controller regulates the output voltage. The synchronous low-side (rectifying) MOSFET is turned on at the beginning of each OFF state to maintain a minimum of conduction loss. The low-side MOSFET is turned off before the high-side MOSFET turns on at next switching cycle or when inductor current information detects zero level. This enables seamless transition to the reduced frequency operation during light-load conditions so that high efficiency is maintained over a broad range of load current. Adaptive On-Time/ PWM Frequency Control Bacause the TPS51225/B/C does not have a dedicated oscillator for control loop on board, switching cycle is controlled by the adaptive on-time circuit. The on-time is controlled to meet the target switching frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. The target switching frequency is varied according to the input voltage to achieve higher duty operation for lower input voltage application. The switching frequency of CH1 (5-V output) is 300 kHz during continuous conduction mode (CCM) operation when VIN = 20 V. The CH2 (3.3-V output) is 355 kHz during CCM when VIN = 20 V. Light Load Condition in Auto-Skip Operation (TPS51225/C) The TPS51225/C automatically reduces switching frequency during light-load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without an increase in output voltage ripple. A more detailed description of this operation is as follows. As the output current decreases from heavy-load condition, the inductor current is also reduced and eventually approaches valley zero current, which is the boundary between continuous conduction mode and discontinuous conduction mode. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreases, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires the next ON cycle. The ON time is maintained the same as that in the heavy-load condition. In reverse, when the output current increase from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (i.e. the threshold between continuous and discontinuous conduction mode) can be calculated as shown in Equation 1. IOUT(LL ) = (VIN - VOUT ) VOUT 1 2 L fSW VIN where * fSW is the PWM switching frequency (1) Switching frequency versus output current during light-load conditions is a function of inductance (L), input voltage (VIN) and output voltage (VOUT), but it decreases almost proportional to the output current from the IOUT(LL). 10 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 Light-Load Condition in Out-of-AudioTM Operation (TPS51225B) Out-of-AudioTM (OOA) light-load mode is a unique control feature that keeps the switching frequency above acoustic audible frequencies toward a virtual no-load condition. During Out-of-AudioTM operation, the OOA control circuit monitors the states of both MOSFETs and forces them to transition into the ON state if both of MOSFETs are off for more than 40 s. When both high-side and low-side MOSFETs are off for 40 s during a light-load condition, the operation mode is changed to FCCM. This mode change initiates the low-side MOSFET on and pulls down the output voltage. Then, the high-side MOSFET is turned on and stops switching again. Table 1. SKIP Mode Operation (TPS51225/B/C) SKIP MODE OPERATION TPS51225 Auto-skip TPS51225B OOA TPS51225C Auto-skip D-CAPTM Mode From small-signal loop analysis, a buck converter using D-CAPTM mode can be simplified as shown in Figure 1. TPS51225 TPS51225B TPS51225C Switching Modulator VIN DRVH R1 R2 L VFB PWM + + Control Logic and Divider VOUT DRVL IIND IC IOUT VREF ESR R LOAD Voltage Divider VC COUT Output Capacitor UDG-12010 Figure 1. Simplifying the Modulator The output voltage is compared with internal reference voltage after divider resistors, R1 and R2. The PWM comparator determines the timing to turn onthe high-side MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each ON cycle substantially constant. For the loop stability, the 0dB frequency, 0, defined in Equation 2 must be lower than 1/4 of the switching frequency. f 1 SW f0 = 2p ESR COUT 4 (2) As 0 is determined solely by the output capacitor characteristics, the loop stability during D-CAPTM mode is determined by the capacitor chemistry. For example, specialty polymer capacitors have output capacitance in the order of several hundred micro-Farads and ESR in range of 10 milli-ohms. These yield an f0 value on the order of 100 kHz or less and the loop is stable. However, ceramic capacitors have 0 at more than 700 kHz, which is not suitable for this operational mode. Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 11 TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com Enable and Powergood VREG3 is an always-on regulator (TPS51225/B), VREG3/VREG5 are always-on regulators (TPS51225C), when the input voltage is beyond the UVLO threshold it turns ON. VREG5 is turned ON when either EN1 or EN2 enters the ON state. The VCLK signal initiates when EN1 enters the ON state (TPS51225/B/C). Enable states are shown in Table 2 through Table 3. Table 2. Enabling/PGOOD State (TPS51225/B) EN1 EN2 VREG5 VREG3 CH1 (5Vout) CH2 (3.3Vout) VCLK PGOOD OFF OFF OFF ON OFF OFF OFF Low Low ON OFF ON ON ON OFF ON OFF ON ON ON OFF ON OFF Low ON ON ON ON ON ON ON High Table 3. Enabling/PGOOD State (TPS51225C) EN1 EN2 VREG5 VREG3 CH1 (5Vout) CH2 (3.3Vout) VCLK PGOOD OFF OFF ON ON OFF OFF OFF Low ON OFF ON ON ON OFF ON Low OFF ON ON ON OFF ON OFF Low ON ON ON ON ON ON ON High VIN-UVLO_threshold VIN VREG3 EN_threshold EN1 VREG5-UVLO_threshold VREG5 95% of VOUT Soft-Start Time (tSS) Soft-Start Time (tSS(ramp)) 5-V VOUT EN_threshold EN2 95% of Vout 3.3-V VOUT Soft-Start Time (tSS) PGOOD Delay tPGDEL Soft-Start Time (tSS(ramp)) PGOOD UDG-12013 Figure 2. TPS51225 and TPS51225B Timing 12 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 VIN-UVLO_threshold VIN 2.4 V VREG3 VREG5 EN_threshold EN1 95% of VOUT Soft-Start Time (tSS) Soft-Start Time (tSS(ramp)) 5-V VOUT EN_threshold EN2 95% of Vout 3.3-V VOUT Soft-Start Time (tSS) PGOOD Delay tPGDEL Soft-Start Time (tSS(ramp)) PGOOD UDG-12015 Figure 3. TPS51225C Timing Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 13 TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com Soft-Start and Discharge The TPS51225/B/C operates an internal, 0.8-ms, voltage servo soft-start for each channel. When the ENx pin becomes higher than the enable threshold voltage, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintained during start-up. When ENx becomes lower than the lower level of threshold voltage, TPS51225/B/C discharges outputs using internal MOSFETs through VO1 (CH1) and SW2 (CH2). VREG5/VREG3 Linear Regulators There are two sets of 100-mA standby linear regulators which output 5 V and 3.3 V, respectively. The VREG5 pin provides the current for the gate drivers. The VREG3 pin functions as the main power supply for the analog circuitry of the device. VREG3 is an Always ON LDO and TPS51225C has Always ON VREG5. (see ) Add ceramic capacitors with a value of 1 F or larger (X5R grade or better) placed close to the VREG5 and VREG3 pins to stabilize LDOs. The VREG5 pin switchover function is asserted when three conditions are present: * CH1 internal PGOOD is high * CH1 is not in OCL condition * VO1 voltage is higher than VREG5-1V In * * * this switchover condition, three things occur: the internal 5-V, LDO regulator is shut off the VREG5 output is connected to VO1 by internal switchover MOSFET VREG3 input pass is changed from VIN to VO1 VCLK for Charge Pump The 260-kHz VCLK signal can be used in the charge pump circuit. The VCLK signal becomes available when EN1. The VCLK driver is driven by VO1 voltage. In a design that does not require VCLK output, leave the VCLK pin open. Overcurrent Protection TPS51225/B/C has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the inductor current is larger than the overcurrent trip level. In order to provide both good accuracy and cost effective solution, TPS51225/B/C supports temperature compensated MOSFET RDS(on) sensing. The CSx pin should be connected to GND through the CS voltage setting resistor, RCS. The CSx pin sources CS current (ICS) which is 10 A typically at room temperature, and the CSx terminal voltage (VCS= RCS x ICS) should be in the range of 0.2 V to 2 V over all operation temperatures. The trip level is set to the OCL trip voltage (VTRIP) as shown in Equation 3. R I VTRIP = CS CS + 1 mV 8 (3) The inductor current is monitored by the voltage between GND pin and SWx pin so that SWx pin should be connected to the drain terminal of the low-side MOSFET properly.The CS pin current has a 4500 ppm/C temperature slope to compensate the temperature dependency of the RDS(on). GND is used as the positive current sensing node so that GND should be connected to the source terminal of the low-side MOSFET. As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 4. IIND(ripple ) (VIN - VOUT ) VOUT V V 1 IOCP = TRIP + = TRIP + RDS(on ) 2 RDS(on ) 2 L fSW VIN (4) In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. Eventually, it ends up with crossing the undervoltage protection threshold and shutdown both channels. 14 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 Output Overvoltage/Undervoltage Protection TPS51225/B/C asserts the overvoltage protection (OVP) when VFBx voltage reaches OVP trip threshold level. When an OVP event is detected, the controller changes the output target voltage to 0 V. This usually turns off DRVH and forces DRVL to be on. When the inductor current begins to flow through the low-side MOSFET and reaches the negative OCL, DRVL is turned off and DRVH is turned on. After the on-time expires, DRVH is turned off and DRVL is turned on again. This action minimizes the output node undershoot due to LC resonance. When the VFBx reaches 0V, the driver output is latched as DRVH off, DRVL on. The undervoltage protection (UVP) latch is set when the VFBx voltage remains lower than UVP trip threshold voltage for 250 s or longer. In this fault condition, the controller latches DRVH low and DRVL low and discharges the outputs. UVP detection function is enabled after 1.35 ms of SMPS operation to ensure startup. Undervoltage Lockout (UVLO) Protection TPS51225/B/C has undervoltage lock out protection at VIN, VREG5 and VREG3. When each voltage is lower than their UVLO threshold voltage, both SMPS are shut-off. They are non-latch protections. Over-Temperature Protection TPS51225/B/C features an internal temperature monitor. If the temperature exceeds the threshold value (typically 155C), TPS51225/B/C is shut off including LDOs. This is non-latch protection. Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 15 TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com External Components Selection The external components selection is relatively simple for a design using D-CAPTM mode. Step 1. Determine the Value of R1 and R2 The recommended R2 value is between 10 k and 20 k. Determine R1 using Equation 5. R1 = (VOUT - 0.5 VRIPPLE - 2.0 ) R2 2.0 (5) Step 2. Choose the Inductor The inductance value should be determined to give the ripple current of approximately 1/3 of maximum output current. Larger ripple current increases output ripple voltage, improves signal:noise ratio, and helps ensure stable operation. L= IN(max ) - VOUT 1 IIND(ripple ) fSW (V ) V OUT VIN(max ) = 3 IOUT(max ) fSW IN(max ) - VOUT (V ) V OUT VIN(max) (6) The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as shown in Equation 7. IIND(peak ) = VIN(max ) - VOUT VOUT VTRIP 1 + RDS(on ) L fSW VIN(max ) ) ( (7) Step 3. Choose Output Capacitor(s) Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet required ripple voltage above. A quick approximation is as shown in Equation 8. V 20mV (1 - D) 20mV L fSW ESR = OUT = 2 V IIND(ripple ) 2V where * * D as the duty-cycle factor the required output ripple voltage slope is approximately 20 mV per tSW (switching period) in terms of VFB terminal (8) VVOUT Slope (1) Jitter (2) Slope (2) Jitter 20 mV (1) VREF VREF +Noise tON tOFF UDG-12012 Figure 4. Ripple Voltage Slope and Jitter Performance 16 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 Layout Considerations Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout. Placement * Place voltage setting resistors close to the device pins. * Place bypass capacitors for VREG5 and VREG3 close to the device pins. Routing (Sensitive analog portion) * Use small copper space for VFBx. There are short and narrow traces to avoid noise coupling. * Connect VFB resistor trace to the positive node of the output capacitor. Routing inner layer away from power traces is recommended. * Use short and wide trace from VFB resistor to vias to GND (internal GND plane). Routing (Power portion) * Use wider/shorter traces of DRVL for low-side gate drivers to reduce stray inductance. * Use the parallel traces of SW and DRVH for high-side MOSFET gate drive in a same layer or on adjoin layers, and keep them away from DRVL. * Use wider/ shorter traces between the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET * Thermal pad is the GND terminal of this device. Five or more vias with 0.33-mm (13-mils) diameter connected from the thermal pad to the internal GND plane should be used to have strong GND connection and help heat dissipation. Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 17 TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS 1.6 60 VIN Supply Current 2 (A) VIN Supply Current 1 (mA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (C) 95 40 30 20 10 0 -40 -25 -10 110 125 G001 Figure 5. VIN Supply Current 1 vs. Junction Temperature 5 20 35 50 65 80 Junction Temperature (C) 95 110 125 G002 Figure 6. VIN Supply Current 2 vs. Junction Temperature 1.6 300 VIN Stand-By Current (A) 1.4 VO1 Supply Current 1 (mA) 50 1.2 1.0 0.8 0.6 0.4 0.2 250 200 150 100 50 TPS51225C Only 0.0 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (C) 95 0 -40 -25 -10 110 125 G003 20 310 18 300 16 290 14 12 10 8 6 4 2 0 -40 -25 -10 110 125 G004 280 270 260 250 240 230 220 5 20 35 50 65 80 Junction Temperature (C) 95 110 125 G005 Figure 9. CS Source Current vs. Junction Temperature 18 95 Figure 8. VIN Stand-By Current vs. Junction Temperature VCLK Frequency (kHz) CS Source Current (A) Figure 7. VO1 Supply Current 1 vs. Junction Temperature 5 20 35 50 65 80 Junction Temperature (C) Submit Documentation Feedback 210 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (C) 95 110 125 G006 Figure 10. Clock Frequency vs. Junction Temperature Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) 100 90 Out-of-Audio VVOUT = 5 V 80 80 Efficiency (%) Efficiency (%) 90 100 Auto-Skip VVOUT = 5 V 70 60 70 60 50 40 30 VVIN = 8 V VVIN = 12 V VVIN = 20 V 50 40 0.001 0.01 0.1 Output Current (A) 1 VVIN = 8 V VVIN = 12 V VVIN = 20 V 20 10 0 0.001 10 Figure 11. Efficiency vs. Output Current Output Volage (V) Output Volage (V) 5.10 5.00 4.95 VVIN = 8 V VVIN = 12 V VVIN = 20 V 4.90 4.85 0.001 10 G008 0.01 0.1 Output Current (A) 1 Out-of-Audio VVOUT = 5 V 5.05 5.00 4.95 VVIN = 8 V VVIN = 12 V VVIN = 20 V 4.90 4.85 0.001 10 0.01 0.1 Output Current (A) G014 Figure 13. Load Regulation 1 10 G015 Figure 14. Load Regulation 100 100 Auto-Skip VVOUT = 3.3 V 90 Efficiency (%) 70 60 50 70 60 50 40 30 40 VVIN = 8 V VVIN = 12 V VVIN = 20 V 30 20 0.001 Out-of_Audio VVOUT = 3.3 V 80 80 Efficiency (%) 1 5.15 Auto-Skip VVOUT = 5 V 5.05 90 0.1 Output Current (A) Figure 12. Efficiency vs. Output Current 5.15 5.10 0.01 G007 0.01 0.1 Output Current (A) 1 Figure 15. Efficiency vs. Output Current Copyright (c) 2012, Texas Instruments Incorporated VVIN = 8 V VVIN = 12 V VVIN = 20 V 20 10 10 0 0.001 0.01 0.1 Output Current (A) G010 1 10 G011 Figure 16. Efficiency vs. Output Current Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 19 TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 3.43 3.43 Out-of-Audio VVOUT = 3.3 V 3.38 Output Volage (V) Output Volage (V) Auto-skip VVOUT = 3.3 V 3.33 3.28 3.23 0.001 0.1 Output Current (A) 1 3.33 3.28 VVIN = 8 V VVIN = 12 V VVIN = 20 V 0.01 3.38 3.23 0.001 10 Switching Frequency (kHz) Switching Frequency (kHz) 200 150 100 50 0.01 0.1 Output Current (A) 1 200 150 100 Out-of-Audio VVOUT = 5 V 0.01 0.1 Output Current (A) 1 10 G017 Figure 20. Switching Frequency vs. Output Current 450 400 Switching Frequency (kHz) Switching Frequency (kHz) G013 VVIN = 8 V VVIN = 12 V VVIN = 20 V G016 VVIN = 8 V VVIN = 12 V VVIN = 20 V 300 250 200 150 100 Auto-Skip VVOUT = 3.3 V 50 0.01 0.1 Output Current (A) 1 Submit Documentation Feedback 350 VVIN = 8 V VVIN = 12 V VVIN = 20 V 300 250 200 150 100 Out-of-Audio VVOUT = 3.3 V 50 10 0 0.001 0.01 G018 Figure 21. Switching Frequency vs. Output Current 20 10 250 0 0.001 10 450 0 0.001 300 50 Auto-Skip VVOUT = 5 V Figure 19. Switching Frequency vs. Output Current 350 1 350 VVIN = 8 V VVIN = 12 V VVIN = 20 V 250 400 0.1 Output Current (A) Figure 18. Load Regulation 350 0 0.001 0.01 G012 Figure 17. Load Regulation 300 VVIN = 8 V VVIN = 12 V VVIN = 20 V 0.1 Output Current (A) 1 10 G019 Figure 22. Switching Frequency vs. Output Current Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) VOUT1 (2 V/div) VOUT1 (2 V/div) VOUT2 (2 V/div) VOUT2 (2 V/div) PGOOD (5 V/div) EN1 = EN2 (5 V/div) PGOOD (5 V/div) EN1 = EN2 (5 V/div) Time (10 ms/div) Time (400 s/div) Figure 23. Start-Up VVIN = 12 V Figure 24. Output Discharge VOUT1 (50 mV/div) I OUT 3A a 8 A VVIN = 12 V VOUT1 (50 mV/div) I OUT 3A a 8 A VOUT2 0 A( 50 mV/div) VOUT2 0 A ( 50 mV/div) I IND1 (5 A/div) I IND1 (5 A/div) SW1 (10 V/div) SW1 (10 V/div) Time (100 s/div) Time (100 s/div) Figure 25. 5-V Load Transient Figure 26. 3.3-V Load Transient 500 500 VOUT = 5 V IOUT = 6 A 400 350 300 250 200 150 100 50 0 VOUT = 3.3 V IOUT = 6 A 450 Switching Frequency (kHz) Switching Frequency (kHz) 450 400 350 300 250 200 150 100 50 5 10 15 Input Voltage (V) 20 25 Figure 27. Switching Frequency vs. Input Voltage Copyright (c) 2012, Texas Instruments Incorporated 0 5 10 15 Input Voltage (V) G000 20 25 G000 Figure 28. Switching Frequency vs. Input Voltage Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 21 TPS51225, TPS51225B, TPS51225C SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 www.ti.com APPLICATION DIAGRAM (TPS51225/TPS51225B/TPS51225C) VIN 2.2 W L1 10 F x 2 U1 TPS51225 TPS51225 B 12 VIN TPS51225C 10 F x 2 0.1 F Q1 VOUT 5 V-8A VBST2 16 DRVH 1 DRVH 2 10 18 SW1 C1 0.1 F 17 VBST1 SW2 2.2 W 9 Q2 L2 VOUT 3.3 V - 8A 8 C2 Q3 15 DRVL 1 Q4 DRVL 2 11 6.57 kW 14 VO1 15.3 kW 51 kW 10 kW 2 VFB1 VFB2 4 1 CS1 CS2 5 PGOOD 7 PGOOD EN2 6 EN 3.3 V VREG3 3 VREG (3.3-V LDO) 47 kW 19 VCLK 0.1 F 0.1 F EN 5V Charge-pump Output VREG5 (5-V LDO) D1 13 VREG5 10 kW 1 F 1 F 0.1 F 0.1 F 20 EN1 UDG-12008 GND Table 4. Key External Components (APPLICATION DIAGRAM (TPS51225/TPS51225B/TPS51225C)) REFERENCE DESIGNATOR 22 FUNCTION MANUFACTURER PART NUMBER L1 Output Inductor (5-VOUT) Toko FDVE1040-3R3M L2 Output Inductor (3.3-VOUT) Toko FDVE1040-2R2M C1 Output Capacitor (5-VOUT) SANYO 6TPE330MIL x 2 C2 Output Capacitor (3.3-VOUT) SANYO 4TPE470MIL Q1 High-side MOSFET (5-VOUT) Fairchild FDMC7692 Q2 High-side MOSFET (3.3-VOUT) Fairchild FDMC7692 Q3 Low-side MOSFET (5-VOUT) Fairchild FDMC7672 Q4 Low-side MOSFET (3.3-VOUT) Fairchild FDMC7672 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS51225 TPS51225B TPS51225C TPS51225, TPS51225B, TPS51225C www.ti.com SLUSAV0A - JANUARY 2012 - REVISED JUNE 2012 Changes from Original (January 2012) to Revision A * Page Deleted references to obsolete option TPS51225A throughout document .......................................................................... 1 Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS51225 TPS51225B TPS51225C 23 PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS51225BRUKR ACTIVE WQFN RUK 20 3000 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR TPS51225BRUKT ACTIVE WQFN RUK 20 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR TPS51225CRUKR ACTIVE WQFN RUK 20 3000 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR TPS51225CRUKT ACTIVE WQFN RUK 20 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR TPS51225RUKR ACTIVE WQFN RUK 20 3000 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR TPS51225RUKT ACTIVE WQFN RUK 20 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS51225BRUKR WQFN RUK 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51225BRUKT WQFN RUK 20 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51225CRUKR WQFN RUK 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51225CRUKT WQFN RUK 20 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51225RUKR WQFN RUK 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51225RUKT WQFN RUK 20 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51225BRUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51225BRUKT WQFN RUK 20 250 210.0 185.0 35.0 TPS51225CRUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51225CRUKT WQFN RUK 20 250 210.0 185.0 35.0 TPS51225RUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51225RUKT WQFN RUK 20 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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