M68HC08
Microcontrollers
freescale.com
MC68HC08GP32A
MC68HC08GP16A
Data Sheet
MC68HC08GP32A
Rev. 1,0
03/2006
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 3
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2004, 2006. All rights reserved.
MC68HC08GP32A
MC68HC08GP16A
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date Revision
Level Description Page
Number(s)
March,
2004 N/A Initial release
July,
2005 0.1 Updated to meet Freescale identity guidelines. Throughout
March,
2006 1.0
9.5 Clock Generator Module (CGM) — Updated description to remove
erroneous information. 94
20.16.1 CGM Component Specifications — Updated to reflect correct
values. 249
Revision History
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
4Freescale Semiconductor
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 5
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Chapter 5 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Chapter 6 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Chapter 7 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Chapter 8 Keyboard Interrupt (KBI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Chapter 9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Chapter 10 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Chapter 11 Mask Option Registers (MOR2 and MOR1) . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Chapter 12 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Chapter 13 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Chapter 14 Serial Communications Interface (SCI) Module . . . . . . . . . . . . . . . . . . . . . . .135
Chapter 15 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Chapter 16 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
Chapter 17 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Chapter 18 Timer Interface Modules (TIM1 and TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
Chapter 20 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .251
List of Chapters
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
6Freescale Semiconductor
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
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Table of Contents
Chapter 1
General Description
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3 Standard Features of the MC68HC08GP32A and MC68HC08GP16A . . . . . . . . . . . . . . . . . . . 19
1.3.1 Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.1 Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.3 External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.5 CGM Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.6 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.7 ADC Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL). . . . . . . . . . . . . . . . 25
1.6.8 Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0) . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.10 Port C I/O Pins (PTC6–PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.12 Port E I/O Pins (PTE1/RxD–PTE0/TxD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 2
Memory
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4 Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.6 Read-Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 3
Analog-to-Digital Converter (ADC)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.4 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
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3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.6.1 ADC Analog Power Pin (VDDAD)/ADC Voltage Reference High Pin (VREFH) . . . . . . . . . . . 43
3.6.2 ADC Analog Ground Pin (VSSAD)/ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . 43
3.6.3 ADC Voltage In (VADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.7.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 4
Clock Generator Module (CGM)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3.1 Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3.5 Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4.4 PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.4.5 PLL Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.4.6 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.4.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.4.8 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.4.9 CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.4.10 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.5 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.5.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.5.3 PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.5.4 PLL Multiplier Select Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.5.5 PLL VCO Range Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.5.6 PLL Reference Divider Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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4.7 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.7.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.8 Acquisition/Lock Time Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.8.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.8.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.8.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 5
Computer Operating Properly (COP)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Chapter 6
Central Processor Unit (CPU)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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Chapter 7
External Interrupt (IRQ)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.4 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.6 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Chapter 8
Keyboard Interrupt (KBI) Module
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.4 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.6 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.7.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Chapter 9
Low-Power Modes
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.1.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.1.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.2 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.2.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.3 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.4 Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.5 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.6 Computer Operating Properly Module (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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9.7 External Interrupt Module (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.8 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.9 Low-Voltage Inhibit Module (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.10 Serial Communications Interface Module (SCI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.11 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.12 Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.12.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.13 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.14 Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.15 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.3.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.3.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.3.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.3.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Chapter 11
Mask Option Registers (MOR2 and MOR1)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.2 Mask Option Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table of Contents
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Chapter 12
Input/Output (I/O) Ports
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
12.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.2.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.2.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.3.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.4 Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.4.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.4.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.4.3 Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.5 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.5.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.5.2 Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.5.3 Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.6 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.6.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Chapter 13
Resets and Interrupts
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.2.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.2.3 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.2.3.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.2.3.2 COP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.2.3.3 Low-Voltage Inhibit Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.2.3.4 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.2.3.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.2.4 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.3.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.3.2 Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.3.2.1 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.3.2.2 Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.3.2.3 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.3.2.4 CGM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.3.2.5 TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.3.2.6 TIM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.3.2.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.3.2.8 SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.3.2.9 KBD0–KBD7 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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13.3.2.10 ADC (Analog-to-Digital Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.3.2.11 TBM (Timebase Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.3.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
13.3.3.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
13.3.3.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
13.3.3.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Chapter 14
Serial Communications Interface (SCI) Module
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
14.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
14.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
14.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
14.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
14.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
14.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
14.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
14.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
14.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
14.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
14.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
14.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14.6 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.7.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.7.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.8.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.8.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.8.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
14.8.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
14.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
14.8.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table of Contents
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
14 Freescale Semiconductor
Chapter 15
System Integration Module (SIM)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
15.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
15.2.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
15.2.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
15.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
15.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
15.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
15.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
15.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
15.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
15.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
15.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
15.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
15.5.1.3 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
15.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
15.5.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
15.5.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
15.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
15.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
15.7.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
15.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
15.7.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Chapter 16
Serial Peripheral Interface (SPI) Module
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.3.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
16.3.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
16.4 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
16.4.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
16.4.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
16.4.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
16.4.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 15
16.5 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
16.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
16.6.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
16.6.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
16.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
16.8 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
16.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
16.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
16.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
16.10 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
16.11 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
16.11.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
16.11.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
16.11.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
16.11.4 SS (Slave Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
16.12 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
16.12.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
16.12.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
16.12.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Chapter 17
Timebase Module (TBM)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
17.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
17.5 TBM Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
17.7 Timebase Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Chapter 18
Timer Interface Modules (TIM1 and TIM2)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
18.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
18.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
18.4.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
18.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
18.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
18.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
18.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
18.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
18.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
18.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
18.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
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MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
16 Freescale Semiconductor
18.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
18.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
18.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
18.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
18.9.2 TIM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
18.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
18.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
18.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Chapter 19
Development Support
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
19.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
19.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
19.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
19.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
19.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
19.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
19.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
19.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
19.2.2.3 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
19.2.2.4 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
19.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
19.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
19.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
19.3.1.1 Monitor Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
19.3.1.2 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
19.3.1.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
19.3.1.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
19.3.1.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
19.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
19.3.3 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Chapter 20
Electrical Specifications
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
20.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
20.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
20.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
20.5 5.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
20.6 3.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
20.7 5.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 17
20.8 3.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
20.9 Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
20.10 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
20.11 Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
20.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
20.13 5.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
20.14 3.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
20.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
20.16 Clock Generation Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
20.16.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
20.16.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
20.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Chapter 21
Ordering Information and Mechanical Specifications
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
21.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table of Contents
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
18 Freescale Semiconductor
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 19
Chapter 1
General Description
1.1 Introduction
The MC68HC08GP32A and MC68HC08GP16A are members of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced
M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and
types, and package types.
1.2 Features
For convenience, features have been organized to reflect:
• Standard features of the MC68HC08GP32A and MC68HC08GP16A
• Features of the CPU08
1.3 Standard Features of the MC68HC08GP32A and MC68HC08GP16A
• High-performance M68HC08 architecture optimized for C-compilers
• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
• 8-MHz internal bus frequency
• System protection features:
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset and selectable trip points for 3.0-V and 5.0-V
operation
– Illegal opcode detection with reset
– Illegal address detection with reset
• Low-power design; fully static with stop and wait modes
• Standard low-power modes of operation:
– Wait mode
– Stop mode
• Master reset pin and power-on reset (POR)
• On-chip read-only memory (ROM)
– MC68HC08GP32A — 32,256 bytes
– MC68HC08GP16A — 15,872 bytes
• 512 bytes of on-chip random-access memory (RAM)
• Serial peripheral interface module (SPI)
• Serial communications interface module (SCI)
• Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture,
output compare, and PWM capability on each channel
General Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
20 Freescale Semiconductor
• 8-channel, 8-bit successive approximation analog-to-digital converter (ADC)
• BREAK module (BRK) to allow single breakpoint setting during in-circuit debugging
• Internal pullups on IRQ and RST to reduce customer system cost
• Clock generator module with on-chip 32-kHz crystal compatible PLL (phase-lock loop)
• Up to 33 general-purpose input/output (I/O) pins, including:
– 26 shared-function I/O pins
– Five or seven dedicated I/O pins, depending on package choice
• Selectable pullups on inputs only on ports A, C, and D. Selection is on an individual port bit basis.
During output mode, pullups are disengaged.
• High current 10-mA sink/10-mA source capability on all port pins
• Higher current 15-mA sink/source capability on PTC0–PTC4
• Timebase module with clock prescaler circuitry for eight user selectable periodic real-time
interrupts with optional active clock source during stop mode for periodic wakeup from stop using
an external 32-kHz crystal
• 8-bit keyboard wakeup port
• 5-mA maximum current injection on all port pins to maintain input protection
• Available packages: 42-pin shrink dual-in-line package (SDIP) and 44-pin quad flat pack (QFP)
• Specific features of the 42-pin SDIP
– Port C is only 5 bits: PTC0–PTC4
• Specific features of the 44-pin QFP
– Port C is 7 bits: PTC0–PTC6
1.3.1 Features of the CPU08
Features of the CPU08 include:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC08GP32A and MC68HC08GP16A.
MCU Block Diagram
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 21
Figure 1-1. MCU Block Diagram
SINGLE BREAKPOINT BREAK
MODULE
CLOCK GENERATOR MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
MONITOR MODULE
SERIAL PERIPHERAL
2-CHANNEL TIMER INTERFACE
MODULE 2
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS
USER ROM
USER RAM
MONITOR ROM
USER ROM VECTOR SPACE
SINGLE EXTERNAL
INTERRUPT MODULE
PORTA
DDRA
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
INTERNAL BUS
OSC1
OSC2
CGMXFC
RST(3)
IRQ(3)
INTERFACE MODULE
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7–
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
VDDAD/VREFH 8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6(1)
PTC5(1)
PTC4(1, 2)
PTC3(1, 2)
PTC2(1, 2)
PTC1(1, 2)
PTC0(1, 2)
PTD7/T2CH1(1)
PTD6/T2CH0(1)
PTD5/T1CH1(1)
PTD4/T1CH0(1)
PTD3/SPSCK(1)
PTD2/MOSI(1)
PTD1/MISO(1)
PTD0/SS(1)
PTE1/RxD
PTE0/TxD
VSSAD/VREFL
2-CHANNEL TIMER INTERFACE
MODULE 1
32-kHz OSCILLATOR
PHASE-LOCKED LOOP
SERIAL COMMUNICATIONS
INTERFACE MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
MASK OPTION REGISTER 1
MODULE
SECURITY
MODULE
MASK OPTION REGISTER 2
MODULE
POWER
VSS
VDD
VSSA
VDDA
1. Ports are software configurable with pullup device if input port.
2. Higher current drive port pins
3. Pin contains integrated pullup device
DDRB
PORTB
64 BYTES
PTA0/KBD0(1)
MC68HC08GP32A — 32,256 BYTES
512 BYTES
307 BYTES
36 BYTES
MC68HC08GP16A — 15,872 BYTES
General Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
22 Freescale Semiconductor
1.5 Pin Assignments
Pin assignments are shown in Figure 1-2 and Figure 1-3. Note that the text in parentheses next to a signal
in Figure 1-2 indicates the module which uses the signal.
Figure 1-2. 42-Pin SDIP Pin Assignments
21 22 PTD5/T1CH1
PTD4/T1CH0
PTB1/AD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
PTB0/AD0
PTD7/T2CH1
VSS
PTD3/SPSCK
PTD2/MOSI
RST
IRQ
PTD0/SS
PTD1/MISO
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
PTA5/KBD5
PTA6/KBD6
PTA7/KBD7
PTB6/AD6
PTB7/AD7
PTB3/AD3
PTB4/AD4
PTB5/AD5
VSSA (PLL)
VDDA (PLL)
VDDAD/VREFH (ADC)
VSSAD/VREFL (ADC)
CGMXFC (PLL)
OSC2
OSC1
PTC0
PTC1
PTC2
PTC3
PTC4
PTE0/TxD
PTE1/RxD
PTB2/AD2
20 23 PTD6/T2CH0
VDD
Pin Assignments
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 23
Figure 1-3. 44-Pin QFP Pin Assignments
44
34
43
42
41
40
39
38
37
36
35
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
12
23
RST
PTE0/TxD
PTE1/RxD
IRQ
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTD5/T1CH1
PTD4/T1CH0
VDD
VSS
PTD3/SPSCK
PTD2/MOSI
PTD1/MISO
PTD0/SS
PTD6/T2CH0
PTD7/T2CH1
PTB0/AD0
PTB6/AD6
PTB7/AD7
VDDAD/VREFH
VSSAD/VREFL
PTA0/KBD0
PTB2/AD2
PTB3/AD3
PTB1/AD1
PTB4/AD4
PTB5/AD5
PTA4/KBD4
PTA5/KBD5
VDDA
OSC1
OSC2
CGMXFC
VSSA
PTA1/KBD1
PTA6/KBD6
PTA7/KBD7
PTA3/KBD3
PTA2/KBD2
General Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
24 Freescale Semiconductor
1.6 Pin Functions
Descriptions of the pin functions are provided here.
1.6.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To
prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response
ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that
require the port pins to source high current levels.
Figure 1-4. Power Supply Bypassing
1.6.2 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Chapter 4 Clock
Generator Module (CGM).
1.6.3 External Reset Pin (RST)
A low on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of
the entire system. It is driven low when any internal reset source is asserted. This pin contains an internal
pullup resistor. See Chapter 15 System Integration Module (SIM).
1.6.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See
Chapter 7 External Interrupt (IRQ)
MCU
VDD
C2
C1
0.1 µF
VSS
VDD
+
Note: Component values shown represent typical applications.
Pin Functions
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 25
1.6.5 CGM Power Supply Pins (VDDA and VSSA)
VDDA and VSSA are the power supply pins for the analog portion of the clock generator module (CGM).
Connect the VDDA pin to the same voltage potential as VDD, and the VSSA pin to the same voltage
potential as VSS. Decoupling of these pins should be as per the digital supply. See Chapter 4 Clock
Generator Module (CGM)
1.6.6 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See Chapter 4 Clock Generator Module
(CGM)
1.6.7 ADC Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL)
VDDAD and VSSAD are the power supply pins for the analog-to-digital converter (ADC). Connect the VDDAD
pin to the same voltage potential as VDD, and the VSSAD pin to the same voltage potential as VSS.
Decoupling of these pins should be as per the digital supply. See Chapter 3 Analog-to-Digital Converter
(ADC).
VREFH is the high reference supply for the ADC, and is internally connected to VDDAD. VREFL is the low
reference supply for the ADC, and is internally connected to VSSAD.
1.6.8 Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0)
PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be
programmed to serve as keyboard interrupt pins. See Chapter 12 Input/Output (I/O) Ports and Chapter 8
Keyboard Interrupt (KBI) Module.
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
1.6.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0)
PTB7–PTB0 are general-purpose, bidirectional I/O port pins that can also be used for analog-to-digital
converter (ADC) inputs. See Chapter 12 Input/Output (I/O) Ports and Chapter 3 Analog-to-Digital
Converter (ADC).
1.6.10 Port C I/O Pins (PTC6–PTC0)
PTC6–PTC0 are general-purpose, bidirectional I/O port pins. See Chapter 12 Input/Output (I/O) Ports.
PTC5 and PTC6 are only available on 44-pin QFP package.
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
1.6.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS)
PTD7–PTD0 are special-function, bidirectional I/O port pins. PTD0–PTD3 can be programmed to be
serial peripheral interface (SPI) pins, while PTD4–PTD7 can be individually programmed to be timer
interface module (TIM1 and TIM2) pins. See Chapter 18 Timer Interface Modules (TIM1 and TIM2),
Chapter 16 Serial Peripheral Interface (SPI) Module, and Chapter 12 Input/Output (I/O) Ports.
General Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
26 Freescale Semiconductor
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
1.6.12 Port E I/O Pins (PTE1/RxD–PTE0/TxD)
PTE0–PTE1 are general-purpose, bidirectional I/O port pins. These pins can also be programmed to be
serial communications interface (SCI) pins. See Chapter 14 Serial Communications Interface (SCI)
Module and Chapter 12 Input/Output (I/O) Ports.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 27
Chapter 2
Memory
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:
• 32,256 bytes user read-only memory (ROM) for MC68HC08GP32A
• 15,872 bytes ROM for MC68HC08GP16A
• 512 bytes of random-access memory (RAM)
• 36 bytes of user-defined vectors
• 307 bytes of monitor ROM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address reset. In the memory map (Figure 2-1)
and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and
in register figures in this document, reserved locations are marked with the word Reserved or with the
letter R.
2.4 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000–$003F. Additional I/O
registers have these addresses:
• $FE00; SIM break status register, SBSR
• $FE01; SIM reset status register, SRSR
• $FE03; SIM break flag control register, SBFCR
• $FE04; interrupt status register 1, INT1
• $FE05; interrupt status register 2, INT2
• $FE06; interrupt status register 3, INT3
• $FE09; break address register high, BRKH
• $FE0A; break address register low, BRKL
• $FE0B; break status and control register, BRKSCR
• $FE0C; LVI status register, LVISR
• $FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
Memory
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
28 Freescale Semiconductor
$0000
↓
$003F
I/O REGISTERS
64 BYTES
$0040
↓
$023F
RAM
512 BYTES
$0240
↓
$7FFF
UNIMPLEMENTED
32,192 BYTES
$8000
↓
$FDFF
ROM
32,256 BYTES
RESERVED
16,384 BYTES
$8000
↓
$BFFF
ROM
15,872 BYTES
$C000
↓
$FDFF
$FE00 SIM BREAK STATUS REGISTER (SBSR) MC68HC08GP16A Memory Map
$FE01 SIM RESET STATUS REGISTER (SRSR)
$FE02 RESERVED (SUBAR)
$FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR)
$FE04 INTERRUPT STATUS REGISTER 1 (INT1)
$FE05 INTERRUPT STATUS REGISTER 2 (INT2)
$FE06 INTERRUPT STATUS REGISTER 3 (INT3)
$FE07 RESERVED
$FE08 RESERVED
$FE09 BREAK ADDRESS REGISTER HIGH (BRKH)
$FE0A BREAK ADDRESS REGISTER LOW (BRKL)
$FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0C LVI STATUS REGISTER (LVISR)
$FE0D
↓
$FE0F
UNIMPLEMENTED
3 BYTES
$FE10
↓
$FE1F
RESERVED FOR COMPATIBILITY
WITH MONITOR CODE
$FE20
↓
$FF52
MONITOR ROM
(RESERVED FOR DEVICE TESTING ONLY)
307 BYTES
$FF53
↓
$FF7D
UNIMPLEMENTED
43 BYTES
$FF7E RESERVED
$FF7F
↓
$FFDB
UNIMPLEMENTED
93 BYTES
$FFDC
↓
$FFFF
ROM VECTORS
36 BYTES
Note:$FFF6–$FFFD reserved for eight security bytes
MC68HC08GP32A Memory Map
Figure 2-1. Memory Map
Input/Output (I/O) Section
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 29
Addr.Register Name Bit 7654321Bit 0
$0000
Port A Data Register
(PTA)
See page 110.
Read:
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
Reset: Unaffected by reset
$0001
Port B Data Register
(PTB)
See page 112.
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
$0002
Port C Data Register
(PTC)
See page 114.
Read: 0
PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
Write:
Reset: Unaffected by reset
$0003
Port D Data Register
(PTD)
See page 116.
Read:
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write:
Reset: Unaffected by reset
$0004
Data Direction Register A
(DDRA)
See page 110.
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
$0005
Data Direction Register B
(DDRB)
See page 113.
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
$0006
Data Direction Register C
(DDRC)
See page 114.
Read: 0
DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset:00000000
$0007
Data Direction Register D
(DDRD)
See page 120.
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset:00000000
$0008
Port E Data Register
(PTE)
See page 119.
Read:000000
PTE1 PTE0
Write:
Reset: Unaffected by reset
$0009
↓
$000B
Unimplemented
Read:
Write:
Reset:00000000
$000C
Data Direction Register E
(DDRE)
See page 120.
Read:000000
DDRE1 DDRE0
Write:
Reset:00000000
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7)
Memory
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
30 Freescale Semiconductor
$000D
Port A Input Pullup Enable
Register (PTAPUE)
See page 112.
Read:
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:00000000
$000E
Port C Input Pullup Enable
Register (PTCPUE)
See page 116.
Read: 0
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
Write:
Reset:00000000
$000F
Port D Input Pullup Enable
Register (PTDPUE)
See page 119.
Read:
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Write:
Reset:00000000
$0010
SPI Control Register
(SPCR)
See page 195.
Read:
SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
Write:
Reset:00101000
$0011
SPI Status and Control
Register (SPSCR)
See page 196.
Read: SPRF
ERRIE
OVRF MODF SPTE
MODFEN SPR1 SPR0
Write:
Reset:00001000
$0012
SPI Data Register
(SPDR)
See page 198.
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
$0013
SCI Control Register 1
(SCC1)
See page 150.
Read:
LOOPS ENSCI TXINV M WAKE ILTY PEN PTY
Write:
Reset:00000000
$0014
SCI Control Register 2
(SCC2)
See page 152.
Read:
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
Write:
Reset:00000000
$0015
SCI Control Register 3
(SCC3)
See page 154.
Read: R8
T8 R R ORIE NEIE FEIE PEIE
Write:
Reset:UU000000
$0016
SCI Status Register 1
(SCS1)
See page 155.
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
$0017
SCI Status Register 2
(SCS2)
See page 157.
Read: BKF RPF
Write:
Reset:00000000
$0018
SCI Data Register
(SCDR)
See page 158.
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7)
Input/Output (I/O) Section
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 31
$0019
SCI Baud Rate Register
(SCBR)
See page 158.
Read:
SCP1 SCP0 R SCR2 SCR1 SCR0
Write:
Reset:00000000
$001A
Keyboard Status
and Control Register
(INTKBSCR) See page 92.
Read:0000KEYF0
IMASKK MODEK
Write: ACKK
Reset:00000000
$001B
Keyboard Interrupt Enable
Register (INTKBIER)
See page 92.
Read:
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Write:
Reset:00000000
$001C
Timebase Module Control
Register (TBCR)
See page 202.
Read: TBIF
TBR2 TBR1 TBR0
0
TBIE TBON R
Write: TACK
Reset:00000000
$001D
IRQ Status and Control
Register (INTSCR)
See page 86.
Read:0000IRQF0
IMASK MODE
Write: ACK
Reset:00000000
$001E
Mask Option Register 2
(MOR2)
See page 103.
Read:00000
TBM-
CLKSEL
OSC-
STOPENB SCIBDSRC
Write:
Reset: Mask defined
$001F
Mask Option Register 1
(MOR1)
See page 104.
Read: COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD
Write:
Reset: Mask defined
$0020
Timer 1 Status and Control
Register (T1SC)
See page 213.
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
$0021
Timer 1 Counter
Register High (T1CNTH)
See page 214.
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
$0022
Timer 1 Counter
Register Low (T1CNTL)
See page 214.
Read:Bit 7654321Bit 0
Write:
Reset:00000000
$0023
Timer 1 Counter Modulo
Register High (T1MODH)
See page 215.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)
Memory
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
32 Freescale Semiconductor
$0024
Timer 1 Counter Modulo
Register Low (T1MODL)
See page 215.
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
$0025
Timer 1 Channel 0 Status and
Control Register (T1SC0)
See page 215.
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
$0026
Timer 1 Channel 0
Register High (T1CH0H)
See page 218.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$0027
Timer 1 Channel 0
Register Low (T1CH0L)
See page 218.
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$0028
Timer 1 Channel 1 Status and
Control Register (T1SC1)
See page 215.
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
$0029
Timer 1 Channel 1
Register High (T1CH1H)
See page 218.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$002A
Timer 1 Channel 1
Register Low (T1CH1L)
See page 218.
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$002B
Timer 2 Status and Control
Register (T2SC)
See page 213.
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
$002C
Timer 2 Counter
Register High (T2CNTH)
See page 214.
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
$002D
Timer 2 Counter
Register Low (T2CNTL)
See page 214.
Read:Bit 7654321Bit 0
Write:
Reset:00000000
$002E
Timer 2 Counter Modulo
Register High (T2MODH)
See page 215.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
$002F
Timer 2 Counter Modulo
Register Low (T2MODL)
See page 215.
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7)
Input/Output (I/O) Section
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 33
$0030
Timer 2 Channel 0 Status and
Control Register (T2SC0)
See page 215.
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
$0031
Timer 2 Channel 0
Register High (T2CH0H)
See page 218.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$0032
Timer 2 Channel 0
Register Low (T2CH0L)
See page 218.
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$0033
Timer 2 Channel 1 Status and
Control Register (T2SC1)
See page 215.
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
$0034
Timer 2 Channel 1
Register High (T2CH1H)
See page 218.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$0035
Timer 2 Channel 1
Register Low (T2CH1L)
See page 218.
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$0036
PLL Control Register
(PCTL)
See page 59.
Read:
PLLIE
PLLF
PLLON BCS PRE1 PRE0 VPR1 VPR0
Write:
Reset:00100000
$0037
PLL Bandwidth Control
Register (PBWC)
See page 61.
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:00000000
$0038
PLL Multiplier Select High
Register (PMSH)
See page 61.
Read:0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
$0039
PLL Multiplier Select Low
Register (PMSL)
See page 62.
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
$003A
PLL VCO Range Select
Register (PMRS)
See page 62.
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
$003B
PLL Reference Divider
Select Register (PMDS)
See page 63.
Read:0000
RDS3 RDS2 RDS1 RDS0
Write:
Reset:00000001
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7)
Memory
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
34 Freescale Semiconductor
$003C
Analog-to-Digital Status and
Control Register
(ADSCR)
See page 43.
Read:
COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
Reset:00011111
$003D
Analog-to-Digital Data
Register (ADR)
See page 45.
Read:AD7AD6AD5AD4AD3AD2AD1AD0
Write:
Reset:00000000
$003E
Analog-to-Digital Clock
Register (ADCLK)
See page 45.
Read:
ADIV2 ADIV1 ADIV0 ADICLK
0000
Write:
Reset:00000000
$003F Unimplemented
Read:
Write:
Reset:
$FE00
SIM Break Status Register
(SBSR)
See page 175.
Read:
RRRRRR
SBSW
R
Write: Note
Reset: 0
Note: Writing a 0 clears SBSW.
$FE01
SIM Reset Status Register
(SRSR)
See page 176.
Read: POR PIN COP ILOP ILAD 0 LVI 0
Write:
POR:10000000
$FE02 Reserved
Read:
RRRRRRRR
Write:
Reset:
$FE03
SIM Break Flag Control
Register (SBFCR)
See page 177.
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE04
Interrupt Status Register 1
(INT1)
See page 133.
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
$FE05
Interrupt Status Register 2
(INT2)
See page 134.
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
$FE06
Interrupt Status Register 3
(INT3)
See page 134.
Read:000000IF16IF15
Write:RRRRRRRR
Reset:00000000
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7)
Input/Output (I/O) Section
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 35
$FE07
↓
$FE08
Reserved
Read:
RRRRRRRR
Write:
Reset:00000000
$FE09
Break Address
Register High (BRKH)
See page 222.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
$FE0A
Break Address
Register Low (BRKL)
See page 222.
Read:
Bit 7654321Bit 0
Write:
Reset:00000000
$FE0B
Break Status and Control
Register (BRKSCR)
See page 221.
Read:
BRKE BRKA
000000
Write:
Reset:00000000
$FE0C
LVI Status Register
(LVISR)
See page 101.
Read:LVIOUT0000000
Write:
Reset:00000000
$FFFF
COP Control Register
(COPCTL)
See page 69.
Read: LOW BYTE OF RESET VECTOR
Write: WRITING CLEARS COP COUNTER (ANY VALUE)
Reset: Unaffected by reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7)
Memory
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
36 Freescale Semiconductor
.
Table 2-1. Vector Addresses
Vector Priority Vector Address Vector
Lowest IF16 $FFDC Timebase Vector (High)
$FFDD Timebase Vector (Low)
IF15 $FFDE ADC Conversion Complete Vector (High)
$FFDF ADC Conversion Complete Vector (Low)
IF14 $FFE0 Keyboard Vector (High)
$FFE1 Keyboard Vector (Low)
IF13 $FFE2 SCI Transmit Vector (High)
$FFE3 SCI Transmit Vector (Low)
IF12 $FFE4 SCI Receive Vector (High)
$FFE5 SCI Receive Vector (Low)
IF11 $FFE6 SCI Error Vector (High)
$FFE7 SCI Error Vector (Low)
IF10 $FFE8 SPI Transmit Vector (High)
$FFE9 SPI Transmit Vector (Low)
IF9 $FFEA SPI Receive Vector (High)
$FFEB SPI Receive Vector (Low)
IF8 $FFEC TIM2 Overflow Vector (High)
$FFED TIM2 Overflow Vector (Low)
IF7 $FFEE TIM2 Channel 1 Vector (High)
$FFEF TIM2 Channel 1 Vector (Low)
IF6 $FFF0 TIM2 Channel 0 Vector (High)
$FFF1 TIM2 Channel 0 Vector (Low)
IF5 $FFF2 TIM1 Overflow Vector (High)
$FFF3 TIM1 Overflow Vector (Low)
IF4 $FFF4 TIM1 Channel 1 Vector (High)
$FFF5 TIM1 Channel 1 Vector (Low)
IF3 $FFF6 TIM1 Channel 0 Vector (High)
$FFF7 TIM1 Channel 0 Vector (Low)
IF2 $FFF8 PLL Vector (High)
$FFF9 PLL Vector (Low)
IF1 $FFFA IRQ Vector (High)
$FFFB IRQ Vector (Low)
—$FFFC SWI Vector (High)
$FFFD SWI Vector (Low)
—$FFFE Reset Vector (High)
Highest $FFFF Reset Vector (Low)
Random-Access Memory (RAM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 37
2.5 Random-Access Memory (RAM)
Addresses $0040 through $023F are RAM locations. The location of the stack RAM is programmable.
The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently
access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
NOTE
For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
2.6 Read-Only Memory (ROM)
The user ROM consists of:
• MC68HC08GP32A — 32,256 bytes
• MC68HC08GP16A — 15,872 bytes
The monitor ROM and vectors are located from $FE20–$FF52. See Figure 2-1.
Thirty-six bytes, $FFDC–$FFFF, are dedicated to user-defined reset and interrupt vectors.
Security has been incorporated to prevent external viewing of the ROM contents. This feature ensures
that customer-developed software remains proprietary. See 19.3.2 Security.
Memory
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
38 Freescale Semiconductor
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 39
Chapter 3
Analog-to-Digital Converter (ADC)
3.1 Introduction
This section describes the 8-bit analog-to-digital converter (ADC).
3.2 Features
Features of the ADC module include:
• Eight channels with multiplexed input
• Linear successive approximation with monotonicity
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock
3.3 Functional Description
The ADC provides eight pins for sampling external sources at pins PTB7/AD7–PTB0/AD0. An analog
multiplexer allows the single ADC converter to select one of eight ADC channels as ADC voltage in
(VADIN). VADIN is converted by the successive approximation register-based analog-to-digital converter.
When the conversion is completed, ADC places the result in the ADC data register and sets a flag or
generates an interrupt. See Figure 3-2.
3.3.1 ADC Port I/O Pins
PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins that share with the ADC channels. The
channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides
the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are
controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or DDR
will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC
will return a 0.
Analog-to-Digital Converter (ADC)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
40 Freescale Semiconductor
Figure 3-1. Block Diagram Highlighting ADC Block and Pins
SINGLE BREAKPOINT BREAK
MODULE
CLOCK GENERATOR MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
MONITOR MODULE
SERIAL PERIPHERAL
2-CHANNEL TIMER INTERFACE
MODULE 2
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS
USER ROM
USER RAM
MONITOR ROM
USER ROM VECTOR SPACE
SINGLE EXTERNAL
INTERRUPT MODULE
PORTA
DDRA
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
INTERNAL BUS
OSC1
OSC2
CGMXFC
RST(3)
IRQ(3)
INTERFACE MODULE
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7–
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
VDDAD/VREFH 8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6(1)
PTC5(1)
PTC4(1, 2)
PTC3(1, 2)
PTC2(1, 2)
PTC1(1, 2)
PTC0(1, 2)
PTD7/T2CH1(1)
PTD6/T2CH0(1)
PTD5/T1CH1(1)
PTD4/T1CH0(1)
PTD3/SPSCK(1)
PTD2/MOSI(1)
PTD1/MISO(1)
PTD0/SS(1)
PTE1/RxD
PTE0/TxD
VSSAD/VREFL
2-CHANNEL TIMER INTERFACE
MODULE 1
32-kHz OSCILLATOR
PHASE-LOCKED LOOP
SERIAL COMMUNICATIONS
INTERFACE MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
MASK OPTION REGISTER 1
MODULE
SECURITY
MODULE
MASK OPTION REGISTER 2
MODULE
POWER
VSS
VDD
VSSA
VDDA
1. Ports are software configurable with pullup device if input port.
2. Higher current drive port pins
3. Pin contains integrated pullup device
DDRB
PORTB
64 BYTES
PTA0/KBD0(1)
MC68HC08GP32A — 32,256 BYTES
512 BYTES
307 BYTES
36 BYTES
MC68HC08GP16A — 15,872 BYTES
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 41
Figure 3-2. ADC Block Diagram
3.3.2 Voltage Conversion
When the input voltage to the ADC equals VREFH, the ADC converts the signal to $FF (full scale). If the
input voltage equals VREFL, the ADC converts it to $00. Input voltages between VREFH and VREFL are a
straight-line linear conversion.
NOTE
Inside the ADC module, the reference voltages VREFH is connected to the
ADC analog power, VDDAD; and VREFL is connected to the ADC analog
ground, VSSAD. Therefore, the ADC input voltage should not exceed these
analog supply voltages.
Connect the VDDAD pin to the same voltage potential as the VDD pin, and
connect the VSSAD pin to the same voltage potential as the VSS pin.
The VDDAD pin should be routed carefully for maximum noise immunity.
INTERNAL DATA BUS
READ DDRBx
WRITE DDRBx
RESET
WRITE PTBx
READ PTBx
PTBx
DDRBx
PTBx
INTERRUPT
LOGIC
CHANNEL
SELECT
ADC
CLOCK
GENERATOR
CONVERSION
COMPLETE
ADC
(VADIN)
ADC CLOCK
CGMXCLK
BUS CLOCK
ADCH4–ADCH0
ADC DATA REGISTER
AIEN COCO
DISABLE
DISABLE
ADC CHANNEL x
ADIV2–ADIV0 ADICLK
VOLTAGE IN
Analog-to-Digital Converter (ADC)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
42 Freescale Semiconductor
3.3.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take between 16 and 17 ADC clock
cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency.
3.3.4 Conversion
In continuous conversion mode, the ADC data register will be filled with new data after each conversion.
Data from the previous conversion will be overwritten whether that data has been read or not.
Conversions will continue until the ADCO bit is cleared. The COCO bit is set after each conversion and
will stay set until the next read of the ADC data register.
In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs
between writes to the ADSCR. When a conversion is in process and the ADSCR is written, the current
conversion data should be discarded to prevent an incorrect reading.
3.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC
conversion. A CPU interrupt is generated if the COCO bit is 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
3.5 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power-consumption standby modes.
3.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the
WAIT instruction.
3.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one
conversion cycle to stabilize the analog circuitry.
3.6 I/O Signals
The ADC module has eight pins shared with port B, PTB7/AD7–PTB0/AD0.
16 to 17 ADC cycles
ADC frequency
Conversion time =
Number of bus cycles = conversion time
×
bus frequency
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 43
3.6.1 ADC Analog Power Pin (VDDAD)/ADC Voltage Reference High Pin (VREFH)
The ADC analog portion uses VDDAD as its power pin. Connect the VDDAD pin to the same voltage
potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results.
NOTE
For maximum noise immunity, route VDDAD carefully and place bypass
capacitors as close as possible to the package.
3.6.2 ADC Analog Ground Pin (VSSAD)/ADC Voltage Reference Low Pin (VREFL)
The ADC analog portion uses VSSAD as its ground pin. Connect the VSSAD pin to the same voltage
potential as VSS.
NOTE
Route VSSAD cleanly to avoid any offset errors.
3.6.3 ADC Voltage In (VADIN)
VADIN is the input voltage signal from one of the eight ADC channels to the ADC module.
3.7 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADCLK)
3.7.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
COCO — Conversions Complete
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion.
COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It
always reads as 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1)
NOTE
The write function of the COCO bit is reserved. When writing to the ADSCR
register, always have a 0 in the COCO bit position.
Address: $003C
Bit 7654321Bit 0
Read:
COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
Reset:00011111
Figure 3-3. ADC Status and Control Register (ADSCR)
Analog-to-Digital Converter (ADC)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
44 Freescale Semiconductor
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared.
Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH4–ADCH0 — ADC Channel Select Bits
ADCH4–ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only eight
channels, AD7–AD0, are available on this MCU. The channels are detailed in Table 3-1. Care should
be taken when using a port pin as both an analog and digital input simultaneously to prevent switching
noise from corrupting the analog signal.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not being used.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
The voltage levels supplied from internal reference nodes, as specified in
Table 3-1, are used to verify the operation of the ADC converter both in production test and for user
applications.
Table 3-1. Mux Channel Select
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select
00000 PTB0/AD0
00001 PTB1/AD1
00010 PTB2/AD2
00011 PTB3/AD3
00100 PTB4/AD4
00101 PTB5/AD5
00110 PTB6/AD6
00111 PTB7/AD7
01000
Reserved↓↓↓↓↓
11100
11101 VREFH
11110 VREFL
1 1 1 1 1 ADC power off
NOTE:
If any unused channels are selected, the resulting ADC conversion will be unknown
or reserved.
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 45
3.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC
conversion completes.
3.7.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be set to
approximately 1 MHz.
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or CGMXCLK as the input clock source to generate the internal
ADC clock. Reset selects CGMXCLK as the ADC clock source.
Address: $003D
Bit 7654321Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset:00000000
= Unimplemented
Figure 3-4. ADC Data Register (ADR)
Address: $003E
Bit 7654321Bit 0
Read:
ADIV2 ADIV1 ADIV0 ADICLK
0000
Write:
Reset:00000000
= Unimplemented
Figure 3-5. ADC Clock Register (ADCLK)
Table 3-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC input clock ÷ 1
0 0 1 ADC input clock ÷ 2
0 1 0 ADC input clock ÷ 4
0 1 1 ADC input clock ÷ 8
1 X X ADC input clock ÷ 16
X = don’t care
Analog-to-Digital Converter (ADC)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
46 Freescale Semiconductor
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be
guaranteed.
1 = Internal bus clock
0 = External clock (CGMXCLK)
ADC input clock frequency
ADIV2 ADIV0–
----------------------------------------------------------------------- 1 M H z=
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 47
Chapter 4
Clock Generator Module (CGM)
4.1 Introduction
This section describes the clock generator module. The CGM generates the crystal clock signal,
CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL)
clock, CGMVCLK, divided by two. In user mode, CGMOUT is the clock from which the SIM derives the
system clocks, including the bus clock, which is at a frequency of CGMOUT/2. In monitor mode, PTC3
determines the bus clock. The PLL is a fully functional frequency generator designed for use with
low-frequency crystals. The PLL can generate an 8-MHz bus frequency using a 32.768-kHz crystal.
4.2 Features
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal
reference
• Low-frequency crystal operation with low-power operation and high-output frequency resolution
• Programmable prescaler for power-of-two increases in frequency
• Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
• Configuration register bit to allow oscillator operation during stop mode
4.3 Functional Description
The CGM consists of three major submodules:
• Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency
clock, CGMXCLK.
• Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock,
CGMVCLK.
• Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives
the system clocks from either CGMOUT or CGMXCLK.
Clock Generator Module (CGM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
48 Freescale Semiconductor
Figure 4-1. Block Diagram Highlighting CGM Block and Pins
SINGLE BREAKPOINT BREAK
MODULE
CLOCK GENERATOR MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
MONITOR MODULE
SERIAL PERIPHERAL
2-CHANNEL TIMER INTERFACE
MODULE 2
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS
USER ROM
USER RAM
MONITOR ROM
USER ROM VECTOR SPACE
SINGLE EXTERNAL
INTERRUPT MODULE
PORTA
DDRA
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
INTERNAL BUS
OSC1
OSC2
CGMXFC
RST(3)
IRQ(3)
INTERFACE MODULE
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7–
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
VDDAD/VREFH 8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6(1)
PTC5(1)
PTC4(1, 2)
PTC3(1, 2)
PTC2(1, 2)
PTC1(1, 2)
PTC0(1, 2)
PTD7/T2CH1(1)
PTD6/T2CH0(1)
PTD5/T1CH1(1)
PTD4/T1CH0(1)
PTD3/SPSCK(1)
PTD2/MOSI(1)
PTD1/MISO(1)
PTD0/SS(1)
PTE1/RxD
PTE0/TxD
VSSAD/VREFL
2-CHANNEL TIMER INTERFACE
MODULE 1
32-kHz OSCILLATOR
PHASE-LOCKED LOOP
SERIAL COMMUNICATIONS
INTERFACE MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
MASK OPTION REGISTER 1
MODULE
SECURITY
MODULE
MASK OPTION REGISTER 2
MODULE
POWER
VSS
VDD
VSSA
VDDA
1. Ports are software configurable with pullup device if input port.
2. Higher current drive port pins
3. Pin contains integrated pullup device
DDRB
PORTB
64 BYTES
PTA0/KBD0(1)
MC68HC08GP32A — 32,256 BYTES
512 BYTES
307 BYTES
36 BYTES
MC68HC08GP16A — 15,872 BYTES
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 49
Figure 4-2 shows the structure of the CGM.
Figure 4-2. CGM Block Diagram
BCS
PHASE
DETECTOR
LOOP
FILTER
FREQUENCY
DIVIDER
VOLTAGE
CONTROLLED
OSCILLATOR
AUTOMATIC
MODE
CONTROL
LOCK
DETECTOR
CLOCK
CGMXCLK
CGMOUT
CGMVDV
CGMVCLK
SIMOSCEN (FROM SIM)
OSCILLATOR (OSC)
INTERRUPT
CONTROL
CGMINT
CGMRDV
PLL ANALOG
÷
2
CGMRCLK
OSC2
OSC1
SELECT
CIRCUIT
VDDA CGMXFC VSSA
LOCK AUTO ACQ
VPR1–VPR0
PLLIE PLLF
MUL11–MUL0
REFERENCE
DIVIDER
VRS7–VRS0
FREQUENCY
DIVIDER
PRE1–PRE0
OSCSTOPENB
(FROM MOR)
(TO: SIM, TIMTB15A, ADC)
PHASE-LOCKED LOOP (PLL)
(TO SIM)
(TO SIM)
RDS3–RDS0
Clock Generator Module (CGM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
50 Freescale Semiconductor
4.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration
module (SIM) or the OSCSTOPENB bit in the mask option register enable the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator
circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
4.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
4.3.3 PLL Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Reference divider
• Frequency prescaler
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGM/XFC noise. The VCO frequency is bound to a
range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the
CGM/XFC pin changes the frequency within this range. By design, fVRS is equal to the nominal
center-of-range frequency, fNOM, (38.4 kHz) times a linear factor, L, and a power-of-two factor, E, or
(L ×2E)fNOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
fRCLK, and is fed to the PLL through a programmable modulo reference divider, which divides fRCLK by a
factor, R. The divider’s output is the final reference clock, CGMRDV, running at a frequency,
fRDV =f
RCLK/R. With an external crystal (30 kHz–100 kHz), always set R = 1 for specified performance.
With an external high-frequency clock source, use R to divide the external frequency to between 30 kHz
and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, fVCLK, is fed back through a programmable
prescale divider and a programmable modulo divider. The prescaler divides the VCO clock by a
power-of-two factor P and the modulo divider reduces the VCO clock by a factor, N. The dividers’ output is
the VCO feedback clock, CGMVDV, running at a frequency, fVDV =f
VCLK/(N ×2P). (See 4.3.6
Programming the PLL for more information.)
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 51
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, described in 4.3.4 Acquisition and Tracking Modes. The value of the external capacitor and the
reference frequency determine the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on
this comparison.
4.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
• Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. (See 4.5.2 PLL Bandwidth Control Register.)
• Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See 4.3.8 Base Clock Selector Circuit.) The PLL is automatically in
tracking mode when not in acquisition mode or when the ACQ bit is set.
4.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
Automatic mode is recommended for most users.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 4.5.2 PLL
Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set,
the VCO clock is safe to use as the source for the base clock. (See 4.3.8 Base Clock Selector Circuit.) If
the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. (See 4.6
Interrupts for information and precautions on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth control mode:
•The ACQ
bit (see 4.5.2 PLL Bandwidth Control Register) is a read-only indicator of the mode of the
filter. (See 4.3.4 Acquisition and Tracking Modes.)
•The ACQ
bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See 4.8 Acquisition/Lock Time Specifications for
more information.)
• The LOCK bit is a read-only indicator of the locked state of the PLL.
Clock Generator Module (CGM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
52 Freescale Semiconductor
• The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See 4.8 Acquisition/Lock Time Specifications for
more information.)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See 4.5.1 PLL Control Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
fBUSMAX.
The following conditions apply when in manual mode:
•ACQ
is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
• Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (see
4.8 Acquisition/Lock Time Specifications), after turning on the PLL by setting PLLON in the PLL
control register (PCTL).
• Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the
clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
4.3.6 Programming the PLL
The following procedure shows how to program the PLL.
NOTE
The round function in the following equations means that the real number
should be rounded to the nearest integer number.
1. Choose the desired bus frequency, fBUSDES.
2. Calculate the desired VCO frequency (four times the desired bus frequency).
3. Choose a practical PLL (crystal) reference frequency, fRCLK, and the reference clock divider, R.
Typically, the reference crystal is 32.768 kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of fRCLK/R. For stability and lock time reduction,
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, fVCLK, and the reference frequency, fRCLK, is
P, the power of two multiplier, and N, the range multiplier, are integers.
In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See Chapter 20 Electrical
Specifications. Choose the reference divider, R = 1. After choosing N and P, the actual bus
frequency can be determined using equation in 2 above.
fVCLKDES 4f
BUSDES
×=
fVCLK
2PN
R
----------- f RCLK
()=
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 53
When the tolerance on the bus frequency is tight, choose fRCLK to an integer divisor of fBUSDES,
and R = 1. If fRCLK cannot meet this requirement, use the following equation to solve for R with
practical choices of fRCLK, and choose the fRCLK that gives the lowest R.
4. Select a VCO frequency multiplier, N.
Reduce N/R to the lowest possible R.
5. If N is < Nmax, use P = 0. If N > Nmax, choose P using this table:
Then recalculate N:
6. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS.
7. Select the VCO’s power-of-two range multiplier E, according to this table:
8. Select a VCO linear range multiplier, L, where fNOM = 38.4 kHz
Current N Value P
0
1
2
3
Frequency Range E(1)
1. Do not program E to a value of 3.
0 < fVCLK < 8 MHz 0
8 MHz ≤ fVCLK < 16 MHz 1
16 MHz ≤ fVCLK < 32 MHz 2
R round RMAX
fVCLKDES
fRCLK
--------------------------
⎝⎠
⎜⎟
⎛⎞
integer fVCLKDES
fRCLK
--------------------------
⎝⎠
⎜⎟
⎛⎞
–
⎩⎭
⎨⎬
⎧⎫
×=
N round Rf
VCLKDES
×
fRCLK
-------------------------------------
⎝⎠
⎜⎟
⎛⎞
=
0N<N
max
≤
Nmax N<N
max 2×≤
Nmax 2×N<N
max 4×≤
Nmax 4×N<N
max 8×≤
N round Rf
VCLKDES
×
fRCLK 2P
×
-------------------------------------
⎝⎠
⎜⎟
⎛⎞
=
fVCLK 2PNR⁄×()fRCLK
×=
fBUS fVCLK
()4⁄=
L roundnfVCLK
2EfNOM
×
--------------------------
⎝⎠
⎜⎟
⎛⎞
=
Clock Generator Module (CGM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
54 Freescale Semiconductor
9. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS. The
center-of-range frequency is the midpoint between the minimum and maximum frequencies
attainable by the PLL.
For proper operation,
10. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS and fVCLKDES. For proper
operation, fVCLK must be within the application’s tolerance of fVCLKDES, and fVRS must be as close
as possible to fVCLK.
NOTE
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
11. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P.
b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E.
c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high
(PMSH), program the binary equivalent of N.
d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program the binary coded equivalent of
R.
Table 4-1 provides numeric examples (numbers are in hexadecimal notation):
Table 4-1. Numeric Example
fBUS fRCLK RNPEL
2.0 MHz 32.768 kHz 1 F5 0 0 D1
2.4576 MHz 32.768 kHz 1 12C 0 1 80
2.5 MHz 32.768 kHz 1 132 0 1 83
4.0 MHz 32.768 kHz 1 1E9 0 1 D1
4.9152 MHz 32.768 kHz 1 258 0 2 80
5.0 MHz 32.768 kHz 1 263 0 2 82
7.3728 MHz 32.768 kHz 1 384 0 2 C0
8.0 MHz 32.768 kHz 1 3D1 0 2 D0
fVRS L2
E
×()fNOM
=
fVRS fVCLK
–fNOM 2E
×
2
--------------------------
≤
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 55
4.3.7 Special Programming Exceptions
The programming method described in 4.3.6 Programming the PLL does not account for three possible
exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for
these exceptions:
• A 0 value for R or N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
(See 4.3.8 Base Clock Selector Circuit.)
4.3.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
4.3.9 CGM External Connections
In its typical configuration, the CGM requires up to nine external components. Five of these are for the
crystal oscillator and two or four are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 4-3.
Figure 4-3 shows only the logical representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
•Crystal, X
1
• Fixed capacitor, C1
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, RB
• Series resistor, RS
The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines. Refer to the
crystal manufacturer’s data for more information regarding values for C1 and C2.
Figure 4-3 also shows the external components for the PLL:
• Bypass capacitor, CBYP
• Filter network
Routing should be done with great care to minimize signal cross talk and noise.
See 20.16 Clock Generation Module Characteristics for capacitor and resistor values.
Clock Generator Module (CGM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
56 Freescale Semiconductor
Figure 4-3. CGM External Connections
4.4 I/O Signals
The following paragraphs describe the CGM I/O signals.
4.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
4.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
4.4.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is
connected to this pin. (See Figure 4-3.)
NOTE
To prevent noise problems, the filter network should be placed as close to
the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
OSC1
C1 C2
SIMOSCEN
CGMXCLK
RB
X1
RS
CBYP
OSC2 CGMXFC VDDA
Note: Filter network in box can be replaced with a signal capacitor, but will degrade stability.
VDD
OSCSTOPENB
(FROM CONFIG)
RF1 CF2
CF1
VSSA
I/O Signals
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 57
4.4.4 PLL Analog Power Pin (VDDA)
VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage
potential as the VDD pin.
NOTE
Route VDDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
4.4.5 PLL Analog Ground Pin (VSSA)
VSSA is a ground pin used by the analog portions of the PLL. Connect the VSSA pin to the same voltage
potential as the VSS pin.
NOTE
Route VSSA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
4.4.6 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and
PLL.
4.4.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB)
OSCSTOPENB is a bit in the mask option register that enables the oscillator to continue operating during
stop mode. If this bit is set, the Oscillator continues running during stop mode. If this bit is not set, the
oscillator is controlled by the SIMOSCEN signal which will disable the oscillator during stop mode.
4.4.8 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes
directly from the crystal oscillator circuit. Figure 4-3 shows only the logical relation of CGMXCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
4.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
4.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
Clock Generator Module (CGM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
58 Freescale Semiconductor
4.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL) — See 4.5.1 PLL Control Register.
• PLL bandwidth control register (PBWC) — See 4.5.2 PLL Bandwidth Control Register.
• PLL multiplier select register high (PMSH) — See 4.5.3 PLL Multiplier Select Register High.
• PLL multiplier select register low (PMSL) — See 4.5.4 PLL Multiplier Select Register Low.
• PLL VCO range select register (PMRS) — See 4.5.5 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS) — See 4.5.6 PLL Reference Divider Select Register.
Figure 4-4 is a summary of the CGM registers.
Addr.Register Name Bit 7654321Bit 0
$0036 PLL Control Register (PCTL)
See page 59.
Read:
PLLIE
PLLF
PLLON BCS PRE1 PRE0 VPR1 VPR0
Write:
Reset:00100000
$0037
PLL Bandwidth Control Reg-
ister (PBWC)
See page 60.
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:00000000
$0038
PLL Multiplier Select High
Register (PMSH)
See page 61.
Read:0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
$0039
PLL Multiplier Select Low
Register (PMSL)
See page 62.
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
$003A
PLL VCO Select Range
Register (PMRS)
See page 62.
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
$003B
PLL Reference Divider
Select Register (PMDS)
See page 63.
Read:0000
RDS3 RDS2 RDS1 RDS0
Write:
Reset:00000001
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
= Unimplemented R = Reserved
Figure 4-4. CGM I/O Register Summary
CGM Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 59
4.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits.
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting
the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the
PLLIE bit also is set. PLLF always reads as 0 when the AUTO bit in the PLL bandwidth control register
(PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 4.3.8 Base Clock Selector
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock,
CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. (See 4.3.8 Base Clock
Selector Circuit.) Reset clears the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base clock
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
Address: $0036
Bit 7654321Bit 0
Read:
PLLIE
PLLF
PLLON BCS PRE1 PRE0 VPR1 VPR0
Write:
Reset:00100000
= Unimplemented
Figure 4-5. PLL Control Register (PCTL)
Clock Generator Module (CGM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
60 Freescale Semiconductor
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
4.3.8 Base Clock Selector Circuit.)
PRE1 and PRE0 — Prescaler Program Bits
These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See
4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) PRE1 and PRE0 cannot be written when the
PLLON bit is set. Reset clears these bits.
NOTE
The value of P is normally 0 when using a 32.768-kHz crystal as the
reference.
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and 4.5.5 PLL VCO Range Select
Register.) controls the hardware center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when
the PLLON bit is set. Reset clears these bits.
4.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
Table 4-2. PRE1 and PRE0 Programming
PRE1 and PRE0 P Prescaler Multiplier
00 0 1
01 1 2
10 2 4
11 3 8
Table 4-3. VPR1 and VPR0 Programming
VPR1 and VPR0 E VCO Power-of-Two
Range Multiplier
00 0 1
01 1 2
10 2 4
11 3(1)
1. Do not program E to a value of 3.
8
CGM Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 61
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as 0 and
has no meaning. The write one function of this bit is reserved for test, so this bit must always be written
a 0. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode
or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
4.5.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the programming information for the high byte of
the modulo feedback divider.
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback divider that selects the VCO
frequency multiplier N. (See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) A value of $0000 in
Address: $0037
Bit 7654321Bit 0
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:00000000
= Unimplemented R = Reserved
Figure 4-6. PLL Bandwidth Control Register (PBWC)
Address: $0038
Bit 7654321Bit 0
Read:0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
= Unimplemented
Figure 4-7. PLL Multiplier Select Register High (PMSH)
Clock Generator Module (CGM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
62 Freescale Semiconductor
the multiplier select registers configures the modulo feedback divider the same as a value of $0001.
Reset initializes the registers to $0040 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
PMSH[7:4] — Unimplemented Bits
These bits have no function and always read as 0s.
4.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback divider that selects the VCO
frequency multiplier, N. (See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) MUL7–MUL0 cannot
be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to
$40 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
4.5.5 PLL VCO Range Select Register
NOTE
PMRS may be called PVRS on other HC08 derivatives.
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
Address: $0038
Bit 7654321Bit 0
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
Figure 4-8. PLL Multiplier Select Register Low (PMSL)
Address: $003A
Bit 7654321Bit 0
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
Figure 4-9. PLL VCO Range Select Register (PMRS)
CGM Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 63
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (see 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and 4.5.1 PLL Control Register), controls the
hardware center-of-range frequency, fVRS. VRS7–VRS0 cannot be written when the PLLON bit in the
PCTL is set. (See 4.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select
register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 4.3.8 Base
Clock Selector Circuit and 4.3.7 Special Programming Exceptions.) Reset initializes the register to $40
for a default range multiply value of 64.
NOTE
The VCO range select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
4.5.6 PLL Reference Divider Select Register
NOTE
PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the programming information for the modulo
reference divider.
RDS3–RDS0 — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects the reference division factor, R.
(See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) RDS7–RDS0 cannot be written when the
PLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the
reference divider the same as a value of $01. (See 4.3.7 Special Programming Exceptions.) Reset
initializes the register to $01 for a default divide value of 1.
NOTE
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
NOTE
The default divide value of 1 is recommended for all applications.
PMDS7–PMDS4 — Unimplemented Bits
These bits have no function and always read as 0s.
Address: $003B
Bit 7654321Bit 0
Read:0000
RDS3 RDS2 RDS1 RDS0
Write:
Reset:00000001
= Unimplemented
Figure 4-10. PLL Reference Divider Select Register (PMDS)
Clock Generator Module (CGM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
64 Freescale Semiconductor
4.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as 0.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry
into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can
be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock
frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency
sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software
performance or from exceeding stack limitations.
NOTE
Software can select the CGMVCLK divided by two as the CGMOUT source
even if the PLL is not locked (LOCK = 0). Therefore, software should make
sure the PLL is locked before setting the BCS bit.
4.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
4.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and
turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power.
Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is
immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from
wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost.
4.7.2 Stop Mode
If the OSCSTOPENB bit in the mask option register is cleared, then the STOP instruction disables the
CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two driving CGMOUT, the
PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal
clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from STOP, the
crystal clock divided by two drives CGMOUT and BCS remains clear.
If the OSCSTOPENB bit in the mask option register is set, then the phase locked loop is shut off but the
oscillator will continue to operate in stop mode.
4.7.3 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See Chapter 15 System Integration Module (SIM).)
Acquisition/Lock Time Specifications
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 65
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write the PLL control register during the break state without affecting the PLLF bit.
4.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design
parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock
times.
4.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or
when it suffers a noise hit. The tolerance is usually specified as a percentage of the step input or when
the output settles to the desired value plus or minus a percentage of the frequency change. Therefore,
the reaction time is constant in this definition, regardless of the size of the step input. For example,
consider a system with a 5 percent acquisition time tolerance. If a command instructs the system to
change from 0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach
1MHz±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers
a –100-kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5kHz.
Five kHz = 5% of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error between
the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may not even be registered. Typical
PLL applications prefer to use this definition because the system requires the output frequency to be
within a certain tolerance of the desired frequency regardless of the size of the initial error.
4.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV.
This frequency is the input to the phase detector and controls how often the PLL makes corrections. For
stability, the corrections must be small compared to the desired frequency, so several corrections are
required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make
these corrections. This parameter is under user control via the choice of crystal frequency fXCLK and the
R value programmed in the reference divider. (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and
4.5.6 PLL Reference Divider Select Register.)
Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by
adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage
changes for a given frequency error (thus change in charge) is proportional to the capacitance. The size
of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make
small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL
may not be able to adjust the voltage in a reasonable time. (See 4.8.3 Choosing a Filter.)
Clock Generator Module (CGM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
66 Freescale Semiconductor
Also important is the operating voltage potential applied to VDDA. The power supply potential alters the
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if
they vary within a known range at very slow speeds. Noise on the power supply is not acceptable,
because it causes small frequency errors which continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because the electrical characteristics of the
PLL change. The part operates as specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of the PLL. These factors include
noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the
circuit board, and even humidity or circuit board contamination.
4.8.3 Choosing a Filter
As described in 4.8.2 Parametric Influences on Reaction Time, the external filter network is critical to the
stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply
voltage.
Figure 4-11 shows two types of filter circuits. In low-cost applications, where stability and reaction time of
the PLL are not critical, the three component filter network of Figure 4-11 (B) can be replaced by a single
capacitor, CF, shown in Figure 4-11 (A). Refer to Table 4-4 for recommended filter components at various
reference frequencies. For reference frequencies between the values listed in the table, extrapolate to the
nearest common capacitor value. In general, a slightly larger capacitor provides more stability at the
expense of increased lock time.
Figure 4-11. PLL Filter
Table 4-4. Example Filter Component Values
fRCLK CF1 CF2 RF1 CF
32 kHz 0.15 µF 15 nF 2 K 0.22 µF
40 kHz 0.12 µF 12 nF 2 K 0.18 µF
50 kHz 0.10 µF 10 nF 2 K 0.18 µF
60 kHz 82 nF 8.2 nF 2 K 0.12 µF
70 kHz 68 nF 6.8 nF 2 K 0.12 µF
80 kHz 56 nF 5.6 nF 2 K 0.1 µF
90 kHz 56 nF 5.6 nF 2 K 0.1 µF
100 kHz 47 nF 4.7 nF 2 K 82 nF
CGMXFC
RF1 CF2
CF1
VSSA
CGMXFC
CF
VSSA
(A) (B)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 67
Chapter 5
Computer Operating Properly (COP)
5.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
mask option register.
5.2 Functional Description
Figure 5-1 shows the structure of the COP module.
Figure 5-1. COP Block Diagram
COPCTL WRITE
CGMXCLK RESET CIRCUIT
RESET STATUS REGISTER
INTERNAL RESET SOURCES
12-BIT SIM COUNTER
CLEAR ALL STAGES
6-BIT COP COUNTER
COP DISABLE
RESET
COPCTL WRITE
CLEAR
COP MODULE
COPEN (FROM SIM)
COP COUNTER
COP CLOCK
COP TIMEOUT
STOP INSTRUCTION
(FROM MOR)
COP RATE SEL
(FROM MOR)
CLEAR STAGES 5–12
Computer Operating Properly (COP)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
68 Freescale Semiconductor
The COP counter is a free-running 6-bit counter preceded by the 12-bit SIM counter. If not cleared by
software, the COP counter overflows and generates an asynchronous reset after 218 –2
4 or 213 –2
4
CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the mask option register.
With a 213 –2
4 CGMXCLK cycle overflow option, a 32.768-kHz crystal gives a COP timeout period of
250 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing
the COP counter and stages 12 through 5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held at VTST. During the break state,
VTST on the RST pin disables the COP.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
5.3 I/O Signals
The following paragraphs describe the signals shown in Figure 5-1.
5.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
5.3.2 STOP Instruction
The STOP instruction clears the SIM counter.
5.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 5.4 COP Control Register) clears the COP
counter and clears stages 12 through 5 of the SIM counter. Reading the COP control register returns the
low byte of the reset vector.
5.3.4 Power-On Reset
The power-on reset (POR) circuit clears the SIM counter 4096 CGMXCLK cycles after power-up.
5.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
5.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the mask option register. See
Chapter 11 Mask Option Registers (MOR2 and MOR1).
COP Control Register
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 69
5.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the mask option register. See
Chapter 11 Mask Option Registers (MOR2 and MOR1),
5.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
5.5 Interrupts
The COP does not generate CPU interrupt requests.
5.6 Monitor Mode
When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains
on the IRQ pin or the RST pin.
5.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
5.7.1 Wait Mode
The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout.
5.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available
that disables the STOP instruction. When the STOP bit in the mask option register has the STOP
instruction is disabled, execution of a STOP instruction results in an illegal opcode reset.
5.8 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on the RST pin.
Address: $FFFF
Bit 7654321Bit 0
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
Figure 5-2. COP Control Register (COPCTL)
Computer Operating Properly (COP)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
70 Freescale Semiconductor
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 71
Chapter 6
Central Processor Unit (CPU)
6.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a
description of the CPU instruction set, addressing modes, and architecture.
6.2 Features
Features of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
• Low-power stop and wait modes
6.3 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map.
Central Processor Unit (CPU)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
72 Freescale Semiconductor
Figure 6-1. CPU Registers
6.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
6.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 6-2. Accumulator (A)
Bit
151413121110987654321
Bit
0
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Figure 6-3. Index Register (H:X)
ACCUMULATOR (A)
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
V11HINZC
H X
0
0
0
0
7
15
15
15
70
CPU Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 73
6.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to
$00FF) frees direct address (page 0) space. For correct operation, the
stack pointer must point only to RAM locations.
6.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
151413121110987654321
Bit
0
Read:
Write:
Reset:0000000011111111
Figure 6-4. Stack Pointer (SP)
Bit
151413121110987654321
Bit
0
Read:
Write:
Reset: Loaded with vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
Central Processor Unit (CPU)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
74 Freescale Semiconductor
6.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code register.
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
Bit 7654321Bit 0
Read:
V11HINZC
Write:
Reset:X11X1XXX
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
Arithmetic/Logic Unit (ALU)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 75
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the
instructions and addressing modes and more detail about the architecture of the CPU.
6.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.5.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
6.5.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
6.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
Central Processor Unit (CPU)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
76 Freescale Semiconductor
6.7 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
Table 6-1. Instruction Set Summary (Sheet 1 of 6)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
Add with Carry A ← (A) + (M) + (C) –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry A ← (A) + (M) –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) ––––––IMM A7 ii 2
AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) ––––––IMM AF ii 2
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
Logical AND A ← (A) & (M) 0 – – –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
Arithmetic Shift Left
(Same as LSL) ––
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
Arithmetic Shift Right ––
DIR
INH
INH
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
ff
4
1
1
4
3
5
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
BCLR n, opr Clear Bit n in M Mn ← 0 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3
BGE opr Branch if Greater Than or Equal To
(Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 ––––––REL 90 rr 3
BGT opr Branch if Greater Than (Signed
Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 ––––––REL 92 rr 3
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 ––––––REL 22 rr 3
C
b0
b7
0
b0
b7
C
Instruction Set Summary
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 77
BHS rel Branch if Higher or Same
(Same as BCC) PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3
BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test (A) & (M) 0 – – –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
BLE opr Branch if Less Than or Equal To
(Signed Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 ––––––REL 93 rr 3
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 ––––––REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1––––––REL 91 rr 3
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 ––––––REL 2D rr 3
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3
BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 –––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 –––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET n,opr Set Bit n in M Mn ← 1 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BSR rel Branch to Subroutine
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
––––––REL AD rr 4
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
Compare and Branch if Equal
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
––––––
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
CLC Clear Carry Bit C ← 0 –––––0INH 98 1
CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2
Table 6-1. Instruction Set Summary (Sheet 2 of 6)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Central Processor Unit (CPU)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
78 Freescale Semiconductor
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Clear
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
0––01–
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
ff
ff
3
1
1
1
3
2
4
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Compare A with M (A) – (M) ––
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (One’s Complement)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
0––1
DIR
INH
INH
IX1
IX
SP1
33
43
53
63
73
9E63
dd
ff
ff
4
1
1
4
3
5
CPHX #opr
CPHX opr Compare H:X with M (H:X) – (M:M + 1) ––
IMM
DIR
65
75
ii ii+1
dd
3
4
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M (X) – (M) ––
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
DAA Decimal Adjust A (A)10 U––INH 72 2
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
Decrement and Branch if Not Zero
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
––––––
DIR
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff rr
rr
ff rr
5
3
3
5
4
6
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
–––
DIR
INH
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
dd
ff
ff
4
1
1
4
3
5
DIV Divide A ← (H:A)/(X)
H ← Remainder ––––INH 52 7
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Exclusive OR M with A A ← (A ⊕ M) 0–––
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
Increment
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
–––
DIR
INH
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
ff
ff
4
1
1
4
3
5
Table 6-1. Instruction Set Summary (Sheet 3 of 6)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Instruction Set Summary
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 79
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Jump PC ← Jump Address ––––––
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
––––––
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
Load A from M A ← (M) 0–––
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
LDHX #opr
LDHX opr Load H:X from M H:X ← (M:M + 1)0–––IMM
DIR
45
55
ii jj
dd
3
4
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
Load X from M X ← (M) 0–––
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AE
BE
CE
DE
EE
FE
9EEE
9EDE
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
Logical Shift Left
(Same as ASL) ––
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Logical Shift Right ––0
DIR
INH
INH
IX1
IX
SP1
34
44
54
64
74
9E64
dd
ff
ff
4
1
1
4
3
5
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
(M)Destination ← (M)Source
H:X ← (H:X) + 1 (IX+D, DIX+)
0–––
DD
DIX+
IMD
IX+D
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
4
4
4
MUL Unsigned multiply X:A ← (X) × (A) –0–––0INH 42 5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
Negate (Two’s Complement)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
––
DIR
INH
INH
IX1
IX
SP1
30
40
50
60
70
9E60
dd
ff
ff
4
1
1
4
3
5
NOP No Operation None ––––––INH 9D 1
NSA Nibble Swap A A ← (A[3:0]:A[7:4]) ––––––INH 62 3
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M A ← (A) | (M) 0 – – –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2
PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2
PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2
Table 6-1. Instruction Set Summary (Sheet 4 of 6)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
C
b0
b7
0
b0
b7
C0
Central Processor Unit (CPU)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
80 Freescale Semiconductor
PULA Pull A from Stack SP ← (SP + 1); Pull (A)––––––INH 86 2
PULH Pull H from Stack SP ← (SP + 1); Pull (H)––––––INH 8A 2
PULX Pull X from Stack SP ← (SP + 1); Pull (X)––––––INH 88 2
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry ––
DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E69
dd
ff
ff
4
1
1
4
3
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry ––
DIR
INH
INH
IX1
IX
SP1
36
46
56
66
76
9E66
dd
ff
ff
4
1
1
4
3
5
RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1
RTI Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
INH 80 7
RTS Return from Subroutine SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL) ––––––INH 81 4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry A ← (A) – (M) – (C) ––
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SEC Set Carry Bit C ← 1 –––––1INH 99 1
SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M M ← (A) 0–––
DIR
EXT
IX2
IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – – DIR 35 dd 4
STOP Enable Interrupts, Stop Processing,
Refer to MCU Documentation I ← 0; Stop Processing ––0–––INH 8E 1
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M M ← (X) 0–––
DIR
EXT
IX2
IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Subtract A ← (A) – (M) ––
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
Table 6-1. Instruction Set Summary (Sheet 5 of 6)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
C
b0
b7
b0
b7
C
Opcode Map
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 81
6.8 Opcode Map
See Table 6-2.
SWI Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
––1–––INH 83 9
TAP Transfer A to CCR CCR ← (A) INH 84 2
TAX Transfer A to X X ← (A) ––––––INH 97 1
TPA Transfer CCR to A A ← (CCR) ––––––INH 85 1
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – –
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
TSX Transfer SP to H:X H:X ← (SP) + 1 ––––––INH 95 2
TXA Transfer X to A A ← (X) ––––––INH 9F 1
TXS Transfer H:X to SP (SP) ← (H:X) – 1 ––––––INH 94 2
WAIT Enable Interrupts; Wait for Interrupt I bit ← 0; Inhibit CPU clocking
until interrupted ––0–––INH 8F 1
A Accumulator nAny bit
C Carry/borrow bit opr Operand (one or two bytes)
CCR Condition code register PC Program counter
dd Direct address of operand PCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte
DD Direct to direct addressing mode REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode
EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer
H Half-carry bit U Undefined
H Index register high byte V Overflow bit
hh ll High and low bytes of operand address in extended addressing X Index register low byte
I Interrupt mask Z Zero bit
ii Immediate operand byte & Logical AND
IMD Immediate source to direct destination addressing mode | Logical OR
IMM Immediate addressing mode ⊕Logical EXCLUSIVE OR
INH Inherent addressing mode ( ) Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX+ Indexed, no offset, post increment addressing mode # Immediate value
IX+D Indexed with post increment to direct addressing mode «Sign extend
IX1 Indexed, 8-bit offset addressing mode ←Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode ? If
IX2 Indexed, 16-bit offset addressing mode : Concatenated with
M Memory location Set or cleared
N Negative bit — Not affected
Table 6-1. Instruction Set Summary (Sheet 6 of 6)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
82 Freescale Semiconductor
Central Processor Unit (CPU)
Table 6-2. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
0 1 2 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F
0
5
BRSET0
3DIR
4
BSET0
2DIR
3
BRA
2REL
4
NEG
2DIR
1
NEGA
1INH
1
NEGX
1INH
4
NEG
2IX1
5
NEG
3 SP1
3
NEG
1IX
7
RTI
1INH
3
BGE
2REL
2
SUB
2IMM
3
SUB
2DIR
4
SUB
3EXT
4
SUB
3IX2
5
SUB
4 SP2
3
SUB
2IX1
4
SUB
3 SP1
2
SUB
1IX
1
5
BRCLR0
3DIR
4
BCLR0
2DIR
3
BRN
2REL
5
CBEQ
3DIR
4
CBEQA
3IMM
4
CBEQX
3IMM
5
CBEQ
3IX1+
6
CBEQ
4 SP1
4
CBEQ
2IX+
4
RTS
1INH
3
BLT
2REL
2
CMP
2IMM
3
CMP
2DIR
4
CMP
3EXT
4
CMP
3IX2
5
CMP
4 SP2
3
CMP
2IX1
4
CMP
3 SP1
2
CMP
1IX
2
5
BRSET1
3DIR
4
BSET1
2DIR
3
BHI
2REL
5
MUL
1INH
7
DIV
1INH
3
NSA
1INH
2
DAA
1INH
3
BGT
2REL
2
SBC
2IMM
3
SBC
2DIR
4
SBC
3EXT
4
SBC
3IX2
5
SBC
4 SP2
3
SBC
2IX1
4
SBC
3 SP1
2
SBC
1IX
3
5
BRCLR1
3DIR
4
BCLR1
2DIR
3
BLS
2REL
4
COM
2DIR
1
COMA
1INH
1
COMX
1INH
4
COM
2IX1
5
COM
3 SP1
3
COM
1IX
9
SWI
1INH
3
BLE
2REL
2
CPX
2IMM
3
CPX
2DIR
4
CPX
3EXT
4
CPX
3IX2
5
CPX
4 SP2
3
CPX
2IX1
4
CPX
3 SP1
2
CPX
1IX
4
5
BRSET2
3DIR
4
BSET2
2DIR
3
BCC
2REL
4
LSR
2DIR
1
LSRA
1INH
1
LSRX
1INH
4
LSR
2IX1
5
LSR
3 SP1
3
LSR
1IX
2
TA P
1INH
2
TXS
1INH
2
AND
2IMM
3
AND
2DIR
4
AND
3EXT
4
AND
3IX2
5
AND
4 SP2
3
AND
2IX1
4
AND
3 SP1
2
AND
1IX
5
5
BRCLR2
3DIR
4
BCLR2
2DIR
3
BCS
2REL
4
STHX
2DIR
3
LDHX
3IMM
4
LDHX
2DIR
3
CPHX
3IMM
4
CPHX
2DIR
1
TPA
1INH
2
TSX
1INH
2
BIT
2IMM
3
BIT
2DIR
4
BIT
3EXT
4
BIT
3IX2
5
BIT
4 SP2
3
BIT
2IX1
4
BIT
3 SP1
2
BIT
1IX
6
5
BRSET3
3DIR
4
BSET3
2DIR
3
BNE
2REL
4
ROR
2DIR
1
RORA
1INH
1
RORX
1INH
4
ROR
2IX1
5
ROR
3 SP1
3
ROR
1IX
2
PULA
1INH
2
LDA
2IMM
3
LDA
2DIR
4
LDA
3EXT
4
LDA
3IX2
5
LDA
4 SP2
3
LDA
2IX1
4
LDA
3 SP1
2
LDA
1IX
7
5
BRCLR3
3DIR
4
BCLR3
2DIR
3
BEQ
2REL
4
ASR
2DIR
1
ASRA
1INH
1
ASRX
1INH
4
ASR
2IX1
5
ASR
3 SP1
3
ASR
1IX
2
PSHA
1INH
1
TA X
1INH
2
AIS
2IMM
3
STA
2DIR
4
STA
3EXT
4
STA
3IX2
5
STA
4 SP2
3
STA
2IX1
4
STA
3 SP1
2
STA
1IX
8
5
BRSET4
3DIR
4
BSET4
2DIR
3
BHCC
2REL
4
LSL
2DIR
1
LSLA
1INH
1
LSLX
1INH
4
LSL
2IX1
5
LSL
3 SP1
3
LSL
1IX
2
PULX
1INH
1
CLC
1INH
2
EOR
2IMM
3
EOR
2DIR
4
EOR
3EXT
4
EOR
3IX2
5
EOR
4 SP2
3
EOR
2IX1
4
EOR
3 SP1
2
EOR
1IX
9
5
BRCLR4
3DIR
4
BCLR4
2DIR
3
BHCS
2REL
4
ROL
2DIR
1
ROLA
1INH
1
ROLX
1INH
4
ROL
2IX1
5
ROL
3 SP1
3
ROL
1IX
2
PSHX
1INH
1
SEC
1INH
2
ADC
2IMM
3
ADC
2DIR
4
ADC
3EXT
4
ADC
3IX2
5
ADC
4 SP2
3
ADC
2IX1
4
ADC
3 SP1
2
ADC
1IX
A
5
BRSET5
3DIR
4
BSET5
2DIR
3
BPL
2REL
4
DEC
2DIR
1
DECA
1INH
1
DECX
1INH
4
DEC
2IX1
5
DEC
3 SP1
3
DEC
1IX
2
PULH
1INH
2
CLI
1INH
2
ORA
2IMM
3
ORA
2DIR
4
ORA
3EXT
4
ORA
3IX2
5
ORA
4 SP2
3
ORA
2IX1
4
ORA
3 SP1
2
ORA
1IX
B
5
BRCLR5
3DIR
4
BCLR5
2DIR
3
BMI
2REL
5
DBNZ
3DIR
3
DBNZA
2INH
3
DBNZX
2INH
5
DBNZ
3IX1
6
DBNZ
4 SP1
4
DBNZ
2IX
2
PSHH
1INH
2
SEI
1INH
2
ADD
2IMM
3
ADD
2DIR
4
ADD
3EXT
4
ADD
3IX2
5
ADD
4 SP2
3
ADD
2IX1
4
ADD
3 SP1
2
ADD
1IX
C
5
BRSET6
3DIR
4
BSET6
2DIR
3
BMC
2REL
4
INC
2DIR
1
INCA
1INH
1
INCX
1INH
4
INC
2IX1
5
INC
3 SP1
3
INC
1IX
1
CLRH
1INH
1
RSP
1INH
2
JMP
2DIR
3
JMP
3EXT
4
JMP
3IX2
3
JMP
2IX1
2
JMP
1IX
D
5
BRCLR6
3DIR
4
BCLR6
2DIR
3
BMS
2REL
3
TST
2DIR
1
TSTA
1INH
1
TSTX
1INH
3
TST
2IX1
4
TST
3 SP1
2
TST
1IX
1
NOP
1INH
4
BSR
2REL
4
JSR
2DIR
5
JSR
3EXT
6
JSR
3IX2
5
JSR
2IX1
4
JSR
1IX
E
5
BRSET7
3DIR
4
BSET7
2DIR
3
BIL
2REL
5
MOV
3DD
4
MOV
2DIX+
4
MOV
3IMD
4
MOV
2IX+D
1
STOP
1INH *
2
LDX
2IMM
3
LDX
2DIR
4
LDX
3EXT
4
LDX
3IX2
5
LDX
4 SP2
3
LDX
2IX1
4
LDX
3 SP1
2
LDX
1IX
F
5
BRCLR7
3DIR
4
BCLR7
2DIR
3
BIH
2REL
3
CLR
2DIR
1
CLRA
1INH
1
CLRX
1INH
3
CLR
2IX1
4
CLR
3 SP1
2
CLR
1IX
1
WAIT
1INH
1
TXA
1INH
2
AIX
2IMM
3
STX
2DIR
4
STX
3EXT
4
STX
3IX2
5
STX
4 SP2
3
STX
2IX1
4
STX
3 SP1
2
STX
1IX
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with
IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment
*Pre-byte for stack pointer indexed instructions
0 High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal 0
5
BRSET0
3DIR
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
MSB
LSB
MSB
LSB
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 83
Chapter 7
External Interrupt (IRQ)
7.1 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
7.2 Features
Features of the IRQ module include:
• A dedicated external interrupt pin (IRQ)
• IRQ interrupt control bits
• Hysteresis buffer
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Internal pullup resistor
7.3 Functional Description
A low level applied to the external interrupt pin can latch a CPU interrupt request. Figure 7-1 shows the
structure of the IRQ module.
Figure 7-1. IRQ Module Block Diagram
IMASK
DQ
CK
CLR
IRQ
HIGH
INTERRUPT
TO MODE
SELECT
LOGIC
REQUEST
VDD
MODE
VOLTAGE
DETECT
IRQF
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
INTERNAL ADDRESS BUS
RESET
VDD
INTERNAL
PULLUP
DEVICE
ACK
IRQ
SYNCHRONIZER
External Interrupt (IRQ)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
84 Freescale Semiconductor
Figure 7-2. Block Diagram Highlighting IRQ Block and Pins
Interrupt signals on the IRQ pin are latched into the IRQ latch. The interrupt latch remains set until one of
the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the latch that caused the vector fetch.
• Software clear — Software can clear the interrupt latch by writing a 1 to the ACK bit in the interrupt
status and control register (INTSCR).
• Reset — A reset automatically clears the interrupt latch.
SINGLE BREAKPOINT BREAK
MODULE
CLOCK GENERATOR MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
MONITOR MODULE
SERIAL PERIPHERAL
2-CHANNEL TIMER INTERFACE
MODULE 2
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS
USER ROM
USER RAM
MONITOR ROM
USER ROM VECTOR SPACE
SINGLE EXTERNAL
INTERRUPT MODULE
PORTA
DDRA
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
INTERNAL BUS
OSC1
OSC2
CGMXFC
RST(3)
IRQ(3)
INTERFACE MODULE
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7–
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
VDDAD/VREFH 8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6(1)
PTC5(1)
PTC4(1, 2)
PTC3(1, 2)
PTC2(1, 2)
PTC1(1, 2)
PTC0(1, 2)
PTD7/T2CH1(1)
PTD6/T2CH0(1)
PTD5/T1CH1(1)
PTD4/T1CH0(1)
PTD3/SPSCK(1)
PTD2/MOSI(1)
PTD1/MISO(1)
PTD0/SS(1)
PTE1/RxD
PTE0/TxD
VSSAD/VREFL
2-CHANNEL TIMER INTERFACE
MODULE 1
32-kHz OSCILLATOR
PHASE-LOCKED LOOP
SERIAL COMMUNICATIONS
INTERFACE MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
MASK OPTION REGISTER 1
MODULE
SECURITY
MODULE
MASK OPTION REGISTER 2
MODULE
POWER
VSS
VDD
VSSA
VDDA
1. Ports are software configurable with pullup device if input port.
2. Higher current drive port pins
3. Pin contains integrated pullup device
DDRB
PORTB
64 BYTES
PTA0/KBD0(1)
MC68HC08GP32A — 32,256 BYTES
512 BYTES
307 BYTES
36 BYTES
MC68HC08GP16A — 15,872 BYTES
IRQ Pin
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 85
The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge
or falling-edge and low-level-triggered. The MODE bit in the INTSCR controls the triggering sensitivity of
the IRQ pin.
When set, the IMASK bit in the INTSCR masks all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
7.4 IRQ Pin
A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software
clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,
both of the following actions must occur to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a 1 to the ACK bit in
the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the
IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an
interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not
affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit
another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter
with the vector address at locations $FFFA and $FFFB.
• Return of the IRQ pin to a high level — As long as the IRQ pin is low, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order.
The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not
affected by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
Addr.Register Name Bit 7654321Bit 0
$001D
IRQ Status and Control
Register (INTSCR)
See page 86.
Read:0000IRQF0
IMASK MODE
Write: ACK
Reset:00000000
= Unimplemented
Figure 7-3. IRQ I/O Register Summary
External Interrupt (IRQ)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
86 Freescale Semiconductor
7.5 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during
the break state. See Chapter 19 Development Support.
To allow software to clear the IRQ latch during a break interrupt, write a 1 to the BCFE bit. If the latch is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default
state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on
the IRQ interrupt flag.
7.6 IRQ Status and Control Register
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
IRQF — IRQ Flag Bit
This read-only status bit is set when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
Address: $001D
Bit 7654321Bit 0
Read:0000IRQF0
IMASK MODE
Write: ACK
Reset:00000000
= Unimplemented
Figure 7-4. IRQ Status and Control Register (INTSCR)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 87
Chapter 8
Keyboard Interrupt (KBI) Module
8.1 Introduction
The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are
accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup
device is also enabled on the pin.
8.2 Features
Features include:
• Eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard
interrupt mask
• Hysteresis buffers
• Programmable edge-only or edge- and level- interrupt sensitivity
• Exit from low-power modes
• I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port
bit(s)
8.3 Functional Description
Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or
disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its
internal pullup device. A falling edge applied to an enabled keyboard interrupt pin latches a keyboard
interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK
bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an
interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on
one pin because another pin is still low, software can disable the latter pin while it is low.
• If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as
long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled.
Keyboard Interrupt (KBI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
88 Freescale Semiconductor
Figure 8-1. Block Diagram Highlighting KBI Block and Pins
SINGLE BREAKPOINT BREAK
MODULE
CLOCK GENERATOR MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
MONITOR MODULE
SERIAL PERIPHERAL
2-CHANNEL TIMER INTERFACE
MODULE 2
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS
USER ROM
USER RAM
MONITOR ROM
USER ROM VECTOR SPACE
SINGLE EXTERNAL
INTERRUPT MODULE
PORTA
DDRA
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
INTERNAL BUS
OSC1
OSC2
CGMXFC
RST(3)
IRQ(3)
INTERFACE MODULE
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7–
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
VDDAD/VREFH 8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6(1)
PTC5(1)
PTC4(1, 2)
PTC3(1, 2)
PTC2(1, 2)
PTC1(1, 2)
PTC0(1, 2)
PTD7/T2CH1(1)
PTD6/T2CH0(1)
PTD5/T1CH1(1)
PTD4/T1CH0(1)
PTD3/SPSCK(1)
PTD2/MOSI(1)
PTD1/MISO(1)
PTD0/SS(1)
PTE1/RxD
PTE0/TxD
VSSAD/VREFL
2-CHANNEL TIMER INTERFACE
MODULE 1
32-kHz OSCILLATOR
PHASE-LOCKED LOOP
SERIAL COMMUNICATIONS
INTERFACE MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
MASK OPTION REGISTER 1
MODULE
SECURITY
MODULE
MASK OPTION REGISTER 2
MODULE
POWER
VSS
VDD
VSSA
VDDA
1. Ports are software configurable with pullup device if input port.
2. Higher current drive port pins
3. Pin contains integrated pullup device
DDRB
PORTB
64 BYTES
PTA0/KBD0(1)
MC68HC08GP32A — 32,256 BYTES
512 BYTES
307 BYTES
36 BYTES
MC68HC08GP16A — 15,872 BYTES
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 89
Functional Description
Figure 8-2. Keyboard Module Block Diagram
Addr.Register Name Bit 7654321Bit 0
$001A
Keyboard Status
and Control Register
(INTKBSCR)
See page 92.
Read:0000KEYF0
IMASKK MODEK
Write: ACKK
Reset:00000000
$001B
Keyboard Interrupt Enable
Register
(INTKBIER)
See page 92.
Read:
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Write:
Reset:00000000
= Unimplemented
Figure 8-3. I/O Register Summary
KB0IE
KB7IE
.
.
.KEYBOARD
INTERRUPT
DQ
CK
CLR
VDD
MODEK
IMASKK REQUEST
VECTOR FETCH
DECODER
ACKK
INTERNAL BUS
RESET
TO PULLUP ENABLE
KBD7
KBD0
TO PULLUP ENABLE
SYNCHRONIZER
KEYF
Keyboard Interrupt (KBI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
90 Freescale Semiconductor
If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low-level sensitive, and both
of the following actions must occur to clear a keyboard interrupt request:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the interrupt request. Software may generate the interrupt acknowledge signal by writing a 1 to the
ACKK bit in the keyboard status and control register (INTKBSCR). The ACKK bit is useful in
applications that poll the keyboard interrupt pins and require software to clear the keyboard
interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also
prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on
the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another
interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program
counter with the vector address at locations $FFE0 and $FFE1.
• Return of all enabled keyboard interrupt pins to high level— As long as any enabled keyboard
interrupt pin is low, the keyboard interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to a high level may
occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt pin stays low.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes
it useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the
pin as an input and read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a 0 for software to read the
pin.
8.4 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a 1. Therefore, a
false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Low-Power Modes
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 91
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction
register A.
2. Write 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
8.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
8.5.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
8.5.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
8.6 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state.
To allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the BCFE bit.
If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the
break state has no effect. See 8.7.1 Keyboard Status and Control Register.
8.7 I/O Registers
These registers control and monitor operation of the keyboard module:
• Keyboard status and control register (INTKBSCR)
• Keyboard interrupt enable register (INTKBIER)
8.7.1 Keyboard Status and Control Register
The keyboard status and control register:
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
Keyboard Interrupt (KBI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
92 Freescale Semiconductor
Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as 0. Reset
clears ACKK.
IMASKK — Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating
interrupt requests. Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears
MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
8.7.2 Keyboard Interrupt Enable Register
The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard
interrupt pin.
KBIE7–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt
requests. Reset clears the keyboard interrupt enable register.
1 = PTAx pin enabled as keyboard interrupt pin
0 = PTAx pin not enabled as keyboard interrupt pin
Address: $001A
Bit 7654321Bit 0
Read:0000KEYF0
IMASKK MODEK
Write: ACKK
Reset:00000000
= Unimplemented
Figure 8-4. Keyboard Status and Control Register (INTKBSCR)
Address: $001B
Bit 7654321Bit 0
Read:
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Write:
Reset:00000000
Figure 8-5. Keyboard Interrupt Enable Register (INTKBIER)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 93
Chapter 9
Low-Power Modes
9.1 Introduction
The MCU may enter two low-power modes: wait mode and stop mode. They are common to all HC08
MCUs and are entered through instruction execution. This section describes how each module acts in the
low-power modes.
9.1.1 Wait Mode
The WAIT instruction puts the MCU in a low-power standby mode in which the CPU clock is disabled but
the bus clock continues to run. Power consumption can be further reduced by disabling the LVI module
and/or the timebase module through bits in the mask option (MOR) register. See Chapter 11 Mask Option
Registers (MOR2 and MOR1).
9.1.2 Stop Mode
Stop mode is entered when a STOP instruction is executed. The CPU clock is disabled and the bus clock
is disabled if the OSCSTOPENB bit in the MOR register is 0. See Chapter 11 Mask Option Registers
(MOR2 and MOR1).
9.2 Analog-to-Digital Converter (ADC)
9.2.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the
WAIT instruction.
9.2.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one
conversion cycle to stabilize the analog circuitry.
Low-Power Modes
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
94 Freescale Semiconductor
9.3 Break Module (BRK)
9.3.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if the SBSW bit in the break status register is set.
9.3.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states.
9.4 Central Processor Unit (CPU)
9.4.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
9.4.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
9.5 Clock Generator Module (CGM)
9.5.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off
the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications that require the PLL to wake the
MCU from wait mode also can deselect the PLL output without turning off the PLL.
9.5.2 Stop Mode
If the OSCSTOPENB bit in the MOR register is cleared (default), then the STOP instruction disables the
CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the OSCSTOPENB bit in the MOR register is set, then the phase locked loop is shut off but the oscillator
will continue to operate in stop mode.
Computer Operating Properly Module (COP)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 95
9.6 Computer Operating Properly Module (COP)
9.6.1 Wait Mode
The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout.
9.6.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the SIM counter. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
The STOP bit in the MOR register enables the STOP instruction. To prevent inadvertently turning off the
COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit.
9.7 External Interrupt Module (IRQ)
9.7.1 Wait Mode
The IRQ module remains active in wait mode. Clearing the IMASK bit in the IRQ status and control
register enables IRQ CPU interrupt requests to bring the MCU out of wait mode.
9.7.2 Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK bit in the IRQ status and control
register enables IRQ CPU interrupt requests to bring the MCU out of stop mode.
9.8 Keyboard Interrupt Module (KBI)
9.8.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
9.8.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
9.9 Low-Voltage Inhibit Module (LVI)
9.9.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
9.9.2 Stop Mode
If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
Low-Power Modes
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
96 Freescale Semiconductor
9.10 Serial Communications Interface Module (SCI)
9.10.1 Wait Mode
The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module
can bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
9.10.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI
module operation resumes after the MCU exits stop mode.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
9.11 Serial Peripheral Interface Module (SPI)
9.11.1 Wait Mode
The SPI module remains active in wait mode. Any enabled CPU interrupt request from the SPI module
can bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
9.11.2 Stop Mode
The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI
operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.
9.12 Timer Interface Module (TIM1 and TIM2)
9.12.1 Wait Mode
The TIM remains active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU
out of wait mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
9.12.2 Stop Mode
The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the
TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
Timebase Module (TBM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 97
9.13 Timebase Module (TBM)
9.13.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before enabling the WAIT instruction.
9.13.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been
enabled to operate during stop mode through the OSCSTOPENB bit in the MOR register. The timebase
module can be used in this mode to generate a periodic wakeup from stop mode.
If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active
during stop mode. In stop mode, the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the power consumption by stopping
the timebase before enabling the STOP instruction.
9.14 Exiting Wait Mode
These events restart the CPU clock and load the program counter with the reset vector or with an interrupt
vector:
• External reset — A low on the RST pin resets the MCU and loads the program counter with the
contents of locations $FFFE and $FFFF.
• External interrupt — A high-to-low transition on the external interrupt pin (IRQ pin) loads the
program counter with the contents of locations: $FFFA and $FFFB; IRQ pin.
• Break interrupt — In emulation mode, a break interrupt loads the program counter with the contents
of $FFFC and $FFFD.
• Computer operating properly module (COP) reset — A timeout of the COP counter resets the MCU
and loads the program counter with the contents of $FFFE and $FFFF.
• Low-voltage inhibit module (LVI) reset — A power supply voltage below the VTRIPF voltage resets
the MCU and loads the program counter with the contents of locations $FFFE and $FFFF.
• Clock generator module (CGM) interrupt — A CPU interrupt request from the phase-locked loop
(PLL) loads the program counter with the contents of $FFF8 and $FFF9.
• Keyboard module (KBI) interrupt — A CPU interrupt request from the KBI module loads the
program counter with the contents of $FFE0 and $FFE1.
• Timer 1 interface module (TIM1) interrupt — A CPU interrupt request from the TIM1 loads the
program counter with the contents of:
– $FFF2 and $FFF3; TIM1 overflow
– $FFF4 and $FFF5; TIM1 channel 1
– $FFF6 and $FFF7; TIM1 channel 0
• Timer 2 interface module (TIM2) interrupt — A CPU interrupt request from the TIM2 loads the
program counter with the contents of:
– $FFEC and $FFED; TIM2 overflow
– $FFEE and $FFEF; TIM2 channel 1
– $FFF0 and $FFF1; TIM2 channel 0
Low-Power Modes
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
98 Freescale Semiconductor
• Serial peripheral interface module (SPI) interrupt — A CPU interrupt request from the SPI loads
the program counter with the contents of:
– $FFE8 and $FFE9; SPI transmitter
– $FFEA and $FFEB; SPI receiver
• Serial communications interface module (SCI) interrupt — A CPU interrupt request from the SCI
loads the program counter with the contents of:
– $FFE2 and $FFE3; SCI transmitter
– $FFE4 and $FFE5; SCI receiver
– $FFE6 and $FFE7; SCI receiver error
• Analog-to-digital converter module (ADC) interrupt — A CPU interrupt request from the ADC loads
the program counter with the contents of: $FFDE and $FFDF; ADC conversion complete.
• Timebase module (TBM) interrupt — A CPU interrupt request from the TBM loads the program
counter with the contents of: $FFDC and $FFDD; TBM interrupt.
9.15 Exiting Stop Mode
These events restart the system clocks and load the program counter with the reset vector or with an
interrupt vector:
• External reset — A low on the RST pin resets the MCU and loads the program counter with the
contents of locations $FFFE and $FFFF.
• External interrupt — A high-to-low transition on an external interrupt pin loads the program counter
with the contents of locations:
– $FFFA and $FFFB; IRQ pin
– $FFE0 and $FFE1; keyboard interrupt pins
• Low-voltage inhibit (LVI) reset — A power supply voltage below the VTRIPF voltage resets the MCU
and loads the program counter with the contents of locations $FFFE and $FFFF.
• Timebase module (TBM) interrupt — A TBM interrupt loads the program counter with the contents
of locations $FFDC and $FFDD when the timebase counter has rolled over. This allows the TBM
to generate a periodic wakeup from stop mode.
Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit
stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external
interrupt.
The short stop recovery bit, SSREC, in the MOR register controls the oscillator stabilization delay during
stop recovery. Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK
cycles.
NOTE
Use the full stop recovery time (SSREC = 0) in applications that use an
external crystal unless the OSCSTOPENB bit is set.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 99
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin
and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.
10.2 Features
Features of the LVI module include:
• Programmable LVI reset
• Selectable LVI trip voltage
• Programmable stop mode operation
10.3 Functional Description
Figure 10-1 shows the structure of the LVI module. The LVI module contains a bandgap reference circuit
and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor VDD voltage.
Clearing the LVI reset disable bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls
below a voltage, VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in
stop mode. Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, VTRIPF, to be
configured for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, VTRIPF, to be
configured for 3-V operation. The actual trip points are shown in Chapter 20 Electrical Specifications.
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the mask option register. See 11.2 Mask Option
Registers for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset
until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 15.3.2.5 Low-Voltage
Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The output of the comparator
controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
10.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling
the LVIOUT bit. In the mask option register, the LVIPWRD bit must be 0 to enable the LVI module, and
the LVIRSTD bit must be 1 to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when VDD falls below the VTRIPF level. In the mask option register, the
LVIPWRD and LVIRSTD bits must be 0 to enable the LVI module and to enable LVI resets.
Low-Voltage Inhibit (LVI)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
100 Freescale Semiconductor
Figure 10-1. LVI Module Block Diagram
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until
VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than
VTRIPF by the hysteresis voltage, VHYS.
10.3.4 LVI Trip Selection
The LVI5OR3 bit in the mask option register selects whether the LVI is configured for 5-V or 3-V
protection.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than this. (See
Chapter 20 Electrical Specifications for the actual trip point voltages.)
Addr.Register Name Bit 7654321Bit 0
$FE0C
LVI Status Register
(LVISR)
See page 101.
Read:LVIOUT0000000
Write:
Reset:00000000
= Unimplemented
Figure 10-2. LVI I/O Register Summary
LOW VDD
DETECTOR
LVIPWRD
STOP INSTRUCTION
LVISTO P
LVI RESET
LVIOUT
VDD > LVITrip = 0
VDD ≤ LVITrip = 1
FROM MOR
FROM MOR
VDD
FROM MOR
LVIRSTD
LVI5OR3
FROM MOR
LVI Status Register
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 101
10.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage. See
Table 10-1. Reset clears the LVIOUT bit.
10.5 LVI Interrupts
The LVI module does not generate interrupt requests.
10.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.6.2 Stop Mode
If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
Address: $FE0C
Bit 7654321Bit 0
Read:LVIOUT0000000
Write:
Reset:00000000
= Unimplemented
Figure 10-3. LVI Status Register (LVISR)
Table 10-1. LVIOUT Bit Indication
VDD LVIOUT
VDD > VTRIPR 0
VDD < VTRIPF 1
VTRIPF < VDD < VTRIPR Previous value
Low-Voltage Inhibit (LVI)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
102 Freescale Semiconductor
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 103
Chapter 11
Mask Option Registers (MOR2 and MOR1)
11.1 Introduction
The two mask option registers at $001E and $001F (see Figure 11-1 and Figure 11-2) are read-only
registers. They are defined by mask options (hard-wired connections) specified at the same time as the
read-only memory (ROM) code submission.
11.2 Mask Option Registers
TBMCLKSEL — Timebase Clock Select Bit
TBMCLKSEL enables an enable of the extra divide-by-128 prescaler in the timebase module. Setting
this bit enables the extra prescaler and clearing this bit disables it. Refer to Table 17-1. Timebase
Divider Selection for timebase divider selection details
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
OSCSTOPENB enables the oscillator to continue operating during stop mode. Setting the
OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode. This is useful
for driving the timebase module to allow it to generate periodic wakeup while in stop mode. (See 9.5
Clock Generator Module (CGM) subsection 9.5.2 Stop Mode.)
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of this bit affects the frequency at
which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
Address: $001E
Bit 765432 1Bit 0
Read:00000
TBMCLK-
SEL
OSCS-
TOPENB SCIBDSRC
Write:
Reset: Mask defined
= Unimplemented
Figure 11-1. Mask Option Register 2 (MOR2)
Mask Option Registers (MOR2 and MOR1)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
104 Freescale Semiconductor
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. See Chapter 5 Computer Operating Properly (COP).
1 = COP timeout period = 213 – 24 CGMXCLK cycles
0 = COP timeout period = 218 – 24 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
See 9.5.2 Stop Mode.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. See Chapter 10 Low-Voltage Inhibit (LVI).
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. See Chapter 10 Low-Voltage Inhibit (LVI).
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. See Chapter 10 Low-Voltage Inhibit
(LVI). The voltage mode selected for the LVI should match the operating VDD. See Chapter 20
Electrical Specifications for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode
0 = LVI operates in 3-V mode
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLKC cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
The short stop recovery delay can be enabled when using a crystal and the OSCSTOPENB bit is set.
The short stop recovery delay can be enabled when an external oscillator is used, regardless of the
OSCSTOPENB setting.
The short stop recovery delay must be disabled when the OSCSTOPENB bit is clear and a crystal is
used.
Address: $001F
Bit 7654321Bit 0
Read: COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD
Write:
Reset: Mask defined
Figure 11-2. Mask Option Register 1 (MOR1)
Mask Option Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 105
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 5 Computer Operating Properly (COP).
1 = COP module disabled
0 = COP module enabled
Mask Option Registers (MOR2 and MOR1)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
106 Freescale Semiconductor
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 107
Chapter 12
Input/Output (I/O) Ports
12.1 Introduction
Thirty-three (33) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable
as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with
pullup devices if configured as input port bits. The pullup devices are automatically and dynamically
disabled when a port bit is switched to output mode.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr. Register Name Bit 7654321Bit 0
$0000
Port A Data Register
(PTA)
See page 110.
Read:
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
Reset: Unaffected by reset
$0001
Port B Data Register
(PTB)
See page 112.
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
$0002
Port C Data Register
(PTC)
See page 114.
Read: 0
PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
Write:
Reset: Unaffected by reset
$0003
Port D Data Register
(PTD)
See page 116.
Read:
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write:
Reset: Unaffected by reset
$0004
Data Direction Register A
(DDRA)
See page 110.
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
$0005
Data Direction Register B
(DDRB)
See page 113.
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
= Unimplemented
Figure 12-1. I/O Port Register Summary
Input/Output (I/O) Ports
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
108 Freescale Semiconductor
$0006
Data Direction Register C
(DDRC)
See page 114.
Read: 0
DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset:00000000
$0007
Data Direction Register D
(DDRD)
See page 117.
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset:00000000
$0008
Port E Data Register
(PTE)
See page 119.
Read:000000
PTE1 PTE0
Write:
Reset: Unaffected by reset
$000C
Data Direction Register E
(DDRE)
See page 120.
Read:000000
DDRE1 DDRE0
Write:
Reset:00000000
$000D
Port A Input Pullup Enable
Register (PTAPUE)
See page 112.
Read:
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:00000000
$000E
Port C Input Pullup Enable
Register (PTCPUE)
See page 116.
Read: 0
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
Write:
Reset:00000000
$000F
Port D Input Pullup Enable
Register (PTDPUE)
See page 119.
Read:
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Write:
Reset:00000000
Addr. Register Name Bit 7654321Bit 0
= Unimplemented
Figure 12-1. I/O Port Register Summary (Continued)
Introduction
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 109
Table 12-1. Port Control Register Bits Summary
Port Bit DDR Module Control Pin
A
0 DDRA0
KBD
KBIE0 PTA0/KBD0
1 DDRA1 KBIE1 PTA1/KBD1
2 DDRA2 KBIE2 PTA2/KBD2
3 DDRA3 KBIE3 PTA3/KBD3
4 DDRA4 KBIE4 PTA4/KBD4
5 DDRA5 KBIE5 PTA5/KBD5
6 DDRA6 KBIE6 PTA6/KBD6
7 DDRA7 KBIE7 PTA7/KBD7
B
0 DDRB0
ADC ADCH4–ADCH0
PTB0/AD0
1 DDRB1 PTB1/AD1
2 DDRB2 PTB2/AD2
3 DDRB3 PTB3/AD3
4 DDRB4 PTB4/AD4
5 DDRB5 PTB5/AD5
6 DDRB6 PTB6/AD6
7 DDRB7 PTB7/AD7
C
0 DDRC0 PTC0
1 DDRC1 PTC1
2 DDRC2 PTC2
3 DDRC3 PTC3
4 DDRC4 PTC4
5 DDRC5 PTC5
6 DDRC6 PTC6
D
0 DDRD0
SPI SPE
PTD0/SS
1 DDRD1 PTD1/MISO
2 DDRD2 PTD2/MOSI
3 DDRD3 PTD3/SPSCK
4 DDRD4 TIM1 ELS0B:ELS0A PTD4/T1CH0
5 DDRD5 ELS1B:ELS1A PTD5/T1CH1
6 DDRD6 TIM2 ELS0B:ELS0A PTD6/T2CH0
7 DDRD7 ELS1B:ELS1A PTD7/T2CH1
E0 DDRE0 SCI ENSCI PTE0/TxD
1 DDRE1 PTE1/RxD
Input/Output (I/O) Ports
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
110 Freescale Semiconductor
12.2 Port A
Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI)
module. Port A also has software configurable pullup devices if configured as an input port.
12.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the eight port A pins.
PTA7–PTA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
KBD7–KBD0 — Keyboard Inputs
The keyboard interrupt enable bits, KBIE7–KBIE0, in the keyboard interrupt control register
(INTKBIER) enable the port A pins as external interrupt pins. See Chapter 8 Keyboard Interrupt (KBI)
Module.
12.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a
1 to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
DDRA7–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA7–DDRA0, configuring all port
A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Address: $0000
Bit 7654321Bit 0
Read:
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
Reset: Unaffected by reset
Alternate
Function: KBD7 KBD6 KBD5 KBD4 KBD3 KBD2 KBD1 KBD0
Figure 12-2. Port A Data Register (PTA)
Address: $0004
Bit 7654321Bit 0
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
Figure 12-3. Data Direction Register A (DDRA)
Port A
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 111
Figure 12-4 shows the port A I/O logic.
Figure 12-4. Port A I/O Circuit
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-2 summarizes the operation of the port A pins.
Table 12-2. Port A Pin Functions
PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode Accesses to DDRA Accesses to PTA
Read/Write Read Write
10
X(1) Input, VDD(4) DDRA7–DDRA0 Pin PTA7–PTA0(3)
00X
Input, Hi-Z(2) DDRA7–DDRA0 Pin PTA7–PTA0(3)
X 1 X Output DDRA7–DDRA0 PTA7–PTA0 PTA7–PTA0
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
DDRAx
PTAx
INTERNAL DATA BUS
VDD
PTAPUEx
INTERNAL
PULLUP
DEVICE
Input/Output (I/O) Ports
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
112 Freescale Semiconductor
12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the eight port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
PTAPUE7–PTAPUE0 — Port A Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port A pin configured to have internal pullup
0 = Corresponding port A pin has internal pullup disconnected
12.3 Port B
Port B is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter
(ADC) module.
12.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port pins.
PTB7–PTB0 — Port B Data Bits
These read/write bits are software-programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
AD7–AD0 — Analog-to-Digital Input Bits
AD7–AD0 are pins used for the input channels to the analog-to-digital converter module. The channel
select bits in the ADC status and control register define which port B pin will be used as an ADC input
and overrides any control from the port I/O logic by forcing that pin as the input to the analog circuitry.
NOTE
Care must be taken when reading port B while applying analog voltages to
AD7–AD0 pins. If the appropriate ADC channel is not enabled, excessive
current drain may occur if analog voltages are applied to the PTBx/ADx pin,
while PTB is read as a digital input. Those ports not selected as analog
input channels are considered digital I/O ports.
Address: $000D
Bit 7654321Bit 0
Read: PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:00000000
Figure 12-5. Port A Input Pullup Enable Register (PTAPUE)
Address: $0001
Bit 7654321Bit 0
Read: PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
Alternate
Function: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Figure 12-6. Port B Data Register (PTB)
Port B
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 113
12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
DDRB7–DDRB0 — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB7–DDRB0, configuring all port
B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 12-8 shows the port B I/O logic.
Figure 12-8. Port B I/O Circuit
When bit DDRBx is a 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-3 summarizes the operation of the port B pins.
Address: $0005
Bit 7654321Bit 0
Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
Figure 12-7. Data Direction Register B (DDRB)
Table 12-3. Port B Pin Functions
DDRB Bit PTB Bit I/O Pin Mode Accesses to DDRB Accesses to PTB
Read/Write Read Write
0X(1) Input, Hi-Z(2) DDRB7–DDRB0 Pin PTB7–PTB0(3)
1 X Output DDRB7–DDRB0 PTB7–PTB0 PTB7–PTB0
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
READ PTB ($0001)
PTBx
DDRBx
PTBx
INTERNAL DATA BUS
Input/Output (I/O) Ports
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
114 Freescale Semiconductor
12.4 Port C
Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup
devices if configured as an input port.
12.4.1 Port C Data Register
The port C data register (PTC) contains a data latch for each of the seven port C pins.
NOTE
Bit 6 and bit 5 of PTC are not available in the 42-pin shrink dual in-line
package.
PTC6–PTC0 — Port C Data Bits
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data.
12.4.2 Data Direction Register C
Data direction register C (DDRC) determines whether each port C pin is an input or an output. Writing a
1 to a DDRC bit enables the output buffer for the corresponding port C pin; a 0 disables the output buffer.
DDRC6–DDRC0 — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears DDRC6–DDRC0, configuring all port
C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Address: $0002
Bit 7654321Bit 0
Read: 0
PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 12-9. Port C Data Register (PTC)
Address: $0006
Bit 7654321Bit 0
Read: 0
DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset:00000000
= Unimplemented
Figure 12-10. Data Direction Register C (DDRC)
Port C
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 115
Figure 12-11 shows the port C I/O logic.
NOTE
For those devices packaged in a 42-pin shrink dual in-line package, PTC5
and PTC6 are connected to ground internally. DDRC5 and DDRC6 should
be set to a 0 to configure PTC5 and PTC6 as inputs.
Figure 12-11. Port C I/O Circuit
When bit DDRCx is a 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a 0,
reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port C pins.
Table 12-4. Port C Pin Functions
PTCPUE Bit DDRC Bit PTC Bit I/O Pin Mode Accesses to DDRC Accesse to PTC
Read/Write Read Write
10
X(1) Input, VDD(4) DDRC6–DDRC0 Pin PTC6–PTC0(3)
00X
Input, Hi-Z(2) DDRC6–DDRC0 Pin PTC6–PTC0(3)
X 1 X Output DDRC6–DDRC0 PTC6–PTC0 PTC6–PTC0
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device.
READ DDRC ($0006)
WRITE DDRC ($0006)
RESET
WRITE PTC ($0002)
READ PTC ($0002)
PTCx
DDRCx
PTCx
INTERNAL DATA BUS
VDD
PTCPUEx
INTERNAL
PULLUP
DEVICE
Input/Output (I/O) Ports
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
116 Freescale Semiconductor
12.4.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each
of the seven port C pins. Each bit is individually configurable and requires that the data direction register,
DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRC is configured for output mode.
PTCPUE6–PTCPUE0 — Port C Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port C pin configured to have internal pullup
0 = Corresponding port C pin internal pullup disconnected
12.5 Port D
Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI)
module and four of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port.
12.5.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight port D pins.
PTD7–PTD0 — Port D Data Bits
These read/write bits are software-programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
T2CH1 and T2CH0 — Timer 2 Channel I/O Bits
The PTD7/T2CH1–PTD6/T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTD7/T2CH1–PTD6/T2CH0 pins are timer channel
I/O pins or general-purpose I/O pins. See Chapter 18 Timer Interface Modules (TIM1 and TIM2).
Address: $000E
Bit 7654321Bit 0
Read: 0
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
Write:
Reset:00000000
= Unimplemented
Figure 12-12. Port C Input Pullup Enable Register (PTCPUE)
Address: $0003
Bit 7654321Bit 0
Read:
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write:
Reset: Unaffected by reset
Alternate
Function: T2CH1 T2CH0 T1CH1 T1CH0 SPSCK MOSI MISO SS
Figure 12-13. Port D Data Register (PTD)
Port D
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 117
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
The PTD5/T1CH1–PTD4/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level
select bits, ELSxB and ELSxA, determine whether the PTD5/T1CH1–PTD4/T1CH0 pins are timer
channel I/O pins or general-purpose I/O pins. See Chapter 18 Timer Interface Modules (TIM1 and
TIM2).
SPSCK — SPI Serial Clock
The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the
PTD3/SPSCK pin is available for general-purpose I/O.
MOSI — Master Out/Slave In
The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTD2/MOSI pin is available for general-purpose I/O.
MISO — Master In/Slave Out
The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTD1/MISO pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used
by the SPI module. However, the DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See Table 12-5.
SS — Slave Select
The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the
SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI
is enabled, the DDRD0 bit in data direction register D (DDRD) has no effect on the PTD0/SS pin.
12.5.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a
1 to a DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.
DDRD7–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD7–DDRD0, configuring all port
D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Address: $0007
Bit 7654321Bit 0
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset:00000000
Figure 12-14. Data Direction Register D (DDRD)
Input/Output (I/O) Ports
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
118 Freescale Semiconductor
Figure 12-15 shows the port D I/O logic.
Figure 12-15. Port D I/O Circuit
When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0,
reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-5 summarizes the operation of the port D pins.
Table 12-5. Port D Pin Functions
PTDPUE Bit DDRD Bit PTD Bit I/O Pin Mode Accesses to DDRD Accesse to PTD
Read/Write Read Write
10
X(1) Input, VDD(4) DDRD7–DDRD0 Pin PTD7–PTD0(3)
00X
Input, Hi-Z(2) DDRD7–DDRD0 Pin PTD7–PTD0(3)
X 1 X Output DDRD7–DDRD0 PTD7–PTD0 PTD7–PTD0
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
READ PTD ($0003)
PTDx
DDRDx
PTDx
INTERNAL DATA BUS
VDD
PTDPUEx
INTERNAL
PULLUP
DEVICE
Port E
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 119
12.5.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
12.6 Port E
Port E is a 2-bit special-function port that shares two of its pins with the serial communications interface
(SCI) module.
12.6.1 Port E Data Register
The port E data register contains a data latch for each of the two port E pins.
PTE1 and PTE0 — Port E Data Bits
PTE1 and PTE0 are read/write, software programmable bits. Data direction of each port E pin is under
the control of the corresponding bit in data direction register E.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See Table 12-6.
Address: $000F
Bit 7654321Bit 0
Read:
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Write:
Reset:00000000
Figure 12-16. Port D Input Pullup Enable Register (PTDPUE)
Address: $0008
Bit 7654321Bit 0
Read:000000
PTE1 PTE0
Write:
Reset: Unaffected by reset
Alternate Function: RxD TxD
= Unimplemented
Figure 12-17. Port E Data Register (PTE)
Input/Output (I/O) Ports
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
120 Freescale Semiconductor
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
Chapter 14 Serial Communications Interface (SCI) Module.
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 14 Serial Communications Interface (SCI) Module.
12.6.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a 1
to a DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer.
DDRE1 and DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE1 and DDRE0, configuring all
port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 12-19 shows the port E I/O logic.
Figure 12-19. Port E I/O Circuit
Address: $000C
Bit 7654321Bit 0
Read:000000
DDRE1 DDRE0
Write:
Reset:00000000
= Unimplemented
Figure 12-18. Data Direction Register E (DDRE)
READ DDRE ($000C)
WRITE DDRE ($000C)
RESET
WRITE PTE ($0008)
READ PTE ($0008)
PTEx
DDREx
PTEx
INTERNAL DATA BUS
Port E
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 121
When bit DDREx is a 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a 0,
reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-6 summarizes the operation of the port E pins.
Table 12-6. Port E Pin Functions
DDRE Bit PTE Bit I/O Pin Mode Accesses to DDRE Accesses to PTE
Read/Write Read Write
0X(1) Input, Hi-Z(2) DDRE1–DDRE0 Pin PTE1–PTE0(3)
1 X Output DDRE1–DDRE0 PTE1–PTE0 PTE1–PTE0
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Input/Output (I/O) Ports
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
122 Freescale Semiconductor
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 123
Chapter 13
Resets and Interrupts
13.1 Introduction
Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes
the MCU to its startup condition. An interrupt vectors the program counter to a service routine.
13.2 Resets
A reset immediately returns the MCU to a known startup condition and begins program execution from a
user-defined memory location.
13.2.1 Effects
A reset:
• Immediately stops the operation of the instruction being executed
• Initializes certain control and status bits
• Loads the program counter with a user-defined reset vector address from locations $FFFE and
$FFFF
• Selects CGMXCLK divided by four as the bus clock
13.2.2 External Reset
A low applied to the RST pin for a time, tRL, generates an external reset. An external reset sets the PIN
bit in the SIM reset status register.
13.2.3 Internal Reset
Sources:
• Power-on reset (POR)
• Computer operating properly (COP)
• Low-power reset circuits
• Illegal opcode
• Illegal address
All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external
devices. The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST pin.
Resets and Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
124 Freescale Semiconductor
Figure 13-1. Internal Reset Timing
13.2.3.1 Power-On Reset
A power-on reset (POR) is an internal reset caused by a positive transition on the VDD pin. VDD at the
POR must below VPOR to reset the MCU. This distinguishes between a reset and a POR. The POR is not
a brown-out detector, low-voltage detector, or glitch detector.
A power-on reset:
• Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles
• Drives the RST pin low during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
• Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
• Sets the POR bit in the SIM reset status register and clears all other bits in the register
Figure 13-2. Power-On Reset Recovery
RST PIN
PULLED LOW BY MCU
INTERNAL
32 CYCLES 32 CYCLES
CGMXCLK
RESET
PORRST(1)
OSC1
CGMXCLK
CGMOUT
RST PIN
INTERNAL
4096
CYCLES
32
CYCLES
32
CYCLES
1. PORRST is an internally generated power-on reset pulse.
RESET
Resets
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 125
13.2.3.2 COP Reset
A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP
bit in the system integration module (SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
13.2.3.3 Low-Voltage Inhibit Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the
VTRIPF voltage.
An LVI reset:
• Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles after the power supply voltage rises to the LVITRIPR voltage
• Drives the RST pin low for as long as VDD is below the VTRIPR voltage and during the oscillator
stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
• Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
• Sets the LVI bit in the SIM reset status register
13.2.3.4 Illegal Opcode Reset
An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal
opcode reset sets the ILOP bit in the SIM reset status register.
If the stop enable bit, STOP, in the mask option register is 0, the STOP instruction causes an illegal
opcode reset.
13.2.3.5 Illegal Address Reset
An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal
address reset sets the ILAD bit in the SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
13.2.4 SIM Reset Status Register
This read-only register contains flags to show reset sources. All flag bits are automatically cleared
following a read of the register. Reset service can read the SIM reset status register to clear the register
after power-on reset and to determine the source of any subsequent reset.
Resets and Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
126 Freescale Semiconductor
The register is initialized on power-up as shown with the POR bit set and all other bits cleared. During a
POR or any other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32
CGMXCLK cycles later. If the pin is not above a VIH at that time, then the PIN bit in the SRSR may be set
in addition to whatever other bits are set.
NOTE
Only a read of the SIM reset status register clears all reset flags. After
multiple resets from different sources without reading the register, multiple
flags remain set.
POR — Power-On Reset Flag
1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset
PIN — External Reset Flag
1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR
Address: $FE01
Bit 7654321Bit 0
Read: POR PIN COP ILOP ILAD 0 LVI 0
Write:
POR:10000000
= Unimplemented R = Reserved
Figure 13-3. SIM Reset Status Register (SRSR)
Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 127
13.3 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. An
interrupt does not stop the operation of the instruction being executed, but begins when the current
instruction completes its operation.
13.3.1 Effects
An interrupt:
• Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the
CPU registers from the stack so that normal processing can resume.
• Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other
interrupt can take precedence, regardless of its priority.
• Loads the program counter with a user-defined vector address
Figure 13-4. Interrupt Stacking Order
After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one
interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the
example shown in Figure 13-5, if an interrupt is pending upon exit from the interrupt service routine, the
pending interrupt is serviced before the LDA instruction is executed.
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE)*
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
•
1
2
3
4
5
5
4
3
2
1
STACKING
ORDER
*High byte of index register is not stacked.
$00FF DEFAULT ADDRESS ON RESET
UNSTACKING
ORDER
Resets and Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
128 Freescale Semiconductor
Figure 13-5. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, save the H
register and then restore it prior to exiting the routine.
13.3.2 Sources
The sources in Table 13-1 can generate CPU interrupt requests.
13.3.2.1 SWI Instruction
The software interrupt instruction (SWI) causes a non-maskable interrupt.
NOTE
A software interrupt pushes PC onto the stack. An SWI does not push PC
– 1, as a hardware interrupt does.
13.3.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a software-programmable break
point.
CLI
LDA
INT1
PULH
RTI
INT2
BACKGROUND
#$FF
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
PSHH
INT2 INTERRUPT SERVICE ROUTINE
ROUTINE
Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 129
Figure 13-6. Interrupt Processing
NO
NO
NO
YES
NO
NO
YES
NO
YES
YES
FROM RESET
BREAK
I BIT SET?
IRQ
INTERRUPT
CGM
INTERRUPT
FETCH NEXT
INSTRUCTION
UNSTACK CPU REGISTERS
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
EXECUTE INSTRUCTION
YES
YES
I BIT SET?
INTERRUPT
YES
OTHER
INTERRUPTS
NO
SWI
INSTRUCTION
RTI
INSTRUCTION
?
?
?
?
?
?
Resets and Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
130 Freescale Semiconductor
13.3.2.3 IRQ Pin
A falling edge on the IRQ pin latches an external interrupt request.
13.3.2.4 CGM
The CGM can generate a CPU interrupt request every time the phase-locked loop circuit (PLL) enters or
leaves the locked state. When the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the PLL bandwidth control register.
PLLF is in the PLL control register.
Table 13-1. Interrupt Sources
Source Flag Mask(1)
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
INT
Register Flag Priority(2)
2. 0 = highest priority
Vector Address
Reset None None None 0 $FFFE–$FFFF
SWI instruction None None None 0 $FFFC–$FFFD
IRQ pin IRQF IMASK IF1 1 $FFFA–$FFFB
CGM (PLL) PLLF PLLIE IF2 2 $FFF8–$FFF9
TIM1 channel 0 CH0F CH0IE IF3 3 $FFF6–$FFF7
TIM1 channel 1 CH1F CH1IE IF4 4 $FFF4–$FFF5
TIM1 overflow TOF TOIE IF5 5 $FFF2–$FFF3
TIM2 channel 0 CH0F CH0IE IF6 6 $FFF0–$FFF1
TIM2 channel 1 CH1F CH1IE IF7 7 $FFEE–$FFEF
TIM2 overflow TOF TOIE IF8 8 $FFEC–$FFED
SPI receiver full SPRF SPRIE
IF9 9 $FFEA–$FFEBSPI overflow OVRF ERRIE
SPI mode fault MODF ERRIE
SPI transmitter empty SPTE SPTIE IF10 10 $FFE8–$FFE9
SCI receiver overrun OR ORIE
IF11 11 $FFE6–$FFE7
SCI noise flag NF NEIE
SCI framing error FE FEIE
SCI parity error PE PEIE
SCI receiver full SCRF SCRIE IF12 12 $FFE4–$FFE5
SCI input idle IDLE ILIE
SCI transmitter empty SCTE SCTIE IF13 13 $FFE2–$FFE3
SCI transmission complete TC TCIE
Keyboard pin KEYF IMASKK IF14 14 $FFE0–$FFE1
ADC conversion complete COCO AIEN IF15 15 $FFDE–$FFDF
Timebase TBIF TBIE IF16 16 $FFDC–$FFDD
Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 131
13.3.2.5 TIM1
TIM1 CPU interrupt sources:
• TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1 counter reaches the modulo value
programmed in the TIM1 counter modulo registers. The TIM1 overflow interrupt enable bit, TOIE,
enables TIM1 overflow CPU interrupt requests. TOF and TOIE are in the TIM1 status and control
register.
• TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x.
The channel x interrupt enable bit, CHxIE, enables channel x TIM1 CPU interrupt requests. CHxF
and CHxIE are in the TIM1 channel x status and control register.
13.3.2.6 TIM2
TIM2 CPU interrupt sources:
• TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter reaches the modulo value
programmed in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable bit, TOIE,
enables TIM2 overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status and control
register.
• TIM2 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x.
The channel x interrupt enable bit, CHxIE, enables channel x TIM2 CPU interrupt requests. CHxF
and CHxIE are in the TIM2 channel x status and control register.
13.3.2.7 SPI
SPI CPU interrupt sources:
• SPI receiver full bit (SPRF) — The SPRF bit is set every time a byte transfers from the shift register
to the receive data register. The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU
interrupt requests. SPRF is in the SPI status and control register and SPRIE is in the SPI control
register.
• SPI transmitter empty (SPTE) — The SPTE bit is set every time a byte transfers from the transmit
data register to the shift register. The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU
interrupt requests. SPTE is in the SPI status and control register and SPTIE is in the SPI control
register.
• Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the SS pin goes high during a
transmission with the mode fault enable bit (MODFEN) set. In a master SPI, the MODF bit is set if
the SS pin goes low at any time with the MODFEN bit set. The error interrupt enable bit, ERRIE,
enables MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI status and
control register.
• Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data
register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE,
enables OVRF CPU interrupt requests. OVRF and ERRIE are in the SPI status and control
register.
Resets and Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
132 Freescale Semiconductor
13.3.2.8 SCI
SCI CPU interrupt sources:
• SCI transmitter empty bit (SCTE) — SCTE is set when the SCI data register transfers a character
to the transmit shift register. The SCI transmit interrupt enable bit, SCTIE, enables transmitter CPU
interrupt requests. SCTE is in SCI status register 1. SCTIE is in SCI control register 2.
• Transmission complete bit (TC) — TC is set when the transmit shift register and the SCI data
register are empty and no break or idle character has been generated. The transmission complete
interrupt enable bit, TCIE, enables transmitter CPU interrupt requests. TC is in SCI status
register 1. TCIE is in SCI control register 2.
• SCI receiver full bit (SCRF) — SCRF is set when the receive shift register transfers a character to
the SCI data register. The SCI receive interrupt enable bit, SCRIE, enables receiver CPU
interrupts. SCRF is in SCI status register 1. SCRIE is in SCI control register 2.
• Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive 1s shift in from the RxD pin. The idle
line interrupt enable bit, ILIE, enables IDLE CPU interrupt requests. IDLE is in SCI status register 1.
ILIE is in SCI control register 2.
• Receiver overrun bit (OR) — OR is set when the receive shift register shifts in a new character
before the previous character was read from the SCI data register. The overrun interrupt enable
bit, ORIE, enables OR to generate SCI error CPU interrupt requests. OR is in SCI status register 1.
ORIE is in SCI control register 3.
• Noise flag (NF) — NF is set when the SCI detects noise on incoming data or break characters,
including start, data, and stop bits. The noise error interrupt enable bit, NEIE, enables NF to
generate SCI error CPU interrupt requests. NF is in SCI status register 1. NEIE is in SCI control
register 3.
• Framing error bit (FE) — FE is set when a 0 occurs where the receiver expects a stop bit. The
framing error interrupt enable bit, FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.
• Parity error bit (PE) — PE is set when the SCI detects a parity error in incoming data. The parity
error interrupt enable bit, PEIE, enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.
13.3.2.9 KBD0–KBD7 Pins
A falling edge on a keyboard interrupt pin latches an external interrupt request.
13.3.2.10 ADC (Analog-to-Digital Converter)
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
13.3.2.11 TBM (Timebase Module)
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2–TBR0. When
the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
Interrupts must be acknowledged by writing a 1 to the TACK bit.
Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 133
13.3.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 13-2 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
13.3.3.1 Interrupt Status Register 1
IF6–IF1 — Interrupt Flags 6–1
These flags indicate the presence of interrupt requests from the sources shown in Table 13-2.
1 = Interrupt request present
0 = No interrupt request present
Bit 1 and Bit 0 — Always read 0
Table 13-2. Interrupt Source Flags
Interrupt Source Interrupt Status
Register Flag
Reset —
SWI instruction —
IRQ pin IF1
CGM (PLL) IF2
TIM1 channel 0 IF3
TIM1 channel 1 IF4
TIM1 overflow IF5
TIM2 channel 0 IF6
TIM2 channel 1 IF7
TIM2 overflow IF8
SPI receive IF9
SPI transmit IF10
SCI error IF11
SCI receive IF12
SCI transmit IF13
Keyboard IF14
ADC conversion complete IF15
Timebase IF16
Address: $FE04
Bit 7654321Bit 0
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
R = Reserved
Figure 13-7. Interrupt Status Register 1 (INT1)
Resets and Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
134 Freescale Semiconductor
13.3.3.2 Interrupt Status Register 2
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the sources shown in Table 13-2.
1 = Interrupt request present
0 = No interrupt request present
13.3.3.3 Interrupt Status Register 3
IF16–IF15 — Interrupt Flags 16–15
This flag indicates the presence of an interrupt request from the source shown in Table 13-2.
1 = Interrupt request present
0 = No interrupt request present
Bits 7–2 — Always read 0
Address: $FE05
Bit 7654321Bit 0
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
R = Reserved
Figure 13-8. Interrupt Status Register 2 (INT2)
Address: $FE06
Bit 7654321Bit 0
Read:000000IF16IF15
Write:RRRRRRRR
Reset:00000000
R = Reserved
Figure 13-9. Interrupt Status Register 3 (INT3)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 135
Chapter 14
Serial Communications Interface (SCI) Module
14.1 Introduction
This section describes the serial communications interface (SCI) module, which allows high-speed
asynchronous communications with peripheral devices and other MCUs.
14.2 Features
Features of the SCI module include:
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• 32 programmable baud rates
• Programmable 8-bit or 9-bit character length
• Separately enabled transmitter and receiver
• Separate receiver and transmitter CPU interrupt requests
• Programmable transmitter output polarity
• Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
• Interrupt-driven operation with eight interrupt flags:
– Transmitter empty
– Transmission complete
– Receiver full
– Idle receiver input
– Receiver overrun
– Noise error
– Framing error
– Parity error
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
• Mask option register bit, SCIBDSRC, to allow selection of baud rate clock source
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
136 Freescale Semiconductor
Figure 14-1. Block Diagram Highlighting SCI Block and Pins
SINGLE BREAKPOINT BREAK
MODULE
CLOCK GENERATOR MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
MONITOR MODULE
SERIAL PERIPHERAL
2-CHANNEL TIMER INTERFACE
MODULE 2
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS
USER ROM
USER RAM
MONITOR ROM
USER ROM VECTOR SPACE
SINGLE EXTERNAL
INTERRUPT MODULE
PORTA
DDRA
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
INTERNAL BUS
OSC1
OSC2
CGMXFC
RST(3)
IRQ(3)
INTERFACE MODULE
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7–
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
VDDAD/VREFH 8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6(1)
PTC5(1)
PTC4(1, 2)
PTC3(1, 2)
PTC2(1, 2)
PTC1(1, 2)
PTC0(1, 2)
PTD7/T2CH1(1)
PTD6/T2CH0(1)
PTD5/T1CH1(1)
PTD4/T1CH0(1)
PTD3/SPSCK(1)
PTD2/MOSI(1)
PTD1/MISO(1)
PTD0/SS(1)
PTE1/RxD
PTE0/TxD
VSSAD/VREFL
2-CHANNEL TIMER INTERFACE
MODULE 1
32-kHz OSCILLATOR
PHASE-LOCKED LOOP
SERIAL COMMUNICATIONS
INTERFACE MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
MASK OPTION REGISTER 1
MODULE
SECURITY
MODULE
MASK OPTION REGISTER 2
MODULE
POWER
VSS
VDD
VSSA
VDDA
1. Ports are software configurable with pullup device if input port.
2. Higher current drive port pins
3. Pin contains integrated pullup device
DDRB
PORTB
64 BYTES
PTA0/KBD0(1)
MC68HC08GP32A — 32,256 BYTES
512 BYTES
307 BYTES
36 BYTES
MC68HC08GP16A — 15,872 BYTES
Pin Name Conventions
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 137
14.3 Pin Name Conventions
The generic names of the SCI I/O pins are:
• RxD (receive data)
• TxD (transmit data)
SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an SCI
input or output reflects the name of the shared port pin. Table 14-1 shows the full names and the generic
names of the SCI I/O pins.
The generic pin names appear in the text of this section.
14.4 Functional Description
Figure 14-3 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial
communication among the MCU and remote devices, including other MCUs. The transmitter and receiver
of the SCI operate independently, although they use the same baud rate generator. During normal
operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes
received data.
The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC, of the MOR2
register ($001E). Source selection values are shown in Figure 14-3.
14.4.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 14-2.
Figure 14-2. SCI Data Formats
Table 14-1. Pin Name Conventions
Generic Pin Names: RxD TxD
Full Pin Names: PTE1/RxD PTE0/TxD
BIT 5
START
BIT BIT 0 BIT 1
NEXT
STOP
BIT
START
BIT
8-BIT DATA FORMAT
BIT M IN SCC1 CLEAR
START
BIT BIT 0
NEXT
STOP
BIT
START
BIT
9-BIT DATA FORMAT
BIT M IN SCC1 SET
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
BIT 2 BIT 3 BIT 4 BIT 6 BIT 7
PARITY
BIT
PARITY
BIT
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
138 Freescale Semiconductor
Figure 14-3. SCI Module Block Diagram
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
R8
T8
ORIE
FEIE
PEIE
BKF
RPF
SCI DATA
RECEIVE
SHIFT REGISTER
SCI DATA
REGISTER
TRANSMIT
SHIFT REGISTER
NEIE
M
WAKE
ILTY
FLAG
CONTROL
TRANSMIT
CONTROL
RECEIVE
CONTROL
DATA SELECTION
CONTROL
WAKEUP
PTY
PEN
REGISTER
TRANSMITTER
INTERRUPT
CONTROL
RECEIVER
INTERRUPT
CONTROL
ERROR
INTERRUPT
CONTROL
CONTROL
ENSCI
LOOPS
ENSCI
INTERNAL BUS
TXINV
LOOPS
÷ 4
÷16
PRE-
SCALER
BAUD
DIVIDER
CGMXCLK
BUS CLOCK
A
B
SL
X
SCIBDSRC
FROM
SL = 0 => X = A
SL = 1 => X = B
MOR2
PTE0/TxDPTE1/RxD
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 139
14.4.2 Transmitter
Figure 14-5 shows the structure of the SCI transmitter.
The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC. Source
selection values are shown in Figure 14-5.
14.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3)
is the ninth bit (bit 8).
Addr.Register Name Bit 7654321Bit 0
$0013
SCI Control Register 1
(SCC1)
See page 150.
Read:
LOOPS ENSCI TXINV M WAKE ILTY PEN PTY
Write:
Reset:00000000
$0014
SCI Control Register 2
(SCC2)
See page 152.
Read:
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
Write:
Reset:00000000
$0015
SCI Control Register 3
(SCC3)
See page 154.
Read: R8
T8 R R ORIE NEIE FEIE PEIE
Write:
Reset:UU000000
$0016
SCI Status Register 1
(SCS1)
See page 155.
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
$0017
SCI Status Register 2
(SCS2)
See page 157.
Read: BKF RPF
Write:
Reset:00000000
$0018
SCI Data Register
(SCDR)
See page 158.
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
$0019
SCI Baud Rate Register
(SCBR)
See page 158.
Read:
SCP1 SCP0 R SCR2 SCR1 SCR0
Write:
Reset:00000000
= Unimplemented R = Reserved U = Unaffected
Figure 14-4. SCI I/O Register Summary
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
140 Freescale Semiconductor
Figure 14-5. SCI Transmitter
14.4.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character out to the PTE0/TxD pin. The SCI
data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
To initiate an SCI transmission:
1. Enable the SCI by writing a 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a 1 to the transmitter enable bit (TE) in SCI control register 2
(SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing
to the SCDR.
4. Repeat step 3 for each subsequent transmission.
PEN
PTY
H876543210L
11-BIT
TRANSMIT
STOP
START
T8
SCTE
SCTIE
TCIE
SBK
TC
PARITY
GENERATION
MSB
SCI DATA REGISTER
LOAD FROM SCDR
SHIFT ENABLE
PREAMBLE
ALL 1s
BREAK
ALL 0s
TRANSMITTER
CONTROL LOGIC
SHIFT REGISTER
TC
SCTIE
TCIE
SCTE
TRANSMITTER CPU
M
ENSCI
LOOPS
TE
PTE0/TxD
TXINV
INTERNAL BUS
÷ 4PRE-
SCALER
SCP1
SCP0
SCR1
SCR2
SCR0
BAUD
DIVIDER ÷ 16
CGMXCLK
BUS CLOCK
A
B
SL
X
SL = 0 => X = A
SL = 1 => X = B
SCIBDSRC
FROM
MOR2
INTERRUPT REQUEST
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 141
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit
shift register. A 0 start bit automatically goes into the least significant bit position of the transmit shift
register. A 1 stop bit goes into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the PTE0/TxD pin goes to the idle
condition, 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter
and receiver relinquish control of the port E pins.
14.4.2.3 Break Characters
Writing a 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A
break character contains all 0s and has no start, stop, or parity bit. Break character length depends on
the M bit in SCC1. As long as SBK is 1, transmitter logic continuously loads break characters into the
transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last
break character and then transmits at least one 1. The automatic 1 at the end of a break character
guarantees the recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by eight or nine 0 data bits and a 0
where the stop bit should be.
Receiving a break character has these effects on SCI registers:
• Sets the framing error bit (FE) in SCS1
• Sets the SCI receiver full bit (SCRF) in SCS1
• Clears the SCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
14.4.2.4 Idle Characters
An idle character contains all 1s and has no start, stop, or parity bit. Idle character length depends on the
M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the PTE0/TxD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the character currently being transmitted.
NOTE
When queueing an idle character, return the TE bit to 1 before the stop bit
of the current character shifts out to the TxD pin. Setting TE after the stop
bit appears on TxD causes data previously written to the SCDR to be lost.
Toggle the TE bit for a queued idle character when the SCTE bit becomes
set and just before writing the next byte to the SCDR.
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
142 Freescale Semiconductor
14.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted
data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is 1. See
14.8.1 SCI Control Register 1.
14.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI transmitter:
• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred
a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate
transmitter CPU interrupt requests.
• Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the
SCDR are empty and that no break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU
interrupt requests.
14.4.3 Receiver
Figure 14-6 shows the structure of the SCI receiver.
14.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2)
is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7).
14.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in from the PTE1/RxD pin. The SCI
data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that
the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the
SCRF bit generates a receiver CPU interrupt request.
14.4.3.3 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a
frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at
the following times (see Figure 14-7):
• After every start bit
• After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at
RT8, RT9, and RT10 returns a valid 1 and the majority of the next RT8, RT9, and RT10 samples
returns a valid 0)
To locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s.
When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 143
Figure 14-6. SCI Receiver Block Diagram
ALL 0s
M
WAKE
ILTY
PEN
PTY
BKF
RPF
H876543210L
11-BIT
RECEIVE SHIFT REGISTER
STOP
START
DATA
RECOVERY
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
WAKEUP
LOGIC
PARITY
CHECKING
MSB
SCI DATA REGISTER
R8
ORIE
NEIE
FEIE
PEIE
RWU
SCRF
IDLE
OR
NF
FE
PE
INTERNAL BUS
PRE-
SCALER
BAUD
DIVIDER
÷ 4÷ 16
SCP1
SCP0
SCR1
SCR2
SCR0
CGMXCLK
BUS CLOCK
A
B
SL
X
SCIBDSRC
FROM
SL = 0 => X = A
SL = 1 => X = B
MOR2
PTE1/RxD
ERROR CPU
INTERRUPT REQUEST
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
144 Freescale Semiconductor
Figure 14-7. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 14-2 summarizes the results of the start bit verification samples.
Start bit verification is not successful if any two of the three verification samples are 1s. If start bit
verification is not successful, the RT clock is reset and a new search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 14-3 summarizes the results of the data bit samples.
Table 14-2. Start Bit Verification
RT3, RT5, and RT7
Samples
Start Bit
Verification Noise Flag
000 Yes 0
001 Yes 1
010 Yes 1
011 No 0
100 Yes 1
101 No 0
110 No 0
111 No 0
Table 14-3. Data Bit Recovery
RT8, RT9, and RT10
Samples
Data Bit
Determination Noise Flag
000 0 0
001 0 1
010 0 1
011 1 1
RT CLOCK
RESET
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT8
RT7
RT6
RT11
RT10
RT9
RT15
RT14
RT13
RT12
RT16
RT1
RT2
RT3
RT4
START BIT
QUALIFICATION
START BIT
VERIFICATION
DATA
SAMPLING
SAMPLES
RT
CLOCK
RT CLOCK
STATE
START BIT LSB
PTE1/RxD
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 145
NOTE
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-4
summarizes the results of the stop bit samples.
14.4.3.4 Framing Errors
If the data recovery logic does not detect a 1 where the stop bit should be in an incoming character, it sets
the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has
no stop bit. The FE bit is set at the same time that the SCRF bit is set.
14.4.3.5 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate.
Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the
actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing
error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment
that is likely to occur.
As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge
within the character. Resynchronization within characters corrects misalignments between transmitter bit
times and receiver bit times.
100 0 1
101 1 1
110 1 1
111 1 0
Table 14-4. Stop Bit Recovery
RT8, RT9, and RT10
Samples
Framing
Error Flag Noise Flag
000 1 0
001 1 1
010 1 1
011 0 1
100 1 1
101 0 1
110 0 1
111 0 0
Table 14-3. Data Bit Recovery (Continued)
RT8, RT9, and RT10
Samples
Data Bit
Determination Noise Flag
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
146 Freescale Semiconductor
Slow Data Tolerance
Figure 14-8 shows how much a slow received character can be misaligned without causing a noise error
or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times ×16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 14-8, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is 9 bit times ×16 RT cycles + 3 RT cycles = 147 RT cycles.
Figure 14-8. Slow Data
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times ×16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 14-8, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is 10 bit times ×16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is
Fast Data Tolerance
Figure 14-9 shows how much a fast received character can be misaligned without causing a noise error
or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
Figure 14-9. Fast Data
MSB STOP
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT11
RT12
RT13
RT14
RT15
RT16
DATA
SAMPLES
RECEIVER
RT CLOCK
154 147–
154
--------------------------100×4.54%=
170 163–
170
--------------------------100×4.12%=
IDLE OR NEXT CHARACTERSTOP
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT11
RT12
RT13
RT14
RT15
RT16
DATA
SAMPLES
RECEIVER
RT CLOCK
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 147
For an 8-bit character, data sampling of the stop bit takes the receiver
9bittimes×16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 14-9, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is 10 bit times ×16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times ×16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 14-9, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is 11 bit times ×16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is
14.4.3.6 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are disabled.
Depending on the state of the WAKE bit in SCC1, either of two conditions on the PTE1/RxD pin can bring
the receiver out of the standby state:
• Address mark — An address mark is a 1 in the most significant bit position of a received character.
When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing
the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then
compare the character containing the address mark to the user-defined address of the receiver. If
they are the same, the receiver remains awake and processes the characters that follow. If they
are not the same, software can set the RWU bit and put the receiver back into the standby state.
• Idle input line condition — When the WAKE bit is clear, an idle character on the PTE1/RxD pin
wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes
the receiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line
type bit, ILTY, determines whether the receiver begins counting 1s as idle character bits after the
start bit or after the stop bit.
NOTE
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
154 160–
154
--------------------------100×3.90%
·
=
170 176–
170
--------------------------100×3.53%=
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
148 Freescale Semiconductor
14.4.3.7 Receiver Interrupts
The following sources can generate CPU interrupt requests from the SCI receiver:
• SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting
the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver
CPU interrupts.
• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive 1s shifted in from the
PTE1/RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.
14.4.3.8 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt requests:
• Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate SCI error CPU interrupt requests.
• Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate SCI error CPU interrupt requests.
• Framing error (FE) — The FE bit in SCS1 is set when a 0 occurs where the receiver expects a stop
bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU
interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data.
The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt
requests.
14.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
14.5.1 Wait Mode
The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
Refer to Chapter 9 Low-Power Modes for information on exiting wait mode.
14.5.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect SCI register states. SCI module operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
Refer to Chapter 9 Low-Power Modes for information on exiting stop mode.
SCI During Break Module Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 149
14.6 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
14.7 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins are:
• PTE0/TxD — Transmit data
• PTE1/RxD — Receive data
14.7.1 PTE0/TxD (Transmit Data)
The PTE0/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/TxD pin
with port E. When the SCI is enabled, the PTE0/TxD pin is an output regardless of the state of the DDRE0
bit in data direction register E (DDRE).
14.7.2 PTE1/RxD (Receive Data)
The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/RxD pin with port
E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data
direction register E (DDRE).
14.8 I/O Registers
These I/O registers control and monitor SCI operation:
• SCI control register 1 (SCC1)
• SCI control register 2 (SCC2)
• SCI control register 3 (SCC3)
• SCI status register 1 (SCS1)
• SCI status register 2 (SCS2)
• SCI data register (SCDR)
• SCI baud rate register (SCBR)
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
150 Freescale Semiconductor
14.8.1 SCI Control Register 1
SCI control register 1:
• Enables loop mode operation
• Enables the SCI
• Controls output polarity
• Controls character length
• Controls SCI wakeup method
• Controls idle character detection
• Enables parity function
• Controls parity type
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the PTE1/RxD pin is disconnected from
the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or nine bits long. See Table 14-5. The
ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the
M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
Address: $0013
Bit 7654321Bit 0
Read:
LOOPS ENSCI TXINV M WAKE ILTY PEN PTY
Write:
Reset:00000000
Figure 14-10. SCI Control Register 1 (SCC1)
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 151
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a 1 (address mark) in the most
significant bit position of a received character or an idle condition on the PTE1/RxD pin. Reset clears
the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting 1s as idle character bits. The counting
begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string
of 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after
the stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. See Table 14-5. When enabled, the parity function
inserts a parity bit in the most significant bit position. See Figure 14-2. Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks for odd parity or even parity. See
Table 14-5. Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
NOTE
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 14-5. Character Format Selection
Control Bits Character Format
M PEN and PTY Start
Bits
Data
Bits Parity Stop
Bits
Character
Length
0 0X 1 8 None 1 10 bits
1 0X 1 9 None 1 11 bits
0 10 1 7 Even 1 10 bits
0 11 1 7 Odd 1 10 bits
1 10 1 8 Even 1 11 bits
1 11 1 8 Odd 1 11 bits
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
152 Freescale Semiconductor
14.8.2 SCI Control Register 2
SCI control register 2:
• Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt requests
– Enables the TC bit to generate transmitter CPU interrupt requests
– Enables the SCRF bit to generate receiver CPU interrupt requests
– Enables the IDLE bit to generate receiver CPU interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables SCI wakeup
• Transmits SCI break characters
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset
clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears
the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears
the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
Address: $0014
Bit 7654321Bit 0
Read:
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
Write:
Reset:00000000
Figure 14-11. SCI Control Register 2 (SCC2)
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 153
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the
transmit shift register to the PTE0/TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the PTE0/TxD returns to the idle condition (1). Clearing and then
setting TE during a transmission queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear.
ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not
affect receiver interrupt flag bits. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out
of the standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break character followed by a 1. The 1 after the
break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter
continuously transmits break characters with no 1s between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling
SBK before the preamble begins causes the SCI to send a break character
instead of a preamble.
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
154 Freescale Semiconductor
14.8.3 SCI Control Register 3
SCI control register 3:
• Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted
• Enables these interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
• Parity error interrupts
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character.
R8 is received at the same time that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on
the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE. See
14.8.4 SCI Status Register 1. Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
Address: $0015
Bit 7654321Bit 0
Read: R8
T8 R R ORIE NEIE FEIE PEIE
Write:
Reset:UU000000
= Unimplemented R= Reserved U = Unaffected
Figure 14-12. SCI Control Register 3 (SCC3)
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 155
14.8.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register.
SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by
reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being
transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set.
TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may
be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the
transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data
register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is
set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading
SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
Address: $0016
Bit 7654321Bit 0
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
= Unimplemented
Figure 14-13. SCI Status Register 1 (SCS1)
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
156 Freescale Semiconductor
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. IDLE
generates an SCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit
by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must
receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after
the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition
can set the IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the SCDR before the receive shift
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the
ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is
not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears
the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence. Figure 14-14 shows the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit
because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the PTE1/RxD pin. NF generates an
SCI error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1
and then reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a 0 is accepted as the stop bit. FE generates an SCI error CPU
interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and
then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
an SCI error CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1
with PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 157
Figure 14-14. Flag Clearing Sequence
14.8.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
• Break character detected
• Incoming data
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break character on the PTE1/RxD pin. In
SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set
and then reading the SCDR. Once cleared, BKF can become set again only after 1s again appear on
the PTE1/RxD pin followed by another break character. Reset clears the BKF bit.
1 = Break character detected
0 = No break character detected
Address: $0017
Bit 7654321Bit 0
Read: BKF RPF
Write:
Reset:00000000
= Unimplemented
Figure 14-15. SCI Status Register 2 (SCS2)
BYTE 1
NORMAL FLAG CLEARING SEQUENCE
READ SCS1
SCRF = 1
READ SCDR
BYTE 1
SCRF = 1
SCRF = 1
BYTE 2 BYTE 3 BYTE 4
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 2
SCRF = 0
READ SCS1
SCRF = 1
OR = 0
SCRF = 1
SCRF = 0
READ SCDR
BYTE 3
SCRF = 0
BYTE 1
READ SCS1
SCRF = 1
READ SCDR
BYTE 1
SCRF = 1
SCRF = 1
BYTE 2 BYTE 3 BYTE 4
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
OR = 1
SCRF = 1
OR = 1
SCRF = 0
OR = 1
SCRF = 0
OR = 0
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
158 Freescale Semiconductor
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a 0 during the RT1 time period of the start bit search.
RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
14.8.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the SCI data register.
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading the SCDR accesses the read-only received data bits, R7:R0. Writing to the SCDR writes the
data to be transmitted, T7:T0.
Reset has no effect on the SCDR.
NOTE
Do not use read/modify/write instructions on the SCI data register.
14.8.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter.
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown in
Table 14-6. Reset clears SCP1 and SCP0.
Address: $0018
Bit 7654321Bit 0
Read:R7R6R5R4R3R2R1R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Figure 14-16. SCI Data Register (SCDR)
Address: $0019
Bit 7654321Bit 0
Read:
SCP1 SCP0 R SCR2 SCR1 SCR0
Write:
Reset:00000000
= Unimplemented R = Reserved
Figure 14-17. SCI Baud Rate Register (SCBR)
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 159
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in Table 14-7. Reset clears
SCR2–SCR0.
Use this formula to calculate the SCI baud rate:
where:
SCI clock source = fBUS or CGMXCLK (selected by SCIBDSRC bit in MOR2)
PD = prescaler divisor
BD = baud rate divisor
Table 14-8 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when fBUS is
selected as SCI clock source.
Table 14-6. SCI Baud Rate Prescaling
SCP1 and SCP0 Prescaler Divisor (PD)
00 1
01 3
10 4
11 13
Table 14-7. SCI Baud Rate Selection
SCR2, SCR1, and SCR0 Baud Rate Divisor (BD)
000 1
001 2
010 4
011 8
100 16
101 32
110 64
111 128
Baud rate SCI clock source
64 PD BD××
---------------------------------------------=
Serial Communications Interface (SCI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
160 Freescale Semiconductor
Table 14-8. SCI Baud Rate Selection Examples
SCP1
and SCP0
Prescaler
Divisor (PD)
SCR2, SCR1,
and SCR0
Baud Rate
Divisor (BD)
Baud Rate
(fBUS = 4.9152 MHz)
00 1 000 1 76,800
00 1 001 2 38,400
00 1 010 4 19,200
00 1 011 8 9600
00 1 100 16 4800
00 1 101 32 2400
00 1 110 64 1200
00 1 111 128 600
01 3 000 1 25,600
01 3 001 2 12,800
01 3 010 4 6400
01 3 011 8 3200
01 3 100 16 1600
01 3 101 32 800
01 3 110 64 400
01 3 111 128 200
10 4 000 1 19,200
10 4 001 2 9600
10 4 010 4 4800
10 4 011 8 2400
10 4 100 16 1200
10 4 101 32 600
10 4 110 64 300
10 4 111 128 150
11 13 000 1 5908
11 13 001 2 2954
11 13 010 4 1477
11 13 011 8 739
11 13 100 16 369
11 13 101 32 185
11 13 110 64 92
11 13 111 128 46
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 161
Chapter 15
System Integration Module (SIM)
15.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all
MCU activities. A block diagram of the SIM is shown in Figure 15-1. Table 15-1 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception
timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP timeout
• Interrupt arbitration
Table 15-1 shows the internal signal names used in this section.
Table 15-1. Signal Name Conventions
Signal Name Description
CGMXCLK Buffered version of OSC1 from clock generator module (CGM)
CGMVCLK PLL output
CGMOUT PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
IAB Internal address bus
IDB Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W Read/write signal
System Integration Module (SIM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
162 Freescale Semiconductor
Figure 15-1. SIM Block Diagram
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
$FE00
SIM Break Status Register
(SBSR)
See page 175.
Read:
RRRRRR
SBSW
R
Write: Note
Reset: 0
Note: Writing a 0 clears SBSW.
$FE01
SIM Reset Status Register
(SRSR)
See page 176.
Read: POR PIN COP ILOP ILAD 0 LVI 0
Write:
POR:10000000
$FE02 Reserved RRRRRRRR
$FE03
SIM Break Flag Control
Register (SBFCR)
See page 177.
Read:
BCFERRRRRRR
Write:
Reset: 0
Figure 15-2. SIM I/O Register Summary
STOP/WAIT
CLOCK
CONTROL CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
MASTER
RESET
CONTROL
RESET
PIN LOGIC
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
RESET
CONTROL
SIM
COUNTER COP CLOCK
CGMXCLK (FROM CGM)
÷ 2
VDD
INTERNAL
PULLUP
DEVICE
SIM Bus Clock Control and Generation
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 163
15.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 15-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 4 Clock Generator Module
(CGM).)
Figure 15-3. CGM Clock Signals
15.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four.
$FE04
Interrupt Status Register 1
(INT1)
See page 171.
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
$FE05
Interrupt Status Register 2
(INT2)
See page 172.
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
$FE06
Interrupt Status Register 3
(INT3)
See page 172.
Read: 0 0 0 0 0 0 IF16 IF15
Write:RRRRRRRR
Reset:00000000
= Unimplemented
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
Figure 15-2. SIM I/O Register Summary (Continued)
÷ 2BUS CLOCK
GENERATORS
SIM
SIM COUNTER
MONITOR MODE
USER MODE
SIMOSCEN
OSCILLATOR (OSC)
OSC2
OSC1
PHASE-LOCKED LOOP (PLL)
CGMXCLK
CGMRCLK
IT12
CGMOUT
SIMDIV2 PTC3
TO TIMTB15A, ADC
OSCSTOPENB
FROM
MOR
TO REST
OF CHIP
IT23
TO REST
OF CHIP
System Integration Module (SIM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
164 Freescale Semiconductor
15.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this entire period. The bus clocks
start upon completion of the timeout.
15.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM
counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 CGMXCLK cycles. (See 15.6.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
15.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 15.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 15.7 SIM Registers.)
15.3.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at
least the minimum tRL time and no other reset sources are present. Figure 15-4 shows the relative timing.
Figure 15-4. External Reset Timing
RST
IAB PC VECT H VECT L
CGMOUT
Reset and System Initialization
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 165
15.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset signal continues to be asserted for an additional 32 cycles. See
Figure 15-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or
POR. (See Figure 15-6.)
NOTE
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 15-5.
Figure 15-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
Figure 15-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
15.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
Table 15-2. Reset Recovery
Reset Recovery Type Actual Number of Cycles
POR/LVI 4163 (4096 + 64 + 3)
All others 67 (64 + 3)
IRST
RST
RST PULLED LOW BY MCU
IAB
32 CYCLES 32 CYCLES
VECTOR HIGH
CGMXCLK
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
System Integration Module (SIM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
166 Freescale Semiconductor
At power-on, these events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
•The RST
pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set
Figure 15-7. POR Recovery
15.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and bits 12 through 5 of the SIM counter. The SIM counter output, which occurs at least
every 213 – 24 CGMXCLK cycles, drives the COP counter. The COP should be serviced as soon as
possible out of reset to guarantee the maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor
mode. The COP module can be disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of
external noise. During a break state, VTST on the RST pin disables the COP module.
PORRST
OSC1
CGMXCLK
CGMOUT
RST
IAB
4096
CYCLES
32
CYCLES
32
CYCLES
$FFFE $FFFF
IRST
SIM Counter
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 167
15.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an
illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal
reset sources.
15.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources.
15.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the VTRIPF
voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held
low if the LVIPWRD and LVIRSTD bits in the mask option register are 0. The RST pin will be held low
while the SIM counter counts out 4096 + 32 CGMXCLK cycles after VDD rises above VTRIPR. Thirty-two
CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The
SIM actively pulls down the RST pin for all internal reset sources.
15.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus clocks. The SIM counter also serves as a
prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock
for the COP module. The SIM counter is 12 bits long.
15.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
15.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096
CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using crystals with the
OSCSTOPENB bit set. External crystal applications should use the full stop recovery time, SSREC
cleared, with the OSCSTOPENB bit cleared.
15.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 15.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. (See 15.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
System Integration Module (SIM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
168 Freescale Semiconductor
15.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
15.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 15-8 shows
interrupt entry timing. Figure 15-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). (See Figure 15-10.)
Figure 15-8. Interrupt Entry Timing
Figure 15-9. Interrupt Recovery Timing
MODULE
IDB
R/W
INTERRUPT
DUMMY SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
IAB
DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE
I BIT
MODULE
IDB
R/W
INTERRUPT
SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1
IAB
CCR A X PC – 1 [15:8] PC – 1 [7:0] OPCODE OPERAND
I BIT
Exception Control
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 169
Figure 15-10. Interrupt Processing
15.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
NO
NO
YES
NO
NO
YES
NO
YES
AS MANY INTERRUPTS
I BIT SET?
FROM RESET
BREAK
I BIT SET?
IRQ
INTERRUPT?
SWI
INSTRUCTION?
RTI
INSTRUCTION?
FETCH NEXT
INSTRUCTION
UNSTACK CPU REGISTERS
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
EXECUTE INSTRUCTION
YES
YES
AS EXIST ON CHIP
INTERRUPT?
System Integration Module (SIM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
170 Freescale Semiconductor
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 15-11 demonstrates what happens when two interrupts are pending. If an interrupt
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
Figure 15-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
15.5.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
15.5.1.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 15-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
CLI
LDA
INT1
PULH
RTI
INT2
BACKGROUND
#$FF
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
PSHH
INT2 INTERRUPT SERVICE ROUTINE
ROUTINE
Exception Control
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 171
Interrupt Status Register 1
IF6–IF1 — Interrupt Flags 1–6
These flags indicate the presence of interrupt requests from the sources shown in Table 15-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
Table 15-3. Interrupt Sources
Priority Interrupt Source Interrupt Status
Register Flag
Highest Reset —
SWI instruction —
IRQ pin IF1
PLL IF2
TIM1 channel 0 IF3
TIM1 channel 1 IF4
TIM1 overflow IF5
TIM2 channel 0 IF6
TIM2 channel 1 IF7
TIM2 overflow IF8
SPI receiver full IF9
SPI transmitter empty IF10
SCI receive error IF11
SCI receive IF12
SCI transmit IF13
Keyboard IF14
ADC conversion complete IF15
Lowest Timebase module IF16
Address: $FE04
Bit 7654321Bit 0
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 15-12. Interrupt Status Register 1 (INT1)
System Integration Module (SIM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
172 Freescale Semiconductor
Interrupt Status Register 2
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the sources shown in Table 15-3.
1 = Interrupt request present
0 = No interrupt request present
Interrupt Status Register 3
Bits 7–2 — Always read 0
IF16–IF15 — Interrupt Flags 16–15
These flags indicate the presence of an interrupt request from the source shown in Table 15-3.
1 = Interrupt request present
0 = No interrupt request present
15.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
15.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output. (See Chapter 18 Timer Interface Modules (TIM1 and TIM2).) The SIM puts the
CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection
of each module to see how each module is affected by the break state.
15.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Address: $FE05
Bit 7654321Bit 0
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 15-13. Interrupt Status Register 2 (INT2)
Address: $FE06
Bit 7654321Bit 0
Read:000000IF16IF15
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 15-14. Interrupt Status Register 3 (INT3)
Low-Power Modes
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 173
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
15.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
15.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 15-15 shows
the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask
option register is 0, then the computer operating properly module (COP) is enabled and remains active in
wait mode.
Figure 15-15. Wait Mode Entry Timing
WAIT ADDR + 1 SAME SAMEIAB
IDB PREVIOUS DATA NEXT OPCODE SAME
WAIT ADDR
SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
System Integration Module (SIM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
174 Freescale Semiconductor
Figure 15-16 and Figure 15-17 show the timing for WAIT recovery.
Figure 15-16. Wait Recovery from Interrupt or Break
Figure 15-17. Wait Recovery from Internal Reset
15.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option register
(MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down
to 32. This is ideal for applications using canned oscillators that do not require long startup times from
stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit unless the OSCSTOPENB bit is set in MOR2.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 15-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a 1 or 0.
$6E0C$6E0B $00FF $00FE $00FD $00FC
$A6 $A6 $01 $0B $6E$A6
IAB
IDB
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt
IAB
IDB
RST
$A6 $A6
$6E0B RST VCT H RST VCT L
$A6
CGMXCLK
32
CYCLES
32
CYCLES
SIM Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 175
Figure 15-18. Stop Mode Entry Timing
Figure 15-19. Stop Mode Recovery from Interrupt
15.7 SIM Registers
The SIM has three memory-mapped registers. Table 15-4 shows the mapping of these registers.
15.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait
mode. This register is only used in emulation mode.
Table 15-4. SIM Registers
Address Register Access Mode
$FE00 SBSR User
$FE01 SRSR User
$FE03 SBFCR User
Address: $FE00
Bit 7654321Bit 0
Read: RRRRRR
SBSW R
Write: Note
Reset: 0
R= Reserved
Note: Writing a 0 clears SBSW.
Figure 15-20. SIM Break Status Register (SBSR)
STOP ADDR + 1 SAME SAMEIAB
IDB PREVIOUS DATA NEXT OPCODE SAME
STOP ADDR
SAME
R/W
CPUSTOP
Note : Previous data can be operand data or the STOP opcode, depending on the last instruction.
CGMXCLK
INT/BREAK
IAB STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3
STOP +1
STOP RECOVERY PERIOD
System Integration Module (SIM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
176 Freescale Semiconductor
SBSW — SIM Break Stop/Wait
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
15.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status bits
have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit
and clears all other bits in the register.
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
Address: $FE01
Bit 7654321Bit 0
Read: POR PIN COP ILOP ILAD 0 LVI 0
Write:
Reset:10000000
= Unimplemented
Figure 15-21. SIM Reset Status Register (SRSR)
SIM Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 177
15.7.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to clear status bits while the MCU is
in a break state.
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
Address: $FE03
Bit 7654321Bit 0
Read:
BCFERRRRRRR
Write:
Reset: 0
R= Reserved
Figure 15-22. SIM Break Flag Control Register (SBFCR)
System Integration Module (SIM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
178 Freescale Semiconductor
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 179
Chapter 16
Serial Peripheral Interface (SPI) Module
16.1 Introduction
This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous,
serial communications with peripheral devices.
The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial
clock), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four
parallel I/O ports.
16.2 Features
Features of the SPI module include:
• Full-duplex operation
• Master and slave modes
• Double-buffered operation with separate transmit and receive registers
• Four master mode frequencies (maximum = bus frequency ÷2)
• Maximum slave mode frequency = bus frequency
• Serial clock with programmable polarity and phase
• Two separately enabled interrupts:
– SPRF (SPI receiver full)
– SPTE (SPI transmitter empty)
• Mode fault error flag with CPU interrupt capability
• Overflow error flag with CPU interrupt capability
• Programmable wired-OR mode
• I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port
bit(s)
16.3 Functional Description
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt
driven.
If a port bit is configured for input, then an internal pullup device may be enabled for that port bit.
The following paragraphs describe the operation of the SPI module. Refer to Figure 16-3 for a summary
of the SPI I/O registers.
Serial Peripheral Interface (SPI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
180 Freescale Semiconductor
Figure 16-1. Block Diagram Highlighting SPI Block and Pins
SINGLE BREAKPOINT BREAK
MODULE
CLOCK GENERATOR MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
MONITOR MODULE
SERIAL PERIPHERAL
2-CHANNEL TIMER INTERFACE
MODULE 2
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS
USER ROM
USER RAM
MONITOR ROM
USER ROM VECTOR SPACE
SINGLE EXTERNAL
INTERRUPT MODULE
PORTA
DDRA
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
INTERNAL BUS
OSC1
OSC2
CGMXFC
RST(3)
IRQ(3)
INTERFACE MODULE
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7–
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
VDDAD/VREFH 8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6(1)
PTC5(1)
PTC4(1, 2)
PTC3(1, 2)
PTC2(1, 2)
PTC1(1, 2)
PTC0(1, 2)
PTD7/T2CH1(1)
PTD6/T2CH0(1)
PTD5/T1CH1(1)
PTD4/T1CH0(1)
PTD3/SPSCK(1)
PTD2/MOSI(1)
PTD1/MISO(1)
PTD0/SS(1)
PTE1/RxD
PTE0/TxD
VSSAD/VREFL
2-CHANNEL TIMER INTERFACE
MODULE 1
32-kHz OSCILLATOR
PHASE-LOCKED LOOP
SERIAL COMMUNICATIONS
INTERFACE MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
MASK OPTION REGISTER 1
MODULE
SECURITY
MODULE
MASK OPTION REGISTER 2
MODULE
POWER
VSS
VDD
VSSA
VDDA
1. Ports are software configurable with pullup device if input port.
2. Higher current drive port pins
3. Pin contains integrated pullup device
DDRB
PORTB
64 BYTES
PTA0/KBD0(1)
MC68HC08GP32A — 32,256 BYTES
512 BYTES
307 BYTES
36 BYTES
MC68HC08GP16A — 15,872 BYTES
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 181
Figure 16-2. SPI Module Block Diagram
Addr.Register Name Bit 7654321Bit 0
$0010
SPI Control Register
(SPCR)
See page 195.
Read: SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
Write:
Reset:00101000
$0011
SPI Status and Control Reg-
ister (SPSCR)
See page 196.
Read: SPRF ERRIE OVRF MODF SPTE MODFEN SPR1 SPR0
Write:
Reset:00001000
$0012
SPI Data Register
(SPDR)
See page 198.
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
R= Reserved = Unimplemented
Figure 16-3. SPI I/O Register Summary
TRANSMITTER CPU INTERRUPT REQUEST
RECEIVER/ERROR CPU INTERRUPT REQUEST
76543210
SPR1
SPMSTR
TRANSMIT DATA REGISTER
SHIFT REGISTER
SPR0
BUSCLK
CLOCK
SELECT
÷ 2
CLOCK
DIVIDER
÷ 8
÷ 32
÷ 128
CLOCK
LOGIC
CPHA CPOL
SPI
SPRIE
SPE
SPWOM
SPRF
SPTE
OVRF
M
S
PIN
CONTROL
LOGIC
RECEIVE DATA REGISTER
SPTIE
SPE
INTERNAL BUS
MODFEN
ERRIE
CONTROL
MODF
SPMSTR
MOSI
MISO
SPSCK
SS
Serial Peripheral Interface (SPI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
182 Freescale Semiconductor
16.3.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
NOTE
In a multi-SPI system, configure the SPI modules as master or slave before
enabling them. Enable the master SPI before enabling the slave SPI.
Disable the slave SPI before disabling the master SPI. See 16.12.1 SPI
Control Register.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. See Figure 16-4.
Figure 16-4. Full-Duplex Master-Slave Connections
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See 16.12.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register (SPDR)
clears SPTE.
16.3.2 Slave Mode
The SPI operates in slave mode when SPMSTR is clear. In slave mode, the SPSCK pin is the input for
the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must
be low. SS must remain low until the transmission is complete. See 16.6.2 Mode Fault Error.
In a slave SPI module, data enters the shift register under the control of the serial clock from the master
SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register,
and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data
register before another full byte enters the shift register.
SHIFT REGISTER
SHIFT REGISTER
BAUD RATE
GENERATOR
MASTER MCU SLAVE MCU
VDD
MOSI MOSI
MISO MISO
SPSCK SPSCK
SS SS
Transmission Formats
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 183
The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is
twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for
an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only
controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency
of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed.
When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the
MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its
transmit data register. The slave must write to its transmit data register at least one bus cycle before the
master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the
MISO pin. Data written to the slave shift register during a transmission remains in a buffer until the end of
the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is
clear, the falling edge of SS starts a transmission. See 16.4 Transmission Formats.
NOTE
SPSCK must be in the proper idle state before the slave is enabled to
prevent SPSCK from appearing as a clock edge.
16.4 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted
in serially). A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select
line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere
with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate
multiple-master bus contention.
16.4.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits
in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects
an active high or low clock and has no significant effect on the transmission format.
The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The
clock phase and polarity should be identical for the master SPI device and the communicating slave
device. In some cases, the phase and polarity are changed between transmissions to allow a master
device to communicate with peripheral slaves having different requirements.
NOTE
Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing
the SPI enable bit (SPE).
16.4.2 Transmission Format When CPHA = 0
Figure 16-5 shows an SPI transmission in which CPHA = 0. The figure should not be used as a
replacement for data sheet parametric information.
Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may
be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave.
The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS
line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select
Serial Peripheral Interface (SPI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
184 Freescale Semiconductor
input (SS) is low, so that only the selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as
general-purpose I/O not affecting the SPI. (See 16.6.2 Mode Fault Error.) When CPHA = 0, the first
SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first
SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave’s
SS pin must be toggled back to high and then low again between each byte transmitted as shown in
Figure 16-6.
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of
SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift
register after the current transmission.
Figure 16-5. Transmission Format (CPHA = 0)
Figure 16-6. CPHA/SS Timing
16.4.3 Transmission Format When CPHA = 1
Figure 16-7 shows an SPI transmission in which CPHA = 1. The figure should not be used as a
replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The
slave SPI drives its MISO output only when its slave select input (SS) is low, so that only the selected
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS
pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB
12345678
SPSCK CYCLE #
FOR REFERENCE
SPSCK; CPOL = 0
SPSCK; CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
SS; TO SLAVE
CAPTURE STROBE
BYTE 1 BYTE 3
MISO/MOSI BYTE 2
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Transmission Formats
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 185
16.6.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK
edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can
remain low between transmissions. This format may be preferable in systems having only one master and
only one slave driving the MISO data line.
Figure 16-7. Transmission Format (CPHA = 1)
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of
SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the
shift register after the current transmission.
16.4.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA
has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle.
When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and
the start of the SPI transmission. (See Figure 16-8.) The internal SPI clock in the master is a free-running
derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and
SPMSTR bits are set. Since the SPI clock is free-running, it is uncertain where the write to the SPDR
occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown
in Figure 16-8. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU
bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus
cycles for DIV128.
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB
12345678
SPSCK CYCLE #
FOR REFERENCE
SPSCK; CPOL = 0
SPSCK; CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
SS; TO SLAVE
CAPTURE STROBE
Serial Peripheral Interface (SPI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
186 Freescale Semiconductor
Figure 16-8. Transmission Start Delay (Master)
WRITE
TO SPDR INITIATION DELAY
BUS
MOSI
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
MSB BIT 6
12
CLOCK
WRITE
TO SPDR
EARLIEST
LATEST
SPSCK = BUS CLOCK ÷ 2;
EARLIEST LATEST
2 POSSIBLE START POINTS
SPSCK = BUS CLOCK ÷ 8;
8 POSSIBLE START POINTS
EARLIEST LATESTSPSCK = BUS CLOCK ÷ 32;
32 POSSIBLE START POINTS
EARLIEST LATESTSPSCK = BUS CLOCK ÷ 128;
128 POSSIBLE START POINTS
WRITE
TO SPDR
WRITE
TO SPDR
WRITE
TO SPDR
BUS
CLOCK
BIT 5
3
BUS
CLOCK
BUS
CLOCK
BUS
CLOCK
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
Queuing Transmission Data
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 187
16.5 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready
to accept new data. Write to the transmit data register only when SPTE is high. Figure 16-9 shows the
timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0).
Figure 16-9. SPRF/SPTE CPU Interrupt Timing
The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes
between transmissions as in a system with a single data buffer. Also, if no new data is written to the data
buffer, the last value contained in the shift register is the next data word to be transmitted.
For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no
more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur
until the transmission is completed. This implies that a back-to-back write to the transmit data register is
not possible. SPTE indicates when the next write can occur.
BIT
3
MOSI
SPSCK
SPTE
WRITE TO SPDR 1
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
3
1
2
2
3
5
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
SPRF
READ SPSCR
MSB BIT
6
BIT
5
BIT
4
BIT
2
BIT
1
LSB MSB BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
LSB MSB BIT
6
BYTE 2 TRANSFERS FROM TRANSMIT DATA
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
BYTE 3 TRANSFERS FROM TRANSMIT DATA
5
8
10
8
10
4FIRST INCOMING BYTE TRANSFERS FROM SHIFT
6CPU READS SPSCR WITH SPRF BIT SET.
4
6
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
9
11
AND CLEARING SPTE BIT.
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
3 AND CLEARING SPTE BIT.
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
12 CPU READS SPDR, CLEARING SPRF BIT.
BIT
5
BIT
4
BYTE 1 BYTE 2 BYTE 3
712
READ SPDR
7CPU READS SPDR, CLEARING SPRF BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
CPHA:CPOL = 1:0
Serial Peripheral Interface (SPI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
188 Freescale Semiconductor
16.6 Error Conditions
The following flags signal SPI error conditions:
• Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift
register sets the OVRF bit. The new byte does not transfer to the receive data register, and the
unread byte still can be read. OVRF is in the SPI status and control register.
• Mode fault error (MODF) — The MODF bit indicates that the voltage on the slave select pin (SS)
is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
16.6.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous
transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe
occurs in the middle of SPSCK cycle 7 (see Figure 16-5 and Figure 16-7.) If an overflow occurs, all data
received after the overflow and before the OVRF bit is cleared does not transfer to the receive data
register and does not set the SPI receiver full bit (SPRF). The unread data that transferred to the receive
data register before the overflow occurred can still be read. Therefore, an overflow error always indicates
the loss of data. Clear the overflow flag by reading the SPI status and control register and then reading
the SPI data register.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also
set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector (see Figure 16-12.) It
is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition.
Figure 16-10 shows how it is possible to miss an overflow. The first part of Figure 16-10 shows how it is
possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by
the second transmission example, the OVRF bit can be set in between the time that SPSCR and SPDR
are read.
In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this
OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the
SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions can set the SPRF bit. Figure 16-11 illustrates this process. Generally, to avoid this second
SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit.
Error Conditions
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 189
Figure 16-10. Missed Read of Overflow Condition
Figure 16-11. Clearing SPRF When OVRF Interrupt Is Not Enabled
READ
READ
OVRF
SPRF
BYTE 1 BYTE 2 BYTE 3 BYTE 4
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
CPU READS BYTE 1 IN SPDR,
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
1
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
CLEARING SPRF BIT. BUT NOT OVRF BIT.
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
AND OVRF BIT CLEAR.
AND OVRF BIT CLEAR.
SPSCR
SPDR
READ
READ
OVRF
SPRF
BYTE 1 BYTE 2 BYTE 3 BYTE 4
1
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
CPU READS BYTE 1 IN SPDR,
CPU READS SPSCR AGAIN
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR,
CPU READS SPSCR AGAIN
CPU READS BYTE 2 SPDR,
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
CPU READS BYTE 4 IN SPDR,
CPU READS SPSCR AGAIN
1
2
3
CLEARING SPRF BIT.
4
TO CHECK OVRF BIT.
5
6
7
8
9
CLEARING SPRF BIT.
TO CHECK OVRF BIT.
10
CLEARING OVRF BIT.
11
12
13
14
2
3
4
5
6
7
8
9
10
11
12
13
14
CLEARING SPRF BIT.
TO CHECK OVRF BIT.
SPI RECEIVE
COMPLETE
AND OVRF BIT CLEAR.
AND OVRF BIT CLEAR.
SPSCR
SPDR
Serial Peripheral Interface (SPI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
190 Freescale Semiconductor
16.6.2 Mode Fault Error
Setting SPMSTR selects master mode and configures the SPSCK and MOSI pins as outputs and the
MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins
as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of
the slave select pin, SS, is inconsistent with the mode selected by SPMSTR.
To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if:
•The SS
pin of a slave SPI goes high during a transmission
•The SS
pin of a master SPI goes low at any time
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the
MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is
cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also
set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 16-12.)
It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS
goes low. A mode fault in a master SPI causes the following events to occur:
• If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request.
• The SPE bit is cleared.
• The SPTE bit is set.
• The SPI state counter is cleared.
• The data direction register of the shared I/O port regains control of port drivers.
NOTE
To prevent bus contention with another master SPI after a mode fault error,
clear all SPI bits of the data direction register of the shared I/O port before
enabling the SPI.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission.
When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes
back to its idle level following the shift of the eighth data bit. When CPHA = 1, the transmission begins
when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK
returns to its idle level following the shift of the last data bit. See
16.4 Transmission Formats.
NOTE
Setting the MODF flag does not clear the SPMSTR bit. SPMSTR has no
function when SPE = 0. Reading SPMSTR when MODF = 1 shows the
difference between a MODF occurring when the SPI is a master and when
it is a slave.
When CPHA = 0, a MODF occurs if a slave is selected (SS is low) and later
unselected (SS is high) even if no SPSCK is sent to that slave. This
happens because SS low indicates the start of the transmission (MISO
driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave
can be selected and then later unselected with no transmission occurring.
Therefore, MODF does not occur since a transmission was never begun.
Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 191
In a slave SPI (MSTR = 0), MODF generates an SPI receiver/error CPU interrupt request if the ERRIE bit
is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI
transmission by clearing the SPE bit of the slave.
NOTE
A high on the SS pin of a slave SPI puts the MISO pin in a high impedance
state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was
already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This
entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared.
16.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests. See Table 16-1.
Reading the SPI status and control register with SPRF set and then reading the receive data register
clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables SPRF to generate receiver CPU interrupt requests,
regardless of the state of SPE. See Figure 16-12.
Figure 16-12. SPI Interrupt Request Generation
Table 16-1. SPI Interrupts
Flag Request
SPTE — Transmitter empty SPI transmitter CPU interrupt request (SPTIE = 1, SPE = 1)
SPRF — Receiver full SPI receiver CPU interrupt request (SPRIE = 1)
OVRF — Overflow SPI receiver/error interrupt request (ERRIE = 1)
MODF — Mode fault SPI receiver/error interrupt request (ERRIE = 1)
SPTE SPTIE
SPRFSPRIE
SPE
CPU INTERRUPT REQUEST
CPU INTERRUPT REQUEST
SPI TRANSMITTER
SPI RECEIVER/ERROR
ERRIE
MODF
OVRF
Serial Peripheral Interface (SPI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
192 Freescale Semiconductor
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error
CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF
bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.
The following sources in the SPI status and control register can generate CPU interrupt requests:
• SPI receiver full bit (SPRF) — SPRF becomes set every time a byte transfers from the shift register
to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF
generates an SPI receiver/error CPU interrupt request.
• SPI transmitter empty (SPTE) — SPTE becomes set every time a byte transfers from the transmit
data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE
generates an SPTE CPU interrupt request.
16.8 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is 0.
Whenever SPE is 0, the following occurs:
• The SPTE flag is set.
• Any transmission currently in progress is aborted.
• The shift register is cleared.
• The SPI state counter is cleared, making it ready for a new complete transmission.
• All the SPI port logic is defaulted back to being general-purpose I/O.
These items are reset only by a system reset:
• All control bits in the SPCR register
• All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
• The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without
having to set all control bits again when SPE is set back high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the
SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be
disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
16.9 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
16.9.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
SPI During Break Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 193
To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt
requests by setting the error interrupt enable bit (ERRIE). See 16.7 Interrupts.
16.9.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by
reset, any transfer in progress is aborted, and the SPI is reset.
16.10 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. BCFE in the SIM break flag control register (SBFCR) enables software to clear status bits
during the break state. See Chapter 15 System Integration Module (SIM).
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE at 0 (its default state), software
can read and write I/O registers during the break state without affecting status bits. Some status bits have
a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the
bit cannot change during the break state as long as BCFE is 0. After the break, doing the second step
clears the status bit.
Since the SPTE bit cannot be cleared during a break with BCFE cleared, a write to the transmit data
register in break mode does not initiate a transmission nor is this data transferred into the shift register.
Therefore, a write to the SPDR in break mode with BCFE cleared has no effect.
16.11 I/O Signals
The SPI module has four I/O pins:
• MISO — Master input/slave output
• MOSI — Master output/slave input
• SPSCK — Serial clock
•SS
— Slave select
16.11.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin
of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is
configured as a slave when its SPMSTR bit is 0 and its SS pin is low. To support a multiple-slave system,
a high on the SS pin puts the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction
register of the shared I/O port.
Serial Peripheral Interface (SPI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
194 Freescale Semiconductor
16.11.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin
of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction
register of the shared I/O port.
16.11.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
16.11.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
(See 16.4 Transmission Formats.) Since it is used to indicate the start of a transmission, SS must be
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See Figure 16-13.
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of SS from creating a MODF error. See 16.12.2 SPI Status and Control Register.
Figure 16-13. CPHA/SS Timing
NOTE
A high on the SS pin of a slave SPI puts the MISO pin in a high-impedance
state. The slave SPI ignores all incoming SPSCK clocks, even if it was
already in the middle of a transmission.
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See 16.6.2 Mode Fault Error.) For the state of
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If MODFEN is 0 for
an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction
register of the shared I/O port. When MODFEN is 1, SS is an input-only pin to the SPI regardless of the
state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. See Table 16-2.
BYTE 1 BYTE 3
MISO/MOSI BYTE 2
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 195
16.12 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
16.12.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
1 = Master mode
0 = Slave mode
Table 16-2. SPI Configuration
SPE SPMSTR MODFEN SPI Configuration Function of SS Pin
0X(1))
1. X = Don’t care
X Not enabled General-purpose I/O;
SS ignored by SPI
1 0 X Slave Input-only to SPI
1 1 0 Master without MODF General-purpose I/O;
SS ignored by SPI
1 1 1 Master with MODF Input-only to SPI
Address: $0010
Bit 7654321Bit 0
Read:
SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
Write:
Reset:00101000
R= Reserved
Figure 16-14. SPI Control Register (SPCR)
Serial Peripheral Interface (SPI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
196 Freescale Semiconductor
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure
16-5 and Figure 16-7.) To transmit data between SPI modules, the SPI modules must have identical
CPOL values. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure
16-5 and Figure 16-7.) To transmit data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be high between bytes. (See
Figure 16-13.) Reset sets the CPHA bit.
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 16.8
Resetting the SPI.) Reset clears the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
16.12.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform these functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Address: $0011
Bit 7654321Bit 0
Read: SPRF
ERRIE
OVRF MODF SPTE
MODFEN SPR1 SPR0
Write:
Reset:00001000
= Unimplemented
Figure 16-15. SPI Status and Control Register (SPSCR)
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 197
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register
with SPRF set and then reading the SPI data register.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears
the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte in the receive data register before
the next full byte enters the shift register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the receive data register. Reset clears the
OVRF bit.
1 = Overflow
0 = No overflow
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with
MODFEN set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear MODF by reading the SPI status and control register (SPSCR) with MODF set
and then writing to the SPI control register (SPCR). Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift
register. SPTE generates an SPTE CPU interrupt request if SPTIE in the SPI control register is set
also.
NOTE
Do not write to the SPI data register unless SPTE is high.
During an SPTE CPU interrupt, the CPU clears SPTE by writing to the transmit data register.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set, allows the MODF flag to be set. If the MODF flag is set, clearing MODFEN
does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is 0, then the SS
pin is available as a general-purpose I/O.
If the MODFEN bit is 1, then the SS pin is not available as a general-purpose I/O. When the SPI is
enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of
MODFEN. See 16.11.4 SS (Slave Select).
Serial Peripheral Interface (SPI) Module
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
198 Freescale Semiconductor
If the MODFEN bit is 0, the level of the SS pin does not affect the operation of an enabled SPI
configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents
the MODF flag from being set. It does not affect any other part of SPI operation. See 16.6.2 Mode Fault
Error.
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as shown in Table 16-3. SPR1 and
SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.
Use this formula to calculate the SPI baud rate:
16.12.3 SPI Data Register
The SPI data register consists of the read-only receive data register and the write-only transmit data
register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data
register reads data from the receive data register. The transmit data and receive data registers are
separate registers that can contain different values. See Figure 16-2.
R7–R0/T7–T0 — Receive/Transmit Data Bits
NOTE
Do not use read-modify-write instructions on the SPI data register since the
register read is not the same as the register written.
Table 16-3. SPI Master Baud Rate Selection
SPR1 and SPR0 Baud Rate Divisor (BD)
00 2
01 8
10 32
11 128
Address: $0012
Bit 7654321Bit 0
Read:R7R6R5R4R3R2R1R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Figure 16-16. SPI Data Register (SPDR)
Baud rate = BUSCLK
BD
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 199
Chapter 17
Timebase Module (TBM)
17.1 Introduction
This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user
selectable rates using a counter clocked by the external clock source. This TBM version uses 15 divider
stages, eight of which are user selectable. A configuration option bit to select an additional 128 divide of
the external clock source can be selected. See Chapter 11 Mask Option Registers (MOR2 and MOR1)
17.2 Features
Features of the TBM module include:
• External clock or an additional divide-by-128 selected by configuration option bit as clock source
• Software configurable periodic interrupts with divide-by: 8, 16, 32, 64, 128, 2048, 8192, and 32768
taps of the selected clock source
• Configurable for operation during stop mode to allow periodic wakeup from stop
17.3 Functional Description
This module can generate a periodic interrupt by dividing the clock source supplied from the clock
generator module, CGMXCLK.
The counter is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 17-1, starts
counting when the TBON bit is set. When the counter overflows at the tap selected by TBR2–TBR0, the
TBIF bit gets set. If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared
by writing a 1 to the TACK bit. The first time the TBIF flag is set after enabling the timebase module, the
interrupt is generated at approximately half of the overflow period. Subsequent events occur at the exact
period.
The timebase module may remain active after execution of the STOP instruction if the crystal oscillator
has been enabled to operate during stop mode through the OSCSTOPENB bit in the mask option register.
The timebase module can be used in this mode to generate a periodic wakeup from stop mode.
17.4 Interrupts
The timebase module can periodically interrupt the CPU with a rate defined by the selected TBMCLK and
the select bits TBR2–TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE
bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt
request.
NOTE
Interrupts must be acknowledged by writing a 1 to the TACK bit.
Timebase Module (TBM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
200 Freescale Semiconductor
Figure 17-1. Timebase Block Diagram
÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2
÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2
SEL
0 0 0
0 0 1
0 1 0
0 1 1
TBIF
TBR1
TBR0
TBIE
TBMINT
TBON
÷ 2
R
TACK
TBR2
1 0 0
1 0 1
1 1 0
1 1 1
TBMCLK
FROM CGM MODULE
TBMCLKSEL
FROM MOR2
DIVIDE BY 128
PRESCALER
0
1
CGMXCLK
TBM Interrupt Rate
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 201
17.5 TBM Interrupt Rate
The interrupt rate is determined by the equation:
where:
fCGMXCLK = Frequency supplied from the clock generator (CGM) module
Divider = Divider value as determined by TBR2–TBR0 settings and TBMCLKSEL, see Table 17-1
As an example, a clock source of 32.768 kHz, with the TBMCLKSEL set for divide-by-128 and
TBR2–TBR0 set to {101}, the divider tap is 1 and the interrupt rate calculates to:
4096/32,768 = 125 ms
NOTE
Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1).
17.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
17.6.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before executing the WAIT instruction.
17.6.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the internal clock
generator has been enabled to operate during stop mode through the OSCSTOPENB bit in the mask
option register. The timebase module can be used in this mode to generate a periodic wakeup from stop
mode.
Table 17-1. Timebase Divider Selection
TBR2 TBR1 TBR0
Divider Tap
TBMCLKSEL
01
0 0 0 32,768 4,194,304
0 0 1 8192 1,048,576
0 1 0 2048 262144
0 1 1 128 16,384
1 0 0 64 8192
1 0 1 32 4096
1 1 0 16 2048
1 1 1 8 1024
tTBMRATE = Divider
fCGMXCLK
Timebase Module (TBM)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
202 Freescale Semiconductor
If the internal clock generator has not been enabled to operate in stop mode, the timebase module will
not be active during stop mode. In stop mode, the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce power consumption by disabling the
timebase module before executing the STOP instruction.
17.7 Timebase Control Register
The timebase has one register, the timebase control register (TBCR), which is used to enable the
timebase interrupts and set the rate.
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
TBR2–TBR0 — Timebase Divider Selection Bits
These read/write bits select the tap in the counter to be used for timebase interrupts as shown in
Table 17-1.
NOTE
Do not change TBR2–TBR0 bits while the timebase is enabled
(TBON = 1).
TACK— Timebase Acknowledge Bit
The TACK bit is a write-only bit and always reads as 0. Writing a 1 to this bit clears TBIF, the timebase
interrupt flag bit. Writing a 0 to this bit has no effect.
1 = Clear timebase interrupt flag
0 = No effect
TBIE — Timebase Interrupt Enabled Bit
This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the
TBIE bit.
1 = Timebase interrupt is enabled.
0 = Timebase interrupt is disabled.
TBON — Timebase Enabled Bit
This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption
when its function is not necessary. The counter can be initialized by clearing and then setting this bit.
Reset clears the TBON bit.
1 = Timebase is enabled.
0 = Timebase is disabled and the counter initialized to 0s.
Address: $001C
Bit 7654321Bit 0
Read: TBIF
TBR2 TBR1 TBR0
0
TBIE TBON R
Write: TACK
Reset:00000000
= Unimplemented R = Reserved
Figure 17-2. Timebase Control Register (TBCR)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 203
Chapter 18
Timer Interface Modules (TIM1 and TIM2)
18.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a
timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 18-2
is a block diagram of the TIM.
This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
18.2 Features
Features of the TIM include:
• Two input capture/output compare channels:
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse-width-modulation (PWM) signal generation
• Programmable TIM clock input with 7-frequency internal bus clock prescaler selection
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIM counter stop and reset bits
18.3 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are
T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where “1” is used to indicate TIM1 and “2”
is used to indicate TIM2. The two TIMs share four I/O pins with four port D I/O port pins. The full names
of the TIM I/O pins are listed in Table 18-1. The generic pin names appear in the text that follows.
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TCH0 may refer generically to
T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
Table 18-1. Pin Name Conventions
TIM Generic Pin Names: T[1,2]CH0 T[1,2]CH1
Full TIM
Pin Names:
TIM1 PTD4/T1CH0 PTD5/T1CH1
TIM2 PTD6/T2CH0 PTD7/T2CH1
Timer Interface Modules (TIM1 and TIM2)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
204 Freescale Semiconductor
Figure 18-1. Block Diagram Highlighting TIM Blocks and Pins
SINGLE BREAKPOINT BREAK
MODULE
CLOCK GENERATOR MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
MONITOR MODULE
SERIAL PERIPHERAL
2-CHANNEL TIMER INTERFACE
MODULE 2
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS
USER ROM
USER RAM
MONITOR ROM
USER ROM VECTOR SPACE
SINGLE EXTERNAL
INTERRUPT MODULE
PORTA
DDRA
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
INTERNAL BUS
OSC1
OSC2
CGMXFC
RST(3)
IRQ(3)
INTERFACE MODULE
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7–
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
VDDAD/VREFH 8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6(1)
PTC5(1)
PTC4(1, 2)
PTC3(1, 2)
PTC2(1, 2)
PTC1(1, 2)
PTC0(1, 2)
PTD7/T2CH1(1)
PTD6/T2CH0(1)
PTD5/T1CH1(1)
PTD4/T1CH0(1)
PTD3/SPSCK(1)
PTD2/MOSI(1)
PTD1/MISO(1)
PTD0/SS(1)
PTE1/RxD
PTE0/TxD
VSSAD/VREFL
2-CHANNEL TIMER INTERFACE
MODULE 1
32-kHz OSCILLATOR
PHASE-LOCKED LOOP
SERIAL COMMUNICATIONS
INTERFACE MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
MASK OPTION REGISTER 1
MODULE
SECURITY
MODULE
MASK OPTION REGISTER 2
MODULE
POWER
VSS
VDD
VSSA
VDDA
1. Ports are software configurable with pullup device if input port.
2. Higher current drive port pins
3. Pin contains integrated pullup device
DDRB
PORTB
64 BYTES
PTA0/KBD0(1)
MC68HC08GP32A — 32,256 BYTES
512 BYTES
307 BYTES
36 BYTES
MC68HC08GP16A — 15,872 BYTES
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 205
18.4 Functional Description
Figure 18-2 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value
at any time without affecting the counting sequence.
The two TIM channels (per timer) are programmable independently as input capture or output compare
channels. If a channel is configured as input capture, then an internal pullup device may be enabled for
that channel. See 12.5.3 Port D Input Pullup Enable Register.
Figure 18-3 summarizes the timer registers.
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC and T2SC.
Figure 18-2. TIM Block Diagram
MS1A
CH0F
PRESCALER
PRESCALER SELECT
INTERNAL
16-BIT COMPARATOR
PS2 PS1 PS0
16-BIT COMPARATOR
16-BIT LATCH
TCH0H:TCH0L
TOF
TOIE
16-BIT COMPARATOR
16-BIT LATCH
TCH1H:TCH1L
CHANNEL 0
CHANNEL 1
TMODH:TMODL
TRST
TSTOP
TOV0
CH0IE
TOV1
CH1IE
CH1MAX
CH0MAX
16-BIT COUNTER
INTERNAL BUS
BUS CLOCK
T[1,2]CH0
T[1,2]CH1
INTERRUPT
LOGIC
PORT
LOGIC
INTERRUPT
LOGIC
INTERRUPT
LOGIC
PORT
LOGIC
ELS0AELS0B
ELS1AELS1B
MS0B
CH1F
MS0A
Timer Interface Modules (TIM1 and TIM2)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
206 Freescale Semiconductor
Addr.Register Name Bit 7654321Bit 0
$0020
Timer 1 Status and Control
Register (T1SC)
See page 213.
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
$0021
Timer 1 Counter
Register High (T1CNTH)
See page 214.
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
$0022
Timer 1 Counter
Register Low (T1CNTL)
See page 214.
Read:Bit 7654321Bit 0
Write:
Reset:00000000
$0023
Timer 1 Counter Modulo
Register High (T1MODH)
See page 215.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
$0024
Timer 1 Counter Modulo
Register Low (T1MODL)
See page 215.
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
$0025
Timer 1 Channel 0 Status and
Control Register
(T1SC0)
See page 215.
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
$0026
Timer 1 Channel 0
Register High (T1CH0H)
See page 218.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$0027
Timer 1 Channel 0
Register Low (T1CH0L)
See page 218.
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$0028
Timer 1 Channel 1 Status and
Control Register (T1SC1)
See page 218.
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
$0029
Timer 1 Channel 1
Register High (T1CH1H)
See page 218.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$002A
Timer 1 Channel 1
Register Low (T1CH1L)
See page 218.
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$002B
Timer 2 Status and Control
Register (T2SC)
See page 213.
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
= Unimplemented
Figure 18-3. TIM I/O Register Summary (Sheet 1 of 2)
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 207
18.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
18.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
$002C
Timer 2 Counter
Register High (T2CNTH)
See page 214.
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
$002D
Timer 2 Counter
Register Low (T2CNTL)
See page 214.
Read:Bit 7654321Bit 0
Write:
Reset:00000000
$002E
Timer 2 Counter Modulo
Register High (T2MODH)
See page 215.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
$002F
Timer 2 Counter Modulo
Register Low (T2MODL)
See page 215.
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
$0030
Timer 2 Channel 0 Status and
Control Register (T2SC0)
See page 215.
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
$0031
Timer 2 Channel 0
Register High (T2CH0H)
See page 218.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$0032
Timer 2 Channel 0
Register Low (T2CH0L)
See page 218.
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$0033
Timer 2 Channel 1 Status and
Control Register (T2SC1)
See page 215.
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
$0034
Timer 2 Channel 1
Register High (T2CH1H)
See page 218.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$0035
Timer 2 Channel 1
Register Low (T2CH1L)
See page 218.
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented
Figure 18-3. TIM I/O Register Summary (Sheet 2 of 2)
Timer Interface Modules (TIM1 and TIM2)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
208 Freescale Semiconductor
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
18.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
18.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 18.4.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
• When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
• When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
18.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
TCH0 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare
function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
Functional Description
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 209
18.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM
signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 18-4 shows, the output compare value in the TIM channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM
to clear the channel pin on output compare if the state of the PWM pulse is 1 (ELSxA = 0). Program the
TIM to set the pin if the state of the PWM pulse is 0 (ELSxA = 1).
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is 000. See 18.9.1 TIM Status and Control Register.
Figure 18-4. PWM Period and Pulse Width
The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of
an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers
produces a duty cycle of 128/256 or 50%.
18.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 18.4.4 Pulse Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect
operation for up to two PWM periods. For example, writing a new value before the counter reaches the
old value but after the counter reaches the new value prevents any compare during that PWM period.
Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the
compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
TCHx
PERIOD
PULSE
WIDTH
OVERFLOW OVERFLOW OVERFLOW
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
TCHx
POLARITY = 1
(ELSxA = 0)
POLARITY = 0
(ELSxA = 1)
Timer Interface Modules (TIM1 and TIM2)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
210 Freescale Semiconductor
• When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in
the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM
period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
18.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.
The TIM channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel
1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM
channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
18.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM
period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB:MSxA. See Table 18-3.
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must
force the output to the complement of the pulse width level. See Table 18-3.
Interrupts
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 211
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM
channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM channel 0 status and
control register (TSC0) controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. See 18.9.4 TIM Channel Status and Control Registers.
18.5 Interrupts
• The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1.
CHxF and CHxIE are in the TIM channel x status and control register.
18.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
18.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
18.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
Timer Interface Modules (TIM1 and TIM2)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
212 Freescale Semiconductor
18.7 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 15.7.3 SIM Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
18.8 I/O Signals
Port D shares four of its pins with the TIM. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0,
and T2CH1 as described in 18.3 Pin Name Conventions.
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins.
18.9 I/O Registers
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC AND T2SC.
These I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0, TSC1)
• TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
18.9.1 TIM Status and Control Register
The TIM status and control register (TSC):
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 213
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete,
then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as
Table 18-2 shows. Reset clears the PS[2:0] bits.
Address: T1SC, $0020 and T2SC, $002B
Bit 7654321Bit 0
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
= Unimplemented
Figure 18-5. TIM Status and Control Register (TSC)
Timer Interface Modules (TIM1 and TIM2)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
214 Freescale Semiconductor
18.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting
the break interrupt. Otherwise, TCNTL retains the value latched during the break.
18.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter
reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow
interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Table 18-2. Prescaler Selection
PS2 PS1 PS0 TIM Clock Source
0 0 0 Internal bus clock ÷ 1
0 0 1 Internal bus clock ÷ 2
0 1 0 Internal bus clock ÷ 4
0 1 1 Internal bus clock ÷ 8
1 0 0 Internal bus clock ÷ 16
1 0 1 Internal bus clock ÷ 32
1 1 0 Internal bus clock ÷ 64
1 1 1 Not available
Address: T1CNTH, $0021 and T2CNTH, $002C
Bit 7654321Bit 0
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
= Unimplemented
Figure 18-6. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D
Bit 7654321Bit 0
Read:Bit 7654321Bit 0
Write:
Reset:00000000
= Unimplemented
Figure 18-7. TIM Counter Registers Low (TCNTL)
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 215
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
18.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: T1MODH, $0023 and T2MODH, $002E
Bit 7654321Bit 0
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
Figure 18-8. TIM Counter Modulo Register High (TMODH)
Address: T1MODL, $0024 and T2MODL, $002F
Bit 7654321Bit 0
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Figure 18-9. TIM Counter Modulo Register Low (TMODL)
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7654321Bit 0
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
Figure 18-10. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033
Bit 7654321Bit 0
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
= Unimplemented
Figure 18-11. TIM Channel 1 Status and Control Register (TSC1)
Timer Interface Modules (TIM1 and TIM2)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
216 Freescale Semiconductor
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x
status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1
channel 0 and TIM2 channel 0 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O. Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation. See Table 18-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See
Table 18-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x
output behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTDx/TCHx is
available as a general-purpose I/O pin. Table 18-3 shows how ELSxB and ELSxA work. Reset clears
the ELSxB and ELSxA bits.
NOTE
Before enabling a TIM channel register for input capture operation, make
sure that the PTDx/TCHx pin is stable for at least two bus clocks.
I/O Registers
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 217
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow
0 = Channel x pin does not toggle on TIM counter overflow
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As Figure 18-12 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
NOTE
The 100% PWM duty cycle is defined as a continuous high level if the PWM
polarity is 1 and a continuous low level if the PWM polarity is 0. Conversely,
a 0% PWM duty cycle is defined as a continuous low level if the PWM
polarity is 1 and a continuous high level if the PWM polarity is 0.
Figure 18-12. CHxMAX Latency
Table 18-3. Mode, Edge, and Level Selection
MSxB MSxA ELSxB ELSxA Mode Configuration
X0 0 0 Output preset Pin under port control; initial output level high
X 1 0 0 Pin under port control; initial output level low
00 0 1
Input capture
Capture on rising edge only
0 0 1 0 Capture on falling edge only
0 0 1 1 Capture on rising or falling edge
01 0 0
Output compare
or PWM
Software compare only
0 1 0 1 Toggle output on compare
0 1 1 0 Clear output on compare
0 1 1 1 Set output on compare
1X 0 1 Buffered output
compare or
buffered PWM
Toggle output on compare
1 X 1 0 Clear output on compare
1 X 1 1 Set output on compare
OUTPUT
OVERFLOW
TCHx
PERIOD
CHxMAX
OVERFLOW OVERFLOW OVERFLOW OVERFLOW
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Timer Interface Modules (TIM1 and TIM2)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
218 Freescale Semiconductor
18.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: T1CH0H, $0026 and T2CH0H, $0031
Bit 7654321Bit 0
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
Figure 18-13. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032
Bit 7654321Bit 0
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
Figure 18-14. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0029 and T2CH1H, $0034
Bit 7654321Bit 0
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
Figure 18-15. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A and T2CH1L, $0035
Bit 7654321Bit 0
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
Figure 18-16. TIM Channel 1 Register Low (TCH1L)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 219
Chapter 19
Development Support
19.1 Introduction
This section describes the break module, the monitor module (MON), and the monitor mode entry
methods.
19.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
Features of the break module include:
• Accessible input/output (I/O) registers during the break Interrupt
• Central processor unit (CPU) generated break interrupts
• Software-generated break interrupts
• Computer operating properly (COP) disabling during break interrupts
19.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU
to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to
$FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the microcontroller unit (MCU) to normal operation.
Figure 19-1 shows the structure of the break module.
Figure 19-2 provides a summary of the I/O registers.
When the internal address bus matches the value written in the break address registers or when software
writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
Development Support
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
220 Freescale Semiconductor
Figure 19-1. Break Module Block Diagram
The break interrupt timing is:
• When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
• When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
• When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
Addr.Register Name Bit 7654321Bit 0
$FE00
Break Status Register
(SBSR)
See page 222.
Read:
RRRRRR
SBSW
R
Write: Note(1)
Reset: 0
$FE02 Reserved
Read:
RRRRRRRR
Write:
Reset:00000000
$FE03
Break Flag Control
Register (SBFCR)
See page 223.
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE09
Break Address High
Register (BRKH)
See page 222.
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:00000000
$FE0A
Break Address Low
Register (BRKL)
See page 222.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:00000000
$FE0B
Break Status and Control
Register (BRKSCR)
See page 221.
Read:
BRKE BRKA
000000
Write:
Reset:00000000
1. Writing a 0 clears SBSW. = Unimplemented R = Reserved
Figure 19-2. Break I/O Register Summary
ADDRESS BUS[15:8]
ADDRESS BUS[7:0]
8-BIT COMPARATOR
8-BIT COMPARATOR
CONTROL
BREAK ADDRESS REGISTER LOW
BREAK ADDRESS REGISTER HIGH
ADDRESS BUS[15:0]
BKPT
(TO SIM)
Break Module (BRK)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 221
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode.
When software does not change the break address and clears the BRKA
bit in the first break interrupt routine, the next break interrupt will not be
generated after exiting the interrupt routine even when the internal address
bus matches the value written in the break address registers.
19.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See 19.2.2.4 Break Flag Control Register and the Break Interrupts
subsection for each module.
19.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
19.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt when VTST is present on the RST pin.
19.2.2 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status register (SBSR)
• Break flag control register (SBFCR)
19.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to
bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
Address: $FE0B
Bit 7654321Bit 0
Read: BRKE BRKA 000000
Write:
Reset:00000000
= Unimplemented
Figure 19-3. Break Status and Control Register (BRKSCR)
Development Support
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
222 Freescale Semiconductor
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = Break address match
0 = No break address match
19.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
19.2.2.3 Break Status Register
The break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
Address: $FE09
Bit 7654321Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
Figure 19-4. Break Address Register High (BRKH)
Address: $FE0A
Bit 7654321Bit 0
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
Figure 19-5. Break Address Register Low (BRKL)
Address: $FE00
Bit 7654321Bit 0
Read:
RRRRRR
SBSW
R
Write: Note(1)
Reset: 0
R = Reserved 1. Writing a 0 clears SBSW.
Figure 19-6. Break Status Register (SBSR)
Monitor Module (MON)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 223
19.2.2.4 Break Flag Control Register
The break control register (SBFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
19.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes. If enabled, the
break module will remain enabled in wait and stop modes. However, since the internal address bus does
not increment in these modes, a break interrupt will never be triggered.
19.3 Monitor Module (MON)
This subsection describes the monitor module (MON) and the monitor mode entry methods. The monitor
allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with
a host computer.
Features include:
• Normal user-mode pin functionality on most pins
• One pin dedicated to serial communication between MCU and host computer
• Standard non-return-to-zero (NRZ) communication with host computer
• 9600 Baud communication with host computer
• Execution of code in random-access memory (RAM) or ROM
19.3.1 Functional Description
Figure 19-8 shows a simplified diagram of monitor mode entry.
The monitor module receives and executes commands from a host computer.
Figure 19-9 shows an example circuit used to enter monitor mode and communicate with a host computer
via a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
Address: $FE03
Bit 7654321Bit 0
Read: BCFERRRRRRR
Write:
Reset: 0
R= Reserved
Figure 19-7. Break Flag Control Register (SBFCR)
Development Support
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
224 Freescale Semiconductor
Figure 19-8. Simplified Monitor Mode Entry Flowchart
MONITOR MODE ENTRY
POR RESET
PTA0 = 1,
PTC0 = 1, PTC1 = 0,
AND PTA7 = 0?
IRQ = VTST?
YES NO
YES
NO
NORMAL
USER MODE
NORMAL
MONITOR MODE
INVALID
USER MODE
NO
HOST SENDS
8 SECURITY BYTES
IS RESET
POR?
YES
YES
NO
ARE ALL
SECURITY BYTES
CORRECT?
NO
YES
ENABLE ROM DISABLE ROM
EXECUTE
MONITOR CODE
DOES RESET
OCCUR?
CONDITIONS
FROM Table 19-2
DEBUGGING
Monitor Module (MON)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 225
Figure 19-9. Normal Monitor Mode Circuit
19.3.1.1 Monitor Mode Entry
Table 19-2 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication provided the pin and clock
conditions are met.
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the
values on PTA7, PTC0, PTC1, and PTC3 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see 19.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
19.3.1.2 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code. The COP module is disabled in
monitor mode as long as VTST is applied to either the IRQ pin or the RST pin.
Table 19-1 summarizes the differences between user mode and monitor mode regarding vectors.
10 k
10 k
NC
10 k
RST
IRQ
PTA0
8
7
DB9
2
3
5
16
15
2
6
10
9
VDD
1 µF
MAX232
V+
V–
VDD
1 µF
+
1
234
5
6
74HC125
74HC125 10 kΩ
VSS
0.1 µF
VDD
C1+
C1–
5
4
1 µF
C2+
C2–
+
3
1
1 µF++
+
1 µF
VDD
VCC
GND
1 kΩ
OSC1
9.8304 MHz
VDDA
PTC3
PTC0
PTC1
VSSA
VDD
MC68HC08GP32A/MC68HC08GP16A
9.1 V
10 k
PTA7
Development Support
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
226 Freescale Semiconductor
19.3.1.3 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
Figure 19-10. Monitor Data Format
19.3.1.4 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of two bits and then echoes back the break signal.
Figure 19-11. Break Transaction
Table 19-1. Mode Differences
Modes
Functions
COP Reset
Vector High
Reset
Vector Low
Break
Vector High
Break
Vector Low
SWI
Vector High
SWI
Vector Low
User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
Monitor Disabled(1)
1. If the high voltage (VTST) is removed from the IRQ pin while in monitor mode, the SIM asserts its COP enable output. The
COP is a mask option enabled or disabled by the COPD bit in the mask option register. (See 20.5 5.0-V DC Electrical Char-
acteristics.)
$FEFE $FEFF $FEFC $FEFD $FEFC $FEFD
BIT 5
START
BIT BIT 1
NEXT
STOP
BIT
START
BIT
BIT 2 BIT 3 BIT 4 BIT 7BIT 0 BIT 6
01234567 01234567
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
Monitor Module (MON)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 227
Table 19-2. Mode Selection
Mode IRQ RST
Serial
Comm.
Mode
Selection Divider
PLL COP
Communication
Speed Comments
PTA0 PTA7 PTC0 PTC1 PTC3 External
Clock
Bus
Frequency
Baud
Rate
Monitor
VTST
VDD
or
VTST
10 1 0 0OffDisabled
4.9152
MHz
2.4576
MHz 9600 PTC3
determines
frequency
divider
VTST
VDDor
VTST
10 1 0 1OffDisabled
9.8304
MHz
2.4576
MHz 9600
User
VDD
or
VSS
VDD X X X X X X Enabled X X X
MON08
Function
[Pin No.]
VTST
[6]
RST
[4]
COM
[8]
SSEL
[10]
MOD0
[12]
MOD1
[14]
DIV4
[16]
OSC1
[13]
1. PTA0 must have a pullup resistor to VDD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600.
Baud rate using external oscillator is bus frequency / 256.
3. External clock is a 4.9152 or 9.8304 MHz canned oscillator on OSC1.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC 1 2 GND
NC 3 4 RST
NC 5 6 IRQ
NC 7 8 PTA0
NC 9 10 PTA7
NC 11 12 PTC0
OSC1 13 14 PTC1
VDD 15 16 PTC3
Development Support
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
228 Freescale Semiconductor
19.3.1.5 Commands
The monitor ROM firmware uses these commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
NOTE
Wait one bit time after each echo before sending the next byte.
Figure 19-12. Read Transaction
Figure 19-13. Write Transaction
READREAD
ECHO
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW DATA
RETURN
13, 21144
Notes:
2 = Data return delay, approximately 2 bit times 3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
44
1 = Echo delay, approximately 2 bit times
WRITE
WRITE
ECHO
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW DATA DATA
Notes:
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
113113332, 3
1 = Echo delay, approximately 2 bit times
Monitor Module (MON)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 229
A brief description of each monitor mode command is given in Table 19-3 through Table 19-8.
Table 19-3. READ (Read Memory) Command
Description Read byte from memory
Operand 2-byte address in high-byte:low-byte order
Data Returned Returns contents of specified address
Opcode $4A
Command Sequence
Table 19-4. WRITE (Write Memory) Command
Description Write byte to memory
Operand 2-byte address in high-byte:low-byte order; low byte followed by data byte
Data Returned None
Opcode $49
Command Sequence
Table 19-5. IREAD (Indexed Read) Command
Description Read next 2 bytes in memory from last address accessed
Operand 2-byte address in high byte:low byte order
Data Returned Returns contents of next two addresses
Opcode $1A
Command Sequence
READ
READ
ECHO
SENT TO MONITOR
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW DATA
RETURN
ADDRESS
LOW
WRITE
WRITE
ECHO
FROM HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW DATA DATA
IREAD
IREAD
ECHO
DATA
RETURN
DATA
FROM HOST
Development Support
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
230 Freescale Semiconductor
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full
64-Kbyte memory map.
Table 19-6. IWRITE (Indexed Write) Command
Description Write to last address accessed + 1
Operand Single data byte
Data Returned None
Opcode $19
Command Sequence
Table 19-7. READSP (Read Stack Pointer) Command
Description Reads stack pointer
Operand None
Data Returned Returns incremented stack pointer value (SP + 1) in high-byte:low-byte
order
Opcode $0C
Command Sequence
Table 19-8. RUN (Run User Program) Command
Description Executes PULH and RTI instructions
Operand None
Data Returned None
Opcode $28
Command Sequence
IWRITE
IWRITE
ECHO
FROM HOST
DATA DATA
READSP
READSP
ECHO
FROM HOST
SP
RETURN
SP
HIGH LOW
RUN
RUN
ECHO
FROM HOST
Monitor Module (MON)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 231
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command
tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program. The READSP command returns
the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at
addresses SP + 5 and SP + 6.
Figure 19-14. Stack Pointer at Monitor Mode Entry
19.3.2 Security
A security feature discourages unauthorized reading of ROM locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all ROM locations and execute code from ROM. Security remains bypassed
until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and
security code entry is not required. See Figure 19-15.
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a ROM location returns an invalid value and trying to execute code from ROM causes an illegal
address reset. After receiving the eight security bytes from the host, the MCU transmits a break character,
signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry.
CONDITION CODE REGISTER
ACCUMULATOR
LOW BYTE OF INDEX REGISTER
HIGH BYTE OF PROGRAM COUNTER
LOW BYTE OF PROGRAM COUNTER
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP
SP + 6
HIGH BYTE OF INDEX REGISTER
SP + 7
Development Support
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
232 Freescale Semiconductor
Figure 19-15. Monitor Mode Entry Timing
19.3.3 Baud Rate
With a 9.8304 MHz canned oscillator and the PTC3 pin high during reset, data is transferred between the
monitor and host at 9600 baud. Table 19-9 lists external frequencies required to achieve a standard baud
rate of 9600 BPS. Other standard baud rates can be accomplished using proportionally higher or lower
frequency generators.
Table 19-9. Monitor Baud Rate Selection
External
Frequency PTC3 Bus
Frequency
Baud
Rate
4.9152 MHz 0 2.4576 MHz 9600
9.8304 MHz 1 2.4576 MHz 9600
BYTE 1
BYTE 1 ECHO
BYTE 2
BYTE 2 ECHO
BYTE 8
BYTE 8 ECHO
COMMAND
COMMAND ECHO
PA0
RST
VDD
4096 + 32 CGMXCLK CYCLES
131121
BREAK
Notes:
2 = Data return delay, approximately 2 bit times
3 = Wait 1 bit time before sending next byte
3
FROM HOST
FROM MCU
1 = Echo delay, approximately 2 bit times
4
4 = Wait until clock is stable and monitor runs
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 233
Chapter 20
Electrical Specifications
20.1 Introduction
This section contains electrical and timing specifications.
20.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without
permanently damaging it.
NOTE
This device is not guaranteed to operate properly at the maximum ratings. Refer to 20.5 5.0-V DC
Electrical Characteristics for guaranteed operating conditions.
NOTE
This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIn and VOut be constrained to the range
VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if unused
inputs are connected to an appropriate logic voltage level (for example,
either VSS or VDD).
Characteristic(1)
1. Voltages referenced to VSS
Symbol Value Unit
Supply voltage VDD –0.3 to + 6.0 V
Input voltage VIn VSS – 0.3 to VDD + 0.3 V
Maximum current per pin excluding
VDD, VSS, and PTC0–PTC4 I± 15 mA
Maximum current for pins
PTC0–PTC4 IPTC0–PTC4 ± 25 mA
Maximum current into VDD IMVDD 150 mA
Maximum current out of VSS IMVSS 150 mA
Storage temperature Tstg –55 to +150 °C
Electrical Specifications
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
234 Freescale Semiconductor
20.3 Functional Operating Range
20.4 Thermal Characteristics
20.5 5.0-V DC Electrical Characteristics
Characteristic Symbol Value Unit
CV M
Operating temperature range TA–40 to +85 –40 to +105 –40 to +125 °C
Operating voltage range VDD 3 V ±10%
5 V ±10%
3 V ±10%
5 V ±10%
—
5 V ±10% V
Characteristic Symbol Value Unit
Thermal resistance
42-pin SDIP
44-pin QFP
θJA 60
95
°C/W
I/O pin power dissipation PI/O User determined W
Power dissipation(1)
1. Power dissipation is a function of temperature.
PDPD = (IDD × VDD) + PI/O = K/(TJ + 273 °C)W
Constant(2)
2. K is a constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and
TJ can be determined for any value of TA.
KPD × (TA + 273 °C) + PD2 × θJA W/°C
Average junction temperature TJTA + (PD × θJA)°C
Characteristic(1) Symbol Min Typ(2) Max Unit
Output high voltage
(ILoad = –2.0 mA) all I/O pins
(ILoad = –10.0 mA) all I/O pins
(ILoad = –10.0 mA) pins PTC0–PTC4 only
Maximum combined IOH for port C, port E,
port PTD0–PTD3
Maximum combined IOH for port PTD4–PTD7,
port A, port B
Maximum total IOH for all port pins
VOH
VOH
VOH
IOH1
IOH2
IOHT
VDD – 0.8
VDD – 1.5
VDD – 0.8
—
—
—
—
—
—
—
—
—
—
—
—
50
50
100
V
V
V
mA
mA
mA
Output low voltage
(ILoad = 1.6 mA) all I/O pins
(ILoad = 10 mA) all I/O pins
(ILoad = 15 mA) pins PTC0–PTC4 only
Maximum combined IOL for port C, port E,
port PTD0–PTD3
Maximum combined IOL for port PTD4–PTD7,
port A, port B
Maximum total IOL for all port pins
VOL
VOL
VOL
IOL1
IOL2
IOLT
—
—
—
—
—
—
—
—
—
—
—
—
0.4
1.5
1.0
50
50
100
V
V
V
mA
mA
mA
— Continued on next page
5.0-V DC Electrical Characteristics
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 235
Input high voltage
All ports, IRQ, RST, OSC1 VIH 0.7 × VDD —VDD V
Input low voltage
All ports, IRQ, RST, OSC1 VIL VSS —0.2 × VDD V
VDD supply current
Run(3)
Wait(4)
Stop(5)
25°C
25°C with TBM enabled(6)
25°C with LVI and TBM enabled(6)
–40°C to 85°C
–40°C to 85°C with TBM enabled(6)
–40°C to 85°C with LVI and TBM enabled(6)
IDD
—
—
—
—
—
—
—
—
15
4
2
20
300
—
50
500
20
8
—
—
—
35
—
—
mA
mA
µA
µA
µA
µA
µA
µA
I/O ports Hi-Z leakage current(7) IIL –10 — +10 µA
Input current IIn –1 — +1 µA
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
RPU 20 45 65 kΩ
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8pF
Monitor mode entry voltage VTST VDD + 2.5 —9.1V
Low-voltage inhibit, trip falling voltage VTRIPF 3.90 4.25 4.50 V
Low-voltage inhibit, trip rising voltage VTRIPR 4.00 4.35 4.60 V
Low-voltage inhibit reset/recover hysteresis
(VTRIPF + VHYS = VTRIPR)VHYS —100 —mV
POR rearm voltage(8) VPOR 0 — 100 mV
POR reset voltage(9) VPORRST 0 700 800 mV
POR rise time ramp rate(10) RPOR 0.035 — — V/ms
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V from rail. No
dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled. Port B leakage is specified in 20.12 ADC Characteristics.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
Characteristic(1) Symbol Min Typ(2) Max Unit
Electrical Specifications
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
236 Freescale Semiconductor
20.6 3.0-V DC Electrical Characteristics
Characteristic(1) Symbol Min Typ(2) Max Unit
Output high voltage
(ILoad = –0.6 mA) all I/O pins
(ILoad = –4.0 mA) all I/O pins
(ILoad = –4.0 mA) pins PTC0–PTC4 only
Maximum combined IOH for port C, port E,
port PTD0–PTD3
Maximum combined IOH for port PTD4–PTD7,
port A, port B
Maximum total IOH for all port pins
VOH
VOH
VOH
IOH1
IOH2
IOHT
VDD – 0.3
VDD – 1.0
VDD – 0.5
—
—
—
—
—
—
—
—
—
—
—
—
30
30
60
V
V
V
mA
mA
mA
Output low voltage
(ILoad = 0.5 mA) all I/O pins
(ILoad = 6.0 mA) all I/O pins
(ILoad = 10.0 mA) pins PTC0–PTC4 only
Maximum combined IOL for port C, port E,
port PTD0–PTD3
Maximum combined IOL for port PTD4–PTD7,
port A, port B
Maximum total IOL for all port pins
VOL
VOL
VOL
IOL1
IOL2
IOLT
—
—
—
—
—
—
—
—
—
—
—
—
0.3
1.0
0.8
30
30
60
V
V
V
mA
mA
mA
Input high voltage
All ports, IRQ, RST, OSC1 VIH 0.7 × VDD —VDD V
Input low voltage
All ports, IRQ, RST, OSC1 VIL VSS —0.3 × VDD V
VDD supply current
Run(3)
Wait(4)
Stop(5)
25°C
25°C with TBM enabled(6)
25°C with TBM enabled(7)
25°C with LVI and TBM enabled(7)
–40°C to 85°C
–40°C to 85°C with TBM enabled(7)
–40°C to 85°C with LVI and TBM enabled(6)
IDD
—
—
—
—
—
—
—
—
—
5.2
1.65
1
12
25
200
—
—
300
8
4
—
—
—
—
5
50
—
mA
mA
µA
µA
µA
µA
µA
µA
µA
I/O ports Hi-Z leakage current(8) IIL –10 — +10 µA
Input current IIn –1 — +1 µA
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
RPU 20 45 65 kΩ
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8pF
Monitor mode entry voltage VTST VDD + 2.5 —VDD + 4.5 V
— Continued on next page
5.0-V Control Timing
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 237
20.7 5.0-V Control Timing
Low-voltage inhibit, trip falling voltage VTRIPF 2.45 2.60 2.70 V
Low-voltage inhibit, trip rising voltage VTRIPR 2.50 2.66 2.80 V
Low-voltage inhibit reset/recover hysteresis
(VTRIPF + VHYS = VTRIPR)VHYS —60—mV
POR rearm voltage(9) VPOR 0 — 100 mV
POR reset voltage(10) VPORRST 0 700 800 mV
POR rise time ramp rate(11) RPOR 0.02 — — V/ms
1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2V from rail. No
dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2 V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Measured with TBM enabled using 32-kHz crystal.
8. Pullups and pulldowns are disabled.
9. Maximum is highest voltage that POR is guaranteed.
10. Maximum is highest voltage that POR is possible.
11. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
Characteristic(1)
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted.
Symbol Min Max Unit
Frequency of operation(2)
Crystal option
External clock option(3)
2. See 20.16 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
fOSC 32
dc(4)
4. Some modules may require a minimum frequency greater than dc for proper operation. See appropriate table for this in-
formation.
100
32.8
kHz
MHz
Internal operating frequency fOP (fBUS)—8.2MHz
Internal clock period (1/fOP)t
CYC 122 — ns
RST input pulse width low(5)
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
tRL 50 — ns
IRQ interrupt pulse width low(6) (edge-triggered)
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
tILIH 50 — ns
IRQ interrupt pulse period tILIL Note(7)
7. The minimum period, tILIL, should not be less than the number of cycles it takes to execute the interrupt service routine
plus tCYC.
—tCYC
Characteristic(1) Symbol Min Typ(2) Max Unit
Electrical Specifications
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
238 Freescale Semiconductor
20.8 3.0-V Control Timing
Figure 20-1. RST and IRQ Timing
Characteristic(1)
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted.
Symbol Min Max Unit
Frequency of operation(2)
Crystal option
External clock option(3)
2. See 20.16 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
fOSC 32
dc(4)
4. Some modules may require a minimum frequency greater than dc for proper operation. See appropriate table for this in-
formation.
100
16.4
kHz
MHz
Internal operating frequency fOP (fBUS)—4.1MHz
Internal clock period (1/fOP)t
CYC 244 — ns
RST input pulse width low(5)
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
tIRL 125 — ns
IRQ interrupt pulse width low(6) (edge-triggered)
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
tILIH 125 — ns
IRQ interrupt pulse period tILIL Note(7)
7. The minimum period, tILIL, should not be less than the number of cycles it takes to execute the interrupt service routine
plus tCYC.
—tCYC
RST
IRQ
tRL
tILIH
tILIL
Output High-Voltage Characteristics
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 239
20.9 Output High-Voltage Characteristics
Figure 20-2. Typical High-Side Driver Characteristics — Port PTA7–PTA0 (VDD = 4.5 Vdc)
Figure 20-3. Typical High-Side Driver Characteristics — Port PTA7–PTA0 (VDD = 2.7 Vdc)
Figure 20-4. Typical High-Side Driver Characteristics — Port PTC4–PTC0 (VDD = 4.5 Vdc)
–35
–30
–25
–20
–15
–10
–5
0
–40
0
25
IOH (mA)
–40
VOH (V)
3 3.4 3.6 3.8 4.0 4.23.2
85
VOH > VDD –0.8 V @ IOH = –2.0 mA
VOH > VDD –1.5 V @ IOH = –10.0 mA
–25
–20
–15
–10
–5
0
–40
0
25
IOH (mA)
1.3 1.7 1.9 2.1 2.3 2.51.5
85
VOH (V)
VOH > VDD –0.3 V @ IOH = –0.6 mA
VOH > VDD –1.0 V @ IOH = –4.0 mA
–35
–30
–25
–20
–15
–10
–5
0
–40
0
25
IOH (mA)
–40
VOH (V)
3 3.4 3.6 3.8 4.0 4.23.2
85
VOH > VDD –0.8 V @ IOH = –10.0 mA
Electrical Specifications
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
240 Freescale Semiconductor
Figure 20-5. Typical High-Side Driver Characteristics — Port PTC4–PTC0 (VDD = 2.7 Vdc)
Figure 20-6. Typical High-Side Driver Characteristics — Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc)
Figure 20-7. Typical High-Side Driver Characteristics — Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc)
–25
–20
–15
–10
–5
0
–40
0
25
IOH (mA)
1.3 1.7 1.9 2.1 2.3 2.51.5
85
VOH (V)
VOH > VDD –0.5 V @ IOH = –4.0 mA
–70
–60
–50
–40
–30
–20
–10
0
–40
0
25
IOH (mA)
–90
VOH (V)
3 3.4 3.6 3.8 4.0 4.23.2
85
–80
4.64.4
VOH > VDD –0.8 V @ IOH = –2.0 mA
VOH > VDD –1.5 V @ IOH = –10.0 mA
–25
–20
–15
–10
–5
0
–40
0
25
IOH (mA)
1.3 1.7 1.9 2.1 2.3 2.51.5
85
VOH (V)
VOH > VDD –0.3 V @ IOH = –0.6 mA
VOH > VDD –1.0 V @ IOH = –4.0 mA
Output Low-Voltage Characteristics
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 241
20.10 Output Low-Voltage Characteristics
Figure 20-8. Typical Low-Side Driver Characteristics — Port PTA7–PTA0
(VDD = 5.5 Vdc)
Figure 20-9. Typical Low-Side Driver Characteristics — Port PTA7–PTA0
(VDD = 2.7 Vdc)
Figure 20-10. Typical Low-Side Driver Characteristics — Port PTC4–PTC0
(VDD = 4.5 Vdc)
5
10
15
20
25
30
35
–40
0
25
IOL (mA)
0
VOL (V)
0 0.4 0.6 0.8 1.0 1.20.2
85
1.4 1.6
VOL < 0.4 V @ IOL = 1.6 mA
VOL < 1.5 V @ IOL = 10.0 mA
2
4
6
8
10
12
14
–40
0
25
IOL (mA)
0
VOL (V)
0.4 0.6 0.8 1.0 1.20.2
85
1.4 1.6
VOL < 0.3 V @ IOL = 0.5 mA
VOL < 1.0 V @ IOL = 6.0 mA
10
20
30
40
50
60
IOL (mA)
0
VOL (V)
0.4 0.6 0.8 1.0 1.2 1.4 1.6
–40
0
25
85
VOL < 1.0 V @ IOL = 15 mA
Electrical Specifications
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
242 Freescale Semiconductor
Figure 20-11. Typical Low-Side Driver Characteristics — Port PTC4–PTC0 (VDD = 2.7 Vdc)
Figure 20-12. Typical Low-Side Driver Characteristics — Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc)
Figure 20-13. Typical Low-Side Driver Characteristics — Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc)
5
10
15
20
25
30
–40
0
25
IOL (mA)
0
VOL (V)
0.40.60.81.01.20.2
85
1.4 1.6
VOL < 0.8 V @ IOL = 10 mA
5
10
15
20
25
30
35
–40
0
25
IOL (mA)
0
VOL (V)
0 0.4 0.6 0.8 1.0 1.20.2
85
1.4 1.6
VOL < 0.4 V @ IOL = 1.6 mA
VOL < 1.5 V @ IOL = 10.0 mA
2
4
6
8
10
12
14
–40
0
25
IOL (mA)
0
VOL (V)
0.2 0.4 0.6 0.8 1.00
85
1.2 1.6
1.4
VOL < 0.3 V @ IOL = 0.5 mA
VOL < 1.0 V @ IOL = 6.0 mA
Typical Supply Currents
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 243
20.11 Typical Supply Currents
Figure 20-14. Typical Operating IDD
Figure 20-15. Typical Wait Mode IDD
Figure 20-16. Typical Stop Mode IDD
0
2
4
6
8
10
12
123456789
fBUS (MHz)
IDD (mA)
14
16
5.5 V
3.3 V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
12 34 567 89
IDD (mA)
fBUS (MHz)
5.5 V
3.3 V
0
0.2
0.4
0.6
0.8
1.0
1.2
123456789
fBUS (MHz)
IDD (mA)
1.4
1.6
5.5 V
3.3 V
Electrical Specifications
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
244 Freescale Semiconductor
20.12 ADC Characteristics
Characteristic(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, VDDAD = 5.0 Vdc ± 10%, VSSAD = 0 Vdc, VREFH = 5.0 Vdc ± 10%, VREFL = 0
Symbol Min Max Unit Comments
Supply voltage VDDAD
2.7
(VDD min)
5.5
(VDD max) V
VDDAD should be tied to
the same potential as VDD
via separate traces.
Input voltages VADIN 0VDDAD VVADIN ≤ VREFH
Resolution BAD 88Bits
Absolute accuracy
(VREFL = 0 V,
VREFH = VDDAD = 5 V ± 10%)
AAD –1 +1 LSB Includes quantization
ADC internal clock fADIC 0.5 1.048 MHz tAIC = 1/fADIC, tested only
at 1 MHz
Conversion range RAD VREFL VREFH VVREFH = VDDAD
VREFL = VSSAD
Power-up time tADPU 16 tAIC cycles
Conversion time tADC 16 17 tAIC cycles
Sample time(2)
2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
tADS 5—
tAIC cycles
Zero input reading(3)
3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
ZADI 00 01 Hex VIN = VREFL
Full-scale reading(3) FADI FE FF Hex VIN = VREFH
Input capacitance CADI — (20) 8 pF Not tested
Input leakage(4)
Port B
4. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
—–1 +1 µA
5.0-V SPI Characteristics
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 245
20.13 5.0-V SPI Characteristics
Diagram
Number(1)
1. Numbers refer to dimensions in Figure 20-17 and Figure 20-18.
Characteristic(2)
2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins.
Symbol Min Max Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
fOP/128
dc
fOP/2
fOP
MHz
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2
1
128
—
tCYC
tCYC
2 Enable lead time tLead(S) 1—
tCYC
3 Enable lag time tLag(S) 1—
tCYC
4
Clock (SPSCK) high time
Master
Slave
tSCKH(M)
tSCKH(S)
tCYC –25
1/2 tCYC –25
64 tCYC
—
ns
ns
5
Clock (SPSCK) low time
Master
Slave
tSCKL(M)
tSCKL(S)
tCYC –25
1/2 tCYC –25
64 tCYC
—
ns
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
30
30
—
—
ns
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
30
30
—
—
ns
ns
8
Access time, slave(3)
CPHA = 0
CPHA = 1
3. Time to data active from high-impedance state
tA(CP0)
tA(CP1)
0
0
40
40
ns
ns
9Disable time, slave(4)
4. Hold time to high-impedance state
tDIS(S) —40ns
10
Data valid time, after enable edge
Master
Slave(5)
5. With 100 pF on all SPI pins
tV(M)
tV(S)
—
—
50
50
ns
ns
11
Data hold time, outputs, after enable edge
Master
Slave
tHO(M)
tHO(S)
0
0
—
—
ns
ns
Electrical Specifications
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
246 Freescale Semiconductor
20.14 3.0-V SPI Characteristics
Diagram
Number(1)
1. Numbers refer to dimensions in Figure 20-17 and Figure 20-18.
Characteristic(2)
2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins.
Symbol Min Max Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
fOP/128
dc
fOP/2
fOP
MHz
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2
1
128
—
tCYC
tCYC
2 Enable lead time tLead(s) 1—
tCYC
3 Enable lag time tLag(s) 1—
tCYC
4
Clock (SPSCK) high time
Master
Slave
tSCKH(M)
tSCKH(S)
tCYC –35
1/2 tCYC –35
64 tCYC
—
ns
ns
5
Clock (SPSCK) low time
Master
Slave
tSCKL(M)
tSCKL(S)
tCYC –35
1/2 tCYC –35
64 tCYC
—
ns
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
40
40
—
—
ns
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
40
40
—
—
ns
ns
8
Access time, slave(3)
CPHA = 0
CPHA = 1
3. Time to data active from high-impedance state
tA(CP0)
tA(CP1)
0
0
50
50
ns
ns
9Disable time, slave(4)
4. Hold time to high-impedance state
tDIS(S) —50ns
10
Data valid time, after enable edge
Master
Slave(5)
5. With 100 pF on all SPI pins
tV(M)
tV(S)
—
—
60
60
ns
ns
11
Data hold time, outputs, after enable edge
Master
Slave
tHO(M)
tHO(S)
0
0
—
—
ns
ns
3.0-V SPI Characteristics
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 247
Figure 20-17. SPI Master Timing
NOTE
Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
SS PIN OF MASTER HELD HIGH
MSB IN
SS
INPUT
SPSCK OUTPUT
SPSCK OUTPUT
MISO
INPUT
MOSI
OUTPUT
NOTE
4
5
5
1
4
BITS 6–1 LSB IN
MASTER MSB OUT BITS 6–1 MASTER LSB OUT
11 10 11
76
NOTE
Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.
SS PIN OF MASTER HELD HIGH
MSB IN
SS
INPUT
SPSCK OUTPUT
SPSCK OUTPUT
MISO
INPUT
MOSI
OUTPUT
NOTE
4
5
5
1
4
BITS 6–1 LSB IN
MASTER MSB OUT BITS 6–1 MASTER LSB OUT
10 11 10
76
a) SPI Master Timing (CPHA = 0)
b) SPI Master Timing (CPHA = 1)
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
Electrical Specifications
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
248 Freescale Semiconductor
Figure 20-18. SPI Slave Timing
Note: Not defined but normally MSB of character just received
SLAVE
SS
INPUT
SPSCK INPUT
SPSCK INPUT
MISO
INPUT
MOSI
OUTPUT
4
5
5
1
4
MSB IN
BITS 6–1
8
610
5
11
NOTE
SLAVE LSB OUT
9
3
LSB IN
2
7
BITS 6–1
MSB OUT
Note: Not defined but normally LSB of character previously transmitted
SLAVE
SS
INPUT
SPSCK INPUT
SPSCK INPUT
MISO
OUTPUT
MOSI
INPUT
4
5
5
1
4
MSB IN
BITS 6–1
8
610
NOTE SLAVE LSB OUT
9
3
LSB IN
2
7
BITS 6–1
MSB OUT
10
a) SPI Slave Timing (CPHA = 0)
b) SPI Slave Timing (CPHA = 1)
11
11
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
Timer Interface Module Characteristics
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 249
20.15 Timer Interface Module Characteristics
Figure 20-19. Input Capture Timing
20.16 Clock Generation Module Characteristics
20.16.1 CGM Component Specifications
Characteristic Symbol Min Max Unit
Timer input capture pulse width tTH, tTL 2—
tCYC
Timer Input capture period tTLTL Note(1)
1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
—tCYC
Characteristic Symbol Min Typ Max Unit
Crystal reference frequency fXCLK 30 32.768 100 kHz
Crystal load capacitance(1)
1. Crystal manufacturer value.
CL— 12.5 — pF
Crystal fixed capacitance(2)
2. Capacitor on OSC1 pin. Does not include parasitic capacitance due to package, pin, and board.
C1—15 —pF
Crystal tuning capacitance(2) C2—15 —pF
Feedback bias resistor RB11022MΩ
Series resistor(3)
3. Capacitor on OSC2 pin. Does not include parasitic capacitance due to package, pin, and board.
RS100 330 470 kΩ
INPUT CAPTURE
RISING EDGE
INPUT CAPTURE
FALLING EDGE
INPUT CAPTURE
BOTH EDGES
tTH
tTL
tTLTL
tTLTL
tTLTL
tTL
tTH
Electrical Specifications
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
250 Freescale Semiconductor
20.16.2 CGM Electrical Specifications
20.17 Memory Characteristics
Description Symbol Min Typ Max Unit
Operating voltage VDD 3.0 — 5.5 V
Operating temperature T –40 25 125 oC
Crystal reference frequency fRCLK 30 32.768 100 kHz
Range nominal multiplier fNOM — 38.4 — kHz
VCO center-of-range frequency(1)
1. 5.0 V ± 10% VDD
fVRS 38.4 k — 40.0 M Hz
Medium-voltage VCO center-of-range frequency(2)
2. 3.0 V ± 10% VDD
fVRS 38.4 k — 40.0 M Hz
VCO range linear range multiplier L 1 — 255
VCO power-of-two range multiplier 2E1—4
VCO multiply factor N 1 — 4095
VCO prescale multiplier 2P118
Reference divider factor R 1 1 15
VCO operating frequency fVCLK 38.4 k — 40.0 M Hz
Bus operating frequency(1) fBUS ——8.2MHz
Bus frequency @ medium voltage(2) fBUS ——4.1MHz
Manual acquisition time tLock ——50ms
Automatic lock time tLock ——50ms
PLL jitter(3)
3. Deviation of average bus frequency over 2 ms. N = VCO multiplier.
fJ0—
fRCLK x
0.025% x
2P N/4
Hz
External clock input frequency
PLL disabled fOSC dc — 32.8 M Hz
External clock input frequency
PLL enabled fOSC 30 k — 1.5 M Hz
Characteristic Symbol Min Max Unit
RAM data retention voltage VRDR 1.3 — V
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor 251
Chapter 21
Ordering Information and Mechanical Specifications
21.1 Introduction
This section provides ordering information for the MC68HC08GP32A and MC68HC08GP16A along with
the dimensions for:
• 42-pin shrink dual in-line package (case 858-01)
• 44-pin plastic quad flat pack (case 824A-01)
The following figures show the latest package drawings at the time of this publication. To make sure that
you have the latest package specifications, contact your local Freescale Sales Office.
21.2 MC Order Numbers
These part numbers are generic numbers only. To place an order, ROM code must be submitted to the
ROM Processing Center (RPC). Refer to the Customer Interface Tool (CIT) link at:
http://freescale.com
Figure 21-1. Device Numbering System
Table 21-1. MC Order Numbers
MC Order Number Operating
Temperature Range(1)
1. Temperature designators:
C = –40°C to +85°C
V = –40°C to +105°C
M = –40°C to +125°C
Package(2)
2. SDIP = Shrink dual in-line package
QFP = Quad flat package
MC68HC08GP32ACB –40°C to +85°C
42-pin SDIP
MC68HC08GP32AVB –40°C to +105°C
MC68HC08GP32AMB(3)
3. Temperature grade “M” is available for 5 V operating voltage only.
–40°C to +125°C
MC68HC08GP16ACB –40°C to +85°C
MC68HC08GP16AVB –40°C to +105°C
MC68HC08GP16AMB(3) –40°C to +125°C
MC68HC08GP32ACFB –40°C to +85°C
44-pin QFP
MC68HC08GP32AVFB –40°C to +105°C
MC68HC08GP32AMFB(3) –40°C to +125°C
MC68HC08GP16ACFB –40°C to +85°C
MC68HC08GP16AVFB –40°C to +105°C
MC68HC08GP16AMFB(3) –40°C to +125°C
M C 6 8 H C 0 8 G P X X A X X X E
FAMILY
PACKAGE DESIGNATOR
TEMPERATURE RANGE
Pb FREE
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MC68HC08GP32A
Rev. 1.0, 03/2006
