www.irf.com 1
7/30/04
IRL3714ZPbF
IRL3714ZSPbF
IRL3714ZLPbF
HEXFET® Power MOSFET
Notes through are on page 12
Applications
Benefits
lLow R DS(on) at 4.5V VGS
lUltra-Low Gate Impedance
lFully Characterized Avalanche Voltage
and Current
lHigh Frequency Synchronous Buck
Converters for Computer Processor Power
lLead-Free
PD - 95661
D2Pak
IRL3714ZS
TO-220AB
IRL3714Z TO-262
IRL3714ZL
VDSS RDS(on) ma x Qg
20V 16m
:
4.8nC
Absolute Maximum Ratings
Parameter Units
VDS Dr ain-t o-Source Vo lt age V
VGS Gat e- to-S ource Voltage
ID @ TC = 25 °C Co nti n uo us D rain C ur rent, VGS @ 10V A
ID @ TC = 10 0°C
Co nti n uo us D rain C ur rent, V
GS
@ 10V
IDM
Pulsed Dr ain Current
c
PD @TC = 25°C Maximum Power D issi pation W
PD @TC = 100°C Maximum Power D issi pation
Linear Derating Factor W/°C
TJ Operating Junc ti on and °C
TSTG Stor ag e Te m per atur e Ra ng e
Soldering Temperature, for 10 seconds
Therm al Resi stance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 4.3 °C/W
RθCS Ca s e- to- S i n k , Fl at Grease d S u r fa ce
e
0.50 –––
RθJA Junction-to-Ambient
e
––– 62
RθJA Junc ti o n- to- Am bien t (P C B Mo unt )
h
––– 40
35
0.23
18
Max.
36
g
25
g
140
± 20
20
300 ( 1.6m m f r o m ca se)
-55 to + 175
IRL3714Z/S/LPbF
2www.irf.com
S
D
G
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BV
DSS Dr ai n- to- Sou r c e B r e ak dow n Volt a ge 20 ––– ––– V
∆Β
V
DSS
∆
T
J Breakdown Vo lt age Temp. Coefficient ––– 0.015 ––– mV/°C
R
DS(on) Static D rain- to- Sou r c e O n- Res i s tanc e ––– 13 16
m
Ω
––– 21 26
V
GS(th) Gate Thr es h old V o ltage 1. 65 2.1 2.55 V
∆
V
GS(th)
∆
T
J G ate Thr es h old V o ltage C oe fficient ––– -5 .2 ––– m V / °C
DSS Dr ai n- to- Sou r c e Leak age Cur r en t ––– ––– 1. 0 µA
––– ––– 150
GSS Gate-to-Sour c e For war d Leak ag e ––– ––– 100 nA
Gate- to- S our c e R ev e r s e Leak age ––– ––– -100
gfs For ward Tra nsconductance 21 ––– ––– S
Q
gTotal Gate Charge ––– 4.8 7.2
Q
gs1 Pre-Vth Gate-to-Source Charge ––– 1.7 –––
Q
gs2 Post-Vth Gate-to-Source Charge ––– 0.80 ––– nC
Q
gd Gate-to-D r ain Char ge ––– 1.7 –––
Q
godr G ate C ha r ge Ov e r dr i ve ––– 0. 60 ––– Se e Fi g. 16
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
––– 2.5 –––
Q
oss Output Charge ––– 2.7 ––– nC
d(on) Turn-On Delay Time ––– 6.0 –––
rRise Time ––– 13 –––
d(off) Turn-Off Delay Ti me ––– 10 ––– n s
fFall Tim e –– – 5.0 –––
C
iss In pu t C apac it a nc e ––– 550 –––
C
oss Out pu t Capac it a nc e ––– 180 ––– pF
C
rss Reve r s e Tr a ns fer C ap ac it a nc e ––– 99 – ––
Avalanc he Ch arac te ri stics
Parameter Units
E
AS
Si ngle Pulse Av alanc he E n er g y
d
mJ
AR
Avalanche Current
c
A
E
AR
Repeti ti ve Avalanche Energy
c
mJ
Diode Charac teristics
Pa r a me te r Min. Ty p . Max . Units
SContin uous Source Cu rren t ––– –––
36
g
(Body Diode) A
SM Pulsed Source Current ––– ––– 140
(Body Diode)
c
V
SD Diode Forward Voltage –– – ––– 1.0 V
rr Reverse Recovery Time ––– 8.3 12 ns
Q
rr Reverse Recovery Charge ––– 1.5 2.3 nC
MOSFET symbol
VGS = 4.5V, ID = 12 A
e
–––
VGS = 4.5V
Typ.
–––
–––
ID = 14A
VGS = 0V
VDS = 10V
TJ = 25°C, IF = 14 A, V DD = 10V
di /dt = 100A/µs
e
TJ = 25°C, IS = 14A, VGS = 0V
e
showing the
integra l revers e
p-n junct ion diode.
VDS = VGS, ID = 250µ A
VDS = 16V , V GS = 0V
VDS = 16V , V GS = 0V , TJ = 12 5°C
Cla m ped I n du ctive Lo ad
VDS = 10V , I D = 14A
VDS = 10V , V GS = 0V
VDD = 10V, V GS = 4.5V
e
ID = 14A
VDS = 10V
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 15A
e
VGS = 20V
VGS = -20V
Conditions
3.5
Max.
23
14
ƒ = 1. 0M H z
IRL3714Z/S/LPbF
www.irf.com 3
Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1 110
VDS, Dr ain-to-Source V oltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM 3.0V
30µs PU LSE WID TH
Tj = 25°C
3.0V
0.1 110
VDS, Dr ain-to-Source V oltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
30µs PU LSE WID TH
Tj = 175°C
3.0V
VGS
TOP 10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM 3.0V
2345678910
VGS, Gate-t o-Sour ce Voltage (V)
1.0
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 175°C
VDS = 10V
30µs PU LSE WID TH
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperat ure (° C )
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 36A
VGS = 10V
IRL3714Z/S/LPbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drai n-to- Source V oltage (V )
10
100
1000
10000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0.0 0.5 1.0 1.5 2.0 2.5
VSD, Source-to- Drai n Voltage (V )
1.00
10.00
100.00
1000.00
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0 1 10 100
VDS, Dr ain-to-Source V oltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
Tc = 25°C
Tj = 175°C
Single Pulse
01234567
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VGS, Gate-to-Source Voltage (V)
VDS= 16V
VDS= 10V
ID= 14A
IRL3714Z/S/LPbF
www.irf.com 5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature Fig 10. Threshold Voltage vs. Temperature
25 50 75 100 125 150 175
TC , Case Temperatur e (°C)
0
5
10
15
20
25
30
35
40
ID, Drain Current (A)
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration ( s ec)
0.01
0.1
1
10
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τi (sec)
1.292 0.000135
2.337 0.000882
0.652 0.005472
τJ
τJ
τ1
τ1τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
τ
τC
Ci=
τ
i
/
Ri
Ci= τi/Ri
IRL3714Z/S/LPbF
6www.irf.com
D.U.T. V
D
S
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
VGS
VDS
9
0%
10%
td(on) td(off)
trtf
VGS
Pulse Widt h < 1µs
D uty Fa c to r < 0. 1%
VDD
VDS
LD
D.U.T
+
-
25 50 75 100 125 150 175
Start ing TJ , Juncti on Temperatur e (°C )
0
20
40
60
80
100
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 3.7A
6.2A
BOTTOM14A
IRL3714Z/S/LPbF
www.irf.com 7
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRL3714Z/S/LPbF
8www.irf.com
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms 2×Rds(on )
()
+I×Qgd
ig
×Vin ×f
⎛
⎝
⎜ ⎞
⎠
⎟ +I×Qgs2
ig
×Vin ×
f
⎛
⎝
⎜ ⎞
⎠
⎟
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝ ⎞
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝
⎜ ⎞
⎠ +Qrr ×Vin ×
f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and of f there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
IRL3714Z/S/LPbF
www.irf.com 9
L EAD ASSIG NME N TS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
- B -
1.32 (.052)
1.22 (.048)
3X 0. 55 (.022)
0. 46 (.018)
2. 92 (.115)
2. 64 (.104)
4. 69 (.185)
4. 20 (.165)
3X 0.93 (.037)
0.69 (.027)
4.06 (.160)
3.55 (.140)
1.15 (.045)
MIN
6.47 (.255)
6.10 (.240)
3.78 (.149)
3.54 (.139)
- A -
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
15.24 (.600)
14.84 (.584)
14.09 (.555)
13.47 (.530)
3X 1.40 (.055)
1.15 (.045)
2.54 (.100)
2X
0.36 (.014) M B A M
4
1 2 3
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMEN SION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
HEXFET
1- GATE
2- DRAIN
3- SOURCE
4- DRAIN
LEAD ASS I G N M ENTS
IGBT s, CoPA C
K
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE:
IN TH E ASSEMBLY LINE "C"
THIS IS AN IRF1010
LOT CODE 1789
ASSEMBLED ON WW 19, 1997 PART NUMBE
R
ASSEMBLY
LOT CODE
DATE CODE
YEAR 7 = 1997
LINE C
WEEK 19
LOGO
RECTIFIER
INTERNATIONAL
Note: "P" in asse mb ly line
posit ion indicates "Lead-Free"
IRL3714Z/S/LPbF
10 www.irf.com
D2Pak Part Marking Information
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
Note: "P" in assembly line
position indicates "Lead-Free"
F530S
THIS IS AN IRF530S WITH
LOT C ODE 8024
ASSEMBLED O N W W 02, 2000
IN T HE ASSEMBLY LINE "L"
AS S E MB L Y
LOT CODE
INTERNATIONAL
RECTIFIER
LOGO
PART NUM BE
R
DATE CODE
YEAR 0 = 2000
WEEK 02
LI NE L
OR
F530S
A = ASSEMBLY SITE CODE
WEEK 02
P = DE S IGNAT ES LEAD-F REE
PRODUCT (OPTIONAL)
RECTIFIER
INTERNATIONAL
LOGO
LOT CODE
AS S E MB L Y YEA R 0 = 2000
DATE C ODE
PART NUM BER
IRL3714Z/S/LPbF
www.irf.com 11
TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
ASS EMBLY
LOT CODE
RECTIFIER
INTERNATIONAL
A SSEMBLED ON WW 19, 1997
Note: "P" in assembly line
position indicates "Lea d-Free"
IN THE ASSEMBLY LINE "C" LOGO
THIS IS AN IRL310 3 L
LOT C ODE 1789
EXAMPLE:
LINE C
DATE CODE
WEEK 19
YEA R 7 = 1997
PART NUMBER
PART NUMBER
LOGO
LOT CODE
ASS EMBLY
INTERNATIONAL
RECTIFIER
PRODUCT ( OPTIONAL)
P = DESIGNATES LEAD-FR EE
A = ASSEMBLY SITE CODE
WEEK 19
YEAR 7 = 199 7
DATE CODE
OR
IRL3714Z/S/LPbF
12 www.irf.com
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/04
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.22mH, RG = 25Ω,
IAS = 14A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging
time as Coss while VDS is rising from 0 to 80% VDSS.
This is only applied to TO-220AB pakcage.
This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
TO-220AB package is not recommended for Surface Mount Application.
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
F
EED DI RECTIO N
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
F
EED DIRECTIO N
10.90 (.429)
10.70 (.421) 16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957
)
23.90 (.941
)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13. 50 (. 53 2)
12. 80 (. 50 4)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 ( 2.362
)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CO NTRO LLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/