LNB
Parabola
Coaxial
Cable
Satellite
Receiver To TV Set
1. ABSTRACT
LNBP is the integrated solution for supplying/interfacing satellite LNB modules. It gives good
performances in a simple and economical way, with a minimum use of external components. It is
comprised of functions that realize LNB supplying/interfacing in accordance to the international
standards.
2. INTRODUCTION.
Figure 1: Basic Satellite Installation
A typical satellite receiver system is formed by these blocks (reported in figure 1):
1. The parabola is the antenna of the system and focuses the satellite signal to the LNB;
2. The LNB (low noise block) is placed on the focus of the parabola and converts the incoming
signal in the 10GHz range to a lower frequency signal (in the 1-2GHz range) called ”first
conversion signal”. This allows the signal to be carried by an inexpensive coaxial cable towards
the receiver. Additionally, it improves the first conversion signal level by a built-in low noise
amplifier. A universal LNB can change the type of polarization (horizontal or vertical) or operative
band by command signals sent by the receiver;
3. The coaxial cable joins the LNB to the receiver and carries out 3 functions:
a) to transfer the first conversion signal from the LNB to the receiver;
b) to transfer the command signals from the receiver to the LNB to change polarization or signal
band;
c) to carry the DC voltage to supply the LNB.
4. The receiver converts the first conversion signal into control signals for the TV system. The
receiver provides for that provides for two important features:
July 2000 1/17
AN1230
APPLICATION NOTE
LNB SUPPLY AND CONTROL VOLTAGE REGULATOR
(PARALLEL INTERFACE)
F. Lentini - G. Benenati
AN1230 - APPLICATION NOTE
2/17
a) to supply the LNB block;
b) to generate all the signals/voltagesthat LNB needs to operate correctly.
5. The supply/interface block is placed inside the receiver. Itmust perform the followingfunctions:
a) be ready to accept future digital standards with an external modulation input and fast oscillator
start-up;
b) implement the loop-through function in slave condition for single dish, multiple receiver
system;
c) accept the paralleling of 2 or more receivers and, in this condition. avoid the flow of reverse
current from the output to the GND;
d) give accurate, thermal compensated outputs with the possibility to compensate the DC
voltage drop caused by long coaxial cables;
e) be reliable;
f) provide overload (better if dynamic) and thermal protection with diagnostic;
g) avoid every type of trimming;
h) provide the possibilityto be driven by amicrocontroller or a simple digital logic to implement all
these functions;
i) Finally, it must be cheap and get a small area in the board.
All these functions are hard to be implemented with discrete components, but are greatly made easier by
using an integrated device, like LNBP, that has been specially designed for this purpose.
3. FUNCTIONAL BLOCKS.
LNBP comprises the following operative blocks (see figure 2):
Figure 2: Internal Block Diagram
PREREG.
OUTPUT VOLT
S ELECTIO N
LINE LENGHT
COMPENSATION
CURRENT LIMIT
Vcc2
EN
VSEL
LLC
CEXT
REFERENCE
ERR.AMP.
OSCILLATOR
22KHz
ENT
CURR.AMP.
OUTPUT PORT
S ELECTIO N
OSEL
LNBA
LNBB
MI
Vcc1
THERMAL PROT.
OLF
EXTM
AN1230 - APPLICATION NOTE
3/17
1. The oscillator is activated by putting the ENT pin (Enable Tone) = H and is factory trimmed at
22KHz ±2KHz, avoiding the need to use external trimming. The rise and fall edges are
controlled to be in the 5 to 15µs range, 10µs typ., to avoid RF pollution towards the receiver. The
Duty Cycle is 50% typ. It modulates the DC output with a ±0.3V amplitude and 0V average. The
presence of this signal usually gives the LNB information about the band to be received.
2. The OSEL (OUTPUT PORT SELECTION) selects the two outputs of the LNB (LNBA and LNBB),
in order to drive a dual-dish system, depending on its present state. When OSEL is L, the LNBA
port is selected. When OSEL is H, the LNBB port is selected. The LNBA and LNBB outputs
supply either 13V or 18V. If VSEL is low (VSEL = L) 13V is selected, otherwise, if VSEL is high
(VSEL = H) 18V is selected. This kind of feature changes the LNBP polarization type. The LNB
switches horizontal or vertical polarization depending on the supply voltage it gets from the
receiver.
3. In order to keep the power dissipation of the device low, the input selector automatically selects
Vcc1, that is the lowest input voltage, when 13 V out is selected (i.e. VSEL is L). If 18V out is
selected (i.e. VSEL is H), Vcc2 input is selected. So power dissipation at Iout=500mA is:
Pd=(22-18)*0.5=2W (with Vcc2=22V and Vout=18V) or (15-13)*0.5=1W (with Vcc1=15V and
Vout=13V).Without input selection we should have Pd=(22-13)*0.5=4.5W, which is much higher.
Moreover, an internal switch selects the MI (MASTER INPUT) to be transferred to the LNBA
when the EN pin is low. This case occurs when two receivers are connected in series and the
slave receiver (the nearest to the antenna) is disabled. The master receiver supplies the LNB by
means of the MI input of the slave receiver.
4. The line length compensation function is useful when the antenna is connected to the receiver
by a long coaxial cable that adds a considerable DC voltage drop. When the LCC pin is H, the
output voltage selected is increased by about 1V.
5. The reference drives all the internal blocks that require a high precision thermal compensated
voltage source.
6. The LNBP has two different protection features, and both turn off the outputs. The first one acts
in overload conditions (i.e. for output current ≥500mA), and the second for overheating (i.e. for
Tamb ≥150°C).
a) The overload protection case occurs when output current request is ≥ 500mA. In this condition
the device limits the output current at 500mA for a time Ton depending on the Cext value.
When Ton has elapsed, output goes low for a time of Toff=15*Ton. This keeps the power
dissipated by the device low in overload conditions, and avoids to oversize the heatsink in
such a condition.
b) In the thermal protection case the output is disabled until the chip temperature has fallen. After
that the LNBP restarts working properly. The LNBA bypass switch is not protected, so the MI
input must be driven by a current limited voltage source.
Figure 3: LNBP Pin Grouping
LNBP20CR
MI
Vcc2
Vcc1
LNBA
LNBB
EN (ACTIVEH)
LLC (ACTIVE H)
ENT (ACTIVE H)
OSEL (L=LNBA,H=LNBB)
VSEL (L=13V, H=18V)
EXTM
CEXT
OLF
INPUTS OUTPUTS
CONTROL
SIGNAL
AN1230 - APPLICATION NOTE
4/17
0 5 10 15 20 25
0
1,000
2,000
3,000
4,000
5,000
CAPACITOR Cext( µF)
toff (ms)
Toff time vs. Cext
0 5 10 15 20 25
0
50
100
150
200
250
300
CAPACITOR Cext( µF)
ton (ms)
Ton timevs. Cext
In figure 3 the LNBP pins are grouped by functions. The 5 control signals are logic inputs that control the
IC function, and it is recommended that the VIH not exceed 7V.
Cext controls the restore timing of the overload protection. If an overload protection is present, output
goes low for a time imposed by the Cext value. At the same time the OLF pin, an open collector output,
goes low.
In figure 4 and figure 5 the behavior of Ton and Toff times vs. Cext is respectively shown. When Toff has
elapsed, the output returns active for a time Ton=Toff/15. Then, OLF returns a high impedance output. If
the overload is still present the cycle is repeated. This behavior greatly reduces the dissipation in the
device. Infact, in short circuit conditions with Vcc2=25 V, considering Iout internally limited at 650mA and
Toff=15*Ton we obtain: Pd average=Vin*Iout*Ton/(Ton+Toff)=25*0.65*1/(1+15)=1.02W, that is lower than
the power dissipated in normal conditions.
Figure 4: Overload Protection On Time versus Cext
Figure 5: Overload Protection Off Time versus Cext
The Cext must be properly chosen. It is related to the Iout and Cout (total capacitor connected to the
LNBA or LNBB output) values. Large Cout values at start-up give high current peak for a long time, and
consequently, an overload condition for a time that could be greater than the Ton imposed by Cext. So
the output will be forced low, completely discharge and will not start. For proper use it is necessary that
AN1230 - APPLICATION NOTE
5/17
External
Modulation
Input
Vin
Cin = 10µFEXTM
LNBP
LNBA
or
LNBB Vout
External
Modulation
Input V1
R2
Cin = 10µFEXTM
LNBA
or
LNBB Vout
LNBP
R1 Vin
Cout/Cext ≤20. The OLF also gives information about the thermal protection status. If the thermal
protection is triggered, the output is disabled and the OLF goes low. When the chip temperature has
fallen, the output returns active and the OLF returns to its 3-state condition.
By sensing the ON/OFF ratio of the OLF signal, a microcontroller can discriminate if an overload or a
thermal protection is present.
EXTM modulates the Vout by a capacitor connected in series (see figure 6). In this case:
Vout a.c.=Vin a.c.*Vout d.c./3 where, respectively, Vout a.c. and Vin a.c. are alternate components of
Vout and Vin, and Vout d.c. is the direct component of Vout. For example, if an a.c. signal of 600mV p.p.
must be imposed to the 13V d.c. out, the formula is as follows:
Vin a.c.= 3*Vout a.c./Vout d.c.=3*600/13 ª140 mV p.p. If we dispose a 0-5V square wave signal to
modulate output voltage, it is necessary to lowerthis signal amplitude.In accordance to figure7 we have:
R1=R2*(V1/Vin-1).
Figure 6: How to Use EXTM Input
Figure 7: How to Adjust the External Modulation Level
R2 must be in the 50Ohm range to minimize the effects of the EXTM input resistance variations. In our
example we obtain:
R1=50*(5/0.14-1)=1.7kOhm.
As a side effect, the EXTM modifies the Vout by a resistor connected between this input and the GND.
Figure 8 and 9 report the Vout value vs. R.
AN1230 - APPLICATION NOTE
6/17
GS
D
SW1
TR1
TR2
TR3
TR4
TR5
LNBA
LNBB
MI
Vcc2
Vcc1
13V OR 18V
13V OR 18V
22V TO 25V
15V TO 25V
∞10K 4.7K2.2K 1K1.5K 680 470 330 220 150 100 47 0
17.50
20.50
OUTPUT VOLTAGE (V)
Ta=+25°C
18.00
18.50
19.00
19.50
20.00
Vcc1= Vcc2 = 24V
Resistance(Ohm)
Vout value vs. Resistance
∞10K 4.7K 2.2K 1K1.5K 680 470 330 220 150 100 47 0
12.00
15.00
Voutvalue vs. Resistance
OUTPUT VOLTAGE (V)
Ta=+25°C
12.50
13.00
13.50
14.00
14.50
Vcc1=Vcc2 = 24V
Resistance(Ohm)
Figure 8: Vout Value vs. Resistance on the EXTM pin at VSEL = L
Figure 9: Vout Value vs. Resistance on the EXTM pin at VSEL = H
Figure 10: LNBP Output Stages
AN1230 - APPLICATION NOTE
7/17
0 100 200 300 400 500 600 700
2
2.5
3
3.5
4
4.5
5
5.5
6
Iout (mA)
Vgs (V)
Vcc2-VMI = 5V
Vcc2-VMI = 4V
Vcc2-VMI = 3V
Vcc2- VMI = 1 ÷
2V
Vgs vs. Iout
Figure10
4. OPERATING MODE.
LNBP has 3 power inputs (Vcc1, Vcc2 and MI) and two outputs (LNBA, LNBB) internally connected
in accordance to the scheme reported in figure 10. By analyzing this scheme we can make out
the following results:
1. TR1 is an N-channel Power MOSFET with its source connected to the LNBA. It is driven bySW1,
that joins the gate to Vcc2. The drop between MI and LNBA is due to the Ron of TR1, but in
some conditions it is increased by inadequate driving. In fact we have:
Vdrop=Vdrain-Vsource=VMI-(Vcc2-Vgs)=Vgs-(Vcc2-VMI).
We can see that the drop can be minimized increasing the (Vcc2-VMI) value. For example, if
Vcc2 increases, the effect of inadequate driving is cancelled.
Vgs depends on the TR1 and Iout characteristics. Figure 11 gives the Vgs vs. Iout plot, with
Vcc2-VMI as the parameter. Therefore, given Iout,Vcc2 and VMI we can calculate the Vdrop. If
Vcc2=22V, MI=21V and Iout=500mA the formula is as follows: Vdrop=Vgs-1V. In figure 11 it
results that Vgs=3.1V at ILOAD=500mA and Vcc2-VMI=1V and in such conditions
Vdrop=3.1V-1V=2.1V.
If we increase Vcc2 at 26V we obtain: Vdrop=5.65V-5V=0.65V, which is much lower.
Figure 11: Loop-Through Switch Gate Voltage
2. In some cases it happens that two or more receivers share the same coaxial cable making their
output hard paralleled, so the same voltage is present at the outputs of the receivers. If a
receiver is not disconnected atthe mains, it will flow a current from the LNBA to the MI by means
of the parasitic D-S TR1 diode. Moreover, the TR2 (or TR4) BVb-e could be exceeded, so a
reverse current could flow from the LNBA to Vcc2 (or Vcc1) or from the LNBB to Vcc2 (or Vcc1),
with possible destruction of the relative transistor. To overcome this drawback it is enough to add
one or two diodes, depending on how many outputs are used, in series at the LNBA or LNBB
pins (see figure 12). In this case we have to consider the voltage drop across the diode that is
load and temperature dependent. These effects can be minimized by using Schottky diodes and
activating the LLC function.
In alternative we can add one, two or three diodes - it depends if one, two or three inputs are used - in
series at input oins M1, Vcc1 and Vcc2 (see figure 13). In this case diodes do not causea change at Vout,
but only a worsening of voltage drop, that can be minimized by using Shottky diodes. Diodes used in
figures 12 and 13 must withstand a continuous current of almost 1A and a breakdown voltage of 30V
(suggested type is BYV10-30).
AN1230 - APPLICATION NOTE
8/17
LNBP
MI
Vcc2
Vcc1
LNBA
LNBB
LNBA’
LNBB’
LNBP
MI
Vcc2
Vcc1
LNBA
LNBB
MI’
Vcc2’
Vcc1’
Figure 12: Reverse Current Protection Using Diodes on the Outputs
Figure 13: Reverse Current Protection Using Diodes on the Inputs
3. In alternative we can add one, two or three diodes, depending on how many inputs are used, in
series at the MI, Vcc1 and Vcc2 input pins (see figure 13). In this case diodes do not cause a
change at Vout, but only worsen the voltage drop, which can be minimized by using Schottky
diodes. Diodes used in figures 12 and 13 must withstand a continuos current of almost 1A and a
breakdown voltage of 30V (suggested type is BYV10-30).
5. APPLICATION HINTS.
1. LNBP has an LLC pin to compensate the voltage drop across the cable. This pin adds a discrete
1V value at the selected output voltage when itis active. It is also possible to obtain a continuous
variation of the LNBA or LNBB voltage by using EXTM input.
2. If only a single 22V source is suitable, at the cost of higher power losses in the device and higher
heatsink surface, it is possible to power the Vcc1 and Vcc2 pins by the same 22V source without
affecting any other circuit performance. In order to reduce power dissipation in the device, it can
be useful to insert an adequate resistor in series to the Vcc1 pin (see figure14). This resistor
must be dimensioned considering that the minimum voltage on the Vcc1 pinmust be ≥ 16 V,with
a supply current ISUPPLY = 500 mA.
This means: R ≤ (22-16) / 500 *10 -3
≅
12 Ohm.
Power dissipated in this resistor is:
Pd = R*Iout2= 12* (500*10 -3)2=3W.
It is recommended to bypass the Vcc1 and Vcc2 pins by 2.2µF electrolytic capacitors.
3W is the power dissipated saved by the device.
3. If Vcc2is not inserted (i.e. the receiver is not connected to the mains) the TR1 can not bypass MI
to the LNBA, because the gate is not driven (see figure 10). It is possible to overcome this
drawback by using the scheme reported in figure 15.
AN1230 - APPLICATION NOTE
9/17
VCC1
VCC2
MI
LNBP
LNBA
LNBBVIN
VCC1
VCC2
MI
LNBP
MC34063
+
+
+Vin
R1
0R15
0.5W
R2
100R
1W
R3
47K
R4
2.7K
R5
1.2K
C1
100uF C2
1nF
7
6
4
2
8
1
5
3
150uH BYV10-40
C3
330uF
1N4007
C5
10nF
BYV10-40
Vcc1
Vcc2 MI
En
VSel
VSel
En
MI
LNBA
HC03 HC03 HC03
+5V
R6
10K R7
10K
12V
LNBP
LNBA
C4
.22uF
C6
4.7uF
+Cext
13/18
V
A
Figure 14: How to Get Vcc1 Using a Drop Resistor
Figure 15: A Loop-Through Switch That Works Without Vcc2
6. SINGLE SUPPLY APPLICATION.
In some applications (TV receivers, PC cards, etc.) a 12V power supply is available. It is possible to use
this voltage to supply the LNBP. Figure 16 reports the schematic of the application proposed. It uses an
MC34063 to step-up the 12V input at a value of 16V or 23V, depending on the Vsel status. If Vsel is H
(i.e. the LNBP gives 18V at out LNBA), a 23V voltage is available at point A. If Vsel is L (i.e. the LNBP
gives 13V at out LNBA), a 16V voltage is available at point A. This keeps the power dissipated by LNBP
low and gives good efficiency because the LNBP is supplied with a minimum drop. Diode D2 protectsthe
LNBP by reverse current. If the LNBP is disabled (i.e. En is L), the 23V voltage is selected at point A,
regardless of the Vsel status. The changing voltage at point A is actuated by HC03, which is an
open-drain quad 2-input nand gate.
Figure 16: Single Supply Application Using MC34063A Plus LNBPxx
AN1230 - APPLICATION NOTE
10/17
LNBP OUT R1
15ΩBUS
LNBA
or
LNBB
L1
270µHDiSEqC
IN
ENT
45
42
39
36
33
30
27
48
7. DiSEqC* SPECIFICATION.
Figure 17: ImpedanceMatching for DiSEqC
The DiSEqC standard was born to implement the most complex system required, for example, by
multiple-satellite installations, where multiple LNB placed in the parabola must communicate with the
receiver in a two-way mode. This standard is compatible with 13/18V and 22kHz tone and is easily
implemented by a microcontroller. It requires hardware specifications that are faithfullysatisfied by LNBP.
In particular, the bus impedance can be matched using the scheme reported in figure 17.
8. THERMAL MANAGEMENT.
Figure 18: Thermal Resistance versus On-Board Copper Heatsink Area
LNBP has a built-in dynamic protection systemthat considerably lowers the power dissipation in short or
overload conditions. Therefore, the operativecondition is the worst condition for powerdissipation. LNBP
is available in 3 packages: PowerSO-10, PowerSO-20 and MULTIWATT15. The last package can be
assembled on a heatsink with:
Rth heatsink ≤ (Tj-Tamb)/Pd -R Thjc -R Thcs, where:
Tj=junction temperature (can be fixed at 150°C max);
Pd=dissipated power=Σ(Vin-Vout)*Iout;
R Thjc = junction-case thermal resistance ~2°C/W;
AN1230 - APPLICATION NOTE
11/17
R Thcs =case-heatsink thermal resistance ~1÷1.5°C/W.
For SMD packages we must obtain the right R Thtot. This can be achieved soldering the metallic case of
the package on an adequate copper surface that acts like a heatsink. In the figure 18 the typical R Thtot
= R Th heatsink + R Thjc + R Thcs vs. copper surface is shown, for a board with 1 or 2 layers. In the 2
layers case, a convenient number of ways (~9/cmsq) must be provided. For best resultsthese ways must
be inserted below the device and near it. Doubling the surface we obtain a 3°C/W of R reduction.
Figure 19: Electrical Schematic Board of PowerSO-20
Figure 20: Electrical Schematic Demoboard of MULTIWATT15
+
+
+
+
IN MI
D1
BYV10-40
VCC1
VCC2
EXTM
+5V R3
470Ohm
1
2
3
45
1101120
6
7
16
13
15
5
C8 10µF
C3
2.2µFC5
220nF
D3
BYV10-40
C2
2.2µFC4
220nF
D2
BYV10-40
DL3
RED OLF
17 C7
4.7µF
C6
10nF R2
2.2K
DL2
GREEN
14
19 TPB OUT
LNBB
C1
10nF R1
2.2K
DL1
GREEN
OUT
LNBA
TPA
4
18
2
3LNBP20PD
VCC1 MI LNBA
VCC2
EXTM LNBB
ENT
LLC
OSEL
EN
VSEL CEXT
GNDOLF
+
+
+
IN MI
D1
BYV10-40
VCC1
VCC2
EXTM
R3
470Ohm
1
2
3
412
4
9
7
5
11
5
C6 10µF
C3
2.2µF
D1
BYV10-40
C2
2.2µFC4
220nF
D2
BYV10-40
DL3
RED Overload
13
C8
10nF R2
2.2K
DL2
GREEN
8
15
Tip
Probe
Out OUT
LNBB
C5
10nF R1
2.2K
DL1
GREEN
OUT
LNBA-F
Tip
Probe
Out
3
18
1
2LNBP20CR
VCC1 MI LNBA
VCC2
EXTM LNBB
ENT
LLC
OSEL
ENT
VSEL
CEXT
OLF
BNC
+5V
+
GND
C7
4.7µF10
GND-S GND-F
OUT
LNBB-S
OUT
LNBA-S
AN1230 - APPLICATION NOTE
12/17
Figure 21: PowerSO-20 Demoboard
Figure 22: MULTIWATT15 Demoboard
AN1230 - APPLICATION NOTE
13/17
JA
JB
ANT CONNECTORS
17V 24V
MCU+V
VCC1 1
VCC2 2
LNBA 3
LNBB 15
GND 8
LLC
12
EXTM
11
OSEL
7EN
5ENT
9VSEL
4
OLF
13 MI 14
CEXT 10
LNBP20CR
C2
10uF
R1
47K
AUX DATA
C3
2x
0.1µF
C1
4.7µFC4 C6C5
2x
47nF
TUNER
I/Os
MCU
I/Os
Vcc
+
REGULATOR(DOUBLE DISH)
LNBSUPPLY AND CONTROL VOLTAGE
+
The two demoboards of the LNBP of the PowerSO-20 and MULTIWATT packages are shown below. The
different layer drawings are shown in figure 19 and 20. The first one is based on the PowerSO-20 pack-
age and the second on the MULTIWATT packages.
10. SCHEMATIC CIRCUIT DESCRIPTION.
10.1 POWER SO-20Package.
Two comb connectors (8 pins each) are used for the input and output voltage and for all control signals
(Vsel, EN, Osel, LLC, ENT). It is possible to force at high levels all the control signals through a 5 pin
dip-switch. If the control signals come from outside the board, the dip-switches must be in the OFF
position. An oscilloscope probe can be connected to the TPA and TPB test points to monitor the 22KHz
signal.
10.2 MULTIWATTPackage.
The MULTIWATT electric schematics is shown in figure 20. In the board some plugs are provided for the
input of the following signals: Vcc1,Vcc2, MI, +5V and GND (force and sense). Also, LNBA and LNBB
(force and sense) are connected by plugs. The load is connected between the output connector LNBA-F
(or LNBB-F) and GND-F. Between the LNBA-S (or LNBB-S) and GND-S two voltmeters can be
connected to monitor the output voltage.Besides, two plugs connected with the two outputs permit the
insertion of the oscilloscope probes to monitor the 22kHz tone. The EXTM input can be connected to the
relative BNC connector. It is, moreover, possible to force at high level the following inputs:
EN, Osel,
ENT, Vsel
, and
LLC
by five switches. It is moreover possible to force such inputs even through the five
poles connector. In this case all the switches must be in off position.
11. CONCLUSION
This paper gives practical information to develop numerous applications using this solution for supplying
satellite LNB. The use of the existing LNBP Demoboard allows the development of the final product. On
the next pages there are numerous examples of typical application schematics based on LNBP.
Typical Application Schematics are shown below.
Figure 23: Two Antenna Ports Receiver
AN1230 - APPLICATION NOTE
14/17
REGULATOR (DOUBLE LNB)
LNB SUPPLY AND CONTROL VOLTAGE
VCC1 1
VCC2 2
LNBA 3
LNBB 15
GND 8
LLC
12
EXTM
11
OSEL
7EN
5ENT
9VSEL
4
OLF
13 MI 14
CEXT10
LNBP20CR
C2
10uF
MCU+V
R1
47K AUX DATA
STR
1D
2CLK
3OE
15
Q1 4
Q2 5
Q3 6
Q4 7
Q5 14
Q6 13
Q7 12
Q8 11
QS 9
QS 10
4094
TUNER
JA
JB
ANT
CONNECTORS
C4 C6C5
2x 47nF
C3
2x 0.1µF
C14.7µF
MCU+V
SERIAL
BUS
MCU
I/Os Vcc
+
17V 24V
REGULATOR(SINGLE LNB)
LNB SUPPLY ANDCONTROL VOLTAGE
MCU+V
VCC1 1
VCC2 2
LNBA 3
LNBB 15
GND 8
LLC
12
EXTM
11
OSEL
7EN
5ENT
9VSEL
4
OLF
13 MI 14
CEXT 10
LNBP20CR
C2
10uF
AUX DATA R1
47K
ANT
MASTER
C4 C5
47nF
C3
2x 0.1µF
C1
4.7µF
I/OsVcc MCU I/Os
+
TUNER
17V 24V
+
Figure 24: Single Antenna Receiver with Master Receiver Port
Figure 25: Using Serial Bus to Save MPU I/Os
AN1230 - APPLICATION NOTE
15/17
REGULATOR (DOUBLE LNB)
LNB SUPPLY AND CONTROL VOLTAGE
JA
JB
ANT
CONNECTORS
VCC1 1
VCC2 2
LNBA 3
LNBB 10
GND 6
CEXT 8
OSEL
9EN
5ENT
7VSEL
4
LNBP10SP
C1
4.7µFC6C5
2x 47nF
C4
0.1µF
TUNER
I/Os
MCU
MCU+V
I/OsVcc
+
24V
REGULATOR(DOUBLE LNB)
LNB SUPPLYAND CONTROL VOLTAGE
Low Cost SolutionUsing
PowerSO-10
JA
JB
ANT
CONNECTORS
VCC1 1
VCC2 2
LNBA 3
LNBB 10
GND 6
CEXT 8
OSEL
9EN
5ENT
7VSEL
4
LNBP10SP
C3
2x 0.1µF
C1
4.7µFC4 C6C5
2x 47nF
TUNER
I/Os
MCU
MCU+V
I/OsVcc
+
17V 24V
Typical Schematics cont’d
Figure 26: Two Antenna Ports Receiver
Figure 27: Connecting Together Vcc1 and Vcc2
AN1230 - APPLICATION NOTE
16/17
REGULATOR (SINGLE LNB)
LNB SUPPLY AND CONTROL VOLTAGE
Low CostSolution
UsingPowerSO-10
VCC1 1
VCC2 2
LNBA3
MI10
GND 6
CEXT 8
EXTM
9
EN
5ENT
7VSEL
4
LNBP13SP
C2
10µF
AUXDATA
TUNER
ANT
MASTER
C4C5
47nF
C3
2x 0.1µF
C1
4.7µF
MCU+V
I/OsVcc MCU I/Os
+
17V 24V
+
REGULATOR (SINGLE LNB)
LNB SUPPLY AND CONTROL VOLTAGE
Low Cost Solution
UsingPowerSO-10
MCU+V C2
10µFVCC1 1
VCC2 2
LNBA 3
GND 6
CEXT 8
EXTM
9
EN
5ENT
7VSEL
4
OLF
10
LNBP15SP
AUX DATA R1
47K TUNER
ANT
C4 C5
47nF
C3
2x 0.1µF
C14.7µF
Vcc I/Os MCU I/Os
+
17V 24V
+
Figure 28: Single Antenna Receiver with Master Port
Figure 29: Single Antenna Receiver Overload Diagnostic
AN1230 - APPLICATION NOTE
17/17
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