Ultralow Offset Voltage
Operational Amplifier
Data Sheet
OP07
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002-2011 Analog Devices, Inc. All rights reserved.
FEATURES
Low VOS: 75 μV maximum
Low VOS drift: 1.3 μV/°C maximum
Ultrastable vs. time: 1.5 μV per month maximum
Low noise: 0.6 μV p-p maximum
Wide input voltage range: ±14 V typical
Wide supply voltage range: ±3 V to ±18 V
125°C temperature-tested dice
APPLICATIONS
Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls
Thermocouples
Resistor thermal detectors (RTDs)
Strain bridges
Shunt current measurements
Precision filters
GENERAL DESCRIPTION
The OP07 has very low input offset voltage (75 μV maximum for
OP07E) that is obtained by trimming at the wafer stage. These
low offset voltages generally eliminate any need for external
nulling. The OP07 also features low input bias current (±4 nA for
the OP07E) and high open-loop gain (200 V/mV for the OP07E).
The low offset and high open-loop gain make the OP07
particularly useful for high gain instrumentation applications.
PIN CONFIGURATION
1
VOS TRIM 8VOS TRIM
2
–IN 7V+
3
+IN 6
OUT
4
V–
5
NC
OP07
NC = NO CONNECT
00316-001
Figure 1.
The wide input voltage range of ±13 V minimum combined
with a high CMRR of 106 dB (OP07E) and high input
impedance provide high accuracy in the noninverting circuit
configuration. Excellent linearity and gain accuracy can be
maintained even at high closed-loop gains. Stability of offsets
and gain with time or variations in temperature is excellent. The
accuracy and stability of the OP07, even at high gain, combined
with the freedom from external nulling have made the OP07 an
industry standard for instrumentation applications.
The OP07 is available in two standard performance grades. The
OP07E is specified for operation over the 0°C to 70°C range,
and the OP07C is specified over the −40°C to +85°C
temperature range.
The OP07 is available in epoxy 8-lead PDIP and 8-lead narrow
SOIC packages. For CERDIP and TO-99 packages and standard
microcircuit drawing (SMD) versions, see the OP77.
1
R2A AND R2B ARE ELECT RONI CALLY ADJUS TED ON CHIP AT F ACTORY FO R M INIM UM INPUT OFF S E T VO LT AGE.
6
V+ 7
8
3
C3
1
4
2
OUT
Q5
R2A
1
R5
R8
R7
V–
R6
R3
R4
Q21
Q22
Q23
Q24
R1A
R2B
1
R1B
Q7 Q3 Q6
Q1
Q4
Q2
Q27
Q26
Q25
C1
Q9 Q10
Q11 Q12
C2
(OPTIONAL
NULL)
Q13
Q14
Q17Q16
Q15
Q18
Q20
Q19
R10
R9
Q8
NONINVERTING
INPUT
INVERTING
INPUT
00316-002
Figure 2. Simplified Schematic
OP07 Data Sheet
Rev. G | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configuration ............................................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
OP07E Electrical Characteristics ............................................... 3
OP07C Electrical Characteristics ............................................... 4
Absolute Maximum Ratings ............................................................6
Thermal Resistance .......................................................................6
ESD Caution...................................................................................6
Typical Performance Characteristics ..............................................7
Typical Applications ....................................................................... 11
Applications Information .......................................................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 14
REVISION HISTORY
10/11—Re v. F. to Rev G
Changes to Features Section............................................................ 1
8/10—Re v. E. to Rev F
Changes to Ordering Guide .......................................................... 14
7/09—Re v. D. to Rev E
Changes to Figure 29 Caption ....................................................... 11
Changes to Ordering Guide .......................................................... 14
7/06—Rev. C. to Rev D
Changes to Features .......................................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications Section .................................................. 3
Changes to Table 4 ............................................................................ 6
Changes to Figure 6 and Figure 8 ................................................... 7
Changes to Figure 13 and Figure 14 ............................................... 8
Changes to Figure 20 ........................................................................ 9
Changes to Figure 21 to Figure 25 ................................................ 10
Changes to Figure 26 and Figure 30 ............................................. 11
Replaced Figure 28 ......................................................................... 11
Changes to Applications Information Section ............................ 12
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
8/03—Re v. B to Re v. C
Changes to OP07E Electrical Specifications .................................. 2
Changes to OP07C Electrical Specifications ................................. 3
Edits to Ordering Guide ................................................................... 5
Edits to Figure 6 ................................................................................. 9
Updated Outline Dimensions ....................................................... 11
3/03—Re v. A to Re v. B
Updated Package Titles ...................................................... Universal
Updated Outline Dimensions ....................................................... 11
2/02—Re v. 0 to Re v. A
Edits to Features ................................................................................. 1
Edits to Ordering Guide ................................................................... 1
Edits to Pin Connection Drawings ................................................. 1
Edits to Absolute Maximum Ratings .............................................. 2
Deleted Electrical Characteristics .............................................. 2–3
Deleted OP07D Column from Electrical Characteristics ....... 4–5
Edits to TPCs ................................................................................ 7–9
Edits to High-Speed, Low VOS Composite Amplifier ................... 9
Data Sheet OP07
Rev. G | Page 3 of 16
SPECIFICATIONS
OP07E ELECTRICAL CHARACTERISTICS
VS = ±15 V, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
TA = 25°C
Input Offset Voltage1
V
OS
30
75
μV
Long-Term VOS Stability2 VOS/Time 0.3 1.5 μV/Month
Input Offset Current IOS 0.5 3.8 nA
Input Bias Current IB ±1.2 ±4.0 nA
Input Noise Voltage en p-p 0.1 Hz to 10 Hz3 0.35 0.6 μV p-p
Input Noise Voltage Density en fO = 10 Hz 10.3 18.0 nV/√Hz
fO = 100 Hz3 10.0 13.0 nV/√Hz
fO = 1 kHz 9.6 11.0 nV/√Hz
Input Noise Current In p-p 14 30 pA p-p
Input Noise Current Density In fO = 10 Hz 0.32 0.80 pA/√Hz
fO = 100 Hz3 0.14 0.23 pA/√Hz
f
O
= 1 kHz
0.12
0.17
pA/√Hz
Input Resistance, Differential Mode4 RIN 15 50 MΩ
Input Resistance, Common Mode RINCM 160 GΩ
Input Voltage Range IVR ±13 ±14 V
Common-Mode Rejection Ratio CMRR VCM = ±13 V 106 123 dB
Power Supply Rejection Ratio PSRR VS = ±3 V to ±18 V 5 20 μV/V
Large Signal Voltage Gain
A
VO
R
L
≥ 2 kΩ, V
O
= ±10 V
200
500
V/mV
RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V4 150 400 V/mV
0°C ≤ TA ≤ 70°C
Input Offset Voltage1 VOS 45 130 μV
Voltage Drift Without External Trim4 TCVOS 0.3 1.3 μV/°C
Voltage Drift with External Trim3 TCVOSN RP = 20 kΩ 0.3 1.3 μV/°C
Input Offset Current IOS 0.9 5.3 nA
Input Offset Current Drift TCIOS 8 35 pA/°C
Input Bias Current IB ±1.5 ±5.5 nA
Input Bias Current Drift TCIB 13 35 pA/°C
Input Voltage Range
IVR
±13
±13.5
V
Common-Mode Rejection Ratio CMRR VCM = ±13 V 103 123 dB
Power Supply Rejection Ratio PSRR VS = ±3 V to ±18 V 7 32 μV/V
Large Signal Voltage Gain AVO RL ≥ 2 kΩ, VO = ±10 V 180 450 V/mV
OUTPUT CHARACTERISTICS
TA = 25°C
Output Voltage Swing VO RL ≥ 10 kΩ ±12.5 ±13.0 V
RL ≥ 2 kΩ ±12.0 ±12.8 V
RL ≥ 1 kΩ ±10.5 ±12.0 V
0°C ≤ TA ≤ 70°C
Output Voltage Swing VO RL ≥ 2 kΩ ±12 ±12.6 V
OP07 Data Sheet
Rev. G | Page 4 of 16
Parameter Symbol Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
TA = 25°C
Slew Rate SR RL ≥ 2 kΩ3 0.1 0.3 V/μs
Closed-Loop Bandwidth BW AVOL = 15 0.4 0.6 MHz
Open-Loop Output Resistance RO VO = 0, IO = 0 60 Ω
Power Consumption Pd VS = ±15 V, No load 75 120 mW
VS = ±3 V, No load 4 6 mW
Offset Adjustment Range RP = 20 kΩ ±4 mV
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2 Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is
sample tested.
3 Sample tested.
4 Guaranteed by design.
5 Guaranteed but not tested.
OP07C ELECTRICAL CHARACTERISTICS
VS = ±15 V, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
TA = 25°C
Input Offset Voltage1 VOS 60 150 μV
Long-Term V
OS
Stability
2
V
OS
/Time
0.4
2.0
μV/Month
Input Offset Current IOS 0.8 6.0 nA
Input Bias Current IB ±1.8 ±7.0 nA
Input Noise Voltage en p-p 0.1 Hz to 10 Hz3 0.38 0.65 μV p-p
Input Noise Voltage Density en fO = 10 Hz 10.5 20.0 nV/√Hz
fO = 100 Hz3 10.2 13.5 nV/√Hz
fO = 1 kHz 9.8 11.5 nV/√Hz
Input Noise Current In p-p 15 35 pA p-p
Input Noise Current Density In fO = 10 Hz 0.35 0.90 pA/√Hz
fO = 100 Hz3 0.15 0.27 pA/√Hz
fO = 1 kHz 0.13 0.18 pA/√Hz
Input Resistance, Differential Mode
4
R
IN
8
33
MΩ
Input Resistance, Common Mode RINCM 120 GΩ
Input Voltage Range IVR ±13 ±14 V
Common-Mode Rejection Ratio CMRR VCM = ±13 V 100 120 dB
Power Supply Rejection Ratio PSRR VS = ±3 V to ±18 V 7 32 μV/V
Large Signal Voltage Gain AVO RL ≥ 2 kΩ, VO = ±10 V 120 400 V/mV
RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V4 100 400 V/mV
−40°C ≤ TA ≤ +85°C
Input Offset Voltage1 VOS 85 250 μV
Voltage Drift Without External Trim4 TCVOS 0.5 1.8 μV/°C
Voltage Drift with External Trim3
TCV
OSN
R
P
= 20 kΩ
0.4
1.6
μV/°C
Input Offset Current IOS 1.6 8.0 nA
Input Offset Current Drift TCIOS 12 50 pA/°C
Input Bias Current IB ±2.2 ±9.0 nA
Input Bias Current Drift TCIB 18 50 pA/°C
Input Voltage Range IVR ±13 ±13.5 V
Common-Mode Rejection Ratio
CMRR
V
CM
= ±13 V
97
120
dB
Power Supply Rejection Ratio PSRR VS = ±3 V to ±18 V 10 51 μV/V
Large Signal Voltage Gain AVO RL ≥ 2 kΩ, VO = ±10 V 100 400 V/mV
Data Sheet OP07
Rev. G | Page 5 of 16
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT CHARACTERISTICS
TA = 25°C
Output Voltage Swing VO RL ≥ 10 kΩ ±12.0 ±13.0 V
RL ≥ 2 kΩ ±11.5 ±12.8 V
RL ≥ 1 kΩ ±12.0 V
−40°C ≤ TA ≤ +85°C
Output Voltage Swing VO RL ≥ 2 kΩ ±12 ±12.6 V
DYNAMIC PERFORMANCE
TA = 25°C
Slew Rate SR RL ≥ 2 kΩ3 0.1 0.3 V/μs
Closed-Loop Bandwidth BW AVOL = 15 0.4 0.6 MHz
Open-Loop Output Resistance RO VO = 0, IO = 0 60 Ω
Power Consumption Pd VS = ±15 V, No load 80 150 mW
VS = ±3 V, No load 4 8 mW
Offset Adjustment Range RP = 20 kΩ ±4 mV
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2 Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is
sample tested.
3 Sample tested.
4 Guaranteed by design.
5 Guaranteed but not tested.
OP07 Data Sheet
Rev. G | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Ratings
Supply Voltage (VS) ±22 V
Input Voltage1
±
22 V
Differential Input Voltage
±
30 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range
S and P Packages −65
°
C to +125
°
C
Operating Temperature Range
OP07E 0°C to 70°C
OP07C −40
°
C to +85
°
C
Junction Temperature 150
°
C
Lead Temperature, Soldering (60 sec) 300°C
1 For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θJC Unit
8-Lead PDIP (P-Suffix) 103 43 °C/W
8-Lead SOIC_N (S-Suffix) 158 43 °C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Data Sheet OP07
Rev. G | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
1000
0
200
400
600
800
900
100
300
500
700
–50–75 100500–25 1257525
OPEN-LOO P G AIN (V/mV)
TEMPERATURE (°C)
VS = ±15V
00316-003
Figure 3. Open-Loop Gain vs. Temperature
30
25
20
15
10
5
0
–20 020 40 60 80 100
ABSO LUTE CHANGE IN INP UT
OFFSET VOLTAGE (µV)
TIME (Seconds)
V
S
= ±15V
T
A
= 25° C, T
A
= 70° C
THERMAL
SHOCK
RESPONSE
BAND
DEVICE IMMERSED
IN 70°C OIL BATH
00316-004
Figure 4. Offset Voltage Change due to Thermal Shock
OP07C
OP07E
25
20
15
10
5
0012345
ABSO LUTE CHANGE IN INP UT
OFFSET VOLTAGE (µV)
TIME AFT ER SUPPLY TURN-ON (Minutes)
VS = ±15V
TA = 25° C
00316-005
Figure 5. Warm-Up Drift
1.0
0.8
0.6
0.4
0.2
0
100 1k 10k 100k
MATCHED OR UNMATCHED SOURCE RESISTANCE (Ω)
MAXIMUM E RROR REFERRED TO INPUT ( mV )
OP07E
OP07C
00316-006
VS = ±15V
TA = 25° C
Figure 6. Maximum Error vs. Source Resistance
1.2
1.0
0.8
0.6
0.4
0.2
0
100 1k 10k 100k
MATCHED OR UNMATCHED SOURCE RESISTANCE (Ω)
MAXIMUM E RROR REFERRED TO INPUT ( mV )
VS = ±15V
0°C ≤ TA ≤ 70°C
OP07C
OP07E
00316-007
Figure 7. Maximum Error vs. Source Resistance
30
–30
–20
–10
0
10
20
–30 –20 –10 3020100
DIFFERENTIAL INPUT VALUE (V)
NONINVERTI NG INP UT BI AS CURRE NT (n A)
AT | V
DIFF
| ≤ 1.0V, | I
B
| ≤ 7nA (OP07C)
V
S
= ±15V
T
A
= 25° C
00316-008
Figure 8. Input Bias Current vs. Differential Input Voltage
OP07 Data Sheet
Rev. G | Page 8 of 16
4
3
2
1
0
TEMPERATURE (°C)
INP UT BIAS CURRE NT (nA)
–50–75 100500–25 1257525
VS = ±15V
OP07C
OP07E
00316-009
Figure 9. Input Bias Current vs. Temperature
2.5
2.0
1.5
1.0
0.5
0
TEMPERATURE (°C)
INP UT OFF S E T CURRENT ( nA)
–50–100 –75 500–25 1007525
VS = ±15V
OP07C
OP07E
00316-010
Figure 10. Input Offset Current vs. Temperature
TIME (1s/DIV)
VOLTAGE (200nV/DIV)
REF E RRE D TO INPUT
5mV/ CM AT OUTPUT
00316-011
Figure 11. Low Frequency Noise
1000
100
10
1
FRE QUENCY ( Hz )
INPUT NOISE VOLTAGE (nV/ Hz)
1011000100
R
S1
= R
S2
= 200kΩ
THE RM AL NOISE S OURCE
RESIST ORS INCLUDE D
EXCLUDED
R
S
= 0
V
S
= ±15V
T
A
= 25° C
00316-012
Figure 12. Total Input Noise Voltage vs. Frequency
10
1
0.1
BANDWIDTH ( Hz )
RMS NOISE (µV)
1k100 100k10k
V
S
= ±15V
T
A
= 25° C
00316-013
Figure 13. Input Wideband Noise vs. Bandwidth,
0.1 Hz to Frequency Indicated
130
120
110
100
90
80
70
60
FRE QUENCY ( Hz )
CMRR (dB)
101100k1k 10k100
OP07C
00316-014
Figure 14. CMRR vs. Frequency
Data Sheet OP07
Rev. G | Page 9 of 16
120
110
100
90
80
70
50
60
FRE QUENCY ( Hz )
PSRR ( dB)
100.1 110k1k100
OP07C
T
A
= 25° C
00316-015
Figure 15. PSRR vs. Frequency
1000
800
600
400
200
0
POWER SUPPLY VOL T AGE (V)
OPEN-LOO P G AIN (V/mV)
±100±5 ±20±15
T
A
= 25° C
00316-016
Figure 16. Open-Loop Gain vs. Power Supply Voltage
120
100
80
60
40
20
0
–20
–40
FRE QUENCY ( Hz )
OPEN-LOOP GAIN (dB)
0.1 110 100 1k 10k 100k 1M 10M
VS = ±15V
TA = 25° C
00316-017
Figure 17. Open-Loop Frequency Response
100
80
60
40
20
0
–20
FRE QUENCY ( Hz )
CLOSED-LOOP GAIN (dB)
10 100 1k 10k 100k 1M 10M
VS = ±15V
TA = 25° C
00316-018
Figure 18. Closed-Loop Frequency Response for Various Gain Configurations
28
24
20
16
12
8
4
0
FRE QUENCY ( Hz )
PEAK-TO-PEAK AMPLIT UDE (V)
1k 10k 100k 1M
VS = ±15V
TA = 25° C
00316-019
Figure 19. Maximum Output Swing vs. Frequency
20
15
10
5
0
LOAD RESISTANCE TO GROUND (Ω)
MAXIMUM OUTPUT (V)
100 1k 10k
V
S
= ±15V
V
IN
= ±10mV
T
A
= 25° C
POSIT I VE SW I NG
NEGATIVE SWI NG
00316-020
Figure 20. Maximum Output Voltage vs. Load Resistance
OP07 Data Sheet
Rev. G | Page 10 of 16
1000
100
10
1
TOTAL SUPPLY VOLTAGE, V+ TO V– (V)
PO WER CO NS UM P TI ON (mW )
010 20 30 40 50 60
T
A
= 25° C
00316-021
Figure 21. Power Consumption vs. Power Supply
35
30
25
20
15
TIME FROM OUTPUT BEING SHORTED (Minutes)
OUTPUT S HORT - CIRCUIT CURRENT (mA)
0 4321
V
S
= ±15V
T
A
= 25° C
V
IN
(PIN 3) = + 10mV , V
O
= –15V
V
IN
(PIN 3) = –10mV , V
O
= +15V
00316-022
Figure 22. Output Short-Circuit Current vs. Time
85.00
42.50
63.75
21.25
0
TEMPERATURE (°C)
ABSOLUTE VALUE OF OFFSET VOLTAGE (µV)
–75 1251007550250–25–50
V
S
= ±15V
R
S
= 100Ω
OP07C
OP07E
00316-023
Figure 23. Untrimmed Offset Voltage vs. Temperature
30.0
15.0
22.5
7.5
0
TEMPERATURE (°C)
ABSOLUTE VALUE OF OFFSET VOLTAGE (µV)
–100 –75 1007550250–25–50
OP07C
OP07E
OP07E
OP07C
V
OS
TRIMME D TO < 5µV AT 25°C
NULLING POT = 20kΩ
00316-024
Figure 24. Trimmed Offset Voltage vs. Temperature
16
–16
–12
–8
–4
0
4
8
12
TIME (Mo n th s)
TOTAL DRIFT WITH TIME (µV)
0121110987654321
0.3µV/MONTH
TREND LI NE
0.3µV/MONTH
TREND LI NE
0.3µV/MONTH
TREND LI NE
0.2µV/MONTH
TREND LI NE 0.2µV/MONTH
TREND LI NE
0.2µV/MONTH
TREND LI NE
00316-025
Figure 25. Offset Voltage Drift vs. Time
Data Sheet OP07
Rev. G | Page 11 of 16
TYPICAL APPLICATIONS
AD7115 OR
AD8510
+
–
6E
O
EIN V+
V–
7
4
2
3
6
OP07C
A1
+
–
V–
V+
7
4
2
3
R3
3kΩ
R5
10kΩ
R2
100kΩ
RF
SUM MODE
BIAS
R1
E
O
= –E
IN
–I
B
RF
RF
R1
00316-026
Figure 26. Typical Offset Voltage Test Circuit
6
OP07C
+
–
–15V
+15V
7
4
2
3
E
O
R5
2.5kΩ
E
3
R3
10kΩ
E
2
R2
10kΩ
E
1
R1
10kΩ
R4
10kΩ
00316-027
Figure 27. Typical Low Frequency Noise Circuit
6
OP07
+
–
V–
187
4
2
INPUT
3
–
+
OUT
V+
20kΩ
00316-028
Figure 28. Optional Offset Nulling Circuit
OP07
+
–
6E
O
V+
V–
7
4
2
3
R5
10kΩ
R4
10kΩ
R3
10kΩ
E
IN
±10V
=
R1
R3 R2
R4
R2
10kΩ
6
OP07
+
–
V–
V+
7
4
2
3
FD333
D1
FD333
D2
R1
10kΩ
0V TO +10V
00316-029
Figure 29. Absolute Value Circuit
OP07C
A2
+
–
6E
O
E
IN
V+
V–
7
4
2
3
6
OP07C
A1
+
–
V–
V+
7
4
2
3
R3
3kΩ
R1
10kΩ
R2
100kΩ
RF
SUM MODE
BIAS
R1
E
O
= –E
IN
+ I
B
RF
RF
R1
NOTES
1. P INOUT SHOWN FO R P P ACKAGE
00316-030
Figure 30. High Speed, Low VOS Composite Amplifier
6
OP07
+
–
–15V
+15V
7
4
2
3
E
O
R5
2.5kΩ
E
3
R3
10kΩ
E
2
R2
10kΩ
E
1
R1
10kΩ
R4
10kΩ
NOTES
1. P INOUT SHOWN FOR P P ACKAGE
00316-031
Figure 31. Adjustment-Free Precision Summing Amplifier
OP07 Data Sheet
Rev. G | Page 12 of 16
NOTES
1. P INOUT SHOWN FOR P P ACKAGE
6
OP07
+
–
V–
V+
7
4
2
3
E
O
R4
REFERENCE
JUNCTION
SENDING
JUNCTION
R3
R1
R2 =
R1
R3 R2
R4
00316-032
Figure 32. High Stability Thermocouple Amplifier
OP07
A2
+
–
6E
O
V+
V–
7
4
2
3
R5
10kΩ
R4
10kΩ
R3
10kΩ
E
IN
±10V
R2
10kΩ
6
OP07
A1
+
–
V–
V+
7
4
2
3
FD333
D1
FD333
D2
R1
10kΩ
0V TO +10V
NOTES
1. PINO UT SHO WN F OR P PACKAGE
V
A
00316-033
Figure 33. Precision Absolute-Value Circuit
APPLICATIONS INFORMATION
The OP07 provides stable operation with load capacitance of up
to 500 pF and ±10 V swings; larger capacitances should be
decoupled with a 50 Ω decoupling resistor.
Stray thermoelectric voltages generated by dissimilar metals at
the contacts to the input terminals can degrade drift
performance. Therefore, best operation is obtained when both
input contacts are maintained at the same temperature,
preferably close to the package temperature.
Data Sheet OP07
Rev. G | Page 13 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DES
IGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 34. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body S-Suffix
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDE C S TANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE RO UNDE D- OFF I NCH E QUIVALENTS FOR
REF E RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNE R LEADS MAY BE CO NFI GURED AS WHO LE OR HALF L E ADS .
070606-A
0.022 ( 0.56)
0.018 ( 0.46)
0.014 ( 0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 ( 5.33)
MAX
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2.92)
0.070 ( 1.78)
0.060 ( 1.52)
0.045 ( 1.14)
8
14
5
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.100 ( 2.54)
BSC
0.400 ( 10.16)
0.365 ( 9.27)
0.355 ( 9.02)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 ( 0.36)
0.010 ( 0.25)
0.008 ( 0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.195 ( 4.95)
0.130 ( 3.30)
0.115 (2.92)
0.015 ( 0.38)
GAUGE
PLANE
0.005 ( 0.13)
MIN
Figure 35. 8-Lead Plastic Dual-in-Line Package [PDIP]
P-Suffix
(N-8)
Dimensions shown in inches and (millimeters)
OP07 Data Sheet
Rev. G | Page 14 of 16
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
OP07EPZ 0°C to 70°C 8-Lead PDIP N-8 (P-Suffix)
OP07CPZ
−40
°
C to +85
°
C
8-Lead PDIP
N-8 (P-Suffix)
OP07CSZ −40
°
C to +85
°
C 8-Lead SOIC_N R-8 (S-Suffix)
OP07CSZ-REEL −40
°
C to +85
°
C 8-Lead SOIC_N R-8 (S-Suffix)
OP07CSZ-REEL7
−40
°
C to +85
°
C
8-Lead SOIC_N
R-8 (S-Suffix)
1 Z = RoHS Compliant Part.
Data Sheet OP07
Rev. G | Page 15 of 16
NOTES
