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FEATURES
DESCRIPTION/ORDERING INFORMATION
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
SN74ALVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES015L – JULY 1995 – REVISED NOVEMBER 2005
•Member of the Texas Instruments Widebus™Family
•Operates From 1.65 V to 3.6 V•Max t
pd
of 3 ns at 3.3 V• ± 24-mA Output Drive at 3.3 V•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Latch-Up Performance Exceeds 250 mA PerJESD 17•ESD Protection Exceeds JESD 22- 2000-V Human-Body Model (A114-A)- 200-V Machine Model (A115-A)
This 16-bit (dual-octal) noninverting bus transceiver isdesigned for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16245 is designed forasynchronous communication between two databuses. The logic levels of the direction-control (DIR)input and the output-enable ( OE) input activate eitherthe B-port outputs or the A-port outputs or place bothoutput ports into the high-impedance mode. Thedevice transmits data from the A bus to the B buswhen the B-port outputs are activated, and from the Bbus to the A bus when the A-port outputs areactivated. The input circuitry on both A and B ports isalways active and must have a logic HIGH or LOWlevel applied to prevent excess I
CC
and I
CCZ
.xxxxxx
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistorswith the bus-hold circuitry is not recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
K
GRD OR ZRD PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
SN74ALVCH16245
16-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
SCES015L – JULY 1995 – REVISED NOVEMBER 2005
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
FBGA – GRD SN74ALVCH16245GRDR
Tape and reel VH245FBGA – ZRD (Pb-free) SN74ALVCH16245ZRDR
Tube SN74ALVCH16245DLSSOP – DL ALVCH16245Tape and reel SN74ALVCH16245DLR
SN74ALVCH16245DGGR–40 °C to 85 °C TSSOP – DGG Tape and reel ALVCH1624574ALVCH16245DGGRG4
SN74ALVCH16245DGVRTVSOP – DGV Tape and reel VH24574ALVCH16245DGVRE4VFBGA – GQL SN74ALVCH16245KRTape and reel VH245VFBGA – ZQL (Pb-free) 74ALVCH16245ZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
TERMINAL ASSIGNMENTS
(1)
(56-Ball GQL/ZQL Package)
123456
A1DIR NC NC NC NC 1 OE
B1B2 1B1 GND GND 1A1 1A2
C1B4 1B3 V
CC
V
CC
1A3 1A4
D1B6 1B5 GND GND 1A5 1A6
E1B8 1B7 1A7 1A8
F2B1 2B2 2A2 2A1
G2B3 2B4 GND GND 2A4 2A3
H2B5 2B6 V
CC
V
CC
2A6 2A5
J2B7 2B8 GND GND 2A8 2A7
XXX
K2DIR NC NC NC NC 2 OEXXX
XXX (1) NC – No internal connection
TERMINAL ASSIGNMENTS
(1)
(54-Ball GRD/ZRD Package)
123456
A1B1 NC 1DIR 1 OE NC 1A1
B1B3 1B2 NC NC 1A2 1A3
C1B5 1B4 V
CC
V
CC
1A4 1A5
D1B7 1B6 GND GND 1A6 1A7
E2B1 1B8 GND GND 1A8 2A1
F2B3 2B2 GND GND 2A2 2A3
G2B5 2B4 V
CC
V
CC
2A4 2A5
H2B7 2B6 NC NC 2A6 2A7
J2B8 NC 2DIR 2 OE NC 2A8
(1) NC – No internal connection
2
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To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13
Absolute Maximum Ratings
(1)
SN74ALVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES015L – JULY 1995 – REVISED NOVEMBER 2005
FUNCTION TABLE
(1)
(EACH 8-BIT SECTION)
CONTROL INPUTS OUTPUT CIRCUITS
OPERATIONOE DIR A PORT B PORT
L L Enabled Hi-Z B data to A busL H Hi-Z Enabled A data to B busH X Hi-Z Hi-Z Isolation
(1) Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 4.6 VV
I
Input voltage range
(2) (3)
–0.5 V
CC
+ 0.5 VV
O
Output voltage range
(2) (3)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 -50 mAI
OK
Output clamp current V
O
< 0 -50 mAI
O
Continuous output current ±50 mAContinuous current through each V
CC
or GND ±100 mADGG package 70DGV package 58θ
JA
Package thermal impedance
(4)
DL package 63 °C/WGQL/ZQL package 42GRD/ZRD package 36T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) This value is limited to 4.6 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
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Recommended Operating Conditions
(1)
SN74ALVCH16245
16-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
SCES015L – JULY 1995 – REVISED NOVEMBER 2005
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 VV
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 VV
CC
= 2.7 V to 3.6 V 2V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 VV
CC
= 2.7 V to 3.6 V 0.8V
I
Input voltage 0 V
CC
VV
O
Output voltage 0 V
CC
VV
CC
= 1.65 V –4V
CC
= 2.3 V –12I
OH
High-level output current mAV
CC
= 2.7 V –12V
CC
= 3 V –24V
CC
= 1.65 V 4V
CC
= 2.3 V 12I
OL
Low-level output current mAV
CC
= 2.7 V 12V
CC
= 3 V 24∆t/ ∆v Input transition rise or fall rate 10 ns/VT
A
Operating free-air temperature –40 85 °C
(1) All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Electrical Characteristics
Switching Characteristics
SN74ALVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES015L – JULY 1995 – REVISED NOVEMBER 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= –100 µA 1.65 V to 3.6 V V
CC
– 0.2I
OH
= –4 mA 1.65 V 1.2I
OH
= –6 mA 2.3 V 2V
OH
2.3 V 1.7 VI
OH
= –12 mA 2.7 V 2.23 V 2.4I
OH
= –24 mA 3 V 2I
OL
= 100 µA 1.65 V to 3.6 V 0.2I
OL
= 4 mA 1.65 V 0.45I
OL
= 6 mA 2.3 V 0.4V
OL
V2.3 V 0.7I
OL
= 12 mA
2.7 V 0.4I
OL
= 24 mA 3 V 0.55I
I
V
I
= V
CC
or GND 3.6 V ±5µAV
I
= 0.58 V 1.65 V 25V
I
= 1.07 V 1.65 V –25V
I
= 0.7 V 2.3 V 45I
I(hold)
V
I
= 1.7 V 2.3 V –45 µAV
I
= 0.8 V 3 V 75V
I
= 2 V 3 V –75V
I
= 0 to 3.6 V
(2)
3.6 V ±500I
OZ
(3)
V
O
= V
CC
or GND 3.6 V ±10 µAI
CC
V
I
= V
CC
or GND, I
O
= 0 3.6 V 40 µA∆I
CC
One input at V
CC
– 0.6 V, Other inputs at V
CC
or GND 3 V to 3.6 V 750 µAC
i
Control inputs V
I
= V
CC
or GND 3.3 V 4 pFC
io
A or B ports V
O
= V
CC
or GND 3.3 V 8 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25°C.(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state toanother.
(3) For I/O ports, the parameter I
OZ
includes the input leakage current.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 1.8 V V
CC
= 2.7 VFROM TO
±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX
t
pd
A or B B or A
(1)
1 3.7 3.6 1 3 nst
en
OE A or B
(1)
1 5.7 5.4 1 4.4 nst
dis
OE A or B
(1)
1 5.2 4.6 1 4.1 ns
(1) This information was not available at the time of publication.
5
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Operating Characteristics
SN74ALVCH16245
16-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
SCES015L – JULY 1995 – REVISED NOVEMBER 2005
T
A
= 25 °C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VPARAMETER TEST CONDITIONS UNITTYP TYP TYP
Outputs enabled
(1)
22 29Power dissipationC
pd
C
L
= 50 pF, f = 10 MHz pFcapacitance
Outputs disabled
(1)
4 5
(1) This information was not available at the time of publication.
6
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PARAMETER MEASUREMENT INFORMATION
VM
VM
VM
VM
VM
VM
VM
VM
VOH
VOL
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 Open
GND
RL
RL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + V∆
VOH − V∆
0 V
VI
0 V
0 V
tw
VIVI
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
0 V
VI
VM
tPHL
VMVM
VI
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VMVM
tPLH
VLOAD
VLOAD/2
1.8 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUT
SN74ALVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES015L – JULY 1995 – REVISED NOVEMBER 2005
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com 3-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
74ALVCH16245DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16245DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16245DGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16245DLG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16245DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16245ZQLR ACTIVE BGA
MICROSTAR
JUNIOR
ZQL 56 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
74ALVCH16245ZRDR ACTIVE BGA
MICROSTAR
JUNIOR
ZRD 54 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
SN74ALVCH16245DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16245DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16245DL ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16245DLR ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16245KR LIFEBUY BGA
MICROSTAR
JUNIOR
GQL 56 1000 TBD SNPB Level-1-240C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 3-May-2012
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74ALVCH16245 :
•Enhanced Product: SN74ALVCH16245-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
74ALVCH16245ZQLR BGA MI
CROSTA
R JUNI
OR
ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1
74ALVCH16245ZRDR BGA MI
CROSTA
R JUNI
OR
ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1
SN74ALVCH16245DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
SN74ALVCH16245DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1
SN74ALVCH16245DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
SN74ALVCH16245KR BGA MI
CROSTA
R JUNI
OR
GQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74ALVCH16245ZQLR BGA MICROSTAR
JUNIOR ZQL 56 1000 333.2 345.9 28.6
74ALVCH16245ZRDR BGA MICROSTAR
JUNIOR ZRD 54 1000 333.2 345.9 28.6
SN74ALVCH16245DGGR TSSOP DGG 48 2000 367.0 367.0 45.0
SN74ALVCH16245DGVR TVSOP DGV 48 2000 367.0 367.0 38.0
SN74ALVCH16245DLR SSOP DL 48 1000 367.0 367.0 55.0
SN74ALVCH16245KR BGA MICROSTAR
JUNIOR GQL 56 1000 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
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