Apr 2012. Version 1.2 MagnaChip Semiconductor Ltd.
1
MDV5524 – Asymmetric Dual N-Channel Trench MOSFET 30V
D
G
S
D
G
S
S1/D2
D1
S2
G2
G1
Absolute Maximum Ratings (Ta = 25oC)
Symbol
FET1
FET2
Unit
VDSS
30
V
VGSS
±20
±12
V
Continuous Drain Current (1)
TC=25oC
ID
24.5
31.2
A
TC=100oC
15.5
19.7
TA=25oC
8.5
9.9
TA=70oC
6.8
7.9
IDM
100
125
A
Power Dissipation
TC=25oC
PD
14.7
20.8
W
TC=100oC
5.9
8.3
TA=25oC
1.8
2.1
TA=70oC
1.1
1.3
EAS
12.1
25.6
mJ
TJ, Tstg
-55~150
oC
Thermal Characteristics
Characteristics
Symbol
FET1
FET2
Unit
Thermal Resistance, Junction-to-Ambient (1)
RθJA
70
60
oC/W
Thermal Resistance, Junction-to-Case
RθJC
8.5
6.0
MDV5524
Asymmetric Dual N-channel Trench MOSFET 30V
General Description
The MDV5524 uses advanced MagnaChip’s MOSFET
Technology, which provides high performance in on-state
resistance, fast switching performance and excellent
quality. MDV5524 is suitable for DC/DC converter and
general purpose applications.
Features
FET1 FET2
VDS = 30V VDS = 30V
ID = 24.5A ID = 31.2A @VGS = 10V
RDS(ON)
< 14.4mΩ < 12.6mΩ @VGS = 10V
< 21.3mΩ < 15.6mΩ @VGS = 4.5V
100% UIL Tested
100% Rg Tested
5
6
7
8
4
3
2
1
G1
D1
D1
D1
G2
S2
S2
S2
S1/D2
D1
Apr 2012. Version 1.2 MagnaChip Semiconductor Ltd.
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MDV5524 – Asymmetric Dual N-Channel Trench MOSFET 30V
Ordering Information
Part Number
Temp. Range
Package
Packing
Rohs Status
MDV5524URH
-55~150oC
Dual PDFN33
Tape & Reel
Halogen Free
FET1 Electrical Characteristics (Ta =25oC)
Characteristics
Symbol
Test Condition
Min
Typ
Max
Unit
Static Characteristics
Drain-Source Breakdown Voltage
BVDSS
ID = 250μA, VGS = 0V
30
-
-
V
Gate Threshold Voltage
VGS(th)
VDS = VGS, ID = 250μA
1.3
1.8
2.4
Drain Cut-Off Current
IDSS
VDS = 30.0V, VGS = 0V
-
-
1
μA
Gate Leakage Current
IGSS
VGS = ±20.0V, VDS = 0V
-
-
±0.1
Drain-Source ON Resistance
RDS(ON)
VGS = 10.0V, ID = 6.0A
-
12.0
14.4
mΩ
VGS = 4.5V, ID = 5.0A
-
17.0
21.3
Forward Transconductance
gfs
VDS = 5.0V, ID = 6.0A
-
19.5
-
S
Dynamic Characteristics
Total Gate Charge
Qg(10V)
VDS = 15.0V, ID = 6.0A,
VGS = 10.0V
5.7
7.2
8.6
nC
Total Gate Charge
Qg(4.5V)
2.8
3.6
4.3
Gate-Source Charge
Qgs
-
1.4
-
Gate-Drain Charge
Qgd
-
1.2
-
Input Capacitance
Ciss
VDS = 15.0V, VGS = 0V,
f = 1.0MHz
290
386
483
pF
Reverse Transfer Capacitance
Cosss
68
91
113
Output Capacitance
Crss
35
47
60
Turn-On Delay Time
td(on)
VDD=15.0V, ID=6.0A,
VGS=10.0V, Rg=6.0Ω
-
6.7
-
ns
Rise Time
tr
-
10.2
-
Turn-Off Delay Time
td(off)
-
17.3
-
Fall Time
tf
-
6.5
-
Gate Resistance
Rg
f=1 MHz
-
3.0
-
Ω
Drain-Source Body Diode Characteristics
Source-Drain Diode Forward Voltage
VSD
IS = 1.0A, VGS = 0V
-
0.7
1.2
V
Body Diode Reverse Recovery Time
trr
IF = 6.0A, dl/dt = 100A/μs
-
16.0
20.0
ns
Body Diode Reverse Recovery Charge
Qrr
-
8.0
10.0
nC
Note :
1. Surface mounted FR-4 board by JEDEC (jesd51-7). Continuous current at TC=25℃ is silicon limited.
2. EAS is tested at starting Tj = 25℃, L = 0.1mH, IAS = 11.0A, VDD = 27V, VGS = 10V (100% UIL Test).
Apr 2012. Version 1.2 MagnaChip Semiconductor Ltd.
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MDV5524 – Asymmetric Dual N-Channel Trench MOSFET 30V
Fig.1 On-Region Characteristics
Fig.2 On-Resistance Variation with
Drain Current and Gate Voltage
Fig.3 On-Resistance Variation with
Temperature
Area
Fig.4 On-Resistance Variation with
Gate to Source Voltage
Fig.5 Transfer Characteristics
Fig.6 Body Diode Forward Voltage
Variation with Source Current and
Temperature
-50 -25 025 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
1.8
※ Notes :
1. VGS = 10 V
2. ID = 6 A
RDS(ON), (Normalized)
Drain-Source On-Resistance
TJ, Junction Temperature [oC]
0 1 2 3
0
10
20
30
40
8.0V
5.0V
3.5V
VGS = 10V
4.5V
4.0V
3.0V
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
510 15 20 25 30 35 40 45 50
5
10
15
20
25
VGS = 10V
VGS = 4.5V
Drain-Source On-Resistance [mΩ]
ID, Drain Current [A]
2 4 6 8 10
5
10
15
20
25
30
35
40
※ Notes :
ID = 6A
TA = 25℃
RDS(ON) [mΩ ],
Drain-Source On-Resistance
VGS, Gate to Source Volatge [V]
1 2 3 4 5
0
5
10
15
20
VGS, Gate-Source Voltage [V]
TJ=25℃
※ Notes :
VDS = 5V
ID, Drain Current [A]
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
10-1
100
101
TJ=25℃
※ Notes :
VGS = 0V
IDR, Reverse Drain Current [A]
VSD, Source-Drain voltage [V]
Apr 2012. Version 1.2 MagnaChip Semiconductor Ltd.
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MDV5524 – Asymmetric Dual N-Channel Trench MOSFET 30V
10-1 100101102
10-2
10-1
100
101
102
103
1 ms
10 s
1 s
100 ms
DC
10 ms
Operation in This Area
is Limited by R DS(on)
Single Pulse
TJ=Max Rated
TC=25℃
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
Fig.7 Gate Charge Characteristics
Fig.8 Capacitance Characteristics
Fig.9 Maximum Safe Operating Area
Fig.10 Maximum Drain Current vs. Case
Temperature
Fig.11 Transient Thermal Response Curve
010 20 30
0
100
200
300
400
500
600 Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
※ Notes ;
1. VGS = 0 V
2. f = 1 MHz
Crss
Coss
Ciss
Capacitance [F]
VDS, Drain-Source Voltage [V]
25 50 75 100 125 150
0
4
8
12
16
20
24
28
ID, Drain Current [A]
TC, Case Temperature [℃]
10-4 10-3 10-2 10-1 100101102103
10-2
10-1
100
101
※ Notes :
Duty Factor, D=t1/t2
PEAK TJ = PDM * Zθ JC
* Rθ JC
(t) + TC
single pulse
D=0.5
0.02
0.2
0.05
0.1
0.01
Zθ JC
, Thermal Response
t1, Rectangular Pulse Duration [sec]
0 2 4 6 8
0
2
4
6
8
10
※ Note : ID = 6.0A
VGS, Gate-Source Voltage [V]
QG, Total Gate Charge [nC]
Apr 2012. Version 1.2 MagnaChip Semiconductor Ltd.
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MDV5524 – Asymmetric Dual N-Channel Trench MOSFET 30V
FET2 Electrical Characteristics (Ta =25oC)
Characteristics
Symbol
Test Condition
Min
Typ
Max
Unit
Static Characteristics
Drain-Source Breakdown Voltage
BVDSS
ID = 250μA, VGS = 0V
30
-
-
V
Gate Threshold Voltage
VGS(th)
VDS = VGS, ID = 250μA
1.0
1.5
2.0
Drain Cut-Off Current
IDSS
VDS = 30.0V, VGS = 0V
-
-
1
μA
Gate Leakage Current
IGSS
VGS = ±12.0V, VDS = 0V
-
-
±0.1
Drain-Source ON Resistance
RDS(ON)
VGS = 10.0V, ID = 9.0A
-
10.5
12.6
mΩ
VGS = 4.5V, ID = 7.0A
-
12.5
15.6
Forward Transconductance
gfs
VDS = 5.0V, ID = 9.0A
-
38.6
-
S
Dynamic Characteristics
Total Gate Charge
Qg(10V)
VDS = 15.0V, ID = 9.0A,
VGS = 10V
14.3
18.0
21.5
nC
Total Gate Charge
Qg(4.5V)
6.4
8.1
9.7
Gate-Source Charge
Qgs
-
2.5
-
Gate-Drain Charge
Qgd
-
2.0
-
Input Capacitance
Ciss
VDS = 15.0V, VGS = 0V,
f = 1.0MHz
778
1037
1297
pF
Reverse Transfer Capacitance
Coss
107
143
179
Output Capacitance
Crss
42
56
70
Turn-On Delay Time
td(on)
VDD=15.0V, ID=9.0A,
VGS=10.0V, Rg=6.0Ω
-
9.3
-
ns
Rise Time
tr
-
10.4
-
Turn-Off Delay Time
td(off)
-
41.8
-
Fall Time
tf
-
7.1
-
Gate Resistance
Rg
f=1 MHz
-
2.0
3.0
Ω
Drain-Source Body Diode Characteristics
Source-Drain Diode Forward Voltage
VSD
IS = 1.0A, VGS = 0V
-
0.7
1.2
V
Body Diode Reverse Recovery Time
trr
IF = 9.0A, dl/dt = 100A/μs
-
19.1
23.8
ns
Body Diode Reverse Recovery Charge
Qrr
-
12.0
15.0
nC
Note :
1. Surface mounted FR-4 board by JEDEC (jesd51-7). Continuous current at TC=25℃ is silicon limited.
2. EAS is tested at starting Tj = 25℃, L = 0.1mH, IAS = 16.0A, VDD = 27V, VGS = 10V (100% UIL Test).
Apr 2012. Version 1.2 MagnaChip Semiconductor Ltd.
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MDV5524 – Asymmetric Dual N-Channel Trench MOSFET 30V
Fig.1 On-Region Characteristics
Fig.2 On-Resistance Variation with
Drain Current and Gate Voltage
Fig.3 On-Resistance Variation with
Temperature
Area
Fig.4 On-Resistance Variation with
Gate to Source Voltage
Fig.5 Transfer Characteristics
Fig.6 Body Diode Forward Voltage
Variation with Source Current and
Temperature
-50 -25 025 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
1.8
※ Notes :
1. VGS = 10 V
2. ID = 9 A
RDS(ON), (Normalized)
Drain-Source On-Resistance
TJ, Junction Temperature [oC]
2 4 6 8 10
0
10
20
30
40
※ Notes :
ID = 9A
TA = 25℃
RDS(ON) [mΩ ],
Drain-Source On-Resistance
VGS, Gate to Source Volatge [V]
0.0 0.5 1.0 1.5 2.0
0
10
20
30
40
4.0V
VGS = 10V
3.5V
4.5V
3.0V
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
510 15 20 25 30
8
10
12
14
16
VGS = 10V
VGS = 4.5V
Drain-Source On-Resistance [mΩ]
ID, Drain Current [A]
1 2 3 4 5
0
5
10
15
20
VGS, Gate-Source Voltage [V]
TJ=25℃
※ Notes :
VDS = 5V
ID, Drain Current [A]
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
10-1
100
101
TJ=25℃
※ Notes :
VGS = 0V
IDR, Reverse Drain Current [A]
VSD, Source-Drain voltage [V]
Apr 2012. Version 1.2 MagnaChip Semiconductor Ltd.
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MDV5524 – Asymmetric Dual N-Channel Trench MOSFET 30V
10-1 100101102
10-1
100
101
102
103
10 s
1 s
100 ms
10 ms
DC
1 ms
Operation in This Area
is Limited by R DS(on)
Single Pulse
TJ=Max Rated
TC=25℃
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
Fig.7 Gate Charge Characteristics
Fig.8 Capacitance Characteristics
Fig.9 Maximum Safe Operating Area
Fig.10 Maximum Drain Current vs. Case
Temperature
Fig.11 Transient Thermal Response Curve
010 20 30
0
200
400
600
800
1000
1200
1400
1600 Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
※ Notes ;
1. VGS = 0 V
2. f = 1 MHz
Crss
Coss
Ciss
Capacitance [F]
VDS, Drain-Source Voltage [V]
25 50 75 100 125 150
0
5
10
15
20
25
30
35
ID, Drain Current [A]
TC, Case Temperature [℃]
10-4 10-3 10-2 10-1 100101102103
10-2
10-1
100
101
※ Notes :
Duty Factor, D=t1/t2
PEAK TJ = PDM * Zθ JC
* Rθ JC
(t) + TC
single pulse
D=0.5
0.02
0.2
0.05
0.1
0.01
Zθ JC
, Thermal Response
t1, Rectangular Pulse Duration [sec]
0 2 4 6 8 10 12 14 16 18 20
0
2
4
6
8
10
※ Note : ID = 9.0A
VGS, Gate-Source Voltage [V]
QG, Total Gate Charge [nC]
Apr 2012. Version 1.2 MagnaChip Semiconductor Ltd.
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MDV5524 – Asymmetric Dual N-Channel Trench MOSFET 30V
Package Dimension
Dimensions are in millimeters, unless otherwise specified
Dual PDFN33 (3x3mm)
Apr 2012. Version 1.2 MagnaChip Semiconductor Ltd.
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MDV5524 – Asymmetric Dual N-Channel Trench MOSFET 30V
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generation, medical appliances, and devices or systems in which malfunction of any Product can reasonably be
expected to result in a personal injury. Seller’s customers using or selling Seller’s products for use in such
applications do so at their own risk and agree to fully defend and indemnify Seller.
MagnaChip reserves the right to change the specifications and circuitry without notice at any time. MagnaChip does not consider responsibility
for use of any circuitry other than circuitry entirely included in a MagnaChip product. is a registered trademark of MagnaChip
Semiconductor Ltd.