K4S641632K-UL75 - Samsung Electronics

K4S640832K

Synchronous DRAM

Rev. 1.1 February 2006

1 of 14

K4S641632K

* Samsung Electronics reserves the right to change products or specification without notice.

64Mb K-die SDRAM Specification

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure couldresult in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

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Synchronous DRAM

Rev. 1.1 February 2006

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K4S641632K

Revision History

Revision Month Year History

0.0 January 2005 - Target spec release

0.1 March 2005 - Change DC current

0.2 April 2005 - Delete bit organization for x4

0.3 July 2005 - Delete 7ns speed bin

1.0 September 2005 - Final spec release

1.1 February 2006 - Added 5ns speed bin for x16

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Part No. Orgainization Max Freq. Interface Package

K4S640832K-T(U)C/L75 8Mb x 8 133MHz(CL=3)

LVTTL 54pin TSOP(II)

Pb (Pb-free)

K4S641632K-T(U)C/L50

4Mb x 16

200MHz(CL=3)

K4S641632K-T(U)C/L60 166MHz(CL=3)

K4S641632K-T(U)C/L75 133MHz(CL=3)

The K4S640832K / K4S641632K is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8

bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows

precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies,

programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock

• Burst read single-bit write operation

• DQM (x8) & L(U)DQM (x16) for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

• Pb/Pb-free Package

• RoHS compliant for Pb-free Package

GENERAL DESCRIPTION

FEATURES

Ordering Information

2M x 8Bit x 4Banks / 1M x 16Bit x 4Banks SDRAM

Row & Column address configuration

Organization Row Address Column Address

8Mx8 A0~A11 A0-A8

4Mx16 A0~A11 A0-A7

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11.76±0.20

0.463±0.008

0.002

0.05 MIN

0.008

0.21

± 0.002

± 0.05

0.020

0.50

( )

0.005 -0.001

+0.003

0.125 -0.035

+0.075

0.400

10.16

0.45~0.75

0.018~0.030

0.010

0.25 TYP

0~8°C

#54 #28

#1 #27

0.004

0.10 MAX

0.028

0.71

( ) 0.012

0.30

0.0315

0.80

0.047

1.20 MAX

0.039

1.00

± 0.004

± 0.10

0.891

22.62 MAX

0.875

22.22

± 0.004

± 0.10

+0.10

-0.05

+0.004

-0.002

54Pin TSOP(II) Package Dimension

Package Physical Dimension

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Synchronous DRAM

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FUNCTIONAL BLOCK DIAGRAM

Bank Select

Data Input Register

2M x 8 / 1M x 16

Sense AMP

Output BufferI/O Control

Column Decoder

Latency & Burst Length

Programming Register

Address Register

Row Buffer

Refresh Counter

Row Decoder Col. Buffer

LRAS

LCBR

LCKE

LRAS LCBR LWE LDQM

CLK CKE CS RAS CAS WE L(U)DQM

LWE

LDQM

DQi

CLK

ADD

LCAS LWCBR

2M x 8 / 1M x 16

Timing Register

Samsung Electronics reserves the right to change products or specification without notice.

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PIN CONFIGURATION (Top view)

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

Pin Name Input Function

CLK System clock Active on the positive going edge to sample all inputs.

CS Chip select Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

CKE Clock enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A11 Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11,

Column address : (x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7)

BA0 ~ BA1Bank select address Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

WE Write enable Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQ0 ~ NData input/output Data inputs/outputs are multiplexed on the same pins.

(x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)

VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.

VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU No connection

/reserved for future use This pin is recommended to be left No Connection on the device.

x16 x8 x16

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

LDQM

CAS

RAS

BA0

BA1

A10/AP

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

N.C/RFU

UDQM

CLK

CKE

N.C

A11

VSS

VDD

DQ0

VDDQ

N.C

DQ1

VSSQ

N.C

DQ2

VDDQ

N.C

DQ3

VSSQ

N.C

VDD

N.C

CAS

RAS

BA0

BA1

A10/AP

VDD

VSS

DQ7

VSSQ

N.C

DQ6

VDDQ

N.C

DQ5

VSSQ

N.C

DQ4

VDDQ

N.C

VSS

N.C/RFU

DQM

CLK

CKE

N.C

A11

VSS

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ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD1W

Short circuit current IOS 50 mA

Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage VDD, VDDQ 3.0 3.3 3.6 V

Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1

Input logic low voltage VIL -0.3 0 0.8 V 2

Output logic high voltage VOH 2.4 - - V IOH = -2mA

Output logic low voltage VOL --0.4VIOL = 2mA

Input leakage current ILI -10 - 10 uA 3

1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Pin Symbol Min Max Unit Note

Clock CCLK 2.5 4.0 pF

RAS, CAS, WE, CS, CKE, DQM CIN 2.5 5.0 pF

Address CADD 2.5 5.0 pF

(x8 : DQ0 ~ DQ7), (x16 : DQ0 ~DQ15) COUT 4.0 6.5 pF

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1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S640832K-T(U)C

4. K4S640832K-T(U)L

5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Notes :

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x8)

Parameter Symbol Test Condition Version Unit Note

Operating current

(One bank active) ICC1

Burst length = 1

tRC ≥ tRC(min)

IO = 0 mA

55 mA 1

Precharge standby current in

power-down mode

ICC2P CKE ≤ VIL(max), tCC = 10ns 1 mA

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞1

Precharge standby current in

non power-down mode

ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns 15

ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable 6

Active standby current in

power-down mode

ICC3P CKE ≤ VIL(max), tCC = 10ns 3 mA

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞3

Active standby current in

non power-down mode

(One bank active)

ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns 30

ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable 25

Operating current

(Burst mode) ICC4

IO = 0 mA

Page burst

4Banks Activated

tCCD = 2CLKs

80 mA 1

Refresh current ICC5 tRC ≥ tRC(min) 85 mA 2

Self refresh current ICC6 CKE ≤ 0.2V C1mA3

L400uA4

DC CHARACTERISTICS (x8)

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1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S641632K-T(U)C

4. K4S641632K-T(U)L

5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Notes :

DC CHARACTERISTICS (x16)

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x16 only)

Parameter Symbol Test Condition Version Unit Note

50 60 75

Operating current

(One bank active) ICC1

Burst length = 1

tRC ≥ tRC(min)

IO = 0 mA

80 70 55 mA 1

Precharge standby current in

power-down mode

ICC2P CKE ≤ VIL(max), tCC = 10ns 1 mA

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞1

Precharge standby current in

non power-down mode

ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns 15

ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable 6

Active standby current in

power-down mode

ICC3P CKE ≤ VIL(max), tCC = 10ns 3 mA

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞3

Active standby current in

non power-down mode

(One bank active)

ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns 30

ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable 25

Operating current

(Burst mode) ICC4

IO = 0 mA

Page burst

4Banks Activated

tCCD = 2CLKs

110 100 85 mA 1

Refresh current ICC5 tRC ≥ tRC(min) 110 100 85 mA 2

Self refresh current ICC6 CKE ≤ 0.2V C1mA3

L400uA4

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AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter Value Unit

AC input levels (Vih/Vil) 2.4/0.4 V

Input timing measurement reference level 1.4 V

Input rise and fall time tr/tf = 1/1 ns

Output timing measurement reference level 1.4 V

Output load condition See Fig. 2

3.3V

1200Ω

870Ω

Output

30pF

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Vtt = 1.4V

50Ω

Output

30pF

Z0 = 50Ω

(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit

Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

6. tRC =tRFC, tRDL = tWR.

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter Symbol

Version

Unit Note

50 60 75

Row active to row active delay tRRD(min) 10 12 15 ns 1

RAS to CAS delay tRCD(min) 15 18 20 ns 1

Row precharge time tRP(min) 15 18 20 ns 1

Row active time tRAS(min) 40 42 45 ns 1

tRAS(max) 100 us

Row cycle time tRC(min) 55 60 65 ns 1, 6

Last data in to row precharge tRDL(min) 2 CLK 2,5,6

Last data in to Active delay tDAL(min) 2 CLK + tRP - 5

Last data in to new col. address delay tCDL(min) 1 CLK 2

Last data in to burst stop tBDL(min) 1 CLK 2

Col. address to col. address delay tCCD(min) 1 CLK 3

Number of valid output data CAS latency = 3 2 ea 4

CAS latency = 2 1

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1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

4. tSS applies for address setup time, clock enable setup time, commend setup time and data setup time

tSH applies for address holde time, clock enable hold time, commend hold time and data hold time

Notes :

DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter Symbol Condition Min Typ Max Unit Notes

Output rise time trh Measure in linear

region : 1.2V ~ 1.8V 1.37 4.37 Volts/ns 3

Output fall time tfh Measure in linear

region : 1.2V ~ 1.8V 1.30 3.8 Volts/ns 3

Output rise time trh Measure in linear

region : 1.2V ~ 1.8V 2.8 3.9 5.6 Volts/ns 1,2

Output fall time tfh Measure in linear

region : 1.2V ~ 1.8V 2.0 2.9 5.0 Volts/ns 1,2

1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.

2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.

3. Measured into 50pF only, use these values to characterize to.

4. All measurements done with respect to VSS.

Notes :

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter Symbol 50 60 75 Unit Note

Min Max Min Max Min Max

CLK cycle time CAS latency=3 tCC

51000 61000 7.5 1000 ns 1

CAS latency=2 - 10 10

CLK to valid

output delay

CAS latency=3 tSAC

- 4.5 - 5 - 5.4 ns 1,2

CAS latency=2 - - - 6 - 6

Output data

hold time

CAS latency=3 tOH

2-2.5- 3 -

ns 2

CAS latency=2 - - 3 - 3 -

CLK high pulse width tCH 2 -2.5-2.5-ns3

CLK low pulse width tCL 2 -2.5-2.5-ns3

Input setup time tSS 1.5 - 1.5 - 1.5 - ns 3, 4

Input hold time tSH 1 - 1 - 0.8 - ns 3, 4

CLK to output in Low-Z tSLZ 1-1 - 1 -ns2

CLK to output

in Hi-Z

CAS latency=3 tSHZ

- 4.5 - 5 - 5.4 ns

CAS latency=2 - - - 6 - 6

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IOH Characteristics (Pull-up)

Voltage 200MHz/133MHz

Min

200MHz/133MHz

Max

(V) I (mA) I (mA)

3.45 - -1.68

3.30 - -19.11

3.00 -0.35 -51.87

2.70 -3.75 -90.44

2.50 -6.65 -107.31

1.95 -13.75 -137.9

1.80 -17.75 -158.34

1.65 -20.55 -173.6

1.50 -23.55 -188.79

1.40 -26.2 -199.01

1.00 -36.25 -241.15

0.20 -46.5 -351.68

IBIS SPECIFICATION

IOL Characteristics (Pull-down)

Voltage 200MHz/133MHz

Min

200MHz/133MHz

Max

(V) I (mA) I (mA)

3.45 43.92 155.82

3.30 - -

3.00 43.36 153.72

1.95 41.20 148.40

1.80 40.56 146.02

1.65 39.60 141.75

1.50 38.40 136.08

1.40 37.28 131.39

1.00 30.08 105.84

0.85 26.64 93.66

0.65 21.52 75.25

0.40 14.16 49.14

-100

-200

-300

-400

-500

-600

030.5 1 1.5 2 2.5 3.5

Voltage

250

200

150

100

030.5 1 1.5 2 2.5 3.5

Voltage

200MHz/133MHz Pull-up

200MHz/133MHz Pull-down

IOH Min (200MHz / 133MHz)

IOH Max (200MHz / 133MHz)

IOL Min (200MHz / 133MHz)

IOL Max (200MHz / 133MHz)

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VDD Clamp @ CLK, CKE, CS, DQM & DQ

VDD (V) I (mA)

0.0 0.0

0.2 0.0

0.4 0.0

0.6 0.0

0.7 0.0

0.8 0.0

0.9 0.0

1.0 0.23

1.2 1.34

1.4 3.02

1.6 5.06

1.8 7.35

2.0 9.83

2.2 12.48

2.4 15.30

2.6 18.31

VSS Clamp @ CLK, CKE, CS, DQM & DQ

VSS (V) I (mA)

-2.6 -57.23

-2.4 -45.77

-2.2 -38.26

-2.0 -31.22

-1.8 -24.58

-1.6 -18.37

-1.4 -12.56

-1.2 -7.57

-1.0 -3.37

-0.9 -1.75

-0.8 -0.58

-0.7 -0.05

-0.6 0.0

-0.4 0.0

-0.2 0.0

0.0 0.0

0312

Voltage

I (mA)

Voltage

I (mA)

Minimum VDD clamp current

(Referenced to VDD)

Minimum VSS clamp current

-10

-20

-30

-40

-3 0-2 -1

-50

-60

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SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t care, H=Logic high, L=Logic low)

Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11,

A9 ~ A0Note

Refresh

Auto refresh HHLL LHX X 3

Self

refresh

Entry L 3

Exit L H LH HHXX3

HX XX 3

Bank active & row addr. H X L L H H X V Row address

Read &

column address

Auto precharge disable HXLHLHXVLColumn

address

Auto precharge enable H 4,5

Write &

column address

Auto precharge disable HXLHLLXVLColumn

address

Auto precharge enable H 4,5

Burst stop H X L H H L X X 6

Precharge Bank selection HXLLHLX

VL X

All banks XH

Clock suspend or

active power down

Entry H L HX XX XXLV VV

Exit L H X X X X X

Precharge power down mode

Entry H L HX XX X

LH HH

Exit L H HX XX X

LV VV

DQM H X V X 7

No operation command H X HX XX XX

LH HH

1. OP Code : Operand code

A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Notes :