GM71V65403C GM71VS65403CL 16,777,216 WORDS x 4 BIT CMOS DYNAMIC RAM Description Pin Configuration The GM71V(S)65403C/CL is the new generation dynamic RAM organized 16,777,216 words by 4bits. The GM71V(S)65403C/CL utilizes advanced CMOS Silicon Gate Process Technology as well as advanced circuit techniques for wide operating margins, both internally and to the system user. System oriented features include single power supply of 3.3V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. The GM71V(S)65403C/CL offers Extended Data Out(EDO) Mode as a high speed access mode. Features * 16,777,216 Words x 4 Bit * Extended Data Out (EDO) Mode Capability * Fast Access Time & Cycle Time (Unit: ns) tRAC tAA tCAC tRC tHPC GM71V(S)65403C/CL-5 50 25 13 84 20 GM71V(S)65403C/CL-6 60 30 15 104 25 32 SOJ / TSOP II VCC 1 32 VSS IO0 2 31 IO3 IO1 3 30 IO2 NC 4 29 NC NC 5 28 NC NC 6 27 VSS VCC 7 26 /CAS /WE 8 25 /OE /RAS 9 24 NC A0 10 23 A11 A1 11 22 A10 A2 12 21 A9 A3 13 20 A8 A4 14 19 A7 A5 15 18 A6 VCC 16 17 VSS *Power dissipation - Active : 504mW/468mW(MAX) - Standby : 1.8 mW ( CMOS level : MAX ) 0.54mW ( L-Version : MAX) *EDO page mode capability *Access time : 50ns/60ns (max) *Refresh cycles - RAS only Refresh 4096 cycles/64 ms (GM71V65403C) 4096 cycles/128ms (GM71VS65403CL)(L_Version) *CBR & Hidden Refresh 4096 cycles/64 ms (GM71V65403C) 4096 cycles/128 ms (GM71VS65403CL)( L-Version ) *4 variations of refresh -RAS-only refresh -CAS-before-RAS refresh -Hidden refresh -Self refresh (L-Version) *Single Power Supply of 3.3V+/-10 % with a built-in VBB generator *Battery Back Up Operation ( L-Version ) Rev 0.1 / Apr'01 (Top View) GM71V65403C GM71VS65403CL Pin Description Pin Function A0-A11 Address Inputs A0-A11 Refresh Address Inputs Pin Function Write Enable WE I/O0 - I/O3 Data Input / Output RAS Row Address Strobe VCC Power (+3.3V) CAS Column Address Strobe VSS Ground OE Output Enable NC No Connection Ordering Information Type No. Access Time Package GM71V(S)65403C/CLJ-5 GM71V(S)65403C/CLJ-66 50ns 60ns 400 Mil 32Pin Plastic SOJ GM71V(S)65403C/CLT-5 GM71V(S)65403C/CLT-6 50ns 60ns 400 Mil 32Pin Plastic TSOP II Absolute Maximum Ratings* Symbol Parameter TSTG Rating Unit -55 to 125 C -0.5 to VCC + 0.5 (MAX ; 4.6V) V -0.5 to 4.6 V Storage Temperature (Plastic) VT Voltage on any Pin Relative to VSS VCC Voltage on VCC Relative to VSS IOUT Short Circuit Output Current 50 mA Power Dissipation 1.0 W PT *Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability. Recommended DC Operating Conditions (TA = 0 ~ 70C) Symbol Parameter Min Typ Max Unit Notes VCC Supply Voltage 3.0 3.3 3.6 V 1,2 VSS Supply Voltage 0 0 0 V 2 VIH Input High Voltage 2.0 - Vcc+0.3 V 1 VIL Input Low Voltage -0.3 - 0.8 V 1 TA Ambient Temperature under Bias 0 - 70 C Rev 0.1 / Apr'01 GM71V65403C GM71VS65403CL DC Electrical Characteristics: (VCC = 3.3V+/-10%, TA = 0 ~ 70C) Symbol Parameter Min Max Unit Note VOH Output Level Output Level Voltage (IOUT = -2mA) 2.4 VCC V VOL Output Level Output Level Voltage (IOUT = 2mA) 0 0.4 V ICC1 Operating Current (tRC = tRC min) 50ns - 140 60ns - 130 - 2 mA ICC2 Standby Current (TTL interface) Power Supply Standby Current (RAS, CAS= VIH, DOUT = High-Z) ICC3 RAS-Only Refresh Current ( tRC = tRC min) 50ns - 140 60ns - 130 Extended Data Out page Mode Current (RAS = VIL, CAS, Address Cycling: tHPC = tHPC min) 50ns - 110 60ns - 100 CMOS interface (RAS, CAS>=VCC-0.2V, DOUT = High-Z) - 0.5 mA Standby Current(L_Version) - 300 uA - 140 ICC4 ICC5 ICC6 CAS-before-RAS Refresh Current (tRC = tRC min) 50ns 60ns 1,2 mA mA 2 mA 1,3 4 mA 130 ICC7 Battery Back Up Operating Current(Standby with CBR) (tRC=31.25us,tRAS=300ns,Dout=High-Z) - 500 uA 4, 5 ICC8 Standby Current (CMOS) Power Supply Standby Current RAS = VIH, CAS = VIL , DOUT = Enable - 5 mA 1 ICC9 Self Refresh Current (RAS, CAS <=0.2V,Dout=High-Z) - 400 uA 5 II(L) Input Leakage Current, Any Input (0V<=VIN<=Vcc) -5 5 uA IO(L) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<=Vcc) -5 5 uA Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, tHPC. 4. VIH>=VCC-0.2V, 0V<=VIL<=0.2V 5. L-Version Rev 0.1 / Apr'01 GM71V65403C GM71VS65403CL Capacitance (VCC = 3.3V+/-10%, TA = 25C) Symbol Parameter Typ Max Unit Note CI1 Input Capacitance (Address) - 5 pF 1 CI2 Input Capacitance (Clocks) - 7 pF 1 CI/O Output Capacitance (Data-in,Data-Out) - 7 pF 1, 2 Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, CAS = VIH to disable DOUT. AC Characteristics (VCC = 3.3V+/-10%, TA = 0 ~ 70C, Notes 1, 2,19) Test Conditions Input rise and fall times : 2ns Output timing reference levels : VOL/VOH = 0.8/2.0V Input level : VIL/VIH = 0.0/3.0V Output load : 1 TTL gate+CL (100pF) Input timing reference levels : VIL/VIH = 0.8/2.0V (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6 Parameter Symbol Unit Min Max Min Max - 104 - ns 40 - ns Notes tRC Random Read or Write Cycle Time 84 tRP RAS Precharge Time 30 tCP CAS Precharge Time 8 - 10 - ns tRAS RAS Pulse Width 50 10000 60 10000 ns tCAS CAS Pulse Width 8 10000 10 10000 ns tASR Row Address Set-up Time 0 - 0 - ns tRAH Row Address Hold Time 8 - 10 - ns tASC Column Address Set-up Time 0 - 0 - ns tCAH Column Address Hold Time 8 - 10 - ns tRCD RAS to CAS Delay Time 12 37 14 45 ns 3 tRAD RAS to Column Address Delay Time 10 25 12 30 ns 4 tRSH RAS Hold Time 13 - 15 - ns tCSH CAS Hold Time 35 - 40 - ns tCRP CAS to RAS Precharge Time 5 - 5 - ns tODD OE to DIN Delay Time 13 - 15 - ns 5 tDZO OE Delay Time from DIN 0 - 0 - ns 6 tDZC CAS Delay Time from DIN 0 - 0 - ns 6 tT TransitionTime (Rise and Fall) 2 50 2 50 ns 7 Refresh Period - 64 - 64 ms Refresh Period ( L-Version ) - 128 - 128 ms tREF Rev 0.1 / Apr'01 - 4096 cycles 4096 cycles GM71V65403C GM71VS65403CL Read Cycles Parameter Symbol GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6 Notes Unit Min Max Min Max tRAC Access Time from RAS - 50 - 60 ns 8,9 tCAC Access Time from CAS - 13 - 15 ns 9,10,17 tAA tOAC Access Time from Column Address - 25 - 30 ns 9,11,17 Access Time from OE - 13 - 15 ns 9 tRCS Read Command Set-up Time 0 - 0 - ns tRCH Read Command Hold Time to CAS 0 - 0 - ns 12 tRRH Read Command Hold Time to RAS 0 - 0 - ns 12 tRAL Column Address to RAS Lead Time 25 - 30 - ns tCAL Column Address to CAS Lead Time 15 - 18 - ns tOFF Output Buffer Turn-off Delay Time from CAS - 13 - 15 ns 13,21 tOEZ Output Buffer Turn-off Delay Time from OE - 13 - 15 ns 13 tCDD CAS to DIN Delay Time 13 - 15 - ns 5 tRDD RAS to DIN Delay Time 13 - 15 - ns tWDD WE to DIN Delay Time 13 - 15 - ns tOFR Output Buffer Turn-off Delay Time from RAS - 13 - 15 ns 13,21 tWEZ Output Buffer Turn-off Delay Time from WE - 13 - 15 ns 13 tOH Output Data Hold Time 3 - 3 - ns 21 tOHR Output Data Hold Time from RAS 3 - 3 - ns 21 tRCHR Read Command Hold Time from RAS 50 - 60 - ns tOHO Output data hold time from OE 3 - 3 - ns tCLZ CAS to Output in Low - Z 0 - 0 - ns Rev 0.1 / Apr'01 GM71V65403C GM71VS65403CL Write Cycles GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6 Parameter Symbol Unit Min Max Min Max Notes tWCS Write Command Set-up Time 0 - 0 - ns tWCH Write Command Hold Time 8 - 10 - ns tWP Write Command Pulse Width 8 - 10 - ns tRWL Write Command to RAS Lead Time 13 - 15 - ns tCWL Write Command to CAS Lead Time 8 - 10 - ns tDS Data-in Set-up Time 0 - 0 - ns 15 tDH Data-in Hold Time 8 - 10 - ns 15 14 Read-Modify-Write Cycles GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6 Parameter Symbol Unit Min Max Min Max Notes tRWC Read-Modify-Write Cycle Time 116 - 140 - ns tRWD RAS to WE Delay Time 67 - 79 - ns 14 tCWD CAS to WE Delay Time 30 - 34 - ns 14 tAWD Column Address to WE Delay Time 42 - 49 - ns 14 tOEH OE Hold Time from WE 13 - 15 - ns Refresh Cycles Cycle GM71V(S)65403C/CL-5 Symbol Parameter GM71V(S)65403C/CL-6 Unit Min Max Min Max tCSR CAS Set-up Time (CAS-before-RAS Refresh Cycle) 5 - 5 - ns tCHR CAS Hold Time (CAS-before-RAS Refresh Cycle) 8 - 10 - ns tWRP WE setup time (CAS-before-RAS Refresh Cycle) 0 - 0 - ns tWRH WE hold time (CAS-before-RAS Refresh Cycle) 8 - 10 - ns tRPC RAS Precharge to CAS Hold Time 5 - 5 - ns Rev 0.1 / Apr'01 Notes GM71V65403C GM71VS65403CL Extended Data Out Mode Cycles GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6 Parameter Symbol Unit Min Max Min Max 20 - 25 - tHPC EDO Page Mode Cycle Time tWPE Write pulse width during CAS Precharge 8 - 10 tRASP EDO Mode RAS Pulse Width - 100000 tACP Access Time from CAS Precharge - tRHCP RAS Hold Time from CAS Precharge Notes 20 - ns ns - 100000 ns 16 28 - 35 ns 9,17 28 - 35 - ns tCOL CAS Hold Time Referred OE 8 - 10 - ns tCOP CAS to OE set-up Time 5 - 5 - ns tRCHP Read Command Hold Time from CAS Precharge 28 - 35 - ns tDOH tOEP Output Data Hold Time from CAS Low 3 - 3 - ns OE Precharge Time 8 - 10 - ns 9,22 EDO Page Mode Read-Modify-Write cycle GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6 Parameter Symbol Unit Min Max Min Max 57 - 68 - ns 45 - 54 - ns tHPRWC EDO Read-Modify-Write Cycle Time tCPW EDO Page Mode Read-Modify-Write Cycle CAS Precharge to WE Delay Time Notes 14 Self Refresh Cycles (L_Version) GM71V(S)65403C/CL-5 Parameter Symbol GM71V(S)65403C/CL-6 Min Max Min Max Unit Notes tRASS RAS Pulse Width(Self-Refresh) 100 - 100 - us 26 tRPS tCHS RAS Precharge Time(Self-Refresh) 90 - 110 - ns 26 CAS Hold Time(Self-Refresh) -50 - -50 - ns Rev 0.1 / Apr'01 GM71V65403C GM71VS65403CL Notes: AC measurements assume tT = 2ns . AC initial pause of 200 us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh) 3. Operation with the t RCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only: if t RCD is greater than the specified t RCD(max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the t RAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only: if t RAD is greater than the specified t RAD(max) limit, then access time is controlled exclusively by tAA. 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and V IL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH(min) and VIL (max). 8. Assumes that t RCD tRCD(max) and t RAD tRAD(max). If t RCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that tRCD tRCD(max) and tRCD + tCAC(max) tRAD + tAA(max). 11. Assumes that tRAD tRAD (max) and tRCD + tCAC(max) tRAD + tAA(max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 1. 2. 13. tOFF(max), tOEZ(max), t OFR(max) and t WEZ(max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. 14. tWCS, t RWD, t CWD, t AWD, and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if t WCS tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if tRWD tRWD(min), t CWD tCWD(min), t AWD tAWD(min) and t CPW tCPW(min), the cycle is a readmodify-write and the data output will contain data read from the selected cell: if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. tDS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in extended data out mode cycles. 17. Access time is determined by the longest among tAA, tCAC and tCPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid daa is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. Rev 0.1 / Apr'01 GM71V65403C GM71VS65403CL 20. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix cycle (1),(2) } minimum value of CAS cycle t HPC(t CAS + t CP + 2t T) becomes greater than the specified tHPC(min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and tOH, and between tOFR and tOFF. t 22. DOH defines the time at which the output level go cross. V OL =0.8V, VOH=2.0V of output timing reference level. 23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us after exiting from self refresh mode. 24. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and after self refresh mode according as note 23. 25. For L_Version, it is available to apply each 128 ms and 31.2 us instead of 64ms and 15.6us at note 23. 26. At t RASS > 100 us , self refresh mode is activated, and not active at tRASS < 10us It is undefined within the range of 10 us < tRASS < 100 us . for tRASS > 10 us , it is necessary to satisfy tRPS. XXX: H or L ( H : VIH(min)<=VIN<=VIH (max), L: VIH(min)<=VIN<=VIH(max)) 27. ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. Rev 0.1 / Apr'01 GM71V65403C GM71VS65403CL SOJ 32 pin PKG Dimension Unit: mm 20.95 MIN 21.38 MAX 1.165 MAX 0.33 MIN 0.53 MAX 1.27 0.33 MIN 0.49 MAX 0.10 Rev 0.1 / Apr'01 2.09 MIN 3.01 MAX 11.31 MAX 11.05 MIN 9.65 MAX 9.15 MIN 10.29 MAX 3.24 MIN 3.76 MAX MIN 10.03 MIN 0.64 MIN 1.16 MAX GM71V65403C GM71VS65403CL TSOPII 32 PIN Package Dimension 0.40 MIN 0.60 MAX 10.16 11.56 MIN 0~5 1.15 MAX 0.42 0.08 0.40 0.06 1.27 0.10 Dimension including the plating thickness Base material dimension Rev 0.1 / Apr'01 0.08 MIN 0.18 MAX 0.145 0.05 0.125 0.04 0.80 0.68 1.20 MAX NORMAL TYPE Unit: mm 11.96 MAX O 20.95 MIN 21.35 MAX