GM71VS65403CL
16,777,216 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
Features
* 16,777,216 Words x 4 Bit
* Extended Data Out (EDO) Mode Capability
* Fast Access Time & Cycle Time
*Power dissipation
- Active : 504mW/468mW(MAX)
- Standby : 1.8 mW ( CMOS level : MAX )
0.54mW ( L-Version : MAX)
*EDO page mode capability
*Access time : 50ns/60ns (max)
*Refresh cycles
- RAS only Refresh
4096 cycles/64 ms (GM71V65403C)
4096 cycles/128ms (GM71VS65403CL)(L_Version)
*CBR & Hidden Refresh
4096 cycles/64 ms (GM71V65403C)
4096 cycles/128 ms (GM71VS65403CL)( L-Version )
*4 variations of refresh
-RAS-only refresh
-CAS-before-RAS refresh
-Hidden refresh
-Self refresh (L-Version)
*Single Power Supply of 3.3V+/-10 % with a built-in VBB generator
*Battery Back Up Operation ( L-Version )
(Unit: ns)
Pin Configuration
The GM71V(S)65403C/CL is the new generation
dynamic RAM organized 16,777,216 words by 4bits.
The GM71V(S)65403C/CL utilizes advanced CMOS
Silicon Gate Process Technology as well as
advanced circuit techniques for wide operating
margins, both internally and to the system user.
System oriented features include single power supply
of 3.3V+/-10% tolerance, direct interfacing
capability with high performance logic families such
as Schottky TTL.
The GM71V(S)65403C/CL offers Extended Data
Out(EDO) Mode as a high speed access mode.
GM71V(S)65403C/CL-5
GM71V(S)65403C/CL-6
tRAC tAA tRC tHPC
50
60
25
30
84
104
20
25
13
15
tCAC
32 SOJ / TSOP II
GM71V65403C
NC
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
IO0
IO1
NC
NC
VCC
/WE
/RAS
A0
A1
A2
A3
A4
A5
VCC
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VSS
A6
A7
A8
A9
A10
A11
NC
/OE
/CAS
VSS
IO2
IO3
VSS
NC
NC
Rev 0.1 / Apr’ 01
Pin Description
Pin Function Pin Function
A0-A11
A0-A11
RAS
CAS
WE
VCC
VSS
NC
Address Inputs
Refresh Address Inputs
Row Address Strobe
Column Address Strobe
Write Enable
Power (+3.3V)
Ground
No Connection
Absolute Maximum Ratings*
Symbol Parameter Rating Unit
TSTG
VT
VCC
IOUT
-55 to 125
-0.5 to VCC + 0.5
(MAX ; 4.6V)
-0.5 to 4.6
50
Storage Temperature (Plastic)
Voltage on any Pin Relative to VSS
Voltage on VCC Relative to VSS
Short Circuit Output Current
C
V
V
mA
PT1.0Power Dissipation W
*Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol Parameter Unit
VCC
VIH
VIL
Supply Voltage
Input High Voltage
Input Low Voltage
V
V
V
Max
3.6
Vcc+0.3
0.8
Typ
3.3
-
-
Min
3.0
2.0
-0.3
OE Output Enable
I/O0 - I/O3 Data Input / Output
Ordering Information
Type No. Access Time Package
GM71V(S)65403C/CLJ-5
GM71V(S)65403C/CLJ-66 50ns
60ns
400 Mil
32Pin
Plastic SOJ
GM71V(S)65403C/CLT-5
GM71V(S)65403C/CLT-6 50ns
60ns
400 Mil
32Pin
Plastic TSOP II
Notes
1,2
1
1
VSS Supply Voltage V
0
00 2
TA70Ambient Temperature under Bias C
-0
GM71VS65403CL
GM71V65403C
Rev 0.1 / Apr’ 01
DC Electrical Characteristics: (VCC = 3.3V+/-10%, TA = 0 ~ 70C)
Symbol Parameter Note
VOH
VOL
Output Level
Output Level Voltage (IOUT = -2mA)
Unit
V
V
Max
VCC
0.4
Min
2.4
0
Output Level
Output Level Voltage (IOUT = 2mA)
ICC1 140-
Operating Current (tRC = tRC min) 50ns mA
60ns 130-
ICC2 mA
Standby Current (TTL interface)
Power Supply Standby Current
(RAS, CAS= VIH, DOUT = High-Z)
2-
ICC3 mA
RAS-Only Refresh Current
( tRC = tRC min)
ICC4 mA
Extended Data Out page Mode Current
(RAS = VIL, CAS, Address Cycling: tHPC = tHPC min)
-50ns
60ns -
110-50ns
60ns 100-
ICC6 mA
CAS-before-RAS Refresh Current
(tRC = tRC min) -50ns
60ns -
ICC8 mA
Standby Current (CMOS)
Power Supply Standby Current
RAS = VIH, CAS = VIL , DOUT = Enable 5-
II(L) 5-5
IO(L) 5-5
Input Leakage Current, Any Input
(0V<=VIN<=Vcc)
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<=Vcc)
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, tHPC.
4. VIH>=VCC-0.2V, 0V<=VIL<=0.2V
5. L-Version
140
130
140
130
500
400
Battery Back Up Operating Current(Standby with CBR)
(tRC=31.25us,tRAS=300ns,Dout=High-Z)
Self Refresh Current
(RAS, CAS <=0.2V,Dout=High-Z)
ICC7
ICC9
Standby Current(L_Version) uA300-
uA
mA
CMOS interface
(RAS, CAS>=VCC-0.2V, DOUT = High-Z) 0.5-
-
-
ICC5
1,2
2
1
1,3
4, 5
uA
uA
uA
4
5
GM71VS65403CL
GM71V65403C
Rev 0.1 / Apr’ 01
Symbol Parameter Note
CI1
CI2
CI/O
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-in,Data-Out)
1
1
1, 2
Unit
pF
pF
pF
Max
5
7
7
Typ
-
-
-
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, CAS = VIH to disable DOUT.
Capacitance (VCC = 3.3V+/-10%, TA = 25C)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
AC Characteristics (VCC = 3.3V+/-10%, TA = 0 ~ 70C, Notes 1, 2,19)
Test Conditions
Input rise and fall times : 2ns Output timing reference levels : VOL/VOH = 0.8/2.0V
Input level : VIL/VIH = 0.0/3.0V Output load : 1 TTL gate+CL (100pF)
Input timing reference levels : VIL/VIH = 0.8/2.0V (Including scope and jig)
Symbol Parameter Min
GM71V(S)65403C/CL-5
Max
tRC Random Read or Write Cycle Time
tRP RAS Precharge Time
tRAS RAS Pulse Width
tCAS CAS Pulse Width
tASR Row Address Set-up Time
tRAH Row Address Hold Time
tASC Column Address Set-up Time
tCAH Column Address Hold Time
tRCD RAS to CAS Delay Time
4
tRAD RAS to Column Address Delay Time
3
tRSH RAS Hold Time
tCSH CAS Hold Time
tCRP CAS to RAS Precharge Time
Max Min
84 104
40
60
10
0
10
0
10
14
12
15
40
5
30
50
8
0
8
0
8
12
10
13
35
5-
-
-
25
37
-
-
-
-
10000
-
- -
-
10000
-
-
-
-
45
30
-
-
-
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tTTransitionTime (Rise and Fall) 22 50 50 ns
tODD OE to DIN Delay Time
tDZO OE Delay Time from DIN
tDZC CAS Delay Time from DIN
15
0
0
13
0
0-
-
--
-
-
ns
ns
ns
GM71V(S)65403C/CL-6
tCP CAS Precharge Time 108- - ns
10000 10000
5
6
6
7
tREF Refresh Period -
-64 64 ms
Refresh Period ( L-Version ) -
-128 128 ms
4096
cycles
4096
cycles
GM71VS65403CL
GM71V65403C
Rev 0.1 / Apr’ 01
Read Cycles
Symbol Parameter Min
GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6
MaxMax Min
- -
-
-
0
0
0
30
-
-
0
0
0
25 -
-
-
25
13
50 60
15
30
-
-
-
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
--
tRAC
tCAC
tAA
tRCS
tRCH
tRRH
tRAL
tCAL
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Read Command Set-up Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Column Address to CAS Lead Time
8,9
tOAC Access Time from OE -13 -15 ns
15 -18 -
9,10,17
9,11,17
ns
ns
tRDD
tWDD
RAS to DIN Delay Time
ns
tOFR Output Buffer Turn-off Delay Time from RAS
ns
tWEZ Output Buffer Turn-off Delay Time from WE
13
13
-
-13 -15
13 -15
-15 -
-15 -
13
ns
ns
ns
tCLZ
tOH
tCDD
CAS to Output in Low - Z
Output Data Hold Time
CAS to DIN Delay Time -15 -
ns
ns
tOHR
tOEZ
Output Data Hold Time from RAS
Output Buffer Turn-off Delay Time from OE
nstOFF
0
3
-
-13 15
13 -15
--
-3-
-
-
-
WE to DIN Delay Time
13,21
13
ns
tRCHR Read Command Hold Time from RAS 50 -60 -
nstOHO Output data hold time from OE 3-3-
0
Output Buffer Turn-off Delay Time from CAS
12
9
12
13,21
13
3 3
21
5
21
GM71VS65403CL
GM71V65403C
Rev 0.1 / Apr’ 01
Write Cycles
Read-Modify-Write Cycles
tRWC Read-Modify-Write Cycle Time
tRWD RAS to WE Delay Time
tCWD CAS to WE Delay Time
tAWD Column Address to WE Delay Time
Refresh Cycle
Symbol Parameter Min MaxMax Min
116 140
79
34
49
67
30
42 -
-
-
- -
-
-
-
Unit Notes
ns
ns
ns
ns
Refresh Cycles
tCSR CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
tCHR CAS Hold Time
(CAS-before-RAS Refresh Cycle)
tRPC RAS Precharge to CAS Hold Time
Symbol Parameter Min MaxMax Min
55
--
Unit Notes
ns
810
- -
5 5- -
ns
ns
tOEH OE Hold Time from WE 15
13 --ns
14
GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6
GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6
tWCS Write Command Set-up Time
tWCH Write Command Hold Time
tWP Write Command Pulse Width
tRWL Write Command to RAS Lead Time
tCWL Write Command to CAS Lead Time
tDS Data-in Set-up Time
tDH Data-in Hold Time
Symbol Parameter Min MaxMax Min
00
10
10
10
0
10
8
8
8
0
8-
-
-
-
-
- -
-
-
-
-
-
Unit Notes
ns
ns
ns
ns
ns
ns
ns
--
14
15
15
GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6
15
13
14
14
tWRP WE setup time
(CAS-before-RAS Refresh Cycle) 0 0- - ns
tWRH WE hold time
(CAS-before-RAS Refresh Cycle) 810- - ns
GM71VS65403CL
GM71V65403C
Rev 0.1 / Apr’ 01
Extended Data Out Mode Cycles
tHPC EDO Page Mode Cycle Time
tWPE Write pulse width during CAS Precharge
tRASP EDO Mode RAS Pulse Width
tACP
Symbol Min MaxMax Min
20 25
10
-
-
8
-
-28
100000
-
- -
-
35
Unit Notes
ns
ns
ns
ns
Parameter GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6
Access Time from CAS Precharge
-
RAS Hold Time from CAS Precharge
tCPW EDO Page Mode Read-Modify-Write Cycle
CAS Precharge to WE Delay Time
tHPRWC
28 35
54
68
45
57 -
-
- -
100000
-
ns
ns
ns
-
EDO Read-Modify-Write Cycle Time
tRHCP
tCOL CAS Hold Time Referred OE
tCOP
10
5
8
5-
- -
-
ns
ns
CAS to OE set-up Time
Read Command Hold Time from CAS
Precharge
tDOH Output Data Hold Time from CAS Low
28 35
- - ns
ns
tRCHP
3
3--
20
9,17
Self Refresh Cycles (L_Version)
tRASS RAS Pulse Width(Self-Refresh)
tRPS
Symbol Parameter Min MaxMax Min
100 - -
Unit Notes
GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6
tCHS
100
RAS Precharge Time(Self-Refresh) 90 - - ns
110
CAS Hold Time(Self-Refresh) -50 - - ns
-50
26
26
16
9,22
14
tOEP OE Precharge Time ns
10
8--
Symbol Min MaxMax Min Unit Notes
Parameter GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6
EDO Page Mode Read-Modify-Write cycle
us
GM71VS65403CL
GM71V65403C
Rev 0.1 / Apr’ 01
Notes:
AC measurements assume tT = 2ns.
AC initial pause of 200 us is required after power up followed by a minimum of eight
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh)
Operation with the t RCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only: if t RCD is greater than the specified t RCD(max) limit, then access time is
controlled exclusively by tCAC.
Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only: if t RAD is greater than the specified t RAD(max) limit, then access time is
controlled exclusively by tAA.
Either tOED or tCDD must be satisfied.
Either tDZO or tDZC must be satisfied.
VIH(min) and V IL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL (max).
Assumes that t RCD ≤ tRCD(max) and t RAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
Assumes that tRCD ≥ tRCD(max) and tRCD + tCAC(max) ≥tRAD + tAA(max).
Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC(max) ≤tRAD + tAA(max).
Either tRCH or tRRH must be satisfied for a read cycles.
tOFF(max), tOEZ(max), tOFR(max) and t WEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
tWCS, tRWD, tCWD, tAWD, and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only: if t WCS ≥ tWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
tRWD ≥ tRWD(min), tCWD ≥tCWD(min), tAWD ≥ tAWD(min) and t CPW≥ tCPW(min), the cycle is a read-
modify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
tDS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in
delayed write or read-modify-write cycles.
tRASP defines RAS pulse width in extended data out mode cycles.
Access time is determined by the longest among tAA, tCAC and tCPA.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
When output buffers are enabled once, sustain the low impedance state until valid daa is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
GM71VS65403CL
GM71V65403C
Rev 0.1 / Apr’ 01
tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t HPC(tCAS + tCP + 2tT) becomes greater than the
specified tHPC(min) value.
Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF.
tDOH defines the time at which the output level go cross. VOL =0.8V, VOH=2.0V of output timing
reference level.
Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
ms period on the condition a and b below.
a. Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us
after exiting from self refresh mode.
In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
For L_Version, it is available to apply each 128 ms and 31.2 us instead of 64ms and 15.6us at
note 23.
At tRASS >100 us , self refresh mode is activated, and not active at tRASS <10us It is undefined
within the range of 10 us <tRASS <100 us . for tRASS >10 us , it is necessary to satisfy tRPS.
XXX: H or L ( H : VIH(min)<=
VIN<=
VIH (max), L: V
IH(min)<=
VIN<=
VIH(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
20.
21.
22.
23.
24.
25.
26.
27.
The value of CAS cycle time of mixed EDO page mode is shown in
EDO page mode mix cycle (1) and (2).
GM71VS65403CL
GM71V65403C
Rev 0.1 / Apr’ 01
SOJ 32 pin PKG Dimension
Unit: mm
21.38 MAX
20.95 MIN
MIN
0.53 MAX
0.33 MIN
1.27
10.29 MAX
0.49 MAX
0.33 MIN
9.15 MIN
9.65 MAX
0.64 MIN
2.09 MIN
11.05 MIN
11.31 MAX
10.03 MIN
3.01 MAX
1.16 MAX
3.76 MAX
3.24 MIN
1.165 MAX
0.10
GM71VS65403CL
GM71V65403C
Rev 0.1 / Apr’ 01
TSOPII 32 PIN Package Dimension
Unit: mm
NORMAL TYPE
10.16
21.35 MAX
20.95 MIN
0.42 0.08 1.27
0.18 MAX
0.08 MIN
0.60 MAX
0.40 MIN
0.125 0.04
0 ~ 5O
0.145 0.05
1.15 MAX
0.40 0.06
1.20 MAX
0.10
11.96 MAX
11.56 MIN
0.80
0.68
Dimension including the plating thickness
Base material dimension
GM71VS65403CL
GM71V65403C
Rev 0.1 / Apr’ 01
