Publicati on Date : October 2013
1
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
OUTLINE
MAIN FUNCTION AND R ATINGS
3 phase DC/AC inverter
500V / 5A (MOSFET)
N-side MOSFET open source
Built-in boot s t rap dio des with current limiting resistor
APPLICATION
AC 100~240Vrms(DC voltage:400V or below) class
low power motor control
TYPE NAME
PSM05S93E5-A
With over temperatur e protection
INTEGRAT E D DRIVE, PROTE CTION AND S Y S TEM CONTROL FUNCTIONS
● For P-side : Drive circuit, High voltage high-speed level shif ting , Control supply under-voltage (UV) protection
● For N-side : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC),
Over temperature protection (OT)
● Fault signal ing : Corresponding to SC fault (N-side MOSFET), UV fau lt (N-side supply) and OT fault
● Input interf ac e : 3, 5V line, Schmitt trigger receiver circuit (High Active)
●UL Recognized : UL1557 File E323585
INTERNAL CIRCUIT
V
UFB
(2)
V
VFB
(3)
V
WFB
(4)
W(21)
P
W
P
(7)
U
P
(5)
V
P1
(8)
V
NC
(9)
U
N
(10)
V
N
(11)
W
N
(12)
F
O
(14)
V
N1
(13)
NC
NW(18)
CIN(15)
NU(20)
NV(19)
V(22)
U(23)
P(24)
LVIC
MOSFET1
MOSFET2
MOSFET3
HVIC
MOSFET4
MOSFET5
MOSFET6
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Publicati on Date : O ct ober 2013
2
MAXIMUM RATINGS (Tch = 25°C, unl ess otherwise noted)
INVERTER PART
Symbol
Parameter
Condition
Ratings
Unit
VDD
Supply voltage
Applied between P-NU,NV,NW
400
V
VDD(surge) Suppl y voltage (surge) Appl i ed bet ween P-NU,NV,NW 450 V
VDSS Drain-source voltage 500 V
±ID Each MOSFET drain current TC= 25°C 5 A
±IDP
Each MOSFET drain current (peak)
TC= 25°C, less than 1ms
10
A
PD
Drain dissipation
TC= 25°C, per 1 chip
35.7
W
Tch
Channel temperature
(Note 1)
-20~+150
°C
Note1: T he maximum junction tem perature r ating of built-in power chips is 150°C(@Tc≤100°C).However, to ensure safe operation of DIPIPM, the average
channel temperature should be limited to Tch(Ave)≤125°C (@Tc≤100°C).
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
Ratings
Unit
V
D
Control supply voltage
Applied between
V
P1
-V
NC
, V
N1
-V
NC
20
V
VDB Control supply voltage Applied bet ween
V
UFB-U, VVFB-V, VWFB-W 20 V
VIN Input voltage Applied between
U
P, VP, WP-VPC, UN, VN, WN-VNC -0.5~VD+0.5 V
VFO
Fault output supply voltage
Applied between
FO-VNC
-0.5~VD+0.5
V
IFO
Fault output current
Sink current at FO terminal
1
mA
VSC
Current sensing input voltage
Applied between CIN-VNC
-0.5~VD+0.5
V
TOTAL SYSTEM
Symbol
Parameter
Condition
Ratings
Unit
VDD(PROT)
Self protection supply voltage limit
(Short circuit protection capability)
V
D
= 13.5~16.5V, Invert er Part
Tch = 125°C, non-repetitive, l ess than 2μs
400 V
TC Module case operation temperature Measurem ent point of Tc is provided in Fig.1 -20~+100 °C
Tstg Storage temperature -40~+125 °C
Viso Isol ation vol tage
60Hz, Sinusoidal, AC 1 min, between connected all pins
and heat sink plate
1500 Vrms
Fig. 1: TC ME ASU R EMENT POINT
THERMAL RESISTANCE
Symbol Parameter Condition
Limits
Unit
Min.
Typ.
Max.
Rth(ch-c)Q
Junction to case thermal resistance (Note2)
1/6 module
-
-
2.8
K/W
Note 2: Grease with good t hermal c onductivit y and long -term endurance should be applied evenly with about +100μm~+200μm on the contacting surface of
DIPIPM a nd he at sink . The c ontact ing t hermal resis tance betwee n D IPIPM ca se and h eat s ink R th(c-f) i s dete rmine d b y the thick n ess and t he the rmal
conductivity of the applied grease. For ref e ren ce, Rt h (c-f) is about 0.3K/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m•k).
Control terminals
DIPIPM
Tc point
IGBT chip position
Heat sink side
11.6mm
3mm
Power terminals
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Publicati on Date : O ct ober 2013
3
ELECTRICAL CHARACTERISTICS
(Tch = 25°C, unless otherwise noted)
INVERTER PART
Symbol Parameter Condition Limits Unit
Min.
Typ.
Max.
VDS(on) Drain-source on-state
resistance VD=VDB = 15V, VIN= 5V, ID= 5A
Tch= 25°C
-
0.60
0.80
Ω
Tch= 125°C
-
1.30
1.70
VSD
Source-drain voltage drop
VIN= 0V, -ID= 5A
-
0.90
1.30
V
ton
Switching times VDD= 300V, VD= VDB= 15V
ID= 5A, Tch= 125°C, VIN= 0↔5V
Inductive Load (upper-lower arm)
0.65
1.15
1.65
μs
tC(on) - 0.35 0.55 μs
toff - 1.00 1.50 μs
tC(off)
-
0.10
0.20
μs
trr
-
0.25
-
μs
IDSS Drain-source cut-off
current VDS=VDSS
Tch= 25°C
-
-
1
mA
Tch= 125°C
-
-
10
CONTROL (PROTECTION) PART
Symbol Parameter Condition
Limits
Unit
Min.
Typ.
Max.
ID Circuit current Total of VP1-VNC, VN1-VNC
VD=15V, VIN=0V
-
-
2.80
mA
VD=15V, VIN=5V
-
-
2.80
IDB Each part of VUFB-U,
VVFB-V, VWFB-W VD=VDB=15V, VIN=0V - - 0.10
VD=VDB=15V, VIN=5V - - 0.10
VSC(ref)
Short circuit trip level
VD = 15V
(Note 3)
0.43
0.48
0.53
V
UVDBt
P-side Control supply
under-voltage protection(UV ) Tch ≤125°C
Trip level
7.0
10.0
12.0
V
UVDBr
Reset level
7.0
10.0
12.0
V
UVDt
N-side Control supply
under-voltage protection(UV )
Trip level
10.3
-
12.5
V
UV
Dr
Reset level
10.8
-
13.0
V
OTt Over temperature protecti on
(OT) (Note4) VD = 15V Trip level 100 120 140 °C
OTrh Detect LVIC temperature Hysteresis of tr ip -reset - 10 - °C
VFOH
Fault output voltage
VSC = 0V, FO terminal pulled up to 5V by 10kΩ
4.9
-
-
V
VFOL
VSC = 1V, IFO = 1mA
-
-
0.95
V
tFO
Fault output pulse width
(Note 5)
20
-
-
μs
IIN
Input current
VIN = 5V
0.70
1.00
1.50
mA
Vth(on) ON threshold voltage
Applied between UP, VP, WP, UN, VN, WN-VNC
- 2.10 2.60
V
Vth(off)
OFF threshold voltage
0.80
1.30
-
Vth(hys)
ON/OFF threshol d
hysteresis voltage
0.35 0.65 -
VF
Bootstrap Di forward voltage
I
F
=10mA including voltage drop by limiting resistor
(Note 6)
1.1
1.7
2.3
V
R
Built-in limiting resistance
Included in bootstrap Di 80 100 120 Ω
Note 3 : SC protection works for N-side only. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating.
4 : When the LV IC temperat ure e xceeds OT t rip tem peratu re level (OTt), OT protection work s and Fo out puts. In that case if the he at sink dropped off or fixed
loosely, don't reuse that DIPIPM. (There is a possibility that channel temper ature of power chips exceeded maximum Tch(150°C).
5 : Fault s ignal Fo out puts when SC, UV or OT prot ection wo rks. Fo pulse width is differe nt fo r eac h prot ection modes. At SC failure, Fo puls e width is a fixed
width (=minimum 20μs), but at UV or OT f ailur e, Fo out pu ts continuously until recovering from UV or OT state. (But minimum Fo pulse width is 20μs.)
6 : The characteristics of bootstrap Di is described i n Fig.2.
Fig. 2 Characteristics of bootstrap Di VF-IF curve (@Ta=25°C) inc l uding voltage drop by limiting resistor (Right chart is enlarged chart.)
0
20
40
60
80
100
120
140
160
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V
F
[V]
I
F
[mA]
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
V
F
[V]
I
F
[mA]
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Publicati on Date : O ct ober 2013
4
MECHANICAL CHARACTERI S TICS AND RATINGS
Parameter Condition
Limits
Unit
Min.
Typ.
Max.
Mounting torque Mounting sc rew : M3 (Note 8) Recommended 0.69N·m 0.59 0.69 0.78 N·m
Terminal pulling strength
Control termi nal: Load 4.9N
Power terminal: Load 9.8N
EIAJ-ED-4701 10 - - s
Terminal bending strengt h
Control termi nal: Load 2.45N
Power terminal: Load 4.9N
90deg. bend
EIAJ-ED-4701 2 - - times
Weight - 8.5 - g
Heat-sink flatness
(Note 9)
-50
-
100
μm
Note 8: Plain washers (ISO 7089~7094) are recommended.
Note 9: Measurement point of heat sink flatness
RECOMMENDED OPERATION CONDITIONS
Symbol Parameter Condition
Limits
Unit
Min. Typ. Max.
VCC Supply voltage Applied between P-NU, NV, NW 0 300 400 V
VD Control supply voltage Applied between VP1-VNC, VN1-VNC 13.5 15.0 16.5 V
VDB
Control supply voltage
Applied between VUFB-U, VVFB-V, VWFB-W
13.0
15.0
18.5
V
ΔVD, ΔVDB
Control supply variat i on
-1
-
+1
V/μs
tdead
Arm shoot-through blocking time
For each input signal
1.0
-
-
μs
fPWM
PWM input frequency
TC ≤ 100°C, Tch ≤ 125°C
-
-
20
kHz
IO Allowable r.m.s . c urrent VDD = 300V, VD = 15V, P.F = 0.8,
Sinusoidal PWM
TC ≤ 100°C, Tch ≤ 125°C (Note10)
fPWM= 5kHz - - 2.5 Arms
fPWM= 1 5kH z - - 2.0
PWIN(on) Minimum input pulse width (Note 11) 0.7 - - μs
PWIN(off) 0.7 - -
VNC
VNC variation
Between VNC-NU, NV, NW (incl uding surge)
-5.0
-
+5.0
V
Tch
Channel temperature
-20
-
+125
°C
Note 10: Allowable r.m.s. current depends on the actual application conditions.
11: DIPIPM might not make response if the input signal pulse width is less than PWIN(on), PWIN(off).
4.6mm
-
+
Heat sink side
Heat sink side
Measurement position
17.5mm
+
-
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Publicati on Date : O ct ober 2013
5
Fig. 3 Timing Charts of The DIPIPM Protective Functions
[A] Short-Circuit Protection (N-side only with the external shunt resistor and RC filter)
a1. Normal operation: MOSFET ON and outputs current.
a2. Short circuit current detecti on (SC tri gger)
(It is recommended to set RC time constant 1.5~2.0μs so that MOSFET shut down within 2.0μs when SC.)
a3. All N -side MOSFET's gates are hard int errupted.
a4. All N -side MOSFETs turn OFF.
a5. FO outputs for tFo=minimum 20μs.
a6. Input = “L”: MOSFET OFF
a7. Fo finishes output, but MOSFETs don't turn on until inputting next ON signal (LH).
(MOSFET of each phase can return to normal state by inputting ON signal to each phase.)
a8. Normal operation: MOSFET ON and outputs current.
[B] Under-Voltage Protection (N-side, UVD)
b1. Control supply voltage V D exceeds under voltage reset level (UVDr), but MOSFET turns ON by next ON signal (LH).
(MOSFET of each phase can return to normal state by inputting ON signal to each phase.)
b2. Normal operation: MOSFET ON and outputs current.
b3. VD level drops to u nder voltage trip level. (UVDt).
b4. All N -side MOSFETs turn OFF in spite of control input condition.
b5. Fo outputs for tFo=minimum 20μs, but output is extended during VD keeps below UVDr.
b6. VD level reaches UVDr.
b7. Normal operation: MOSFET ON and outputs current.
Lower-side cont rol
input
Protection circuit state
Internal gate
Output current I
D
Sense voltage of
the
shunt resistor
Error output Fo
SC trip current level
a2
SET
RESET
SC reference voltage
a1
a3
a6
a7
a4
a8
a5
Delay by RC filtering
UVDr
RESET
SET
RESET
UV
Dt
b1
b2
b3
b4
b6
b7
b5
Control input
Protection circuit state
Control supply voltage V
D
Output current I
D
Error output Fo
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PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Publicati on Date : O ct ober 2013
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[C] Under-Voltage Protection (P-side, UVDB)
c1. Control supply voltage VDB rises. A fter the voltage reaches under voltage reset level UVDBr, MOSFET turns on by next ON signal (LH).
c2. Normal operation: MOSFET ON and outputs current.
c3. VDB level drops t o under voltage trip level (UVDBt).
c4. MOSFET of the corres pond phase only turns OFF in spit e of control input signal level, but there is no FO signal output.
c5. VDB level reaches UVDBr.
c6. Normal operati on: MOSFET ON and outputs current.
[D] Over Tempera ture Protection (N-side, Detecting LVIC temperature)
d1. Normal operation: MOSFET ON and outputs current.
d2. LVIC temperature exceeds over temperature trip l evel(OTt).
d3. All N-side MOSFETs turn OFF in spite of control input condition.
d4. Fo outputs for tFo=minimum 20μs, but output is extended during LVIC temperature keeps over OTt.
d5. LVIC temperature drops to over temperat ure reset level.
d6. Normal operation: MOSFET turns on by next ON signal (LH).
(MOSFET of each phase can return to normal state by inputting ON signal to each phase.)
Control input
Protection circuit state
Control supply voltage V
DB
Output current I
D
Error output Fo
UV
DBr
RESET
SET
RESET
UV
DBt
Keep High-level (no fault output)
c1
c2
c3
c4
c5
c6
SET
RESET
OT
t
d1
d2
d3
d5
d6
d4
OT
t
- OT
rh
Control input
Protection circuit state
Temperature of LVIC
Output current I
D
Error output Fo
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Publicati on Date : O ct ober 2013
7
Fig. 4 Example of Applic ation Circuit
(1) If contr ol GND is connect ed w ith power G N D by commo n broad pattern, i t may cause malf uncti on by power GND fluct uation.
It is recom m ended to connect control G N D and power G ND at onl y a point N1 ( near t he termi nal of s hunt res istor).
(2) It is rec om mended to inser t a Zener diode D1(24V/1W) between each pair of control s upply term inals to prevent s urge dest ruct ion.
(3) To prevent s urge dest ruct ion, the wiring betw een the smoothing capaci tor and t he P, N1 t erminal s shoul d be as short as possibl e.
Generally a 0.1-0.22μF snubber capacitor C 3 between the P-N1 terminals is r ecommended.
(4) R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type.
The time constant R1C 4 shoul d be set so that SC current is shut down within 2μs. (1.5μs~2μs is general value.) SC interrupting time
might vary wit h the wiring pattern, so t he enough eval uation on the real system is nec essary.
(5) To prevent mal funct ion, the w iring of A, B, C should be as short as possible.
(6) The point D at whi c h the wi r ing to CI N fi l ter i s divi ded s hould be near t he terminal of s hunt r es is tor. NU, NV, NW term inal s should be
connected at ne ar NU, NV, NW terminals.
(7) All capaci tors shoul d be mounte d as clos e to the termi nals as possible. (C1: good temper ature, frequenc y characterist ic electrolytic
type and C2:0.2 2μ-2μF, good temper ature, frequenc y and DC bias charac teristic ceram ic type are recommended.)
(8) Input drive is High-active type. There is a minimum 3.3kΩ pull-down resistor in the input circuit of IC. To prevent malfunction, the
wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on
and turn-off thres hold voltage.
(9) Fo output is open drain type. It should be pul led up to MC U or control power supply ( e.g. 5V,15V) by a r esistor t hat makes IFo up to
1mA. (IFO is estimated roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to
5V, 10k Ω (5kΩ or more) is recommended.)
(10) Thanks to built-in HVIC , direct coupling to MC U witho ut any opt o-coupler or tr ansfor m er isolation is possible.
(11) Two V NC ter minals (9 & 16 pin) are connec ted insi de DIPIPM, please connect either one t o the 15V power s upply GND outsi de and
leave another one open.
(12) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation.
To avoid s uch probl em , line ripple voltage should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
(13) For D IPIPM, i t isn't r ecommende d to drive same load by parallel connec tion with other phase MOSFET or other DIPIPM.
Long GND wiring might generate
noise to input signal and cause
MOSFET malfunction.
Long wiring might cause SC level
fluctuation and malfunction.
Long wiring might cause
short circuit failure
Bootstrap negat i ve electrodes
should be connected to U,V,W
terminals direct l y and separated
from the main output wires
Power GND wiring
Control GND wiring
D1
+
+
MCU
C2
15V VD
M
C4
R1
Shunt
resistor
N1
B
C
5V
A
C2
V
UFB
(2)
V
VFB
(3)
V
WFB
(4)
+
U
N
(10)
V
N
(11)
W
N
(12)
Fo(14)
V
N1
(13)
V
NC
(16)
P(24)
U(23)
W(21)
LVIC
V(22)
V
P
(6)
W
P
(7)
U
P
(5)
V
P1
(8)
CIN(15)
MOSFET1
MOSFET2
MOSFET3
C1
C1
C2
+
D
D1
V
NC
(9)
C3
HVIC
NW(18)
MOSFET4
MOSFET5
MOSFET6
NU(20)
NV(19)
+
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PSM05S93E5-A
TRANSFER MOLDING TYPE
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Fig. 5 MCU I/O Interface Circuit
Fig. 6 Pattern Wiring Around the Shunt Resistor
Fig. 7 Pattern Wiring Around the Shunt Resistor (for the case of open source)
When DIPIPM is operated with three shunt resistors, voltage of each shunt resistor cannot be input to CIN terminal directly. In that case, it is necessary to use
the exter nal pr otection circ uit as below.
(1) It is necessary to set the time constant RfCf of external comparator input so that MOSFET stops within 2μs when short circuit occurs.
SC interrupting time might vary with the wiring pattern, comparator speed and so on.
(2) It is recommended for the threshold voltage Vref to set to the same rating of short circuit trip level (Vsc(ref): typ. 0.48V).
(3) Sel ect the ext er nal shunt resis tance so that SC trip-level is less than sp eci fie d val ue (=1.7 times of rating current).
(4) To avoid malfunction, the wiring A, B, C should be as short as possible.
(5) The point D at which the wiring to comparator is divided should be close to the terminal of shunt resistor.
(6) OR output high level wh en pr ote cti o n works should be over 0.53V (=maximum Vsc(ref) rating).
UP,VP,WP,UN,VN,WN
Fo
VNC(Logic)
DIPIPM
MCU
10kΩ
5V line
3.3kΩ(min)
Note)
Design fo r input RC filter depe nds on PW M control schem e used
in the applicati on and wiring impedance of the printed circuit board.
DIPIPM input signal interface integrates a minimum 3.3kΩ
pull-down resistor. Therefore, when inserting RC filter, it is
necessary to satisfy turn-on threshold voltage requirement.
Fo output is open drain type. It should be pulled up to control
power supply (e.g. 5V, 15V) with a resistor that makes Fo sink
current IFo 1mA or less. In the case of pulled up to 5V supply, 10kΩ
（5kΩ or more） is recommended.
Wiring Inductance should be less than 10nH.
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
NU, NV, NW should be connected
each other at near terminals.
N1
V
NC
NU
NV
NW
DIPIPM
V
NC
GND wiring fro m V
NC
should
be
connected close to the
terminal of shunt res istor.
DIPIPM
NU
NV
NW
N1
Low inductance shunt resistor like surface mounted (SMD) type is recommended.
GND wiring fro m V
NC
should
be
connected close to the
terminal of shunt res istor.
Shunt
resistors
Each wiring Inductance should be less than 10nH.
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
Comparators
(Open collector output type)
External protection circuit
OR output
-
Vref
+
Vref
Vref
Shunt
resistors
Rf
Cf
5V
B
A
C
D
N1
-
+
-
+
V
U
W
DIPIPM
P
N-side MO SFETs
P-sid e MOSFETs
Drive circuit
VNC
NW
Drive circuit
CIN
NV
NU
Protection circuit
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
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9
Fig. 8 Package Outlines
Long terminal type (PSM05S93E5-A) Dimensions in mm
1) 9 & 16 pins (VNC) are connected inside DIPIPM, please connect either one to the control power supply GND outside and leave another one open.
QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries.
TERMINAL CODE
1-A
NC(VNC)
1-B
NC(VP1)
2
VUFB
3
VVFB
4
VWFB
5
UP
6
VP
7
WP
8
VP1
9
VNC *1
10
UN
11
VN
12
WN
13
VN1
14
Fo
15
CIN
16
VNC *1
17
NC
18
NW
19
NV
20
NU
21
W
22
V
23
U
24
P
25
NC
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Publicati on Date : O ct ober 2013
10
Revision Record
Rev. Date Page Revised contents
1
10/15/2013
-
New
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
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Publicati on Date : O ct ober 2013
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© 2013 MITSUBISHI ELECTRIC CORPORATION. ALL RIGHTS RESERVED.
DIPIPM and CSTBT are registered trademarks of MITSUBISHI ELECTRIC CORPORATION.
Keep saf ety fir s t in your circ uit des igns!
Mitsu bis hi Electri c Corp oration put s the max imu m ef fort into ma king se micond uct or product s better and mor e
reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors
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Notes r e gar ding these mat er ia ls
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