© Freescale Semiconductor, Inc., 2001–2007. All rights reserved.
Freescale Semicondu ctor
Te chni cal Data
The MPC8245 combines a PowerPC™ MPC603e processor
core built on Power Architecture™ technol ogy with a PC I
bridge so that system designers can rapidly design systems
using peripherals designed for PCI and the other standard
interfaces. Also, a high-performance m emory controller
supports various types of ROM and SDRAM. The MPC8245
is the second of a family of products that provide
system-level support for industry-standard interfaces with an
MPC603e processor core.
This hardware speci f icat i on descr ibes per t inen t electri cal
and physical characteristics of the MPC8245. For functional
characteristics of the processor, refer to the MPC8245
Integrated Proces sor Reference Manual (MPC 8245UM).
For published errata or updates to this document, visit the
website listed on the back cover of the document.
1Overview
The MPC8245 integrated processor is composed of a
peripheral logic block and a 32-bit super scalar MPC603e
core, as shown in Figure 1.
MPC8245EC
Rev. 10, 08/2007
Contents
1. Ove rview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. El ectrical and Th er mal Character istics . . . . . . . . . . . . 5
5. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 31
6. PLL Configura tions . . . . . . . . . . . . . . . . . . . . . . . . . 39
7. System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8. Doc ument Revision History . . . . . . . . . . . . . . . . . . . 56
9. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 62
MPC8245 Integrated Processor
Hardware Specifications
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
2Freescale Semiconductor
Overview
Figure 1. MPC8245 Block Diagra m
Peripheral Logic Bus
Instruction Unit
System Integer Load/Store Floating-
Data Instruction
16-Kbyte 16-Kbyte
Processor Core Block
Processor
PLL
(64-Bi t) Two-Ins truction Fetch
(64-Bit) Two-Instruction Dispatch
64-Bit
Branch
Processing
Unit
(BPU)
MPC8245
Register
Unit
(SRU)
Unit
(IU) Unit
(LSU) Point
Unit
(FPU)
Data
Cache Instruction
Cache
MMUMMU
Additional Features:
• Prog I/O with W atchpoint
• JTAG/COP Interface
• Po wer Management
Address
Translator
DLL
Fanout
Buffers
PCI
Arbiter
Message
Unit
(with I2O)
I2C
Controller
DMA
Controller
Interrupt
Controller/
PIC
Timers
PCI Bus
Inte r fa c e U n it
Memory
Controller
Data Path
ECC Controller
Central
Control
Unit
32-Bit OSC_IN
Five
Request/Grant Pairs
I2C
5 IRQs/
Peripheral Logic Block
Peripheral Logic
PLL
PCI Bus
Data (64-Bit)
Address Data Bus
(32- or 64-Bit)
Memory/ROM/
PortX Cont rol /Address
PCI In terfac e
Clocks
16 Serial
Interrupts Configuration
Registers
(32-Bit) with 8-Bit Pari ty
or ECC
PCI_SYNC_IN
SDRAM_SYNC_IN
Watchpoint
Facility
DUART
Performance
Monitor
SDRAM Clocks
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 3
Features
The peripheral logic integrates a PCI br idge, dual uni ver sal asynchr onous receiver/transmitter (DUART),
memory controlle r, DMA controller, PIC interrupt controlle r, a message unit (and I2O i nt erfac e), and an
I2C controller. The processor core is a full-f eatur ed, high-performance processor with floating-point
support, memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and power
management features. The integration reduces the overall packaging re quirements and the numbe r of
discrete devices required for an embedded system.
An internal peripheral logic bus interfaces the processor core to the peripheral logic. The core can operate
at a variety of frequencies, allowing the des igner to tr ade off performance for power consumption. The
processor core is clocked f rom a separate PLL that is re fere nce d to the periphe ral logic PLL . This allows
the microprocessor and the peripheral logic block to operat e at different fre que ncie s while maintaining a
synchronous bus interface. The interface us es a 64- or 32-bit data bus (depending on memory data bus
width) and a 32-bit address bus al ong with control signals that enable the interface between the pr ocessor
and peripheral logic to be optimized for performance . PCI accesses to the MPC8245 memory space are
passed to the processor bus for snooping when snoop mode is enabled.
The general-purpose proces sor core and peripheral logi c serve a variety of embedded applications. The
MPC8245 can be used as either a PCI host or PCI agent controller.
2Features
Major features of the MPC8245 are as follows:
• Proce ssor core
— High-performance, superscalar processor core
— Integer unit (I U), floating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system regi ster unit (SRU), and branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 caches—Entire cache or on a per -way basis up to three of four ways
— Dynamic power management: 60x nap, doze, and sleep modes
• Peripheral logic
— Peripheral logic bus
– Various operating fre quencies and bus divide r ratios
– 32-bit address bus, 64-bit data bus
– Full memory coherency
– Decoupled address and data buses f or pipelining of peripheral logic bus accesses
– Store gathering on peripheral logic bus-to-PCI wri tes
— Memory interface
– Up to 2 Gbytes of SDRAM memory
– High-bandwidth data bus (32- or 64-bit) to SDRA M
– Programmable timing supporting SDRAM
– One to eight banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
4Freescale Semiconductor
Features
– Write buff ering for PCI and processor accesses
– No r mal parity, rea d -mod ify-write (RMW), or ECC
– Data-path buffer ing between memory interface and processor
– Low-voltage TTL logic (LVTTL) interfaces
– 272 Mbytes of base and extended ROM/Flash/PortX s pace
– Base ROM space for 8-bit data path or s ame size as the SDR AM data path (32- or 64-bit)
– Extended ROM space for 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data path
– PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects
— 32-bit PCI interfac e
– Operates up to 66 MHz
– PCI 2.2-compatible
– PCI 5.0-V tolerance
– Dual address cycle (DA C) for 64-bit PCI addressi ng (master only)
– Accesses to PCI memory, I/O, and configuration spaces
– Selectable big- or little-endian operation
– Store gathering of processor-to-PCI write and PCI- to-memory write accesses
– Memory prefetching of P CI read accesses
– Selectable hardware-enfor ced coher ency
– PCI bus arbitration unit (five request/grant pairs)
– PCI agent mode capability
– Address translation with two inbound and outbound units (ATU)
– Internal configuration regist ers accessible from PCI
— Two-channel integrated DMA controller (writes to ROM/PortX not supported)
– Direct mode or chaining mode (automatic linking of DMA transfers)
– Scatter gathering—Read or write discontinuous memory
– 64-byte tra n sfer queue per channel
– Interrupt on completed segment, chain, and error
– Local- to-loca l memory
– PCI -t o-PCI m e m ory
– Local-to-PCI memory
– PCI memory- to-loc a l memory
— Message unit
– Two doorbell regist ers
– Two inbound and two outbound messaging re gisters
–I
2O mess age in terface
—I
2C controller with full master/slave support that accepts broadcast messages
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 5
General Parameters
— Programmable interrupt controller ( PIC)
– Five hardware interr upts (IRQs) or 16 serial interrupts
– Four programmable timers with c ascade
— Two (dual) universal asynchr onous receiver/transmitters (UAR Ts)
— Integrated PCI bus and SDRAM clock generation
— Programmable PCI bus and memory interface output drivers
• Syste m-level performance monitor fac ility
• Debug features
— Memory attribute and PC I attribute signals
— Debug addr ess signals
—MIV
signal—Marks valid address and dat a bus cycles on the memory bus
— Programmable input and output signals with watchpoint capability
— Error inje ction/capture on data path
— IEEE Std 1149.1® (JTAG)/test interfac e
3 General Parameters
The following list summarizes the gene ral parameters of the MPC8245:
Technology 0.25-µm C MOS, five-layer metal
Die size 49.2 mm2
Transistor count 4.5 million
Logic design Fully-static
Packages Surface-mount 352 tape ba ll grid array (TBGA)
Core power s upply 1.7 V to 2.1 V DC for 266 and 300 MHz with the condition that the us age
is “nominal” ± 100 mV where “ nominal” is 1.8/1. 9/2.0 volts.
1.9 V to 2.2 V DC for 333 and 350 MHz with the condition that the us age
is “nominal” ± 100 mV where “nominal” is 2.0/2.1 volts.
See Table 2 f or details of r ecom mended operating condi tions)
I/O power supply 3.0- to 3.6-V DC
4 Electrical and Thermal Characteristics
This section provides th e AC and DC electrical speci f icat ions and the rmal char acter i stics f or the
MPC8245.
4.1 DC Electri cal Ch aracteristics
This section cover s ratings, conditions, and other DC electrical characteristics.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
6Freescale Semiconductor
Electrical and Thermal Characteristics
4.1.1 Absolute Maximum Ratings
The tables in this section describe the MPC8245 DC electrical ch aracteristics. Table 1 provides the
absolute maximum ratings.
4.1.2 Recomme nded Operating Conditions
Table 2 provides the recommended oper ating conditions for the MPC8245. Some voltage values do not
apply to the 400-MHz parts. For details, refer to the hardware specifications addendum
MPC8245ECSO2AD.
Tab le 1. Absolute M aximum Rati ngs
Characteristic 1Symbol Range Unit
Supply vol tage—CPU core and peripheral logi c VDD –0.3 to 2.25 V
Supply vol tage—memory bus drivers GVDD –0.3 to 3.6 V
Supply vol tage—PCI and standard I/O buf fers OVDD –0.3 to 3.6 V
Supply vol tage—PLLs AVDD/AVDD
2–0.3 to 2. 25 V
Supply vol tage—PCI refer ence LVDD –0.3 to 5.4 V
Input vol tage 2Vin –0.3 to 3.6 V
Operati onal die-junction te mp erature rang e Tj0 to 1053°C
Storage temperature range Tstg –55 to 150 °C
Notes:
1. Functional and tested operati ng conditi ons are gi ven in Table 2. Absol ute maximum ratings are stre ss ratings only, and
functional operation at the max imums is not guaran teed. Stress beyond those listed may affect device reli abili ty or cause
permanent damage to the device.
2. PCI inputs wit h LVDD = 5 V ± 5% V DC may be correspondin gly stress ed at vol tages exceeding LVDD + 0.5 V DC.
3. Note that this temperature range does not apply to the 400 MHz parts. For details, refer to the hardware specifications
addendum MPC8245ECSO2AD.
Tab le 2. Recommen ded Ope rating Conditions1
Characteristic Symbol Recommended
Value Unit Notes
Supply vol tage VDD 1.8/1.9/2.0 V ±
100 mV V4, 7
2.0/2.1 V ±
100 mV V5, 7
I/O buffer supply for PCI and standard OVDD 3.3 ± 0.3 V 7
Supply vol tages for mem ory bus drivers GVDD 3.3 ± 5% V 9
CPU PLL supply voltage AVDD 1.8/ 1.9/2.0 V ± V 4, 7, 12
2.0/2.1 V ± V 5, 7, 12
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 7
Electrical and Thermal Characteristics
PLL supply voltage—peripher al l ogic AVDD2 1. 8/1.9/2.0 V ± V 4, 7, 12
2.0/2.1 V ± V 5, 7, 12
PCI reference L VDD 5.0 ± 5% V 2, 10, 11
3.3 ± 0.3 V 3, 10, 11
Input voltage PCI inputs Vin 0 to 3.6 or 5. 75 V 2, 3
All other inputs 0 to 3.6 V 6
Die-junction temperature Tj0 to 105 °C
Notes:
1. These are the recomm ended and tested operating conditio ns. Proper device operatio n outside of these condition s is not
guaranteed.
2. PCI pins are desi gned to wi thstand LVDD + 5% V DC when LVDD is connected to a 5.0-V DC power supply.
3. PCI pins are desi gned to wi thstand LVDD + 0.5 V DC when LVDD is connected to a 3.3-V DC power supply.
4. The voltage supply val ue of 1. 8/1.9/2.0 V ± 100 m V applies to parts marked as having a maximum CPU spe ed of 266 and
300 MHz. See Table 7. For each chosen nominal value (1.8/1. 9/2.0 V) the supply voltage should not exceed ± 100 mV of
the nominal value.
5. The voltage supply value of 2.0/2. 1 V ± 100 m V a pplie s to parts mar ked as having a m aximum CPU speed of 333 and 350
MHz. See Table 7. For each chosen nomi nal value (2.0/2.1 V) the suppl y voltage should not exceed ± 10 0 mV of the nom in al
value.
Cautions:
6. Input vol tage (V in) must not be gr eater than t he su pply vol tage ( VDD/AVDD/AVDD2) by mo re than 2 .5 V at al l times, includ ing
during power-on reset. Input voltage (Vin) m u st not be g reater than GV DD/OVDD by more than 0.6 V at all times, including
during power-on reset.
7. OVDD must not exceed VDD/AVDD/AVDD2 by more t han 1.8 V at any t ime, incl uding during power-on reset. This limit may
be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
8. VDD/AVDD/AVDD2 must not exceed OVDD by more than 0. 6 V at any ti m e, i ncluding dur ing power-on res et. This limit may
be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
9. GVDD must not exceed VDD/AVDD/AVDD2 by more t han 1.8 V at any t ime, incl uding during power-on reset. This limit may
be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
10.LVDD mus t not exc eed V DD/AVDD/AVDD2 by more than 5. 4 V at any t ime, i ncludi ng durin g power -on res et. This l imit may b e
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
11.LVDD must not exceed OVDD by more tha n 3.0 V at any tim e, i ncluding during po wer- on reset. This limit m ay be exceeded
for a maximum of 20 ms during power-on reset and power-down sequences.
12.Thi s voltage is the input to t he filter discussed i n Sect ion 7.1, “PLL Power Suppl y Filt ering,” and not necessarily the volt age
at the AVDD pin, which m ay be reduced from VDD by the filter.
Tabl e 2. Recommended Operating Condit ions1 (continued)
Characteristic Symbol Recommended
Value Unit Notes
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
8Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 2 shows supply voltage sequencing and separation cautions.
Figure 2. Supply Voltage Sequencing and Separation Cautions
OVDD/GVDD/(LVDD @ 3.3 V - - - -)
VDD/AVDD/AVDD2
LVDD @ 5 V
Time
3.3 V
5 V
2.0 V
0
8
11 10
1011
7, 9
DC Power Supply Vol tage
Reset
Config uration Pins
HRST_CPU,
HRST_CTRL
PLL
Relock
Time 3
100 µs
Nine Ext ernal Memory
Asserted 255
External Memory
HRST_CPU,
HRST_CTRL
VDD Stable
Power Supply Ramp Up 2
Se e No te 1
Clock C ycles 3
Clock Cycl es Setup Time 4
VM = 1.4 V
Maximum Rise T ime Must Be Les s Than
One External Me mo ry Cl ock Cycle 5
Notes:
1. Numb ers associat ed wit h waveform separations cor respond to caut ion numbers listed in Table 2.
2. See the Cautions section of Table 2 for detai ls on t his topic.
3. See Table 8 for details on PLL relock and reset signal assertion timing requirements.
4. Refe r t o Table 10 for additional info rmation on reset configura tion pin setup ti m ing require me nts.
5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a l ogic 1 in less than one
SDRAM_SYNC_IN clock cycle for t he device to be in the nonreset state.
6. PLL_CFG signals must be driven on re set and must be held for at least 25 clock cycles after the
negation of HRST_CTRL and HRST_CPU in order to be latched.
PLL
6
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 9
Electrical and Thermal Characteristics
Figure 3 shows the undershoot and overshoot voltage of the memory interface.
Figure 3. Overshoot/Undershoot Voltage
Figure 4 and Figure 5 show the undershoot and overshoot voltage of the PCI interface for the 3.3- and 5-V
signals, respectively.
Figure 4. Maximum AC Waveforms for 3.3-V S ignaling
GND
GND – 0.3 V
GND – 1.0 V
Not to Exceed 10%
GVDD
of tSDRAM_CLK
GVDD + 5%
4 V
VIH
VIL
Undervoltage
Waveform
Overvoltage
Waveform
11 ns
(Min) +7.1 V
7.1 V p-t o-p
(Min)
4 ns
(Max)
–3.5 V
7.1 V p-t o-p
(Min)
62.5 ns+3.6 V
0 V
4 ns
(Max)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
10 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 5. Maximum AC Waveforms for 5-V Signaling
4.2 DC Electri cal Ch aracteristics
Table 3 provides the DC electrical char acter istics for the MPC8245 at recommended operating conditions.
Tab le 3. DC Electrical Specifications
At r ecommend ed ope rating conditions (see Table 2)
Characteristic Condition 3Symbol Min Max Unit Notes
Input hi gh voltage PCI only, except
PCI_SYNC_IN VIH 0.65 × OVDD LVDD V1
Input l ow voltage PCI only, except
PCI_SYNC_IN VIL —0.3 × OVDD V
Input hi gh voltage All other pins, including
PCI_SYNC_IN
(GVDD = 3.3 V)
VIH 2.0 3.3 V
Input l ow voltage All i nputs, including
PCI_SYNC_IN VIL GND 0.8 V
Input leakage cur rent fo r pins us ing
DRV_PCI driver 0.5 V ≤ Vin ≤ 2.7 V
@ LVDD = 4.75 V IL—±70µA4
Input l eakage current for
all others LVDD = 3.6 V
GVDD ≤ 3.465 V IL—±10µA4
Output high voltage IOH = driver-dependent
(GVDD = 3.3 V) VOH 2.4 — V 2
Output l ow vol tage IOL = driver-dependent
(GVDD = 3.3 V) VOL —0.4V2
Undervoltage
Waveform
Overvoltage
Waveform
11 n s
(Min) +11 V
11 V p-to-p
(Min)
4 ns
(Max)
–5.5 V
10.75 V p-to-p
(Min)
62.5 ns+5.25 V
0 V
4 ns
(Max)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 11
Electrical and Thermal Characteristics
4.2.1 Output Driver Char ac teristics
Table 4 provides information on the characteristics of the output drivers referenced in Table 16. The values
are preliminary est ima tes from an IBIS model and are not tes ted .
Capacitance Vin = 0 V, f = 1 MHz Cin — 16.0 pF
Notes:
1. See Table 16 fo r pins with internal pull-up resistors.
2. See Table 4 for the typi cal dri ve capability of a specific signal pin based on the type of output driver as sociated with that pin
as lis ted in Table 16.
3. These specifications are for the default driver strengths indicated in Table 4.
4. Leakage current is mea sured on input and out put pins in the high-impedanc e state. The leakage current i s measured for
nominal OVDD/LVDD, and VDD or both OVDD/LVDD and VDD must vary in the same direction.
Ta b l e 4. Dr iv e Ca pability of MP C8 245 Output Pins 5
Driver Type Programmable
Output Impedance
(Ω)
Supply
Voltage IOH IOL Unit Notes
DRV_STD_MEM 20 (default) OVDD = 3.3 V 36.6 18.0 mA 2, 4, 6
40 18.6 9.2 mA 2, 4, 6
DRV_PC I 20 12.0 12.4 mA 1, 3
40 (default) 6.1 6.3 mA 1, 3
DRV_MEM_CTRL 6 (default)
20
40
GVDD = 3.3 V 89.0 42 .3 mA 2, 4
DRV_PC I_CLK 36.6 18.0 mA 2, 4
DRV_MEM_CLK 18.6 9.2 mA 2, 4
Notes:
1. For DRV_PCI , I OH read from th e IBIS l isting in the pul l-up mode , I(Mi n) column, at the 0.33-V l ab el by i nterpo lati ng between
the 0.3- and 0.4-V table entries’ current values that corr espond to the PCI V OH = 2.97 = 0.9 ×OVDD (OVDD = 3.3 V) where
table entry voltage = OVDD – PCI VOH.
2. For al l ot hers wit h GV DD or OVDD = 3.3 V, IOH re ad fr om t he IBI S l isting i n the pull -up m ode, I (Min) c olumn, at t he 0 .9-V t able
entry t hat corresponds to the VOH = 2.4 V where table entry voltage = GVDD/OVDD – VOH.
3. For DRV_PCI, IOL read from the I B IS listi ng in the pull -down mode, I(Min) column, at 0.3 3 V = PCI V OL = 0 ×OVDD (OVDD
= 3.3 V) by interpolating bet ween the 0.3- and 0.4-V table entries .
4. For all others with GVDD or OVDD = 3.3 V, IOL read f rom the I B IS l isting in the pul l-down mode, I (Min) column, at the 0.4-V
table ent ry.
5. See driver bit details for out put driver control regist er (0x73) in the MPC8245 Integrated Processor Reference Manual.
6. See Chip Errata No. 19 in the MPC8245/MPC8241 RISC Microprocessor Chip Errata.
Table 3. DC Electrical Specification s (continued)
At r ecommend ed ope rating conditions (see Table 2)
Characteristic Condition 3Symbol Min Max Unit Notes
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
12 Freescale Semiconductor
Electrical and Thermal Characteristics
4.3 Power Characteristics
Table 5 provides power consumption data for the M PC8245.
Table 5. P ower Consumption
Mode PCI Bus Cl ock/Memory Bus Clock/CPU Clock Frequency (MHz) Unit Notes
66/66/266 66/133/266 66/66/300 66/100/300 33/83/333 66/133/333 66/100/350
Typical 1.7
(1.5) 2.0
(1.8) 1.8
(1.7) 2.0
(1.8) 2.0 2.3 2.2 W 1, 5
Max—FP 2.2
(1.9) 2.4
(2.1) 2.3
(2.0) 2.5
(2.2) 2.6 2.8 2.8 W 1, 2
Max—INT 1.8
(1.6) 2.1
(1.8) 2.0
(1.8) 2.1
(1.8) 2.2 2.4 2.4 W 1, 3
Doze 1.1
(1.0) 1.4
(1.3) 1.2
(1.1) 1.4
(1.3) 1.4 1.6 1.5 W 1, 4, 6
Nap 0.4
(0.4) 0.7
(0.7) 0.4
(0.4) 0.6
(0.6) 0.5 0.7 0.6 W 1, 4, 6
Sleep 0.2
(0.2) 0.4
(0.4) 0.2
(0.4) 0.3
(0.3) 0.3 0.4 0.3 W 1, 4, 6
I/O Power Supplies 10
Mode Min Max Unit Notes
Typ—OVDD 134 (121) 334 (301) mW 7, 8
Typ—GVDD 324 (292) 800 (720) mW 7, 9
Notes:
1. The values include VDD, AVDD, and AVDD2 but do not inc lude I /O supply power. Information on O VDD and GVDD supply
power i s captured in the I/O power supp lies sect ion of t his ta ble. V al ues shown in parenthesi s ( ) ind ic ate power consumption
at VDD/AVDD/AVDD2 = 1.8 V.
2. Maximum—FP power is measured at VDD = 2.1 V with dynamic power management enabled while runni ng an entirely
cache-resident, looping, floati ng-point mul tiplication instruction.
3. Maximum—IN T power i s me asured at VDD = 2.1 V with dynamic power management enabled while running entirely
cache-resident, looping, integer i nstructi ons.
4. Power saving mode ma ximums are measured at VDD = 2.1 V whi le the devic e is i n doze, nap, or sleep mo de.
5. Typica l power is measured at VDD = AV DD = 2.0 V, OVDD = 3.3 V where a nominal FP value, a nominal INT value, and a
value wh ere there is a c ont inuous f lush o f cache l ines wi t h alte rnating on es and zer os on 64-b it bou ndar ies to local memory
are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. The typical minimum I/O power values were results of the MPC8245 performing cache resident integer operations at the
slowest frequen cy combinatio n of 33:66:200 (PCI:Mem :CPU) MHz.
8. The typical maximum OVDD val ue resulted fr om the MPC8245 operating at the fastest fr equency combinat ion of 66:100 :35 0
(PCI: Me m:C PU) MHz and performin g continuous flushes of cache lines with alternating ones and zeros to PCI memor y.
9. The typical maximum GVDD val ue resulted fr om the MPC8245 operating at the fastest fr equency combinat ion of 66:100 :35 0
(PCI: Mem:CPU) MHz a nd perfor ming con ti nuous fl ushes of cache lines with alternatin g ones and zeros on 6 4-b it boundar ies
to local memo ry.
10.Power consum ption of PLL sup ply pi ns (AVDD and AVDD2) < 15 mW. Guaranteed by design and not tested.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 13
Electrical and Thermal Characteristics
4.4 T h ermal Characteristics
Table 6 provides the pac k age thermal characteristics for the M PC8245. For details, s ee Sec tion 7.8,
“Thermal Management.”
4.5 AC Electri cal Ch aracteristics
After fabrication, functional parts are sorted by maximum proc essor core frequency as shown in Table 7
and tested for conformance to the AC specifications for that frequency. The processor core frequency is
determined by t he bus (P CI_SYNC_IN) clock frequency and the s ettings of the P LL_CFG[0:4] signals.
Parts are sold by maximum processor core frequency. See Section 9, “Ordering Infor mation,” for details
on ordering parts.
Tab le 6. T her mal Characteri stics
Characteristic Symbol Value Unit Notes
Junction-to-ambient natural convection
(Single-layer board—1s) RθJA 16.1 °C/W 1, 2
Junction-to-ambient natural convection
(Four-layer board—2s2p) RθJMA 12.0 °C/W 1, 3
Junction-to-ambient (@200 ft/min)
(Single-layer board—1s) RθJMA 11.6 °C/W 1, 3
Junction-to-ambient (@200 ft/min)
(Four l ayer board—2s 2p) RθJMA 9.0 °C/W 1, 3
Junction-to-board RθJB 4.8 °C/W 4
Junction-to-case RθJC 1.8 °C/W 5
Junction-to-package top (natural convection) ΨJT 1.0 °C/W 6
Notes:
1. Juncti on tem peratu re is a fu nctio n of die size, on- chip power dissi patio n, package ther mal resi stanc e, moun ting si te (boa rd)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51- 2 wit h the si ngle-l ayer board horizontal.
3. Per JEDEC JESD51-6 with th e board horizontal.
4. Thermal re sista nce bet ween the di e and t he print ed-ci rcuit b oard per J EDEC JESD5 1-8. Bo ard tempera ture is measured on
the top sur face of the boar d near t he package.
5. Thermal resistanc e between the die and the case top surf ace as meas ure d by the col d plate meth od (MIL SPEC-883 Method
1012.1) with the cold plate used for case temperature.
6. Thermal character ization pa rameter indicating the temperature difference between the package top and the junction
temperat ure per JEDEC JESD51- 2. When Greek let ters are not avai labl e, the therm al charac terizat ion paramet er is writt en
as Psi-JT.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
14 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 7 provides the operating frequency information for the MPC8245 at recommended operating
conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V.
4.5.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications at re commended operating conditions , as defined in
Section 4.5.2, “Input AC Timing Specifications . ” These specifications are f or the default driver strengths
indicated in Table 4.
Table 7. Operating Frequency 1
Characteristic 2, 3
266 MHz 300 MHz 333 MHz 350 MHz
Unit
VDD/AVDD/AVDD2 = 1.8/1.9/2.0 V
± 100 mV VDD/AVDD/AVDD2 = 2.0/2.1 V
± 100 mV
Processor freque ncy (CPU) 100–266 100–300 100–333 100–35 0 MHz
Memory bus fre quency 50–133 50–100 450–133 50–100 4MHz
PCI input frequency 25–66 MHz
Notes:
1. For detai ls, refer to the hardware speci fi cations addendum MPC8245ECSO2AD.
2. Caution: The PCI_SYNC_IN frequency and PLL_CFG[ 0:4] settings must be chosen such that the resulting peripheral
logic /mem ory bus frequ ency and CPU (core) frequencies do not exceed their respecti ve ma ximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in Section 6, “PLL Configurations,” for valid PLL_CFG[0:4] settings
and PCI_SYNC_IN frequencies.
3. See Table 17 and Table 18 for details on VCO limitations for memory and CPU VCO frequenci es of various PLL
configurations.
4. No available PLL_CFG[0:4] settings support 133-MHz memory interface operation at 300- and 350-MHz CPU operation,
since the mul tipliers do not allow a 300:133 and 350:133 rat io relation. However, running these par ts at slower proces sor
speeds ma y produce rati os that run above 100 MHz. See Table 17 for the PLL settings.
Table 8. Clock AC Timing Specifications
At r ecommend ed ope rating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V
Num Characteristics and Conditions Min Max Unit Notes
1 Frequency of operation (PCI_SYNC_IN) 25 66 M Hz
2, 3 PCI_SYNC_IN rise and fall times — 2.0 ns 1
4 PCI_ SYNC _IN duty cycle measured at 1.4 V 40 60 %
5a PCI_SYNC_IN pul se width high measu red at 1.4 V 6 9 ns 2
5b PCI_SYNC_IN pulse width low measured at 1.4 V 6 9 ns 2
7 PCI_SYNC_IN jit ter — 200 ps
8a PCI_CLK[0:4] skew (pin-to-pin) — 250 ps
8b SDRAM_CLK[0:3] skew (pin-to-pi n) — 190 ps 3
10 Internal PLL relock time — 100 µs 2, 4, 5
15 DLL lock ran ge wit h DLL_EXTEND = 0 (disabled)
and normal tap delay; (default DLL mode) See Figure 7 ns 6
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 15
Electrical and Thermal Characteristics
Figure 6 shows the PCI_SYNC_IN input clock timing diagram with the labeled number items listed in
Table 8.
Figu re 6. P C I_S Y NC _ I N In put C l ock Timi ng D i agram
Figure 7 through Figure 10 show the DL L locking range loop delay vs. frequency of operation. These
graphs define the areas of DLL locking for various modes. The gray areas show where the DLL locks.
16 DLL lock range for other modes See Figure 8 through Figure 10 ns 6
17 Frequency of operation (OSC_IN) 25 66 M Hz
19 OSC_IN rise and fall times — 5 ns 7
20 OSC_IN duty cycle measured at 1.4 V 40 60 %
21 OSC_IN frequency stabi lity — 100 ppm
Notes:
1. Rise and fall t imes for the PCI_SYNC_IN i nput are measured from 0.4 to 2.4 V.
2. Specification value at maximum frequency of operation.
3. Pin-to-pin skew i ncludes quant ifying the ad ditional amount of clock skew (or ji tter) fr om the DLL b esides any in tentional skew
added to the cl ocking signals from the variable length DLL synchro nization feedback loop, t hat is, the amoun t of var iance
between t he int ernal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL i s loc ked. Whi le pin-to-p in sk ew betwe en
SDRAM_CLKs can be measured, the rel ati onship between t he internal sys_logic_clk and th e external SDRAM_SYNC_IN
cannot be measured and is guaranteed by design.
4. Relock time is guaranteed by design and character ization . Rel ock time is not tested.
5. Relock timing is guarant eed by design. PLL-r elock ti me is the maxi mu m am ount of tim e required for PLL lock after a stable
VDD and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been
disabl ed and sub sequently r e-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL m ust be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
6. DLL_EXTEND is bit 7 o f the PMC2 r egist er <72>. N i s a non-z ero in teger ( see Figure 7 through Figure 10). Tclk is the period
of one SDRAM_SYNC_OUT clock cycle in ns. Tloop is the propagat ion del ay of the DLL sync hroniz ation f eedback lo op (PC
board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner)
corresponds to approximately 1 ns of delay. For details about how Figure 7 through Figure 10 may be used refer to the
Freescale application not e AN2164, MPC8245/MPC824 1 Memor y Clock Design Guideli nes, for details on MPC8245
memory clock design.
7. Rise and fal l ti me s for t he OSC_IN input is guaranteed by design and characterization. OS C_IN input rise an d fall times are
not tested.
Tab le 8. Clock AC Timing Specifications (continued)
At r ecommend ed ope rating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V
Num Characteristics and Conditions Min Max Unit Notes
5a 5b
VM
VM = Midpoint Voltage (1.4 V)
2 3
1
PCI_SYNC_IN VM VM
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
16 Freescale Semiconductor
Electrical and Thermal Characteristics
Register setti ngs that define each DLL mode are shown in Table 9.
The DLL_MAX_DE LAY bit can lengthen the amount of tim e through the delay line by increasing the
time between each of the 128 tap points in the delay line. Although this increased time makes it eas ier to
guarantee that the reference clock i s within the DLL lock range, there may be slightly more jitter in the
output clock of the DLL; that is, the phase comparator shifts the clock between adjacent tap points. Refer
to the Freescale application note AN2164, MPC8245/MPC8241 Memory Clock Design Guideli nes:
Part 1, for details on DLL modes and me mory design.
The value of the current tap point after the DLL locks can be determined by reading bits 6–0
(DLL_TAP_COUNT ) of the DLL tap count r egister (DTCR, located at offset 0xE3). These bits store the
value (binary 0 through 127) of the current tap point and can indicate whether the DLL advances or
decrements as it maintains the DLL lock. Therefore, for evaluation purposes, DTCR can be read for all
DLL modes that support the Tloop value used for the trace length of SDRAM_SYNC_OUT to
SDRAM_SYNC_IN. The DLL mode with the smallest tap point value in the DTCR s hould be used
because the bigger the tap point value, the more jitter that can be expected for clock signals. Note that
keeping a DLL mode that is locked be low tap point decimal 12 is not recommended.
Ta b le 9. DL L Mo de D ef i ni t io n
DLL Mode Bit 2 of Configuration
Register at 0x76 Bit 7 of Configuration
Register at 0x72
Normal tap delay,
No DLL extend 00
Normal tap delay,
DLL e xt end 01
Max tap delay,
No DLL extend 10
Max tap delay,
DLL e xt end 11
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 17
Electrical and Thermal Characteristics
Figure 7. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=0
and Normal Tap Delay
23
10
15
20
0
25
30
1
Tloop Propagation Delay Ti me (ns)
T
clk
SDRAM_SYNC_OUT Period (ns)
27.5
22.5
17.5
12.5
7.5
4 5
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
18 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 8. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=1
and Normal Tap Delay
23
10
15
20
0
25
30
1
Tloop Propagation Delay Tim e (ns)
T
clk
SDRAM_SYNC_OUT Period (ns)
27.5
22.5
17.5
12.5
7.5
4 5
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 19
Electrical and Thermal Characteristics
Figure 9. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=0
and Max Ta p Delay
23
10
15
20
0
25
30
1
Tloop Propagation Delay Tim e (ns)
T
clk
SDRAM_SYNC_OUT Period (ns)
27.5
22.5
17.5
12.5
7.5
4 5
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
20 Freescale Semiconductor
Electrical and Thermal Characteristics
Figu re 10 . DLL Lockin g Ra n ge Lo op Delay Ver s us Frequ ency of Opera ti on for DLL_Extend=1
and Max Ta p Dela y
4.5.2 Input AC Timing Specifications
Table 10 provides the input AC timing specifications at recommended operating conditions (see Table 2)
with LVDD = 3.3 V ± 0.3 V.
23
10
15
20
0
25
30
1
Tloop Propagation Delay Ti me (ns)
T
clk
SDRAM_SYNC_OUT Period (ns)
27.5
22.5
17.5
12.5
7.5
4 5
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 21
Electrical and Thermal Characteristics
Table 10. Input AC Timi ng Specific at i ons
Num Characteristic Min Max Unit Notes
10a PCI input signals valid to PCI_SYNC_IN (input setup) 3.0 — ns 1, 3
10b Memory input signals valid to sys_logic_clk (input setup)
10b0 Tap 0, regist er offset <0x77>, bits 5–4 = 0b00 2.6 — ns 2, 3, 6
10b1 Tap 1, regist er offset <0x77>, bits 5–4 = 0b01 1.9 —
10b2 Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default) 1.2 —
10b3 Tap 3, regist er offset <0x77>, bits 5–4 = 0b11 0.5 —
10 c PIC, misc. debug input si gnals valid to sys_logic_clk
(input setup) 3.0 — ns 2, 3
10d I2C input signal s valid to sys_logic_clk (input set up) 3.0 — ns 2, 3
10e Mode select inputs valid to HRST_CPU/HRST_CTRL (input setup) 9 × tCLK — ns 2, 3–5
11 Tos—SDRAM_SYNC_IN to sys_logic_clk o ffs e t time 0.4 1.0 ns 7
11a sys_logic_clk to memory signal inputs invalid (input hold)
11a0 Tap 0, regist er of fset <0x77>, bits 5–4 = 0b00 0 — ns 2, 3, 6
11a1 Tap 1, regist er of fset <0x77>, bits 5–4 = 0b01 0.7 —
11a2 Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default) 1.4 —
11a3 Tap 3, regist er of fset <0x77>, bits 5–4 = 0b11 2.1 —
11b HRST_CPU/HRST_CTRL to mode select inputs inva li d (i nput hold) 0 — ns 2, 3, 5
11c PCI_SYNC_IN to I nputs inval id ( input hold) 1.0 — ns 1, 2, 3
Notes:
1. All PCI signal s are measured from OV DD/2 of the ris ing edge of PCI_SYNC_IN to 0.4 ×OVDD of the signal in question for
3.3-V PCI signaling levels. See Figure 12.
2. All memory and r elated interface inpu t si gnal specif ications are measured from the TTL level (0.8 or 2.0 V) of the signal in
questi on to the VM = 1.4 V of the ri sing edge of the memor y bus clock, sys_logic_clk. sys_logic_clk is the same as
PCI_SYNC_ IN in 1 :1 mode but is twice the frequency in 2:1 mode (pr ocessor/memory bus cloc k rising edges occur on every
rising and falling edge of PCI _SYNC_IN). See Figure 11.
3. Input t imings are measured at the pin.
4. tCLK is the time of one SDRAM_SYNC_I N cloc k cycle.
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the
VM = 1.4 V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 13.
6. The memor y int erfac e input setup and h old times are pro grammabl e to four possi ble co mbina tions by pr ogramm ing bi ts 5–4
of regi ster off set <0x77> to sel ect the desir ed input setup and hold times.
7. Tos represents a tim ing adjustmen t for SDRAM_ SYNC_IN with respect to sys_logic_clk. Due to the inter nal delay prese nt
on the SDRAM_SYNC_IN signal with respect to the sys_logic_cl k inputs to the DLL, t he resulting SDRAM clocks become
offset by th e delay amount. To maintain phase-ali gnm ent of the memory clocks wi th respect to sys_logic_clk, the fe edback
trace l ength of SDRAM_SYNC_OUT to SDRAM_SYNC_IN must be shor tened to accommodate t his range. The feedback
trace length is relative to t he SDRAM cl ock output tr ace lengths. We recommend that the lengt h of SDRAM_SYNC_O U T to
SDRAM_SYNC_IN be shortened by 0.7 ns bec ause that is the midpoint of the range of Tos and allows the impact from the
range of Tos to be reduced. Addi tional analyses of trace lengths and SDRAM loading m ust be performed to optimize timing .
For detai ls on t race measurem ents and the probl em of Tos, refer to the Freescale appl ication note AN2164,
MPC8245/MPC8241 Memory Clock Design Guidelines.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
22 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 11 and Figure 12 show the input/output timing diagrams referenced to SDRAM_SYNC_IN and
PCI_SYNC_IN, respectively.
Figur e 11. Input/Output Timing Diagram Referenced to SDRAM_ SYNC_IN
Figu re 12 . I np ut / Ou tp ut Tim i ng Di a gr a m Reference d t o PCI _S Y N C _I N
11a
VM = Midpoint voltage (1.4 V) .
Memory
10b-d
Inputs/Outputs
13b
14b
VM
VM
SDRAM_SYNC_IN
Input Timing Output Timing
12b-d
2.0 V
0.8 V
0.8 V
2.0 V
Tos
11a = Input hold time of SDRAM_SYNC_IN to memory.
12b-d = sys_logic_clk to output valid timing.
13b = Output hol d time for non- PCI si gnals.
14b = SDRAM-SYNC_IN to out put hi gh-impedance timing for non- PCI si gnals.
Tos = Offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal
sys_logic_clk VM
PCI_SYNC_IN VM
VM
is adj usted by the DLL to acco mmodate for internal delay. This causes SDRAM_SYNC_IN to appear
before sys_logic_clk once the DLL loc ks.
(af ter DLL locks )
Shown in 2:1 Mode
Notes:
10b-d = Input signals valid timing.
OVDD ÷ 2
10a
11c
PCI_SYNC_IN
PCI
12a
13a
14a
OVDD ÷ 2
OVDD ÷ 2
0.4 × OVDD
0.615 × OVDD
0.285 × OVDD
Input Timing Output Timing
Inputs/Outputs
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 23
Electrical and Thermal Characteristics
Figure 13 shows the input timing diagram f or mode select signals .
Fig ure 13 . In pu t Timi ng Dia g ra m for Mode Se le c t Si gnals
4.5.3 Output AC Timing Specification
Table 11 provides the processor bus AC timing specifications for the MPC8245 at recommended operating
conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V. See Figure 11 for the input/output timing diagram
referenced to sys_logic_clk. All output timings assume a purely resistive 50-Ω load (see Figure 14 for the
AC test loa d for the MPC8245). Output timings are measured at the pin; time-of-fl ight delays must be
added for trace lengths, vias, and connectors in the system. These specif ications are for the default driver
strengths indicated in Table 4.
Tabl e 11. Outp ut AC T i ming Specifications
Num Characteristic Min Max Unit Notes
12a PCI_SYNC_IN to output valid, see Figure 15
12a0 Tap 0, PCI_HOLD_DEL=00, [MCP,CKE] = 11, 66 MHz PCI (default) — 6.0 ns 1, 3
12a1 Tap 1, PCI_HOLD_DEL=01, [MCP,CKE] = 10 — 6.5
12a2 Tap 2, PCI_HOLD_DEL=10, [MCP,CKE] = 01, 33 MHz PCI — 7.0
12a3 Tap 3, PCI_HOLD_DEL=11, [MCP,CK E ] = 00 — 7.5
12b sys_logic_clk to output valid (memory control, address, and data signals) — 4.0 ns 2
12c sys_logic_clk to output valid (for all other s) — 7.0 ns 2
12d sys_logic_clk to output valid (for I2C) — 5.0 ns 2
12e sys_logic_clk to output valid (RO M /Flash/Po rtX) — 6.0 ns 2
13a Output hold (PCI), see Figure 15
13a0 Tap 0, PCI_HOLD_DEL=00, [MCP,CKE] = 11, 66-MHz PCI (default) 2.0 — ns 1, 3, 4
13a1 Tap 1, PCI_HOLD_DEL=01, [MCP,CKE] = 10 2.5 —
13a2 Tap 2, PCI_HOLD_DEL=10, [MCP,CKE] = 01, 33-MHz PCI 3.0 —
13a3 Tap 3, PCI_HOLD_DEL=11, [MCP,CKE] = 00 3.5 —
13b Output hold (all others) 1.0 — ns 2
14a PCI_SYNC_IN to output high impedance (for PCI) — 14.0 ns 1, 3
VM
VM = Midpoint Vol tage (1.4 V)
11b
Mode Pins
10e
HRST_CPU/HRST_CTRL
2.0 V
0.8 V
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
24 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 14 provides the AC test load for t he MPC8245.
Figure 14. AC Test Load for the MPC8245
14b sys_logic_clk to output high imp edance (for all ot hers) — 4.0 ns 2
Notes:
1. All PCI signals are measured from GVDD/2 of the rising edge of PCI_SYNC_IN to 0.2 85 ×OVDD or 0.61 5 ×OVDD of the
signal in question f or 3.3 V PCI signaling l evels. See Figure 12.
2. All memor y and rel ated interface output signal specificati ons are specified from the VM = 1.4 V of the rising edge of the
memory bus clock, sys_logic_clk to the TTL level (0.8 or 2.0 V) of the signal in question. sys_logic_clk i s the same as
PCI_SYNC_I N in 1:1 mode , but is twice th e frequency in 2:1 mode (proce ssor/memor y bus cloc k rising edges oc cur on ever y
rising and falli ng edge of PCI_SYNC_IN). See Figure 11.
3. PCI bused signals are composed of the following signals: LOCK, IRDY, C /B E [3:0], PAR, TRDY, FRA ME, S T O P, DEVSEL,
PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, and INTA.
4. To meet mini mum out put hol d spe cificat ions r elati ve to PCI _SYNC_IN fo r both 33 - an d 66-MHz PCI s ystem s, the MPC8245
has a programm able output hol d delay for PCI signals (the P CI_SYNC_IN to output valid t iming is also affect ed). The initial
value of the output hold delay is determined by the values on the MCP and CKE reset configuration signals; the values on
these two signal s are i nverted and sto red as the initia l set tings of PCI_HOL D_DEL = PMCR2[5, 4] (power management
configurat ion register 2 <0x72>), res pectivel y. Si nce M CP and CKE have internal pull-up resistors, the default value of
PCI_HOLD_DEL after reset is 0b00. Further output hold delay values are available by programming the PCI_HO LD_DEL
value of the PMCR2 configuration register. Figure 15 shows the PCI_HOLD_D EL effect on output valid and hold t imes.
Table 11. Output AC Ti ming Specifications (continued)
Num Characteristic Min Max Unit Notes
Output Z0 = 50 ΩOVDD/2 for PC I
RL = 50 Ω
Output Measurem ents are Made at the Device Pin
GVDD/2 for Me mory
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 25
Electrical and Thermal Characteristics
Figure 15 provides the PCI_HOLD_DEL effect on output valid and hold times.
Figure 15. PCI_HOLD_DEL Effect on Ou tput Valid and Hold Times
4.6 I2C
This section describes the DC and AC electrical ch aracteristics f or the I2C interfaces of the MPC8245.
4.6.1 I2C DC Electrical Characteristics
Table 12 provides the DC electrical characteristics for the I2C interfaces.
Tab le 12. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5% .
Parameter Symbol Min Max Unit Notes
Input hi gh voltage lev el VIH 0.7 × OVDD OVDD +0.3 V
Input low voltage level VIL –0.3 0.3 × OVDD V
Low -l evel output voltage VOL 00.2 × OVDD V1
PCI_SYNC_IN
PCI Inputs/Outputs
33 MHz PCI
12a2, 7.0 ns for 33 MHz PCI
PCI_HOLD_DEL = 10
12a0, 6.0 ns for 66 MHz PCI
PCI_HO LD_DEL = 00
13a2, 2.1 ns for 33-MHz PCI
PCI_H OLD_ DEL = 10
13a0, 1 ns for 66- MHz PCI
PCI_HOLD_DEL = 00
Ou tput Vali d Output Hold
Note: Diagram not to scale.
A s PCI_HO LD_ DEL
Values Decrease
PCI Inputs
and Outputs
PCI Inputs/Outputs
66 MHz PCI
PCI_HO LD_DEL = 00
As PCI_HOLD_DEL
Values Increase
OVDD/2 OVDD/2
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
26 Freescale Semiconductor
Electrical and Thermal Characteristics
4.6.2 I2C AC Electrical Spe cificatio ns
Table 13 provid es the AC timing parameters for the I2C interf aces .
Pulse width of spikes which must be suppressed by
the input filter tI2KHKL 050ns2
Input cur rent each I/O pin (i nput voltag e is bet ween
0.1 × OVDD and 0. 9 × OVDD(max) II–10 10 μA3
Capacitance for each I/O pin CI—10pF
Notes:
1. Output voltage (op en drai n or open collec tor) condi ti on = 3 mA sink current.
2. Re fer to the MPC8245 Integr ated Processor Reference Manual for information on the digital filter used.
3. I/O pins obstruct the SDA and SCL lines if the OVDD is switched off.
Table 13. I2C AC Electrical Specifications
All values refer to VIH (min) an d VIL (max) levels (se e Table 12).
Parameter Symbol 1Min Max Unit
SCL clock frequenc y fI2C 0 400 kHz
Low peri od of the SCL c lock tI2CL 4 1.3 — μs
High period of the SCL clock tI2CH 4 0.6 — μs
Setup time for a repeate d START condition tI2SVKH 4 0.6 — μs
Hold tim e (repeated) START cond it ion (after this period, the first
clock pulse is generated) tI2SXKL 4 0.6 — μs
Data setup time tI2DVKH 4 100 — ns
Data input hold time: CBUS compatible masters
I2C bus dev ices
tI2DXKL —
0 2—
—
μs
Data output delay time: tI2OVKL —0.9
3
Set-up time for STOP condition tI2PVKH 0.6 — μs
Bus free time between a STOP and START condition tI2KHDX 1.3 — μs
Noise marg in at the LO W level for each conne cted dev ice ( inclu ding
hysteresis) VNL 0.1 × OVDD —V
Tab le 12. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5% .
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 27
Electrical and Thermal Characteristics
Figure 16 provides the AC test load for the I2C.
Figure 16. I2C AC Tes t Load
Noise ma rgi n at the HIGH level for each connected device (i ncluding
hysteresis) VNH 0.2 × OVDD —V
No te :
1. The sym bols used for timing specification s follow the patte rn of t(first two letters of funct ional block)(signal)(state) (reference)(state) for
inpu ts and t(first two l etters of functional block)(re ference)(state)(signal)(state) for out puts. For exa mp le, tI2DVKH symbolizes I2C t iming (I 2)
wit h respec t to the time dat a input sign als ( D) reac h t he val id st ate (V) rel at ive t o the t I2C clock ref erence (K) g oin g to t he high
(H) state or setup ti m e. Al so, tI2SXKL symbolizes I2C timi ng (I 2) for the time that the dat a wit h respect to the star t condition
(S ) we nt i nv ali d ( X) rel at iv e t o th e tI2C cl ock ref erence (K) going t o the l ow (L) s tate or hold t ime. Al so, tI2PVKH sy mbol izes I 2C
ti ming (I2) for the t ime that the data with re spec t to the st op condit ion (P) r eac hing the va lid state (V) rela tive t o the tI2C clock
ref eren ce (K) going to the high (H) stat e or setup time. For rise an d fall ti mes, the l atter convention is used with th e appropriate
lett er : R (ris e ) o r F (fa ll).
2. As a transmitter, the MPC8245 provides a delay time of at least 300 ns for the SDA signal (referred to as the Vihmin of the
SCL si gnal) t o bridge th e undefined regi on of t he fall in g edge of SCL to avoid unintended generati on of Sta rt or Stop cond it ion.
When t he MP C8245acts as the I 2C bus master whi le t ransmitt ing, it drives both SCL and SDA. As long as the l oad on SCL
and SDA is balanced, the MPC8245 does not cause the unintended generation of a Start or Stop condition. Therefore, the
300 ns SDA output del ay time is not a concern. If, under some rar e condition, the 300 ns SDA output delay ti m e is required
for the MPC8245 as tr ansm itter, the following s ett ing is r ecommended f or the FDR bit fie ld of the I2CFDR regis ter to e nsure
both the desire d I2C SCL cl ock frequency and SDA output delay ti me are achi eved. It is assum ed that the desired I 2C SCL
cloc k fr equency is 400 KHz and the digital filt er sampl ing rate register ( DFFSR bits in I2CFDR) is progr ammed with its defaul t
setting of 0x10 (deci m al 16):
SDRAM Clock Frequency 100 MHz 133 MHz
FDR Bit Setting 0x00 0x2A
Actual FDR Divider Selected 384 896
Actual I2C SCL Frequency Generated 260.4 KHz 14 8.4 KHz
For detai ls on I2C frequency calculation, re fer to the applic ati on note AN2919 “Determining the I2C Frequency Divider Rat io
for S C L ”.
3. The maximum tI2DXKL has only to be met if the device does not stre tch the LOW period (tI2CL) of the SCL signal.
4. Guaranteed by desi gn.
Table 13. I2C AC Electrical Specifications (conti nued)
All values refer to VIH (min) an d VIL (max) levels (se e Table 12).
Parameter Symbol 1Min Max Unit
Output Z0 = 5 0 ΩOVDD/2
RL = 50 Ω
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
28 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 17 shows the AC timing diagram for the I2C bus.
Figure 17. I2C Bus AC Timing Diagram
4.7 PIC Serial Interrupt Mode AC Timing Specifications
Table 14 provides the PIC serial interrupt mode AC timing specifications for the MPC8245 at
recommended operating conditions (s ee Table 2) with GVDD = 3.3 V ± 5% and LVDD = 3.3 V ± 0.3 V.
Table 14. PIC S eri a l Int errupt Mo de A C Timi ng S pecifi cat io ns
Num Characteristic Min Max Unit Notes
1 S_CLK frequ ency 1/14 SDRAM_SYNC_IN 1/2 SDRAM_SYNC_IN MHz 1
2 S_CLK duty cycle 40 60 % —
3 S_CLK output valid time — 6 ns —
4 Output hold time 0 — ns —
5S_FRAME
, S_RST out p ut va lid time — 1 sys_logic_clk period + 6 ns 2
6 S_INT in put se tup time to S _ C L K 1 sys_logic_clk period + 2 — ns 2
7 S_INT inp uts invali d (hol d t ime) to S_ CLK — 0 ns 2
Notes:
1. See the MPC8245 Integrat ed Processor Reference Manual for a descri ption of the PIC interrupt control register (ICR) and
S_CLK frequency program ming.
2. S_RST, S_FRAME, and S_I NT shown in Figure 18 and Figure 19, depict ti m ing relationships to sys_logic_clk and S_CLK
and do not describe functional rela ti onships between S_RST, S_FRAME, and S_INT. The MP C8245 Integrated Processor
Reference Manual describes the functiona l re lationships between these signals .
3. The sys_logic_clk wavef orm is t he cloc king si gnal of the i nter nal peri pheral logi c from t he output of the pe ripher al logic P LL;
sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is
implemented and the DLL is locked. See the MPC8245 Integ rat ed Processor Ref erence Manual f o r a compl e te clockin g
description.
SrS
SDA
SCL
tI2CF
tI2SXKL
tI2CL
tI2CH
tI2DXKL,tI2OVKL
tI2DVKH tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
tI2CR
tI2CF
PS
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 29
Electrical and Thermal Characteristics
Figure 18. PIC Serial Interrupt Mode Output Timing Diagram
Fig ure 19 . PIC Serial Interrupt Mo de In put Timin g D iag ram
4.8 IEEE 1149.1 (JTAG) AC Timing Specifications
Table 15 provides the JT AG AC timing specifications for the MPC8245 while in the JTAG operating mode
at recommended operating conditions (see Table 2) with LVDD = 3 .3 V ± 0.3 V. Timings are independent
of the system clock (PCI_SYNC_IN).
Table 15. JTAG AC Timi ng Specification (Independent of PCI_SYNC_I N)
Num Characteristic Min Max Unit Notes
TCK frequency of operation 0 25 MHz
1 TCK cycle time 40 — ns
2 T CK clo ck pulse width measured at 1.5 V 20 — ns
3 TCK rise and fall tim es 0 3 ns
4TRST
setup tim e to TCK falling edge 10 — ns 1
5TRST
assert t ime 10 — ns
6 Input data set up ti m e 5 — ns 2
7 Input data hol d ti m e 15 — ns 2
8 TCK to output data valid 0 30 ns 3
9 TCK to output high impedance 0 30 ns 3
10 TMS, TDI data setup time 5 — ns
S_CLK
S_RST
VM
VM
VM
S_FRAME
sys_logic_clk
VM
VM
VM
VM
4
3
54
6
S_CLK
S_INT
7
VM
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
30 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 20 through Figure 23 show the different timing diagrams.
Figu re 20 . JTAG C lo ck In put Timi ng Diag ram
Figu re 21 . JTAG TR S T Tim i ng Dia g ra m
Figure 22. JTAG Boundary Scan Timing Diagram
11 TMS, TDI data hold ti m e 15 — ns
12 TCK to TDO data valid 0 15 ns
13 TCK to TDO high impedance 0 15 n s
Notes:
1. TRST is an asynchronous sig nal. The setup t ime is f or test purpo ses only.
2. Nontest (other than TDI and TMS) signal input timing with respect to TCK.
3. Nontest ( other than TDO) signal output timi ng wit h respect to TCK.
Table 15. JTAG AC Timing Specification (Independent of PCI_SYNC_IN) (conti nued)
Num Characteristic Min Max Unit Notes
TCK
22
1
VM
VM
VM
33
VM = Midpoint Voltage
4
5
TRST
TCK
67
Input Data Va li d
8
9
Output Data Valid
TCK
Data Inputs
Data Out puts
Data Out puts
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 31
Pa ck ag e D es cr iption
Figure 23. Test Access Port Timing Di agram
5 Package Description
This section details package parameters, pin assignments, and dimensions.
5.1 Packag e Parameters
The MPC8245 use s a 35 mm × 35 mm, cavity-up, 352-pin tape ball gr id array (TBGA) package. The
package parameter s ar e as follows.
Package Outline 35 mm × 35 mm
Interconnects 352
Pitch 1.27 mm
Solder Ball s ZU (TBGA packag e) —62 Sn/36 Pb/2 Ag
VV (Lead-free version of package)—95. 5 Sn/4.0 Ag/0.5 Cu
Solder Ball Diam eter 0.75 mm
Maximum Module Height 1.65 mm
Co-Planarity Specification 0.15 mm
Maximum Force 6.0 lbs. total, uniformly distributed over package (8 grams/ball)
10 11
Input Data Valid
12
13
Ou tp u t Da ta Valid
TCK
TDI, TMS
TDO
TDO
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
32 Freescale Semiconductor
Package Description
5.2 Pin Assignment s and Package Di men sions
Figure 24 shows the top surfac e, side profile, and pinout of the MPC8245, 352 TBGA package.
Figure 24. MP C8245 Package Dimension s and Pinou t Assignmen ts
B
A
C
– E –
– F –
0.150
– T –
T
H
G
25 23 21 19 17 15 13 11 9 7 5 3 1
A
C
E
G
J
L
N
R
U
W
AA
AC
AE
352X ∅ D
MIN MAX
A 34.8 35.2
B 34.8 35.2
C 1.45 1.65
D.60 .90
G 1.27 BASIC
H.85 .95
K 31.75 BASIC
L.50 .70
To p View
Notes:
26 24 22 20 18 16 14 12 10 8 6 4 2
B
D
F
H
K
M
P
T
V
Y
AB
AD
AF
CORNER
K
L
Bottom View
1. Drawing not to sc ale.
2. All measurem ents are in millimeter s (mm).
K
Dot on top ind ic a tes
c orner of A1 pin on
bottom
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 33
Pa ck ag e D es cr iption
5.3 Pinout Listings
Table 16 provides the pinout listi ng for the MP C8245, 352 TBGA package.
Table 16. MPC8245 Pin out Listing
Name Pin Numbers Type Power
Supply Output
Driver Type Notes
PCI Interface Signals
C/BE[3:0] P25 K23 F23 A25 I/ O OVDD DRV_PCI 6, 15
DEVSEL H26 I/O OVDD DRV_PCI 8, 15
FRAME J24 I/O OVDD DRV_PCI 8, 15
IRDY K25 I/O OVDD DRV_PCI 8, 15
LOCK J26 Input OVDD —8
AD[31:0] V25 U25 U26 U24 U23 T25 T26
R25 R26 N26 N25 N23 M26 M25
L25 L26 F24 E26 E25 E23 D26
D25 C26 A26 B26 A24 B24 D19
B23 B22 D22 C22
I/O OVDD DRV_PCI 6, 15
PAR G25 I/O OVDD DRV_PCI 15
GNT[3:0] W25 W24 W23 V26 Output OVDD DRV_PCI 6, 15
GNT4/DA5 W26 Output OVDD DRV_PCI 7, 15, 14
REQ[3: 0] Y25 AA26 AA25 AB26 Input OVDD —6, 12
REQ4/DA4 Y26 I/O OVDD — 12, 14
PERR G26 I/O OVDD DRV_PCI 8 , 15, 18
SERR F26 I/O OVDD DRV_PCI 8, 15, 16
STOP H25 I/O OVDD DRV_PCI 8, 15
TRDY K26 I/O OVDD DRV_PCI 8, 15
INTA AC26 Output OVDD DRV_PCI 10, 15, 16
IDSEL P26 Input OVDD —
Memory Interface Signals
MDL[0:31] AD17 AE17 AE15 AF15 AC14
AE13 AF13 AF12 AF1 1 AF10 AF9
AD8 AF8 AF7 AF6 AE5 B1 A1 A3
A4 A5 A6 A7 D7 A8 B8 A10 D10
A12 B11 B12 A14
I/O GVDD DR V_STD_MEM 5, 6
MDH[0:31] AC17 AF16 AE16 AE14 AF14
AC13 AE12 AE11 AE10 AE9 AE8
AC7 AE7 AE6 AF5 AC5 E4 A2 B3
D4 B4 B5 D6 C6 B7 C9 A9 B10
A11 A13 B13 A15
I/O GVDD DRV_STD_MEM 6
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
34 Freescale Semiconductor
Package Description
DQM[0:7] AB1 AB2 K3 K2 AC1 AC2 K1 J1 Output GVDD DRV_MEM_CTRL 6
CS[0:7] Y4 AA3 AA4 AC4 M2 L2 M1 L1 Output GVDD DRV_MEM_CTRL 6
FOE H1 I/O GVDD DR V_MEM_CTRL 3, 4
RCS0 N4 Output GVDD DRV_MEM_CTRL 3, 4
RCS1 N2 Output GVDD DRV_MEM_CTRL
RCS2/TRIG_IN AF20 I/O OVDD 6 ohms 10, 14
RCS3/TRIG_OUT AC18 Output GVDD DRV_MEM_CTRL 14
SDMA[1:0] W1 W2 I/O G VDD DRV_MEM_CTRL 3, 4, 6
SDMA[11:2] N1 R1 R2 T1 T2 U4 U2 U1 V1 V3 Out put GV DD DRV_MEM_CTRL 6
DRDY B20 Input OVDD —9, 10
SDMA12/SRESET B16 I/O GVDD DRV_MEM_CTRL 10, 14
SDMA13/TBEN B14 I/O GVDD DR V_MEM_CTRL 10, 14
SDMA14/
CHKSTOP_IN D14 I/O GVDD DRV_MEM_CTRL 10, 14
SDBA1 P1 Output GVDD DRV_MEM_CTRL
SDBA0 P2 Output GVDD DRV_MEM_CTRL
PAR[0:7] AF3 AE3 G4 E2 AE4 AF4 D2 C2 I/O GVDD DRV_STD_MEM 6
SDRAS AD1 Output GVDD DRV_MEM_CTRL 3
SDCAS AD2 Output GVDD DRV_MEM_CTRL 3
CKE H2 Output GVDD DRV_MEM_CTRL 3, 4
WE AA1 Output GVDD DRV_MEM_CTRL
AS Y1 Output GVDD DRV_MEM_CTRL 3, 4
PIC Control Signals
IRQ0/S_INT C19 Input OVDD —
IRQ1/S_CLK B21 I/O OVDD DRV_PCI
IRQ2/S_RST AC22 I/O OVDD DRV_PCI
IRQ3/S_FRAME AE24 I/O OVDD DRV_PCI
IRQ4/L_INT A23 I/O OVDD DRV_PCI
I2C Control Signals
SDA AE20 I/O OVDD DRV_STD_MEM 10, 16
SCL AF21 I/O OVDD DRV_STD_MEM 10, 16
Ta ble 1 6. MPC8245 Pinout Listing (continued )
Name Pin Numbers Type Power
Supply Output
Driver Type Notes
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 35
Pa ck ag e D es cr iption
DUART Control Signal s
SOUT1/PCI_CLK0 AC25 Output GVDD DRV_MEM_CTRL 13, 14
SIN1/PCI_CLK1 AB25 I/O GVDD DRV_MEM_CTRL 13, 14, 26
SOUT2/RTS1/
PCI_CLK2 AE26 Output GVDD DR V_MEM_CTRL 13, 14
SIN2/CTS1/
PCI_CLK3 AF25 I GVDD DRV_MEM_CTRL 13, 14, 26
Clock-Out Signals
PCI_CLK0/SOUT1 AC25 Output GVDD DRV_PCI_CLK 13, 14
PCI_CLK1/SIN1 AB25 Output GVDD DRV_PCI_CLK 13, 14, 26
PCI_CLK2/RTS1/
SOUT2 AE26 Output GVDD DRV_PCI _CLK 13, 14
PCI_CLK3/CTS1/
SIN2 AF25 Output GVDD DRV_PCI_CLK 13, 14, 26
PCI_CLK4/DA3 AF26 Output GVDD DRV_PCI_CLK 13, 14
PCI_SYNC_OUT AD25 Output GVDD DRV_PCI_CLK
PCI_SYNC_IN AB23 Input GVDD —
SD RA M _ C L K [0 :3 ] D1 G 1 G2 E1 Ou tp u t G VDD DRV_MEM_CTRL
or
DRV_MEM_CLK
6, 21
SDRAM_SYNC_OUT C1 Output GVDD DRV_MEM_CTRL
or
DRV_MEM_CLK
21
SDRAM_SYNC_IN H3 Input GVDD —
CKO/DA1 B15 Output OVDD DRV_STD_MEM 14
OSC_IN AD21 Input OVDD —19
Miscellaneous Signals
HRST_CTRL A20 Input OVDD —27
HRST_CPU A19 Input OVDD —27
MCP A17 Output OVDD DRV_STD_MEM 3, 4, 17
NMI D16 Input OVDD —
SMI A18 Input OVDD —10
SRESET/SDMA12 B16 I/O GVDD DRV_MEM_CTRL 10, 14
TBEN/SDMA13 B14 I/O GVDD DR V_MEM_CTRL 10, 14
Ta ble 1 6. MPC8245 Pinout Listing (continued )
Name Pin Numbers Type Power
Supply Output
Driver Type Notes
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
36 Freescale Semiconductor
Package Description
QACK/DA0 F2 Output OVDD DRV_STD_MEM 4 , 14, 25
CHKSTOP_IN/
SDMA14 D14 I/O GVDD DRV_MEM_CTRL 10, 14
TRIG_IN/RCS2 AF20 I/O OVDD — 10, 14
TRIG_OUT/RCS3 AC18 Output GVDD DRV_MEM_CTRL 14
MAA[0:2] AF2 AF1 AE1 Output GVDD DRV_STD_MEM 3, 4, 6
MIV A16 Output OVDD —24
PMAA[0:1] AD18 AF18 Output OV DD DRV_STD_MEM 3, 4, 6, 15
PMAA[2] AE19 Output OVDD DRV_STD_MEM 4, 6, 15
Test/Confi guration Signals
PLL_CFG[0:4]/
DA[10:6] A22 B19 A21 B18 B17 I/O OVDD DR V_STD_M EM 6, 14, 20
TEST0 AD22 Input OVDD —1, 9
RTC Y2 Input GVDD —11
TCK AF22 Input OVDD —9, 12
TDI AF23 Input OVDD —9, 12
TDO AC21 Output OVDD —24
TMS AE22 Input OVDD —9, 12
TRST AE23 Input OVDD —9, 12
Power and Ground Signals
GND AA2 AA23 AC12 AC15 AC24 AC3
AC6 AC9 AD1 1 AD14 AD16 AD19
AD23 AD4 AE18 AE2 AE21 AE25
B2 B25 B6 B9 C11 C13 C16 C23
C4 C8 D12 D15 D18 D21 D24 D3
F25 F4 H24 J25 J4 L24 L3 M23
M4 N24 P3 R23 R4 T24 T3 V2
V23 W3
Ground — —
LVDD AC20 AC23 D20 D23 G23 P23
Y23 Reference
voltage
3.3 V, 5.0 V
LVDD —
GVDD AB3 AB4 AC10 AC11 AC8 AD10
AD13 AD15 AD3 AD5 AD7 C10
C12 C3 C5 C7 D13 D5 D9 E3 G3
H4 K4 L4 N3 P4 R3 U3 V4 Y3
Po w e r fo r
memory drivers
3.3 V
GVDD —
OVDD AB24 AD20 AD24 C14 C20 C24
E24 G24 J23 K24 M24 P24 T23
Y24
PCI/Stnd 3.3 V OVDD —
Ta ble 1 6. MPC8245 Pinout Listing (continued )
Name Pin Numbers Type Power
Supply Output
Driver Type Notes
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 37
Pa ck ag e D es cr iption
VDD AA24 AC16 AC19 AD12 AD6 AD9
C15 C18 C21 D11 D8 F3 H23 J3
L23 M3 R24 T4 V24 W4
Power for core
1.8/2.0 V VDD —22
No Connect D17 — — — 23
AVDD C17 Power for PLL
(CPU core logic)
1.8/2.0 V
AVDD —22
AVDD2 AF24 Power for PLL
(peripheral
logic)
1.8/2.0 V
AVDD2— 22
Debug/Manufacturing Pi ns
DA0/QACK F2 Output OVDD DR V_STD_M EM 4, 10, 25
DA1/CKO B15 Output OVDD DRV_STD_MEM 14
DA2 C25 Output OVDD DRV_PCI 2
DA3/PCI_CLK4 AF26 Output GVDD DRV_PCI_CLK 14
DA4/REQ4 Y26 I/O OVDD — 12, 14
DA5/GNT4 W26 Output OVDD DRV_PCI 7, 15, 14
DA[10:6]/
PLL_CFG[0:4] A22 B19 A21 B18 B17 I/O OVDD DRV_STD_MEM 6, 14, 20
DA[11] AD26 Output OVDD DRV_PCI 2
DA[12:13] AF17 AF19 Output OVDD DRV_STD_MEM 2, 6
Ta ble 1 6. MPC8245 Pinout Listing (continued )
Name Pin Numbers Type Power
Supply Output
Driver Type Notes
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
38 Freescale Semiconductor
Package Description
DA[14:15] F1 J2 Output GVDD DRV_MEM_CTRL 2, 6
Notes:
1. Place a pull-up resis tor of 120 Ω or less on the TEST0 pin.
2. Treat these pins as no connects (NC) unless debug address functionality is used.
3. This pi n h as an int ernal pull -up res istor that is enab led only i n the r eset st at e. The v alue of th e inte rnal pu ll- up resi stor i s not
guarant eed but is s ufficient to ens ure that a logic 1 is r ead into co nfi guration bits during reset if the signal is left unterminated.
4. This pin i s a reset configuration pin.
5. DL[0] is a reset configuration pin with an internal pull-up resistor that is enabled only in the reset state. The value of the
inter nal pull -up resi stor is not guaranteed but is suf ficien t to ensure that a logic 1 is r ead into confi guration bits during reset.
6. Multi -pin signa ls such as AD[ 31:0] and MDL[0: 31] have thei r physical package pin numbers list ed in an order co rr esponding
to the signal names. Example: AD0 is on pin C22, AD1 is on pin D22, ..., AD31 is on pin V25.
7. GNT4 is a reset configuration pin with an i nternal pull- up resistor that is enabl ed only in the reset st ate.
8. A weak pull- up resisto r (2– 10 kΩ) should be placed on this PCI control pin t o LVDD.
9. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3.
10.A weak pull-up resistor (2–10 kΩ) should be placed on th is pi n to OVDD.
11. A we ak pull-up resistor (2–10 kΩ) should be placed on this pin to GVDD.
12.This pin h as an inte rnal pull- up resist or that is enabled a t all t imes . The va lue of the i nte rnal pull-up resi stor is not guaranteed
but is sufficient to prevent unused inputs from floating.
13.An external PCI clocking source or fan-out buffer may be required for the MPC8245 DUART functionality since
PCI_CLK[0:3] are not availa ble i n DUART mode. Only PCI_CLK4 is avai la ble i n DUART m ode.
14.This pin is a multi plexed signal and appears more than once i n this table.
15.This pin is aff ected by the program m able PCI_HOLD_DEL paramet er.
16.This pin is an open-drain signal.
17.This pin can be programm ed as driven (default) or as open-drain (in MIOCR 1).
18.This pin is a sustai ned three-st ate pin as defined by the PCI Local Bus Specificati on.
19.OSC_IN uses the 3.3-V PCI int erf ace driver, which is 5-V tolerant. See Table 2 for details.
20.PLL_CFG signals must be driven on reset and must be held for at least 25 clock cyc les after the negati on of HRST_CTRL
and HRST_CPU in order to be lat ched.
21.SDRAM_CLK[0:3] and SDRAM_SYNC_OUT sig nals use DRV_MEM_CTRL for chi p Rev 1.1 ( A). These signa ls us e
DRV_MEM_CLK f or chi p Rev 1.2 ( B).
22.The 266- and 300-MHz p art offerings can run at a sourc e voltage of 1.8 ± 100 m V or 2.0 ± 100 mV. Source v oltage should
be 2.0 ± 100 mV for 333- and 350-MHz parts.
23.This pin is LAVDD on the MPC8240. It is an NC on the MPC8245, which should not pose a problem when an MPC824 0 is
repla ced wit h an M PC8245.
24.The driver capa bility of this pi n is hardwired to 40 Ω and cannot be changed.
25.A weak pull-up resistor (2–10 kΩ) should be placed on th is pi n to OVDD so that a 1 can be detected at reset if an external
memory clock is not used and PLL[0:4] does not select a half- clock frequency ratio.
26.T ypica lly, the seria l port has suf f icient dr ivers in the RS232 transce iv er to drive th e CTS pin act ivel y as an input . No pullu ps
are needed in this case.
27. HRST_CPU/HRST_CTRL must transi tion f rom a logic 0 to a logic 1 in le ss than one SDRAM_SYNC_ IN clock cy cle for t he
device to be in the nonreset state
Ta ble 1 6. MPC8245 Pinout Listing (continued )
Name Pin Numbers Type Power
Supply Output
Driver Type Notes
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 39
PLL Config uratio ns
6 PLL Configurations
The internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN (PCI bus)
frequency , the PLL configuration signals set both the peripheral logic/memory bus PLL (VC O) frequency
of operation for the PCI-to-memory frequ ency multiplying and the MPC603e CPU PLL (VCO) frequency
of operation for memory -to-CPU fre quenc y multiplying. The PLL configurations are shown in Table 17
and Table 18.
Ta ble 17 . PLL Configurations (266- and 300-MHz Parts)
Ref. No. PLL_CFG
[0:4] 10,13
266-MH z Part 9300-MHz Part 9Multipliers
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/
MemBus
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/
MemBus
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI-to-
Mem
(Mem
VCO)
Mem-to-
CPU
(CPU
VCO)
0 0000012 25–35575–105 188–263 25–405,7 75–120 188–300 3 (2) 2.5 (2)
1 0000112 25–29575–88 225–264 25–33575–99 225–297 3 (2) 3 (2)
2 0001011 5018–595,7 50–59 225–266 5018–66150–66 225–297 1 (4) 4.5 (2)
300011
11,14 5017–66150–66 100–133 5017–66150–66 100–133 1 (Bypass) 2 (4)
4 0010012 25–46450–92 100–184 25–46450–92 100–184 2 (4) 2 (4)
6 0011015 Bypass Bypass Bypass
7
Rev B 0011114 606–66160–66 180–198 606–66160–66 180–198 1 (Bypass) 3 (2)
7
Rev D 0011114 Not available
8 0100012 606–66160–66 180–198 606–66160–66 180–198 1 (4) 3 (2)
9 0100112 456–66190–132 180–264 456–66190–132 180–264 2 (2) 2 (2)
A 0101012 25–29550–58 225–261 25–33550–66 225–297 2 (4) 4.5 (2)
B 0101112 453–59568–88 204–264 453–66168–99 204–297 1.5 (2 ) 3 (2)
C 0110012 366–46472–92 180–230 366–46472–92 180–230 2 (4) 2.5 (2)
D 0110112 453–50568–75 238–263 453–57568–85 238–298 1.5 (2 ) 3.5 (2)
E 0111012 306–44560–88 180–264 306–46460–92 180–276 2 (4) 3 (2)
F 0111112 255 75 263 25–285 75–85 263–298 3 (2) 3.5 (2)
10 1000012 306–442,5 90–132 180–264 306–44290–132 180–264 3 (2) 2 (2)
11 1000112 25–265,7 100–106 250–266 25–292100–116 250–290 4 (2) 2.5 (2)
12 1001012 606–66190–99 180–198 606–66190–99 180–198 1.5 (2) 2 (2)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
40 Freescale Semiconductor
PLL Config uratio ns
13 1001112 Not avail able 252,7 100 30 0 4 (2 ) 3 (2 )
14 1010012 266–38552–76 182–266 266–42552–84 182–294 2 (4) 3.5 (2)
15 1010112 Not avail able 273–305,7 68–75 272–300 2.5 (2) 4 (2)
16 1011012 25–33550–66 200–264 25–37550–74 200–296 2 (4) 4 (2)
17 1011112 25–335100–132 200–264 25–332100–132 200–264 4 (2) 2 (2)
18 1100012 273–35568–88 204–264 273–405,7 68–100 204–300 2.5 (2 ) 3 (2)
19 1100112 366–53572–106 180–265 366–59272–118 180–295 2 (2) 2.5 (2)
1A 1101012 5018–66150–66 200–264 5018–66150–66 200–264 1 (4) 4 (2)
1B 1101112 343–44568–88 204–264 343–505,7 68–100 204–300 2 (2) 3 (2)
1C 1110012 443–59566–88 198–264 443–66166–99 198–297 1.5 (2) 3 (2)
1D 1110112 486–66172–99 180–248 486–66172 –99 180–248 1.5 (2) 2. 5 (2)
1E
Rev B 111108Not usable Not usabl e Off Off
1E
Rev D 11110 333–38566–76 231–266 333–42566–84 231–294 2(2) 3.5(2)
Tab le 17. PLL Configuration s (266- and 300-MHz Parts) (continued)
Ref. No. PLL_CFG
[0:4] 10,13
266-MH z Part 9300-MHz Part 9Multipliers
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/
MemBus
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/
MemBus
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI-to-
Mem
(Mem
VCO)
Mem-to-
CPU
(CPU
VCO)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 41
PLL Config uratio ns
1F 111118Not usable Not usable Off Off
Notes:
1. Lim it ed by the maximum PCI input f requency (66 MHz).
2 Limit ed by the maximum sys tem me mo ry i nterface operating fr equency (100 MHz @ 300 MHz CPU).
3. Lim it ed by the minimum memor y VCO frequency (133 MHz).
4. Lim it ed due to the maximum memor y VCO f requency (372 MHz).
5. Limited by the maximum CPU operating freque ncy.
6. Limited by the minimum CPU VCO frequency ( 360 M H z).
7. Limit ed by the maximum CPU VCO frequency (maximum marked CPU speed X 2).
8. In clock-of f mode, no clocki ng occurs inside the MP C8245, regar dless of the PCI_SYNC_IN input.
9. Range values are rounded down to the nearest whole number (decimal place accuracy removed).
10.PLL_CFG[0:4] settings not listed are reserved.
11. Multiplier ratios for thi s PLL_CFG[0:4] setting differ fr om the MPC8240 and are not backward-compatible.
12.PCI_SYNC_IN range fo r this PLL_CFG[0:4] setting differs from or does not exist on the MPC8240 and may not be ful ly
backward-compatible.
13.Bits 7–4 of regist er offs et <0xE2> contai n the PLL_CFG[0:4] se tt ing value.
14.I n PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is
disabl ed, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode i s for hardware mode li ng. The AC timing
specif icati ons in this document do not apply in PLL bypas s mo de.
15.In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic
PLL is dis abled, and the bus mode is set f or 1: 1 (PCI_SYNC_IN:Mem) mode operatio n. I n thi s mo de, t he O SC_IN input
signal clocks the internal process or directly in 1:1 (O SC_IN: CPU) mode operation, and the processor PLL is disabled. The
PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. T his mode is fo r hardware modeling. The AC
timing specifications in this document do not apply in dual PLL bypass mode.
16.Limited by th e maximum system memory interface ope rating frequency (133 MHz @ 266 MHz CPU).
17.Limited by the minimum CPU operating frequency (100 MHz).
18.Limited by th e minimum memory bus fr equency (50 MHz) .
Ta ble 18 . PLL Configurations (333- and 350-MHz Parts)
Ref PLL_
CFG[0:4] 10,13
333 MHz Part 9350 MHz Part 9Multipliers
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/Mem
Bus Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/Mem
Bus Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI-to-
Mem
(Mem
VCO)
Mem-to-
CPU
(CPU
VCO)
0 0000012 25–4416 75–132 188–330 25–4416 75–132 188–330 3 (2) 2. 5 (2)
1 0000112 25–375,7 75–111 225–333 25–38575–114 225–342 3 (2) 3 (2)
Tab le 17. PLL Configuration s (266- and 300-MHz Parts) (continued)
Ref. No. PLL_CFG
[0:4] 10,13
266-MH z Part 9300-MHz Part 9Multipliers
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/
MemBus
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/
MemBus
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI-to-
Mem
(Mem
VCO)
Mem-to-
CPU
(CPU
VCO)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
42 Freescale Semiconductor
PLL Config uratio ns
2 0001011 5018–66150–66 225–297 5018–66150–66 225–297 1 (4) 4.5 (2)
300011
11,14 5017–66150–66 100–133 5017–66150–66 100–133 1 (Bypass) 2 (4)
4 0010012 25–46450–92 100–184 25–46450–92 100–184 2 (4) 2 (4)
6 0011015 Bypass Bypass Bypass
7
Rev B 0011114 606–66160–66 180–198 606–66160–66 180–198 1 (Bypass ) 3 (2)
7
Rev D 0011114 Not available 25 100 350 4(2) 3.5(2)
8 0100012 606–66160–66 180–198 606–66160–66 180–198 1 (4) 3 (2)
9 0100112 456–66190–132 180–264 456–66190–132 180–264 2 (2) 2 (2)
A 0101012 25–375,7 50–74 225–333 25–38550–76 225–342 2 (4 ) 4.5 (2)
B 0101112 453–66168–99 204–297 453–66168–99 204–297 1.5 (2) 3 (2)
C 0110012 366–46472–92 180–230 366–46472–92 180–230 2 (4) 2.5 (2)
D 0110112 453–635,7 68–95 238–333 453–66168–99 238–347 1.5 (2) 3.5 (2)
E 0111012 306–46460–92 180–276 306–46460–92 180–276 2 (4) 3 (2)
F 0111112 25–315 75–93 263–326 25–335 75–99 263–347 3 (2) 3.5 (2)
10 1000012 306–44290–132 180–264 306–44290–132 180–264 3 (2) 2 (2)
11 1000112 25–332,16 100–132 250–330 25–332,16 100–132 250 –330 4 (2) 2. 5 (2)
12 1001012 606–66190–99 180–198 606–66190–99 180–198 1.5 (2) 2 (2)
13 1001112 25–275100–108 300–324 25–295100–116 300–348 4 (2) 3 (2)
14 1010012 266–47452–94 182–329 266–47452–94 182–329 2 (4) 3.5 (2)
15 1010112 273–33568–83 272–332 273–34568–85 272–340 2.5 (2) 4 (2)
16 1011012 25–41550–82 200–328 25–43550–86 200–344 2 (4) 4 (2)
17 1011112 25–332100–132 200–264 25–332100–132 200–264 4 (2 ) 2 (2)
18 1100012 273–44568–110 204–330 273–46568–115 204–345 2.5 (2) 3 (2)
19 1100112 366–66172–132 180–330 366–66172–132 180–330 2 (2) 2. 5 (2)
1A 1101012 5018–66150–66 200–264 5018–66150–66 200–264 1 (4) 4 (2)
1B 1101112 343–55568–110 204–330 343–58568–116 204–348 2 (2) 3 (2)
1C 1110012 443–66166–99 198–297 443–66166–99 198–297 1.5 (2) 3 (2)
1D 1110112 486–66172–99 180–248 486–66172–99 180–248 1.5 (2) 2.5(2)
Tab le 18. PLL Configuration s (333- and 350-MHz Parts) (continued)
Ref PLL_
CFG[0:4] 10,13
333 MHz Part 9350 MHz Part 9Multipliers
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/Mem
Bus Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/Mem
Bus Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI-to-
Mem
(Mem
VCO)
Mem-to-
CPU
(CPU
VCO)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 43
PLL Config uratio ns
1E
Rev B 111108Not usable Not usable Off Off
1E
Rev D 11110 333–47566–94 231–329 333–502,5,7 66–100 231–350 2(2) 3.5(2)
1F 111118Not usable Not usable Off Off
Notes:
1. Lim it ed by the maximum PCI input f requency (66 MHz).
2. Lim it ed by the maximum sys tem me mo ry i nterface operating fr equency (100 MHz @ 350 MHz CPU).
3. Lim it ed by the minimum memor y VCO frequency (132 MHz).
4. Lim it ed due to the maximum memor y VCO f requency (372 MHz).
5. Limited by the maximum CPU operating freque ncy.
6. Limited by the minimum CPU VCO frequency ( 360 M H z).
7. Limit ed by the maximum CPU VCO frequency (Maximum marked CPU speed X 2).
8. In clock-of f mode, no clocki ng occurs inside the MP C8245, regar dless of the PCI_SYNC_IN input.
9. Range values are rounded down to the nearest whole number (decimal place accuracy removed).
10.PLL_CFG[0:4] settings not listed are reserved.
11. Multipl ier ratios for thi s PLL_CFG[ 0:4] setting differ fr om or do not exist on the MP C8240 and a re not backward-compatible.
12.PCI_SYNC_IN range fo r this PLL_CFG[0:4] setting differs from the MPC8240 and may not be ful ly backward- com patibl e.
13.Bits 7–4 of regist er offs et <0xE2> contai n the PLL_CFG[0:4] se tt ing value.
14.I n PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is
disabl ed, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode i s for hardwar e modeli ng. The AC timing
specif icati ons in this document do not apply in PLL bypas s mo de.
15.In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic
PLL is dis abled, and the bus mode is set f or 1:1 (PCI_SYNC_IN:Mem ) mode operatio n. I n thi s mo de, t he O S C_IN i nput
signal clocks the internal process or directly in 1:1 (O SC_IN: CPU) mode operation, and the processor PLL is disabled. The
PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. T his mode is fo r hardware modeling. The AC
timing specifications in this document do not apply in dual PLL bypass mode.
16.Limited by th e maximum system memory interface ope rating frequency (133 MHz @ 333 MHz CPU).
17.Limited by the minimum CPU operating frequency (100 MHz).
18.Limited by th e minimum memory bus fr equency (50 MHz) .
Tab le 18. PLL Configuration s (333- and 350-MHz Parts) (continued)
Ref PLL_
CFG[0:4] 10,13
333 MHz Part 9350 MHz Part 9Multipliers
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/Mem
Bus Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/Mem
Bus Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI-to-
Mem
(Mem
VCO)
Mem-to-
CPU
(CPU
VCO)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
44 Freescale Semiconductor
System Design
7 System Design
This section provides electrical and thermal design recommendations for succes sful application of the
MPC8245.
7.1 PLL Power Supply Filtering
The AVDD and AVDD2 power signal s on the MPC8245 pr ovide power to the per ipheral logic/memory bus
PLL and the MPC603e processor PLL. T o ensure stability of the internal clocks, the power supplied to the
AVDD and AVDD2 input signals should be filtered of any noise in the 500-kHz to 10-MHz resonant
frequency range of the PLLs. Two separate circuits similar to the one shown in Figure 25 using surface
mount capacitors with minimum effective series inductance (ESL) is recommended for AVDD and AVDD2
power signal pins. Consis tent with the recommendations of Dr. Howard Johnson in High Speed Digital
Design: A Handbook of Black Magic (Prentice Hall, 1993), using multiple small capacitors of equal value
is recommended over using multiple values.
Place the circuits as closely as possible to the respective input signal pins to minimize noise coupled from
nearby circuits. Routi ng from the capacitor s to the input signal pins should be as direct as possible with
minimal inductance of vias.
Figure 25. PLL Power Supply Filter Circuit
7.2 Decoupling Reco mm endations
Due to its dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC8245 can gener ate transient power surges and high frequency noise in its power
supply, especially while driving lar ge capacitive loads. T his noise m ust be prevented from r eaching other
components in the MPC8245 system, and the MPC8245 itself requires a clean, tightly regulated source of
power. The refore, place at lea st one decoupling capacitor at each VDD, OVDD, GV DD, and LVDD pin.
These decoupling capacitors should receive their power from dedicated power planes in the PCB, with
short traces to minimize inductance. These capacitors should have a value of 0.1 µF. Only ceramic SMT
(surface mount technolog y) capacitors should be used to minimize lead inductance, preferably 0508 or
0603, oriented suc h that connections are made along the length of the part.
In addition, several bulk storage capacitors should be distributed around the PCB, feeding the VDD, OVDD,
GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR ( equivalent series resi stance) rating to ens ure the quick response time necessary.
They should also be connected to the power and gro und planes through two vias to minimize inductance.
Suggested bulk capa citors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON ).
VDD AVDD or AVDD2
2.2 µF 2.2 µF
GND Low ESL Sur face Mount Capacitors
10 Ω
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 45
System Desi gn
7.3 Connecti o n Recom mend ations
To ensure reliable operation, connect unused inputs to an appropriate signal level. Tie unused active-low
inputs t o OVDD. Connect unused active-high input s tie to GND. All NC signals must remain unconnected.
Power and ground connections must be made to al l external VDD, OVDD, G V DD, LVDD, and GND pins.
The PCI_SYNC_OUT sig nal is to be routed halfway out to the PCI devices and returned to the
PCI_SYNC_IN input of the MPC8245.
The SDRAM_SYNC_OUT s ignal is to be routed halfway out to the SDRAM d evices and then r et urned to
the SDRAM_SYNC_IN input of the MPC8245. The trace length can be used to skew or adjus t the timing
window as needed. See t he T undra Tsi107™ Design Guide (AN1849) and Freescale appl icat ion notes
AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines: Part 1 and AN2746,
MPC8245/MPC8241 Memory Clock Design Guidelines: Part 2 for details. Note that there is an
SDRAM_SYNC_IN to PCI_SYNC_IN time requirement (refer to Table 10 for the input AC timing
specifications).
7.4 Pu ll- Up/P u ll -Down R e sistor Req u irem ent s
The data bus input r eceivers are no rmally turned off when no r ead o peration is in progress; therefore, they
do not require pull-up res istors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and
PAR[0:7].
If the 32-bit data bus m ode is selected, the i nput receivers of the unu sed data and parity bits (MDL[0:31]
and PAR[4:7]) are dis abled, and their outputs drive logic zer os when they would otherwise normally be
driven. For this mode, these pins do not require pull-up resistors and should be left unconnected to
minimize possible output s witching.
The TEST0 pin requires a pull-up resistor of 120 Ω or less connected to OVDD.
RTC should have weak pull-up resis tors (2–10 kΩ) connected to GVDD.
The following signals should be pulled up to OVDD with weak pull-up resis tors (2–10 kΩ): SDA, SCL,
SMI, SRES ET/SDMA12, TBEN/SDMA13, CHKST OP_IN/SDM A14, TRIG_IN/RCS2, INTA,
QACK/DA0 and DRDY. Note that QACK/DA0 should be left without a pull-up resistor only if an external
clock is used because this signal enables internal clock flipping logic when it is low on reset, which is
necessar y when the PLL[0:4] signals select a half-cl ock frequency r ati o and an e xte rnal PLL is used to
drive the SDRAM device.
It is recommended that the following PCI control signals be pulled up to L VDD (the clamping voltage) with
weak pull-up resi stors (2–10 kΩ): DEVSEL, FRA ME, IR DY, LOCK, PERR, SER R, ST O P, and TRDY.
The resistor values may need to be adjust ed stronger to reduce induced nois e on specific board des igns.
The following pins have internal pull-up resistors enabled at all times: REQ[3:0], REQ4/DA4, TCK, T DI,
TMS, and TRST. Se e Table 16.
The following pins have internal pull-up resistors enabled only while device is in the rese t state:
GNT4/DA5 , MDL0, FOE, RCS0 , SDRAS, SD CAS , CK E, AS, MC P, MAA[0:2], and PM AA[ 0:2]. See
Table 16.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
46 Freescale Semiconductor
System Design
The following pins are reset configuration pins: GN T4/D A5, MDL[0], FOE , RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These
pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks
after the ne gation of HRST_CPU and HRST_CTRL.
Reset configuration pins s hould be tied to GND via 1-kΩ pull-down resistors to ens ure a logic 0 level is
read into the configuration bits during reset if the default logic 1 level is not desired.
Any other unused active low input pins should be tied to a logic-one level through weak pull-up resistors
(2–10 kΩ) to the appropriate power supply listed in Table 16. Unused active high input pins should be tied
to GND through weak pull-down re sistors (2–10 kΩ).
7.5 PCI Referen ce Voltage—LVDD
The MPC8245 PCI reference voltage (LVDD) pins should be connected to a 3.3 ± 0.3 V power supply if
interfacing the MPC8245 into a 3.3-V PCI bus system. Similarly, the LVDD pins should be connected to
a 5.0 V ± 5% power s upply if interfacing the MPC8245 into a 5-V PCI bus system. For either reference
voltage, the MPC8245 always perf orms 3.3-V signaling as described in t he PCI Local Bus Specification
(Rev. 2.2). The MPC8245 toler ates 5-V signals whe n interfaced into a 5-V PCI bus syste m.
7.6 MPC8245 Compatibility with MPC8 240
The MPC8245 AC timing specifications are backward-compatible with those of the MPC8240, except for
the requirements of item 11 in Table 10. Timing adjustments are needed as specified for Tos
(SDRAM_SYNC_IN to sys_logic_clk offset) time requirements.
The MPC8245 does not support the SDRAM flow-through memory interface .
The nominal core VDD power supply changes from 2.5 V on the MPC8240 to 1.8/2.0 V on the MPC8245.
See Table 2.
For example, the MPC8245 PLL_CFG[0:4] s etting 0x02 (0b00010) has a different PCI-to-M em and
Mem-to-CPU multipli er ratio than the same setting on the MPC8240, so it is not backward-compatible.
See Table 17.
Most of the MPC8240 PLL_CFG[0:4] settings ar e subsets of the PCI_SYNC_IN input frequency range
accepted by the MPC8245. However , the parts are not fully backward-compatible since the ranges of the
two parts do not always match. Modes 0x8 and 0x18 of the MPC8245 are not compatible with settings 0x8
and 0x18 on the MPC8240. See Table 17 and Table 18.
Two reset configurati on signals on the MPC8245 are not used as reset configuration signals on the
MPC8240: SDMA0 and SDMA1.
The SDMA0 reset configuration pin selec ts between the MPC 8245 DUART and the MPC8240
backward-compatible mode PCI_CLK[0:4] functionality on these multiplexed signals. The default state
(logic 1) of SDMA0 se lects the MPC8240 bac kward-compatible mode of PCI_CLK[0:4] f unctionality
while a logic 0 sta te on the SDMA0 signa l selects DUART functionality. In DUART mode, four of the
five PCI clocks, PCI_CLK[0:3], are not available.
The SDMA1 reset configuration pin selects between MPC8245 extended R OM functionality and
MPC8240 backward-compatible functionality on the multiplexed signals: TBEN, CHKST OP_IN,
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 47
System Desi gn
SRESET, TRIG_I N, and TRIG_OUT. The default state (logic 1) of SDMA1 selects the MPC8240
backward-compatible mode func tiona lity, while a logic 0 state on the SDMA1 signal selects extended
ROM functionality. In ext ended ROM mode, the TBEN, CHKSTOP _IN, S RESE T, TRIG_IN, and
TRIG_OUT functionalities are not available.
The driver names and pin capability of the MPC 8245 and the MPC 8240 dif f er s lightly. Refer to the drive
capability table (f or the ODCR regis ter at 0x73) in the MPC8240 Integrated Pr ocessor Hardwar e
Specifications and Table 4.
The programmable PCI output valid and output hold feature controlled by bits in the power management
configuration register 2 (PMCR2) <0x72> dif fers slightly in the MPC824 5. For the MPC8240, three bit s,
PMCR2[6:4] = PCI_HOLD_DEL, are used to select 1 of 8 possible PCI output timing configurations.
PMCR2[ 6:5] are s oftware-contr ollable but are in itially s et by the reset conf iguration state of t he MCP and
CKE signals, respectively. Sof tware can change PMCR2[4]. The default configuration for PMCR2[6:4] =
0b110 since the MCP and C KE signals have internal pull-up re sistors, but this default configuration does
not select 33- or 66-MHz PCI operation output timing parameters for the MPC8240. Soft ware makes this
selection. For the MPC 8245, only two bits in the power management configuration register 2 ( PMCR2),
PMCR2[5:4] = PCI_HOLD_DEL, control the variable PCI output timing. PMCR 2[5:4] are software
controllable but are initially set by the inverted rese t configuration state of the MCP and CKE signals ,
respectively. Th e default configuration for PMCR2[5:4] = 0b00 since the MCP and CKE signals have
internal pull-up resistors and the values from these signals are inverted; this defa ult configuration selects
66-MHz PCI operation output timing parameters. There are four programmable PCI output timing
configurations on the MPC8245. See Table 11.
Voltage s equencing requirements f or the MP C8245 are s imilar to those for the MPC8240, with two
exceptions in the MPC8245. In the MP C8245, the non-PCI input voltages (Vin) must not be greater than
GVDD or OVDD by more tha n 0.6 V at all times, including during power-on res et (see Caution 5 in
Table 2). Second, LVDD must not exceed OVDD by more than 3.0 V at any time, including during
power-on reset (see Caution 10 in Table 2); the all owable separation between LVDD and OVDD is 3.6 V
for the MPC8240.
There is no LAV DD input voltage supply signal on the MP C8245 since the SDRAM clock delay-locked
loop (DLL) has power supplied internally. Signal D17 should be treated as a NC for the MPC8245.
Application note AN2128 highlights the differences between the MPC8240 and the MPC8245.
7.7 JTAG Configuration Si gnals
Boundary scan testing is enabl ed through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification but is provided on all proc ess ors that impleme nt the Power Architecture
technology . While the TAP controller can be forced to the reset state using only the TCK and TMS signals,
more reliable power -on reset performance can be obtained if the TRST si gnal is asserted during po wer -on
reset. Because the JTAG interface is also used f or accessing the common on-chip processor (COP)
function, simply tying TRST t o HRES ET is not pr acti cal.
The COP function of these process or s allows a remote computer sys tem (typically, a PC with dedicated
hardware and debugging software) to access and control the i nternal operations of the processor . The COP
interface connect s primarily through the JTAG, with additional status monitoring signals. The COP port
must independently assert HRESET or TRST to control the processor . If the target system has independent
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
48 Freescale Semiconductor
System Design
reset sources, such as voltage monitors, watchdog timers, power supply failur es, or push-button switches,
the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 26 allows the COP port to independently assert HRESET or TRST,
while ensuring that the targe t can drive HRESET as well . If the JTAG interface and COP header will not
be used, TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is ass e rted when the
sys t em reset sign al (H RES E T) is asserted, ensuring that the JTAG scan chain is initialize d during
power- on. Although Freescale r ecommends that the COP header be desi gned into the system as shown in
Figure 26, if this is not possible , the isolation resis tor will a llow future acces s to TRST in the case where
a JTAG interface may need to be wired onto the system in debug situations .
The COP interface has a standard header for connection to the target system based on the 0.025"
square-post, 0.100" centered header assembly (often cal led a Be r g header). Typically, pin 14 is removed
as a connector key.
There is no standardized way to number the COP header shown in Figure 26. Consequently, differe nt
emulator vendors number the pins differently. Some pins are numbered top-to-bottom and left-to-right
while others use left-to-r ight then top-to-bottom and st ill others number the pins counter clockwise from
pin 1 (as with an IC). Regardless of the numbering, the signal placement r ecommended in Figure 26 is
common to all known emulators.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 49
System Desi gn
Figure 26. COP Connector Diagram
HRESET 7HRST_CPU
HRST_CTRL
From Target
Board Sources
COP_HRESET
13 SRESET 5
SRESET 5SRESET 5
NC
NC
NC
11
VDD_SENSE
6
5 2
15 3
1 kΩ
10 kΩ
10 kΩ
10 kΩ
OVDD
OVDD
OVDD
OVDD
CHKSTOP_IN 6CHKSTOP_IN 6
8TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4COP_TRST
7
16
2
10
12
(if any)
COP Header
14 4
Key
QACK 1
OVDD
OVDD
10 kΩ
OVDD
TRST 7
10 kΩOVDD
10 kΩ
10 kΩ
MPC8245
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pin Out
0 Ω 8
No te :
1QACK is an output and is not required at the COP header for emulation.
2RUN/STOP nor mally found on pin 5 of the COP header is n ot implemen ted on t he MPC8245. Connect pin 5 of the COP
header to OVDD with a 1-kΩ pull- up resistor.
3CKSTP_OUT normally on pin 15 of the COP header i s not i mplemented on the MPC8245. Connect pin 15 of the COP
header to OVDD with a 10-kΩ pull -up resist or.
4Pin 14 is not physically pr esent on the COP header.
5SRESET functions as output SDMA12 in extended ROM mode .
6CHKSTOP_IN functions as output SDMA14 in extended ROM mode.
7The COP port and t arget board should be able to independently asser t HRESET and TRST to the processor to contr ol
the processor as shown.
8If t he JTAG interface is implemented, connect HRESET from the target source to TRST from th e COP heade r th rough
an AND gate t o TRST of the pa rt . I f the JTAG interface is not implemented, connect HRESET from the target source to
TRST of the par t t hrough a 0-Ω isolation resistor.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
50 Freescale Semiconductor
System Design
7.8 Thermal Management
This section provides thermal management information for the tape ball grid array (TBGA) package for
air -cooled applications. Depending on the application environment and the operating frequency , heat sinks
may be required to maintain junction temperature within specifica tions . Proper thermal c ontrol de sign
primarily depe nds on the system-level design: the heat sink, airfl ow, and thermal interface material. To
reduce the die-junction temperature, heat sinks can be attac hed to the package by several methods:
adhesive, spring clip to holes in the printed-circuit board or package, or mounting clip and screw assembly.
Figure 27 displ ays a package-exploded cross-sectional view of a TBGA package with several heat sink
options.
Figure 27. Package-Explod ed Cro ss-Sectional View with Several Heat Sink Option s
Figure 28 depicts the die junction-to-ambient thermal resistance for four typical cases:
• A heat sink is not attached to t he TBGA package, and there exists high board-level thermal loading
from adjacent com ponents.
• A heat sink is not attached to the TBGA package, and there is low board-level thermal loading from
adjacent components.
• A heat si nk (for example, ChipCoolers) is attached to the TBGA package, and there is high
board-level therm al loading from adjacent components.
• A heat sink (for example, ChipCoolers) is attached to the TBGA package, and there is low
board-level therm al loading from adjacent components.
Thermal Interface
Heat Sink TBGA Package
Heat Sin k
Clip
Prin ted-Circuit Board Option
Material
Die
Adhesive or
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 51
System Desi gn
Figure 28. Die Junction-to-Ambient Resi stance
The board designer can choose between several types of heat sinks to place on the M PC8245. Several
commercially-available heat sinks for the MPC8245 are provided by the following vendors:
Aavid Thermalloy 603-224-9988
80 Commer cial St .
Concord, NH 03301
Internet: www.aavidthermalloy.com
Alpha Novatech 408-749-7601
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Rese arc h Corporation (IE RC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Tyco Electronics 800-522-6752
Chip Coolers™
P.O. Box 3668
Harrisbur g, PA 17105-3668
Internet: www.chipcoolers.com
2
4
6
8
10
12
14
16
18
00.511.522.5
Die Junct ion-to-Amb ient Thermal Resistance (°C/ W)
Airflow V elocity (m/s)
No heat sink and high thermal board-level loading of
adjacent components
No heat sink and low t hermal board-level loading of
adjacent components
Attached heat sink a nd hig h thermal board- level loading of
adjacent components
Att ac hed he at si nk and low therma l bo ar d -leve l lo ad in g of
adjac ent compone nts
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
52 Freescale Semiconductor
System Design
Wakefield Engineering 603-635-5102
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
Selection of an appropriate heat sink depends on thermal performance at a given a ir velocity, spatial
volume, mass, attachment method, assembly, and cost. Other heat sinks of fered by Aavid Thermalloy,
Alpha Novatech, IERC, Chip Coolers, and Wakefi eld Engineering offer differ ent heat sink-to-ambient
thermal resistances and ma y or may not need airflow.
7.8.1 Internal Package Conduction Resistance
The intrinsic conduction thermal resistance paths for the TBGA cavity-down packaging technology shown
in Figure 29 are as follows:
• Die junc tion-to- cas e thermal res istance
• Die junc tion-to- bal l thermal resistanc e
Figure 29 depicts the primary heat transfer pat h for a package with an attached heat sink mounted on a
printed-circuit board.
Figure 29. TBGA Package with Heat Sink Mounted to a Printed-Circuit Board
In a TBGA package, the active side of the die faces the printed-circuit board. Most of the heat travels
through the die, across the die attach layer , and into the copper spreader . Some of the heat is removed from
the top surface of the spreader through convection and radiat ion. Another percentage of the heat enters the
printed-circuit board through the solder balls. The heat is then r emoved from the exposed surfaces of the
board through convect ion and radiation. If a heat sink is used, a larger percentage of heat leaves t hrough
the top side of the s pre ader.
External Resi stance
External Resi stance
Inter nal Resist ance
Radiation Convection
Radiation Convection
Heat Si nk
Printed-Circuit Board
Th er ma l In te rfac e Ma te rial
Package/Leads
Die Junction
Die/Package
(Note the internal versus external pa ckage resist ance)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 53
System Desi gn
7.8.2 Adhesives an d Thermal Interfac e Materials
A thermal interface mater ial placed betwee n the top of the package and the bottom of the heat sink
minimiz es thermal contact resista nc e. For applications that attach the heat sink by a spring clip
mechanism, Figure 30 shows the thermal performance of thr ee thin-she et thermal-inter f ace m ater ials
(silicone, gra phite/oil, floroethe r oil), a ba re joint, and a joint with therma l grea s e a s a func tion of c ontac t
pressure. As shown, the performance of these thermal interface materials improves with increasing contact
pressure. Therma l grease significantly reduces the interfa ce the rmal resistance. That is, the bare joint
offers a thermal resistance approximately s even times greater than the therma l grease joint.
A spring clip attaches heat sinks to hol es in t he pri nted-circuit board (see Figure 30). Therefore, synt het ic
grease offers the best the rmal performance, considering the low interface pressure. The se lection of any
therma l interfac e materi al depends on factor s such as ther m al perfo rmance require ments,
manufactura bility, service temperature, dielectric properties, and cost.
Figure 30. Thermal Performance of Select Thermal Interface Material
The board designer can choose between several types of thermal interf aces. Heat sink adhesive m aterials
are selected on the basis of high conductivity and adequate mechanical str ength to meet equipment
shock/vibration requirements. Several commercia lly-available thermal interfaces and adhesive materials
are provided by the following vendors:
Chomerics, Inc. 781-935-4850
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
0
0.5
1
1.5
2
0 1020304050607080
Silicone Sheet (0.006 in.)
Bare Joint
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic G rease
Contact Pressure (psi)
Specific Therm al Resistance (K-in.
2
/W)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
54 Freescale Semiconductor
System Design
Dow-Corning Corpora t ion 800-248-2481
Dow-Corning Electronic Materials
2200 W. Salzbur g R d.
Midland, MI 48686- 0997
Internet: www.dow.com
Shin-Etsu MicroSi, Inc. 888-642-7674
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.c om
The Bergquist Company 800-347-4572
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
Thermagon Inc. 888-246-9050
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
7.8.3 Heat Sink Usage
An estimation of the chip junction temperature, TJ, can be obtained f rom the equation:
TJ = TA + (RθJA × PD)
where
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Unfortunately, two values are in common usage: the value determi ned
on a single-layer board and the value obta ined on a board with two planes. Which value is closer to the
application depends on the power dissipated by other components on the board. The value obtained on a
single-layer board is appropriate for the tightly packed printed-circuit board. The value obtained on the
board with the internal planes is usually appropriate if the board has low power dissipation and the
components are well sepa rated.
When a heat sink is used, the thermal resis tan ce is expressed as the sum of a junction-to-ca se thermal
resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where
RθJA = junction-to-ambient thermal resistance (°C/W)
RθJC = junction- to-case thermal resistance (°C/W)
RθCA = case-to-ambient thermal resistance (°C/W)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 55
System Desi gn
RθJC is device-related and cannot be influenced by the user. The us er con trols t he thermal environment to
change the case-to-ambient thermal resistance, RθCA. For instance, the user can change the size of the heat
sink, the airflow around the device, the interface material, th e mounting arrangement on the printed-circuit
board, or the thermal dissipation on the printed-circuit board surrounding the device.
To deter mine the junction temperature of the device in the application without a heat sink, the thermal
characterization parameter (ΨJT) measures the temperature at the top center of t he package case using the
following equation:
TJ = TT + (ΨJT × PD)
where:
TT = thermocouple temperature atop the package (°C)
ΨJT = thermal characterizat ion parame te r (°C/W)
PD = power dissipation in package (W)
The thermal c hara cteriz at ion parame te r is measure d per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top cente r of the pa ckage case . The thermocouple should be positioned s o
that the thermocoupl e junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement er rors caus ed by cooling effects of the
thermocoup le wire.
When a heat sink is used, the junction temperature is determined from a thermocoupl e inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance minimizes the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
dif ficulties with this technique, many engineers measure the heat sink temperature and then back-calculate
the case temperature using a separate measurement of the thermal resistance of the inter face. F rom this
case temperatur e, th e junction temper at ure is determine d from the junction-to -c ase ther ma l resis tan ce.
In many cases, it is appropriate to simulate the sys tem environment using a computational f luid dynamics
thermal simulation tool. In such a tool, the simples t thermal model of a package that has demons tra ted
reasonable accu racy (about 20%) is a two-resistor model consisting of a junction-to-board and a
junction-to-c ase thermal resis ta nce. The junction-to-case covers the situation where a heat sink is used or
a substantial amount of heat is dis sipated from the top of the package. The junction-to-boar d thermal
resistance describes the thermal per formance when most of the heat is conduct ed to the printed-circuit
board.
7.9 References
Semiconductor Equipment and Materials International
805 East Middlefield Rd.
Mountain View, CA 94043
(415) 964-5111
MIL-S P EC and EIA/JE SD (JEDE C) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specif ic ati ons are available on the web at http://www.jedec.org.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
56 Freescale Semiconductor
Document Revision History
8 Document Revision History
Table 19 provides a revision history for this hardwa re specification.
Table 19. Revision History Table
Revision Date Substantive Change(s)
10 8/07 Section 3, Table 3, and Table 7—Cha nged format o f recommende d voltage su pply values so that del ta
to the chosen nominal does not exceed ± 100 mV.
Completel y replaced Section 4.6 with com pliant I2C spe cificati ons as wit h other related i ntegrated
processor devices.
9 12/27/05 Docum ent—Added Power Archi tecture informatio n.
Section 4.1—Change d increased absol ute maximum range for VDD in Table 1. Updated format of
nominal voltage listings in Table 2.
Section 9.2—Removed Note 3 from Table 21.
Updated back page information.
8 11/15/2005 Document—Imported new template and made minor editorial changes.
Removed references to a 466 MHz part since it is not avai lable for n ew order s.
Section 4.3.2— Added paragraph for using DLL mode tha t pro vides lowest locked tap point read i n
0xE3.
Section 5.3—Updated the driver and I/O assignment information for the multiplexed PCI clock and
DUART signal s. Added note for HRST_CPU and HRST_CTRL, which had bee n mentioned only in
Figure 2.
Section 9.2—Updated the part ordering specifications for the extended temperature parts. Also
updated the section to ref lect what we offer for new orders.
Section 9. 3— Added new section, “Part Marking.” Up dated Figure 33 to match with cur rent part
marking f ormat.
7 10/07/2004 Section 4.1.2—Table 2: Corrected range of AVDD and AVDD2.
Sectio n 9.1—Table 21 : Corr ected vol tage r ange under Pr ocess Des cr iptor column. Minor re formatt ing.
6.1 05/24/ 2004 Section 4.5. 3—Table 11: Spec 12b was impr oved from 4.5 ns to 4.0 ns. Thi s improvement is
guaranteed on devices marked after work week (WW) 28 of 2004. A device's work week may be
determined from the “YYWW” portion of the devices trace ability code which i s m arked on t he top of
the device. So for WW28 in 200 4, the devi ce’s YYW W is marked as 0428. For more inform ation refer
to Figur e 33
6 05/11/2004 Section 4.1.2—Table 2: Corrected range of GVDD to 3.3 ± 5%.
Section 4.2.1—Table 4: Changed the default for drive strength of DRV_STD_MEM.
Section 4. 5.1—Table 8: Changed the wording desc ription for i tem 15.
Section 4.5.2—Table 10: Changed Tos range and wording in note; Figure 11:changed wording for
SD RA M_SY N C _ I N des cr ip tion re la ti v e to TOS.
Section 4. 5.3—Table 11: Changed timing specification for sys_logic_clk to output valid (memory
control, address, and data signals).
5.1 — Sect ion 4. 3.1—Table 9: Corrected last row to state the correct descript ion for the bit setting. Max tap
delay, DLL ext end. Fi gure 8: Co rrect ed the l abel name f or the DLL grap h to sta te “DLL Loc king Range
Loop Delay vs. Frequency of Op erat ion for DLL_Ext end=1 and Normal Tap Delay”
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 57
Document Revision History
5 — Sect ion 4. 1.2 — Added note 6 and relat ed label for lat ching of the PLL_CFG signals.
Section 4.1.3 — Updated specifications for the input high and input low voltages of PCI_SYNC_IN.
Section 4. 3 — Table 7, updated specif ications for t he voltage ran ge of VDD fo r s pe c if ic CPU
frequencies.
Section 4. 3.1 — Table 8: Corre cted typo for fir st number 1a to 1; Updated characteristics for the DLL
lock r ange fo r the def ault and rem aini ng thr ee DLL l ocking modes; Rewo rded not e d escrip tion for no te
6. Replaced content s of Table 9 with bit descript ions for the four DLL l ocking modes. In Fi gures 7
through 10, updated the D LL locking mode graphs.
Section 4. 3.2 — Table 10: Changed the name of references for timing parameters f rom
SDRAM_SYNC_IN to sys_logic_clk to be consistent wit h Figure 11. Followed the same change for
note 2.
Section 4. 3.3— Table 11: Changed the name of referenc es for timing paramet ers from
SDRAM_SYNC_IN to sys_logic_clk to be consistent with Figure 11. Followed the same change for
note 2.
Section 5.3 — Table 17: Removed extra listing of DRDY in Test/Configuration signal list and updated
relevant notes for si gnal in Memory Interface sign al l isting. Updated note #20. Adde d note 26 for the
signal s of the UART inter face.
Sectio n 7.6 — Added r eference to AN2128 appl icatio n note that highl ights the dif ference s between the
MPC8240 and the MPC824 5.
Section 7. 7 — Adde d relevant not es to t his sectio n and updated Figure 29.
4 — Section 1.4.1.2—Updated notes for GVDD, AVDD, AVDD2.
Section 1.5.1—Updated solder ball information to include lead-free (V V) balls.
Sectio n 1.5.3—Updated Note 25 f or QACK/DA0 signal. Added a sentence to Note 3.
Section 1.6 —Incorporated Note 19 into Note 12 and modified Tables 18 and 19 accordingly.
Section 1. 9— Updated part marking nomencl ature where appropriate to incl ude the lead-free offering.
Replaced r efer ence to PNS document MPC8245RZUPNS with MPC8245ARZUPNS.
3 — Sect ion 1.4.1.2— Figure 2: Updated Note 2 and removed ‘voltage r egulator de lay’ label si nce Section
1.7.2 i s being delet ed th is revisi on. A dded Figur es 4 and 5 to show vol tage over sho ot and unders hoot
of the PCI interface on the MPC8245 .
Section 1. 4.1.3—Table 3: Updat ed the maximum input capacita nce from 7 to 16 pF based on
characteriza ti on data.
Section 1.4.3.1—Updated PCI_SYNC_IN jitter specifications to 200 ps.
Section 1.4.3.3—Table 11, item 12b: added the word ‘address’ to help clarify which signals the spec
applie s to. Figure 15: edited timing for items 12a0 and 12a2 to cor respond with Table 11.
Section 1. 5.3—Updated notes for the Q ACK/DA0 signal bec ause this sign al has been found to have
no inter nal pull resis tor.
Section 1. 6— Corrected not e num bers for reference numbers 3,10,1B, and 1C of the PLL tab les.
Updated PLL specifications for modes 7 and 1E.
Section 1.7.2—Removed this section since the information already exists in Section 1.4.1.5.
Section 1.7.4—Added the words ‘the clamping voltage’ to describe LVDD in the sixth paragraph.
Changed the QACK/DA0 signal from the list of signals having an internal pull-up resistor to the list of
signal s needing a weak pull -up resist or to OVDD.
Section 1. 9.1—Tables 21 thru 23: Added processor version register value.
Table 19. Revision History Table (continued)
Revision Date Substantive Change(s)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
58 Freescale Semiconductor
Document Revision History
2 — Globa lly cha nged EPIC t o PIC.
Section 1. 4.1.4—Note 5: Changed register reference from 0x72 to 0x73.
Section 1. 4.1.5—Table 5: Updat ed power dissi pati on num bers based on lat est charact erizati on data.
Section 1. 4.2—Table 6: Updated t able t o show m ore thermal specificat ions.
Section 1. 4.3—Table 7: Updated mi nimum m em ory bus value to 50 MHz.
Section 1. 4.3.1—Changed equations f or DLL locking range based on characterization data. Added
updates and reference to AN2164 for note 6. Added tabl e defining Tdp parameters. Labeled N val ue
in Figures 5 through 8.
Section 1. 4.3.2—Table 10: Changed bit defini tions for tap poi nts. Update d note on Tos and added
refer ence to AN2164 for note 7. Updated Figure 9 to show sig nificanc e of Tos.
Sectio n 1.4.3.4—Added col um n for SDRAM_CL K @ 133 MHz
Sections 1.5.1 and 1.5.2—Corrected packaging i nformati on to state TBGA packaging.
Section 1.5.3—Corrected some signals in Table 16 which were m issing overbars in the Rev 1.0
release of the document.
Section 1. 6— Updated Note 10 of Tables 18 and 19.
Section 1.7.3—Changed sentence recommendation regarding decoupling capacitors.
Section 1. 9— Updated format of tab les i n Ordering Information section.
1 — Updat ed docum ent templat e.
Section 1.4.1.4—Changed the driver type names in Table 6 to match with the nam es used in the
MPC8245 Reference Manual.
Section 1. 5.3—Updated dri ver type names for signals in Table 16 to match wi th names used in the
MPC8245 Integrated Processor Referenc e Man ual.
Section 1.4.1.2—Updated Table 7 to refer to new PLL Tables for VCO li mits.
Sectio n 1.4.3.3—Added item 12e to Table 10 for SDRAM_SYNC_IN to Output Valid timi ng.
Section 1.5.1—Updated solder balls information to 62Sn/36PB/2Ag.
Section 1.6—Updated PLL Tables 17 and 18 and appropriate notes to ref lect changes of VCO ranges
for memory and CPU frequencies.
Section 1.7—Updated voltage sequencing requirements in Table 2 and removed Section 1.7.2.
Sectio n 1.7.8—Updated TRST inf ormation and Figure 26.
New Section 1.7.2—Updated the range of I/O power consumption numbers f or OVDD and GVDD to
correct values as in Table 5. Upda ted f astest fre quency combination to 66:1 00:350 MHz.
Section 1. 7.9—Updated li st for heat sink and thermal i nterface vendors.
Section 1.9—Changed format of Ordering Information section. Added tables to reflect part number
specifications also available.
Added Sections 1.9.2 and 1.9.3.
0.5 — Corrected label s for Figures 5 throu gh 8.
Table 19. Revision History Table (continued)
Revision Date Substantive Change(s)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 59
Document Revision History
0.4 — Sectio n 1. 2—Changed Featur es list ( format ) to matc h wit h the fea tures list o f the MPC8245 Integrat ed
Processor Reference Manual.
Section 1. 4.1.2—Updated Table 2 to inclu de 1.8 ± 100mV numbers.
Section 1.4.3—Changed Table 7 to include new part offerings of 333 and 350 MHz. Added rows to
include VCO frequency ranges for all parts for both memory VCO and CPU VCO.
Section 1.4.1.5—Updated power consumption table to include 1.8 V (VDD) and higher frequency
numbers.
Sectio n 1.4.3—Updat ed Table 7 to i nclude h igher f requency of ferings and CPU VCO fre quency ran ge.
Section 1.4.3.1—Changed letteri ng to caps for DLL_EXTEND and DLL_MAX_DELAY in graph
description section.
Section 1. 4.3.2—Changed nam e of i tem 11 from Tsu—S DR A M _ SY N C _ IN to PC I_ S Y NC _ IN Time to
Tos—SDRAM_SYNC_IN to sys_logic_clk Offset T ime. Changed name to Tos in Note 7 as well.
Sectio n 1.6—Updated no tes in Table 17. Incl uded mini mum and maxi mum VCO number s for memor y
VCO. Changed Note 13 for locat ion o f PL L_CFG[0:4] to c orrect bit s loca tion. Bits 7–4 of regis ter offs et
<0xE2>. Added Table 18 t o cover PLL configu ration of higher f requency part offerings.
Sectio n: 1 .7—Changed f requ ency ranges f or refer ence numbers 0, 9, 10, and 17, for th e 300-MHz par t
to include the higher memory bus frequen cies when operating at l ower CPU bus frequenc ies. Added
Table 18 to include PLL configur ati ons for the 333 MHz and the 350 MHz CPU part offerings. Added
VCO multipliers in Tables 17 and 18.
Section 1.7.8—Changed Tsu—SDRAM _ SY NC_I N to PC I_ S Y N C _ IN Tim e to Tos—SDRAM_
SYN C_IN to sys_logic_clk O ffs e t Time. ”
Section 1. 7.10—Added ve ndor (Cool Innov ati ons, Inc.) to list of heat si nk vendors.
0.3 — Section 1.4.1.5—Changed Max-FP value for 33/133/266 of Table 5 f rom 2.3 to 2.1 watts to represent
characteriza ti on data. Changed Not e 4 to say VDD = 2.1 for power measurements (for 2-V part).
Changed num bers f or m aximum I/O power suppl ie s for OV DD and GVDD to rep resent charact eriz ation
data.
Section 1. 4.3.1—Added four graphs (Figures 5–8) and description f or DLL Locking Range vs.
Frequency of Operati on to replace Figure 5 of Rev 0.2 document.
Sectio n 1.4.3.2—Added row (item 11: Tsu—SDRAM_SYNC_IN to PCI_SYNC_IN timing) to Table 9 to
inclu de offset change requirement.
Section 1.5.3—Changed Note 4 of PLL_CFG pins in Table 16 to Note 20.
Section 1. 7.2—Added diode (MUR420) to Figure 27, Voltage Sequencing Circui t, to compensat e for
voltage extremes in design.
Section 1.7.5—Added sentence with regards to SDRAM_SYNC_IN to PCI_SYNC_IN timing
requirement (Tsu) as a connection recommendation.
Section 1.7.8—M ention of Tsu offset timing and driver capability differences between the MPC8240
and the MPC8245.
Table 19. Revision History Table (continued)
Revision Date Substantive Change(s)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
60 Freescale Semiconductor
Document Revision History
0.2 — Changed core supply voltage to 2.0 ± 100 mV in Section 1.3. (Supply volt age of 1.8 ± 100 mV is no
longer recommended.)
Changed rows 2, 5, and 6 of Table 2 to 2.0 ± 100 mV in the “Recommended Value” column.
Changed the power consumpti on num bers in Table 5 to reflect the power values for VDD = 2.0 V.
(Notes 2, 3, 4, and 5 of the ta ble were also updated to reflect the new value of VDD.)
Updated Table 9 for V DD/AVDD/AVDD2 to 2.0 ± 100 mV.
Table 8: VDD/AVDD/AVDD2 was changed to 2.0 V for both CPU frequency off eri ngs. Note 2 was
updated by removing the “ at reduced voltage...” stat em ent.
Table 10: Update maxi m um time of the rows 12a0 through 12a3.
Table 16: Fi xed overbars for t he active- low signals. Changed pin type i nformati on for VDD, AVDD, and
AVDD2 to 2.0 V.
Changed Note 16 of Table 17 to a value of 2.0 V for VDD/AVDD/AVDD2.
Removed sec ond sentence of th e second paragraph i n Section 1.7. 2 because it referenced
infor mation about a 1.8-V design.
Removed reference to 1.8 V in third sentence of Sect ion 1.7.7.
Table 19. Revision History Table (continued)
Revision Date Substantive Change(s)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 61
Document Revision History
0.1 — Made VDD/AVDD/AVDD2 = 1.8 V ± 100 mV inf ormation fo r 133-MHz memory interface oper ation to
Section 1.3, Table 2, Table 5, Table 9, Table 17, and Section 1.7.2.
Pin D17, formerly LAVDD (supply vol tage f or DLL), is a NC on the MPC8245 since the DLL voltage i s
suppli ed internally. El iminated all ref erences to LAVDD; updat ed Section 1.7 .1.
Previou s Note 4 of Table 2 did not apply t o the MPC8245 (MPC8240 docu ment l egacy). New Note 4
added in ref erence to maximum CPU speed at r educed VDD voltage.
Updated the Programmable Output Impedance of DEV_MEM_ADDR in Table 4 to 6 Ω to reflect
characteriza ti on data.
Updated Table 5 to refl ect reduced power consumpti on when operating VDD/AVDD/AVDD2 = 1.8 V ±
100 mV. Changed Notes 2, 3, and 4 to ref lect VDD a t 1.9 V . Changed Note 5 to rep resent VDD = AVDD
= 1.8 V.
Updated Table 7 to refl ect VDD/AVDD/AVDD2 voltage level operating frequency dependencies;
changed 250 MHz device colum n to 266 MH z; modifie d Note 1 elim inating VCO references; added
Note 2. Changed 250 MHz processor f requency offering to 266 MH z.
Changed Spec 12b for memory output valid time in Table 11 f rom 5.5 ns to 4.5 ns; this i s a key
specification change to enable 133-MHz memory interface designs.
Updated Pin out Table 16 wi th t he fol lowing chang es:
• Pin types for RCS0, RCS3/TRIG_OUT and DA[11: 15] were erroneously listed as I/ O, changed Pin
Types to O utput.
• Pi n typ e s for RE Q4 /DA4, RCS2/TRIG_I N, and PLL_CFG[0:4]/DA[10:6] were er roneously listed as
Input, changed Pin Types to I /O.
• Changed Pin D17 from LAVDD to No Connect; dele ted Not e 21 and ref erences.
• Notes 3, 5, and 7 contained refe rences to the MPC8240 (MPC8240 document legacy); ch anged
these references to MPC8245.
• Prev ious Not es 13 and 14 di d not app ly t o t he MPC82 45 (MPC8240 docu ment legacy ), t hese notes
were deleted; moved Note 19 to become new Note 13; moved Note 20 to become new Note 14;
updated associated r eferences.
• Added Note 3 to SDMA[1:0] signals about internal pull-up resist ors dur ing reset state.
• Reversed vector orde ri ng for the PCI Interface Signals: C/BE[0: 3] changed to C/BE[3:0], AD[0:31]
changed to AD[31:0], GNT [0:3] cha nged to GN T[3:0], and REQ[0:3] changed to R EQ[3:0]. The
package pin numbe r orderings were also reversed me aning that pin functionalit y did NOT change.
For exampl e, AD0 is s till on si gnal C22, AD1 is still o n signal D22,.. ., AD31 is sti ll on signal V25. This
change was made to m ake the vectored PCI signals in this hardware specification consistent with
the PCI Local Bus Specification and the MPC8 245 Integra ted Processor Refere nce Manu al vector
ordering.
• Changed TEST1/DRDY signal on pin B20 t o DRDY.
• Changed TEST2 s ignal on pin Y2 to RTC for per formance monit or use.
Updated PLL Table 17 with the f ollowing ch anges for 133-MHz memory i nterface ope ration:
• Added Ref. 9 ( 01001) and Ref. 17 ( 10111) details; removed these settings fr om Note 10 (reserv ed
se tt in g s lis t ).
• Enhanced range of Ref. 10 (10000).
• Updated Note 13, changed bits 16–20 erroneous information to correct bits 23–19.
• Added Notes 16 and 17.
Added info rmation to Section 1.7.8 in refe rence t o CHKST OP_ IN and SRESET being unavail able in
extended ROM mode.
0.0 — Initial release.
Table 19. Revision History Table (continued)
Revision Date Substantive Change(s)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
62 Freescale Semiconductor
Orde ri ng Info rma tion
9 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 9.1,
“Part Numbers Fully Addr es sed by This Document.” Secti on 9.2, “ Part Numbers Not Fully Addressed by
This Document,” lists the part numbers that do not fully conform to the specifications of this document.
These special part numbers re quire an additional document called a hardware specifications addendum.
9.1 Part Numbers Fu lly Addressed by This Docu ment
Table 20 provides the Freescale part numbering nomenclature for the MPC8245. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact a
local Freescale sales office. In addition to the processor frequency, the par t numbering scheme also
includes an appli cation modifier that may specify special application conditions. Each part number also
contains a revision code that refers to the die mask revis ion number . The revision level can be determined
by reading the Revision ID register at address offset 0x08.
Tab le 20. P art Numb eri ng Nomenc lature
MPC nnnn Lxx nnn x
Product
Code Part
Identifier Process Descript or Package 1Processor
Frequency 2
(MHz) Revision Level Processor
V ersion Register
Value
MPC 8245 L: 0° to 105°CZU=TBGA
V V = Lead-fr ee
TBGA
266, 300
1.7 V to 2.1 V D:1.4 Rev ID:0x14 0x80811014
L: 0° to 105°CZU=TBGA
V V = Lead-fr ee
TBGA
333, 350
1.9 V to 2.2 V
Notes:
1. See Section 5, “Package Description,” for more inf orm ation on avai lable package t ypes.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specifica ti on support all core frequenc ies. Additionally, parts addr essed by a hardware specifications addendum may
support other maximum core frequencies.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 63
Ordering Info rma tion
9.2 Part Numbers Not Fully Addressed by This Document
Parts with application modifi ers or revision levels not fully addressed in this specification document are
described in separate pa rt number specifications that supplement and supersede this document . Table 21
shows the part numbers addressed by the MPC8245TXXnnnx series. The revision level can be determined
by reading the Revision ID register at address offset 0x08.
Table 22 shows the part numbers addressed by the MPC8245ARZUnnnx ser i es.
Table 21. Part Numb ers Addressed by MPC8245TXXnnnx Series
Part Numb er Specifica tion Markings
(Document Order No. MPC824 5E CS01AD)
MPC nnnn Xxx nnn x
Product
Code Part
Identifier Process
Descriptor Package 1Processor
Frequency 2Revision Level Processor
Version
Register Value
MPC 8245 T: –40°
to 105°CZU = TBGA
V V= Lead-free
TBGA
266 MHz , 300 MHz:
1.7 V to 2. 1 V
333 MHz , 350 MHz:
1.9 V to 2. 2 V
D:1. 4 Rev ID:0x14 0x80811014
Notes:
1. See Section 5, “Pac kage Description,” for more information on availabl e package types.
2. Processor core frequencies supported by parts address ed by this speci fi cation onl y. Not all part s described i n this
specif icatio n support all core fr equencies. Additi onally, parts addressed by a hardwar e specifications addendum m ay
support other maximum core frequencies.
Table 2 2. Part Numbers Add ressed by MPC824 5ARZUnnnx Series
Part Numb er Specifica tion Markings
(Document Order No. MPC824 5E CS02AD)
MPC nnnn X Xxx nnn x
Product
Code Part
Identifier Process 3
Identifier Process
Descriptor Package 1Processor
Frequency 2Revision Level
Processor
Version
Register
Value
MPC 8245 A R: 0° to 85°CZU=TBGA
V V= Lead-fr ee
TBGA
400 MHz
2.1 V ±
100 mV
D:1.4 Rev I D:0x14 0x80811014
Notes:
1. See Section 5, “Package Description,” for more information on available package types.
2. Processor core frequencies supported by parts addre ssed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by a hardware specifications addendum may
support other maxi m um core frequenci es.
3. Proces s ide ntifier ‘A’ r eprese nts pa rts tha t are man ufactu red under a 29- angstr om proce ss verses the origi nal 35- angstr om
process.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
64 Freescale Semiconductor
Orde ri ng Info rma tion
9.3 Part Marking
Parts are marked as the example shown in Figure 31.
Fig ure 31. Pa rt Marking for TB GA D evi ce
Notes:
MMMMM is the 5-digit mas k number.
ATWLYYWW is test traceability code.
MPC8245LXXnnnx
MMMMM
ATWLYYWW
CCCCC
YWWLAZ
YWWLAZ is the assem bly trac eability code.
CCCCC is the country code.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 65
Ordering Info rma tion
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MPC8245 Integrated Processor Hardware Specifications, Rev. 10
66 Freescale Semiconductor
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Freescale Semiconductor 67
Ordering Info rma tion
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Document Number: MPC8245EC
Rev. 10
08/2007
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