SiP32411
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2 A, 1.2 V, Slew Rate Controlled Load Switch
DESCRIPTION
The SiP32411 is a slew rate controlled load switch that is
designed for 1.1 V to 5.5 V operation.
The device guarantees low switch on-resistance at 1.2 V
input. It features a controlled soft-on slew rate of typical
150 µs that limits the inrush current for designs of capacitive
load or noise sensitive loads.
The device features a low voltage control logic interface
(on/off interface) that can interface with low voltage digital
control without extra level shifting circuit. It also integrates
an output discharge switch that enables fast shutdown load
discharge. When the switch is off, it provides the reverse
blocking to prevent high current flowing into the power
source.
The SiP32411DN is in TDFN4 package of 1.2 mm by
1.6 mm. It supports over 2 A of continuous current. The
SiP32411DR is in SC70-6 package.
FEATURES
• 1.1 V to 5.5 V operation voltage range
• 62 mΩ typical from 2 V to 5 V for SiP32411DN
• 101 mΩ typical from 2 V to 5 V for SiP32411DR
•Low R
ON down to 1.2 V
• Slew rate controlled turn-on: 150 µs at 3.6 V
• Fast shutdown load discharge
• Low quiescent current
< 1 A when disabled
6.7 A at VIN = 1.2 V
• Switch off reversed blocking
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Cellular phones
• Portable media players
• Digital camera
•GPS
• Computers
• Portable instruments and healthcare devices
TYPICAL APPLICATION CIRCUIT
Fig. 1 - SiP32411 Typical Application Circuit
Notes
•x = lot code
• -GE3 and -GE4 denotes halogen-free and RoHS-compliant
Available
ORDERING INFORMATION
TEMPERATURE RANGE PACKAGE MARKING PART NUMBER
-40 °C to 85 °C SC70-6 MBxx SiP32411DR-T1-GE3
TDFN4 1.2 mm x 1.6 mm Ex SiP32411DNP-T1-GE4
SiP32411
INVOUT
OUT
VIN
GND
GND
GND
EN
EN
C
4.7 µF
INC
0.1 µF
OUT
SiP32411
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Notes
a. Device mounted with all leads and power pad soldered or welded to PC board, see PCB layout.
b. Derate 4.5 mW/°C above TA = 70 °C, see PCB layout.
c. Derate 5.9 mW/°C above TA = 70 °C, see PCB layout.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
PARAMETER LIMIT UNIT
Supply Input Voltage (VIN) -0.3 to 6
VEnable Input Voltage (VEN) -0.3 to 6
Output Voltage (VOUT)-0.3 to VIN +0.3
Maximum Continuous Switch Current (Imax.)SC70-6 package 1.8
A
TDFN4 1.2 mm x 1.6 mm 2.4
Maximum Pulsed Current (IDM) VIN
(pulsed at 1 ms, 10 % duty cycle)
SC70-6 package 2.2
TDFN4 1.2 mm x 1.6 mm 3
ESD Rating (HBM) 4000 V
Junction Temperature (TJ) -40 to 125 °C
Thermal Resistance (θJA) a6 pin SC70-6 b240 °C/W
4 pin TDFN4 1.2 mm x 1.6 mm c170
Power Dissipation (PD) a6 pin SC70- 6 b 230 mW
4 pin TDFN4 1.2 mm x 1.6 mm c324
RECOMMENDED OPERATING RANGE
PARAMETER LIMIT UNIT
Input Voltage Range (VIN) 1.1 to 5.5 V
Operating Temperature Range -40 to 85 °C
SiP32411
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Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. For VIN outside this range consult typical EN threshold curve.
d. Not tested, guarantee by design.
SPECIFICATIONS
PARAMETER SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
VIN = 5, TA = -40 °C to 85 °C
(Typical values are at TA = 25 °C)
LIMITS
-40 °C TO 85 °C UNIT
MIN. a TYP.
bMAX. a
Operating Voltage c VIN 1.5 - 5.5 V
Quiescent Current IQ
VIN = 1.2 V, EN = active - 6.7 14
µA
VIN = 1.8 V, EN = active - 14 24
VIN = 2.5 V, EN = active - 25 40
VIN = 3.6 V, EN = active - 40 60
VIN = 4.3 V, EN = active - 52 75
VIN = 5 V, EN = active - 71 99
Off Supply Current IQ(off) EN = inactive, OUT = open - - 1
Off Switch Current IDS(off) EN = inactive, OUT = GND - - 1
Reverse Blocking Current IRB VOUT = 5 V, VIN = 1.2 V, VEN = inactive - - 10
On-Resistance RDS(on)
SC70-6
VIN = 1.2 V, IL = 100 mA, TA = 25 °C - 105 125
mΩ
VIN = 1.8 V, IL = 100 mA, TA = 25 °C - 101 120
VIN = 2.5 V, IL = 100 mA, TA = 25 °C - 101 120
VIN = 3.6 V, IL = 100 mA, TA = 25 °C - 101 120
VIN = 4.3 V, IL = 100 mA, TA = 25 °C - 101 120
VIN = 5 V, IL = 100 mA, TA = 25 °C - 101 120
TDFN4
1.2 mm
x 1.6 mm
VIN = 1.2 V, IL = 100 mA, TA = 25 °C - 66 76
VIN = 1.8 V, IL = 100 mA, TA = 25 °C - 62 72
VIN = 2.5 V, IL = 100 mA, TA = 25 °C - 62 72
VIN = 3.6 V, IL = 100 mA, TA = 25 °C - 62 72
VIN = 4.3 V, IL = 100 mA, TA = 25 °C - 62 72
VIN = 5 V, IL = 100 mA, TA = 25 °C - 62 72
On-Resistance
Temperature-Coefficient TCRDS
SC70-6 package - 4300 - ppm/°C
TDFN4 1.2 mm x 1.6 mm package - 3400 -
EN Input Low Voltage cVIL
VIN = 1.2 V - - 0.3
V
VIN = 1.8 V - - 0.4 d
VIN = 2.5 V - - 0.5 d
VIN = 3.6 V - - 0.6 d
VIN = 4.3 V - - 0.7 d
VIN = 5 V - - 0.8 d
EN Input High Voltage cVIH
VIN = 1.2 V 0.9 d--
VIN = 1.8 V 1.2 d--
VIN = 2.5 V 1.4 d--
VIN = 3.6 V 1.6 d--
VIN = 4.3 V 1.7 d--
VIN = 5 V 1.8 - -
EN Input Leakage ISINK VEN = 5.5 V -1 - 1 µA
Output Pulldown Resistance RPD EN = inactive, TA = 25 °C - 217 280 Ω
Output Turn-On Delay Time td(on)
VIN = 3.6 V, Rload = 10 Ω, TA = 25 °C
- 140 210
µsOutput Turn-On Rise Time t(on) 80 150 220
Output Turn-Off Delay Time td(off) -0.271
SiP32411
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PIN CONFIGURATION
Fig. 2 - SC70-6 Package Fig. 3 - TDFN4 1.2 mm x 1.6 mm Package
TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
Fig. 4 - Quiescent Current vs. Input Voltage
Fig. 5 - Off Supply Current vs. Input Voltage
Fig. 6 - Quiescent Current vs. Temperature
Fig. 7 - Off Supply Current vs. Temperature
OUT 1
GND 2
EN 3
N/C
6
GND
5
IN
4
Top View
4
3
1
2
Bottom View
EN
IN
OUT
GND
GND
PIN DESCRIPTION
PIN NUMBER NAME FUNCTION
SC70-6 TDFN4
4 3 IN This pin is the n-channel MOSFET drain connection. Bypass to ground through a 2.2 µF capacitor
2, 5 2 GND Ground connection
3 4 EN Enable input
1 1 OUT This pin is the n-channel MOSFET source connection. Bypass to ground through a 0.1 µF capacitor
VIN (V)
IQ - Quiescent Current (µA)
0
20
40
60
80
100
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN
(V)
I
Q(OFF)
- Off Supply Current (nA)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature (°C)
I
Q
- Quiescent Current (µA)
0
10
20
30
40
50
60
70
80
- 40 - 20 0 20 40 60 80 100
V
IN
= 5 V
V
IN
= 3.6 V
V
IN
= 1.2 V
Temperature (°C)
I
Q(OFF)
- Off Supply Current (nA)
0.0001
0.001
0.01
0.1
1
10
100
1000
- 40 - 20 0 20 40 60 80 100
V
IN
= 5 V
V
IN
= 3.6 V
V
IN
= 1.2 V
SiP32411
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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
Fig. 8 - Off Switch Current vs. Input Voltage
Fig. 9 - RDS(on) vs. VIN for TDFN4 package
Fig. 10 - RDS(on) vs. VIN for SC70-6 package
Fig. 11 - Off Switch Current vs. Temperature
Fig. 12 - RDS(on) vs. Temperature for TDFN4 package
Fig. 13 - RDS(on) vs. Temperature for SC70-6 package
VIN (V)
IDS(off) - Off Switch Current (nA)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
60
62
64
66
68
70
72
74
76
VIN
(V)
R
DS
- On-Resistance (mΩ)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
TDFN4 1.2 mm x 1.6 mm package
I
O
= 2 A
I
O
= 1.5 A
I
O
= 0.1 A
I
O
= 1.0 A
I
O
= 0.5 A
85
90
95
100
105
110
115
120
125
130
V
IN (V)
RDS - On-Resistance (mΩ)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SC70-6 package
IO = 2 A
IO = 1.5 A
IO = 0.1 A
IO = 0.5 A
IO = 1.0 A
Temperature (°C)
I
DS(off)
- Off Switch Current (nA)
0.001
0.01
0.1
1
10
100
1000
- 40 - 20 0 20 40 60 80 100
V
IN
= 5 V
V
IN
= 3.6 V
V
IN
= 1.2 V
Temperature (°C)
R
DS
- On-Resistance (mΩ)
70
80
90
100
110
120
130
- 40 - 20 0 20 40 60 80 100
SC70-6 package
I
O
= 0.1 A
V
IN
= 5 V
SiP32411
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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
Fig. 14 - Output Pull Down vs. Input Voltage
Fig. 15 - Reverse Blocking Current vs. Output Voltage
Fig. 16 - Turn-On Delay Time vs. Temperature
Fig. 17 - Output Pull Down vs. Temperature
Fig. 18 - EN Threshold Voltage vs. Input Voltage
Fig. 19 - Rise Time vs. Temperature
VIN (V)
RPD - Output Pulldown Resistance (Ω)
100
150
200
250
300
350
400
450
500
550
600
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VOUT = VIN
V
OUT
(V)
I
IN
- Input Current (nA)
0.01
0.1
1
10
100
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
IN
= 1.2 V
V
EN
= 0 V
80
85
90
95
100
105
110
115
120
Temperature (°C)
td(on) - Turn-On Delay Time (µs)
- 40 - 20 0 20 40 60 80 100
VIN = 5 V
CL = 0.1 µF
RL = 10 Ω
Temperature (°C)
RPD - Output Pulldown Resistance (Ω)
160
180
200
220
240
260
280
300
- 40 - 20 0 20 40 60 80 100
VOUT = VIN = 5 V
VIN
(V)
EN Threshold Voltage (V)
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
IH
V
IL
Temperature (°C)
t(on) - Rise Switching Time (µs)
- 40 - 20 0 20 40 60 80 100
VIN = 5 V
CL = 0.1 µF
RL = 10 Ω
130
140
150
160
170
180
190
200
SiP32411
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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
Fig. 20 - Turn-Off Delay Time vs. Temperature
TYPICAL WAVEFORMS
Fig. 21 - Switching (VIN = 3.6 V)
Fig. 22 - Switching (VIN = 5 V)
Fig. 23 - Turn-Off (VIN = 3.6 V)
Fig. 24 - Turn-Off (VIN = 5 V)
0.10
0.12
0.14
0.16
0.18
0.20
0.22
Temperature (°C)
td(off) - Turn-Off Delay Time (µs)
- 40 - 20 0 20 40 60 80 100
VIN = 5 V
CL = 0.1 µF
RL = 10 Ω
SiP32411
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BLOCK DIAGRAM
Fig. 25 - Functional Block Diagram
PCB LAYOUT
Fig. 26 - Top, PCB Layout for TDFN4 1.2 mm x 1.6 mm
(board size: 1 inch x 1 inch)
Fig. 27 - Bottom, PCB Layout for TDFN4 1.2 mm x 1.6 mm
(board size: 1 inch x 1 inch)
Fig. 28 - Top, PCB Layout for SC70-6
(board size: 1 inch x 1 inch)
Fig. 29 - Bottom, PCB Layout for SC70-6
(board size: 1 inch x 1 inch)
Control
Logic
Tu r n - O n
Slew Rate
Control
GND
EN
OUT
IN
Reverse
Blocking
+
-
Charge
Pump
SiP32411
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DETAILED DESCRIPTION
SiP32411 is an n-channel power MOSFET designed as high
side load switch with slew rate control to prevent in-rush
current. Once enable the device charge pumps the gate of
the power MOSFET to 5 V gate to source voltage while
controlling the slew rate of the turn on time. The mostly
constant gate to source voltage keeps the on resistance low
through out the input voltage range. When disable, the
output discharge circuit turns on to help pull the output
voltage to ground more quickly. Also in disable mode, the
reverse blocking circuit is activated to prevent current from
going back to the input in case the output voltage is higher
than the input voltage. Input voltage is needed for the
reverse blocking circuit to work properly, it can be as low as
VIN(min.).
APPLICATION INFORMATION
Input Capacitor
While a bypass capacitor on the input is not required, a
2.2 F or larger capacitor for CIN is recommended in almost
all applications. The bypass capacitor should be placed as
physically close as possible to the SiP32411 to be effective
in minimizing transients on the input. Ceramic capacitors are
recommended over tantalum because of their ability to
withstand input current surges from low impedance sources
such as batteries in portable devices.
Output Capacitor
A 0.1 F capacitor or larger across VOUT and GND is
recommended to insure proper slew operation. COUT may
be increased without limit to accommodate any load
transient condition with only minimal affect on the SiP32411
turn on slew rate time. There are no ESR or capacitor type
requirement.
Enable
The EN pin is compatible with both TTL and CMOS logic
voltage levels.
Protection Against Reverse Voltage Condition
The SiP32411 contains a reverse blocking circuitry to
protect the current from going to the input from the output
in case where the output voltage is higher than the input
voltage when the main switch is off. A supply voltage as low
as the minimum required input voltage is necessary for this
circuitry to work properly.
Thermal Considerations
The SiP32411 is designed to maintain a constant output
load current. Due to physical limitations of the layout and
assembly of the device the maximum switch current is 1.8 A
for SC70-6 package and 2.4 A for TDFN4 package, as
stated in the Absolute Maximum Ratings table. However,
another limiting characteristic for the safe operating load
current is the thermal power dissipation of the package. To
obtain the highest power dissipation (and a thermal
resistance of 240 °C/W for SC70-6 and 170 °C/W for
TDFN4) the power pad of the device should be connected to
a heat sink on the printed circuit board.
The maximum power dissipation in any application is
dependent on the maximum junction temperature,
TJ(max.) = 125 °C, the junction-to-ambient thermal resistance
for the TDFN4 1.2 mm x 1.6 mm package, θJ-A = 170 °C/W,
and the ambient temperature, TA, which may be
formulaically expressed as:
It then follows that, assuming an ambient temperature of
70 °C, the maximum power dissipation will be limited to
about 324 mW.
So long as the load current is below the 2.4 A limit, the
maximum continuous switch current becomes a function
two things: the package power dissipation and the RDS(on) at
the ambient temperature.
As an example let us calculate the worst case maximum
load current at TA = 70 °C. The worst case RDS(on) at 25 °C
occurs at an input voltage of 1.2 V and is equal to 75 mΩ.
The RDS(on) at 70 °C can be extrapolated from this data using
the following formula
RDS(on) (at 70 °C) = RDS(on) (at 25 °C) x (1 + TC x ΔT)
Where TC is 3400 ppm/°C. Continuing with the calculation
we have
RDS(on) (at 70 °C) = 75 mΩ x (1 + 0.0034 x (70 °C - 25 °C)) =
86.5 mΩ
The maximum current limit is then determined by
which in case is 1.94 A. Under the stated input voltage
condition, if the 1.94 A current limit is exceeded the internal
die temperature will rise and eventually, possibly damage
the device.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?66710.
P (max.) TJ (max.) TA
–
θJA–
---------------------------------125 TA
–
170
----------------------
==
ILOAD (max.)
P (max.)
RDS on()
----------------------<
Package Information
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TDFN4 1.2 x 1.6 Case Outline
Note
(1) The dimension depends on the leadframe that assembly house used.
DIM. MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.45 0.55 0.60 0.017 0.022 0.024
A1 0.00 - 0.05 0.00 - 0.002
A3 0.15 REF. or 0.127 REF. (1) 0.006 or 0.005 (1)
b 0.20 0.25 0.30 0.008 0.010 0.012
D 1.15 1.20 1.25 0.045 0.047 0.049
D2 0.81 0.86 0.91 0.032 0.034 0.036
e 0.50 BSC 0.020
E 1.55 1.60 1.65 0.061 0.063 0.065
E2 0.45 0.50 0.55 0.018 0.020 0.022
K 0.25 typ. 0.010 typ.
L 0.25 0.30 0.35 0.010 0.012 0.014
ECN: T16-0143-Rev. C, 18-Apr-16
DWG: 5995
Top View Bottom View
Side View
21
43
34
12
D
E
A
A1
b
e
L
A3
E2
D2
K
Index Area
(D/2 x E/2)
Pin #1 ID
(Optional)
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Controlling dimensions: millimeters converted to inch dimensions are
not necessarily exact.
3. Dimension “D” does not include mold flash, protrusion or gate burr.
Mold flash, protrusion or gate burr shall not exceed 0.15 mm
(0.006 inch) per side.
4. The package top shall be smaller than the package bottom.
Dimension “D” and “E1” are determined at the outer most extremes
of the plastic body exclusive of mold flash, tie bar burrs, gate burrs
and interlead flash, but including any mismatch between the top and
bottom of the plastic body.
C0.15 (0.006)
D
eB
D
e1
N5 N4 N3
N1 N2
E
E/2
b
Pin 1
E/1
E1/2
C0.15 (0.006)
C0.10 (0.004) MA BC
C0.10 (0.004)
A
C
SEATING
PLANE
A1
A2
SECTIION A-A
Base Metal
(b)
b1
c1 c
A A
DETAIL A
See Detail A
GAGE PLANE
0.15 (0.0059)
H
LU
U1
Package Information
Vishay Siliconix
Document Number: 73201
19-Nov-04
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1
SC-70: 3/4/5/6-LEADS (PIC ONLY)
Pin LEAD COUNT
Pin
Code 3 4 5 6
N1 − − 2 2
N2 2 2 3 3
N3 −3 4 4
N4 3− − 5
N5 −4 5 6
Package Information
Vishay Siliconix
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2Document Number: 73201
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MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A0.80 −1.10 0.031 −0.043
A1 0.00 −0.10 0.000 −0.004
A2 0.80 0.90 1.00 0.031 0.035 0.040
b0.15 −0.30 0.006 −0.012
b1 0.15 0.20 0.25 0.006 0.008 0.010
c0.08 −0.25 0.003 −0.010
c1 0.08 0.13 0.20 0.003 0.005 0.008
D1.90 2.10 2.15 0.074 0.082 0.084
E2.00 2.10 2.20 0.078 0.082 0.086
E11.15 1.25 1.35 0.045 0.050 0.055
e0.65 BSC 0.0255 BSC
e11.30 BSC 0.0512 BSC
L0.26 0.36 0.46 0.010 0.014 0.018
U0_−8_0_−8_
U1 4_10_4_10_
ECN: S-42145—Rev. A, 22-Nov-04
DWG: 5941
Document Number: 66558 www.vishay.com
Revision: 05-Mar-10 1
PAD Pattern
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TDFN4 1.2 x 1.6
Recommended Minimum Pads
Dimensions in mm
12
3
4
0.30
0.50
0.86
0.20 0.50
2.0
0.20
0.55 0.55
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Revision: 13-Jun-16 1Document Number: 91000
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