1
FEATURES
DESCRIPTION
APPLICATIONS
UV
OV
VDD
A
C
GND
GA TE
RSET
FL TR
R(SET)
PG
FLTB
STAT
V ol tage Source
Note:ComponentsonRSET,FLTR,
UVandOVareOPTIONAL.
BY P
RSV D
Common V oltage Rail
A C
C(BYP)
C(FLTR)
TPS2410
TPS2411
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.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
Full Featured N+1 and ORing Power Rail Controller
•Control External FET for N+1 and ORing
The TPS2410/11 controller, in conjunction with an•Wide Supply Voltage Range of 3 V to 16.5 V
external N-channel MOSFET, emulates the function•Controls Buses From 0.8 V to 16.5 V
of a low forward-voltage diode. The TPS2410/11 can•Linear or On/Off Control Method
be used to combine multiple power supplies to acommon bus in an N+1 configuration, or to combine•Internal Charge Pump for N-Channel MOSFET
redundant input power buses. The TPS2410 provides•Rapid Device Turnoff Protects Bus Integrity
a linear turn-on control while the TPS2411 has an•Positive Gate Control on Hot Insertion
on/off control method.•Soft Turn on Reduces Bus Transients
Applications for the TPS2410/11 include a wide range•Input Voltage Monitoring
of systems including servers and telecom. Theseapplications often have either N+1 redundant power•Shorted Gate Monitor
supplies, redundant power buses, or both. These•MOSFET Control-State Indicator
redundant power sources must have the equivalent of•Industrial Temperature Range: – 40 ° C to 85 ° C
a diode OR to prevent reverse current during faultsand hotplug. A TPS2410/11 and N-channel MOSFET•Industry-Standard 14-Pin TSSOP Package
provide this function with less power loss than aschottky diode.•N+1 Power Supplies
Accurate voltage sensing, programmable fast turn-offthreshold, and input filtering allow operations to be•Server Blades
tailored for a wide range of implementations and bus•Telecom Systems
characteristics.•High Availability Systems
A number of monitoring features are provided toindicate voltage bus UV/OV, ON/OFF state, and ashorted MOSFET gate.
Table 1. Family Features
TPS2410
TPS2411
TPS2412
TPS2413
Linear gate control √ √
ON/OFF gate control √ √
Adjustable turn-off threshold √ √ √ √
Fast comparator filtering √ √
Voltage monitoring √ √
Enable control √ √
Mosfet fault monitoring √ √
Status pin √ √
Figure 1. Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
DEVICE TEMPERATURE PACKAGE
(2)
ORDERING CODE MARKING
TPS2410 TPS2410PW TPS2410– 40 ° C to 85 ° C PW (TSSOP-14)TPS2411 TPS2411PW TPS2411
(1) Add an R suffix to the device type for tape and reel.(2) For the most current package and ordering information, see the Package Option Addendum at the endof this document, or see the TI website at www.ti.com .
over operating free-air temperature range, voltage are referenced to GND (unless otherwise noted)
VALUE UNIT
A, C, FLTR, V
DD
, STAT voltage – 0.3 to 18 VA above C voltage
(2)
7.5 VC above A voltage 18 VGATE
(3)
, BYP voltage – 0.3 to 30 VBYP
(3)
to A voltage – 0.3 to 13 VGATE above BYP voltage 0.3 VFLTR
(3)
to C voltage – 0.3 to 0.3 VOV, UV voltage – 0.3 to 5.5 VRSET voltage
(3)
– 0.3 to 7 VFLTB, PG voltage – 0.3 to 18 VSTAT, PG, FLTB sink current 40 mAGATE short to A or C or GND IndefiniteHuman body model 2 kVESD
Charged device model 500 VT
J
Maximum junction temperature Internally limited ° CT
stg
Storage temperature – 65 to 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) See the section " Bidirectional Blocking and Protection of C. "(3) Voltage should not be applied to these pins.
POWER RATINGPACKAGE θ
JA
– Low k ° C/W θ
JA
– High k ° C/W
High k T
A
= 85 ° C (mW)
PW (TSSOP) 173 99 404
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS: TPS2410/11
(1) (2) (3) (4) (5) (6) (7)
TPS2410
TPS2411
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.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
voltages are referenced to GND (unless otherwise noted)
MIN NOM MAX UNIT
V
DD
= V
(C)
(1)
3 16.5A, C Input voltage range TPS2410 V3≤V
DD
≤16.5 V 0.8 16.5A to C Operating voltage
(2)
5 VOV, UV Voltage range 0 5.25 VSTAT, PG, FLTB Continuous sinking current 6.8 mAR
(RSET)
Resistance range
(3)
1.5 ∞kΩ
C
(FLTR)
Capacitance Range
(3)
0 1000 pFC
(BYP)
Capacitance Range
(3) (4)
800 2200 10k pFT
J
Operating junction temperature – 40 125 ° CT
A
Operating free-air temperature – 40 85 ° C
(1) V
DD
must exceed 3 V to meet GATE drive specifications(2) See the section " Bidirectional Blocking and Protection of C. "(3) Voltage should not be applied to these pins.(4) Capacitors should be X7R, 20% or better
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(A)
, V
(C)
, V
DD
V
DD
rising 2.25 2.5V
DD
UVLO VHysteresis 0.25| I
(A)
|, Gate in active range 0.66 1A current mA| I
(A)
|, Gate saturated high 0.1C current | I
(C)
|, V
AC
≤0.1 V 10 µAWorst case, gate in active range 4.25 6V
DD
current mAGate saturated high 1.2
UV / OV / PG
UV threshold voltage V
(UV)
rising, V
(OV)
= 0 V, PG goes high 0.583 0.6 0.615 VOV threshold voltage V
(OV)
rising, V
(UV)
= 1 V, PG goes low 0.583 0.6 0.615 VResponse time 50-mV overdrive 0.3 0.6 µsHysteresis V
(UV)
and V
(OV)
7 mVPG sink current V
(UV)
= 0 V, V
(OV)
= 0 V, V
(PG)
= 0.4 V 4 mAUV / OV leakage current (source or sink) 1 µAPG leakage current (source or sink) V
(UV)
= 1 V, V
(OV)
= 0 V, 0 ≤V
(PG)
≤5 V 1 µA
FLTB
Sink current V
(FLTB)
= 0.4 V, V
(GATE-)A
= 0 V, V
(A-C)
= 0.1 V 4 mAV
(A)
= V
(C)
+ 20 mV, V
(GATE-A)
falling until FLTBV
(GATE-A)
fault threshold 0.5 0.78 1 Vswitches lowV
(A-C)
= 0.1 V, increase V
(A-C)
until FLTB switchesV
(A-C)
fault threshold 0.325 0.425 0.525 VlowDeglitch on assertion 3.4 msLeakage current (source or sink) 1 µA
(1) [3 V ≤V
(A)
≤18 V, V
(C)
= V
DD
] or [0.8 V ≤V
(A)
≤3 V, 3 V ≤V
DD
≤18 V](2) C
(FLTR)
= open, C
(BYP)
= 2200 pF, R
(RSET)
= open, STAT = open, FLT = open(3) UV = 1 V, OV = GND(4) – 40 ° C ≤T
J
≤125 ° C(5) Positive currents are into pins(6) Typical values are at 25 ° C(7) All voltages are with respect to GND.
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TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
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ELECTRICAL CHARACTERISTICS: TPS2410/11 (continued)over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STAT
Sink current V
(STAT)
= 0.4 V, V
(A)
= V
(C)
+ 0.1 V 4 mAInput threshold V
DD
≥3 V V
DD
/2 VResponse time From fast turn-off initiation 50 nsSource pull-up resistance 30 46 60 k Ω
FLTR
Filter resistance R
(FLTR-C)
520 Ω
TURN ON
TPS2410 forward turn-on and regulation
7 10 13 mVvoltage
TPS2410 forward turn-on / turn-off difference R
(RSET)
= open 7 mVTPS2411 forward turn-on voltage 7 10 13 mV
TURN OFF
GATE sinks > 10 mA at V
(GATE-A)
= 2 VV
(A-C)
falling, R
(RSET)
= open 1 3 5Fast turn-off threshold voltage mVV
(A-C)
falling, R
(RSET)
= 28.7 k Ω-17 -13.25 -10V
(A-C)
falling, R
(RSET)
= 3.24 k Ω-170 -142 -114Additional threshold shift with STAT held low -157 mVV
(A)
= 12 V, V
(A-C)
: 20 mV →-20 mV,Turn-off delay 70 nsV
(GATE-A)
begins to decreaseV
(A)
= 12 V, C
(GATE-GND)
= 0.01 µF,Turn-off time V
(A-C)
: 20 mV →-20 mV, 130 nsmeasure the period to V
(GATE)
= V
(A)
GATE
V
DD
= 3 V, V
(A-C)
= 20 mV 6 7 8Gate positive drive voltage, V
(GATE-A)
V5 V ≤V
DD
≤18 V, V
(A-C)
= 20 mV 9 10.2 11.5Gate source current V
(A-C)
= 50 mV, V
(GATE-A)
= 4 V 250 290 350 µASoft turn-off sink current (TPS2410) V
(A-C)
= 4 mV, V
(GATE-A)
= 2 V 2 5 mAV
(A-C)
= -0.1 VV
(GATE)
= 8 V 1.75 2.35 AFast turn-off pulsed current, I
(GATE)
V
(GATE)
= 5 V 1.25 1.75Period 7.5 12.5 µsV
(A-C)
= – 0.1 V, V
(C)
= V
DD
, 3 ≤V
DD
≤18 V,Sustain turn-off current, I
(GATE)
15 19.5 mA2 V ≤V
(GATE)
≤18 V
MISCELLANEOUS
Thermal shutdown temperature Temperature rising, T
J
135 ° CThermal hysteresis 10 ° C
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0.4V
+
-
C
+
-
FLTB
+
-
+
-
10mV
A
ON
GATE
’10: AMP.
’11:COMP.
VDD
Biasand
Control
UVLO
FLTR
OV
UV
0.6V
EN
UVLO
VBIAS
STAT
VDC
0.4V
RSET
A
PG
+
-
10V
A
BYP
C
+
-
GND
3mV
0.6V
+
-0.75V
ON
3ms
A
1
RSVD
ChargePump
andBiasSupply
HVUV
HVUV
EN
EN
FAST
COMP.
VDD
T >135 C
o
TPS2410
TPS2411
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.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
FUNCTIONAL BLOCK DIAGRAM
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VDD
RSET
STAT
OV
FLTB
UV
GND
PG
BYP
FLTR
A
C
RSVD
GATE
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
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PW PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
Input power for the gate drive charge pump and internal controls. V
DD
must be connected to a supply voltageV
DD
1 PWR
≥3 V.Connect a resistor to ground to program the turn-off threshold. Leaving RSET open results in a slightlyRSET 2 I
positive V
(A-C)
turn-off threshold.STAT is a multifunction pin. A high output indicates that the MOSFET gate is being driven high. OverdrivingSTAT 3 I/O
STAT low while GATE is high shifts the fast-turnoff threshold negative. STAT has a weak pull-up to V
DD
.Open drain fault output. Fault is active (low) for any of the following conditions:1. Insufficient V
DDFLTB 4 O
2. GATE should be high but is not.3. The MOSFET should be ON but the forward voltage exceeds 0.4 V.OV is a voltage monitor that contributes to the PG output, and also causes the MOSFET to turn off if it isOV 5 I above the 0.6-V threshold. OV is programmable via an external resistor divider. An OV voltage above 0.6 Vindicates a bus voltage that is too high.UV is a voltage monitor that contributes to the PG output. The UV input has a 0.6 V threshold and isUV 6 I programmable via an external resistor divider. A UV voltage above 0.6V indicates a bus voltage that is aboveits minimum acceptable voltage. A low UV input does not effect the gate drive.GND 7 PWR Device ground.GATE 8 O Connect to the gate of the external MOSFET. Controls the MOSFET to emulate a low forward-voltage diode.RSVD 9 PWR This pin must be connected to GND.Voltage sense input that connects to the simulated diode cathode. Connect to the MOSFET drain in theC 10 I
typical configuration.
Voltage sense input that connects to the simulated diode anode. A also serves as the reference for theA 11 I
charge-pump bias supply on BYP. Connect to the MOSFET source in the typical configuration.A capacitor connected from FLTR to A filters the input to the fast comparator. Filtering allows the TPS2410 toFLTR 12 I ignore spurious transients on the A and C inputs. This pin may be left open to achieve the fastest responsetime.BYP 13 I/O Connect a storage capacitor from BYP to A to filter the gate drive supply voltage.An open-drain Power Good indicator. PG is open if the UV input is above its threshold, the OV is below itsPG 14 O
threshold, and the internal UVLO is satisfied.
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DETAILED DESCRIPTION
TPS2410
TPS2411
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.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
The following descriptions refer to the pinout and the functional block diagram.
A, C: The A pin serves as the simulated diode anode and the C as the cathode. GATE is driven high when V
(AC)exceeds 10 mV. Both devices provide a strong GATE pull-down when V
(AC)
is less than the programmable fastturn-off threshold. The TPS2410 has a soft pull-down when V
(AC)
is less than 10 mV but above the fast turn-offthreshold.
Several internal comparator and amplifier circuits monitor these two pins. The inputs are protected from excessdifferential voltage by a clamp diode and series resistance. If C falls below A by more than about 0.7 V, a smallcurrent flows out of A. Protect the internal circuits with an external clamp if C can be more than 6 V lower than A.A small signal clamp diode and 1-k Ωresistor, or circuit per Figure 18 are suitable.
The internal charge pump output, which provides bias power to the comparators and voltage to drive GATE, isreferenced to A. Some charge pump current appears on A due to this topology. The A and C pins should beKelvin connected to the MOSFET source and drain. A and C connections should also be short and lowimpedance, with special attention to the A connection. Residual noise from the charge pump can be reduced witha bypass capacitor at A if the application permits.
BYP: BYP is the internal charge pump output, and the positive supply voltage for internal comparator circuits andGATE driver. A capacitor must be connected from BYP to A. While the capacitor value is not critical, a 2200-pFceramic is recommended. Traces to this part must be kept short and low impedance to provide adequate filtering.Shorting this pin to a voltage below A damages the TPS2410/11.
FLTR: The internal fast comparator input may be filtered by placing a small capacitor from FLTR to A. This isuseful in situations where the ambient noise or transients might falsely trigger a MOSFET turnoff. While C
(FLTR)will suppress small transients, large voltage reversals will see relatively small additional turn-off delay.
FLTR is clamped to C and should only be used with a capacitor as shown in Figure 14 . Connections to FLTRshould be short and direct to minimize parasitic capacitive loading and crosstalk. The filter pin may not beshorted to any other voltage.
FLTB: The FLTB pin is the open-drain fault output. FLTB sinks current when the MOSFET should be enabled,but either there is no GATE voltage, V
(AC)
is greater than 0.4 V with GATE driven ON, the internal UVLO is notsatisfied. FLTB has a 3-ms deglitch filter on the falling edge to prevent transients from creating false signals.FLTB may not be valid at voltages below the internal V
DD
UVLO.
GATE: Gate connects to the external N channel MOSFET gate. GATE is driven positive with respect to A by adriver operating from the voltage on BYP. A time-limited high current discharge source pulls GATE to GND whenthe fast turn-off comparator is activated. The high-current discharge is followed by a sustaining pull-down. Theturn-off circuits are disabled by the thermal shutdown, leaving a resistive pull-down to keep the gate from floating.The gate connection should be kept low impedance to maximize turn-off current.
GND: This is the input supply reference. GND should have a low impedance connection to the ground plane. Itcarries several Amperes of rapid-rising discharge current when the external MOSFET is turned off, and alsocarries significant charge pump currents.
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-470.02
R(RSET) V - 0.00314
(OFF)
æ ö
ç ÷
=ç ÷
è ø
(1)
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
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RSET: A resistor connected from this pin to GND sets the MOSFET fast turn-off comparator threshold. Thethreshold is slightly positive when the RSET pin is left open. Current drawn by the resistor programs the turn-offvoltage to increasing negative values. The TPS2411 must have a negative threshold programmed to avoid anunstable condition at light load. The expression for R(RSET) in terms of the fast comparator-trip voltage, V
(OFF)
,follows.
The units of the numerator are (V × V/A). V
(OFF)
is positive for V
(A)
greater than V
(C)
, V
(OFF)
is less than 3 mV, andR
(RSET)
is in ohms.
RSVD: Connect to ground.
STAT: STAT is a multifunction pin. STAT outputs the status of the GATE pin drive. The internal weak pull-uppulls STAT to V
DD
when GATE is being driven high and V
(GATE)
is 0.4 V greater than V
(A)
. If STAT is externallypulled below V
DD
/2 while the pin would otherwise be high, the turnoff threshold is shifted negative (~157 mV)from the RSET programmed value. Interconnecting the STAT pins of redundant devices, in systems thatnormally have both devices on, reduces the likelihood that both devices will turn off in the event of a transient.See the FUNCTIONAL BLOCK DIAGRAM,INPUT ORing and STAT, and Figure 13 .
UV, OV, PG: These signals are used to monitor an input voltage for proper range. PG sinks current to GND if UVis below its threshold, OV is above its threshold, or V
DD
is below the internal UVLO. PG may not be valid whenV
DD
is below the UVLO.
A high input on OV causes GATE to be driven low. UV does not effect the MOSFET operation. This permits OVto be used as an active-high disable.
OV and UV should be connected to ground when not used, and PG may be left open. Multiple PG pins to be wireORed using a common pull-up resistor.
V
DD
:V
DD
is the primary supply for the gate drive charge pump and other internal circuits. This pin must beconnected a source that is 3 V or greater when the external MOSFET is to be turned on. V
DD
may be greater orlower than the controlled bus voltage.
A 0.01- µF bypass capacitor, or 10- Ωand a 0.0 1- µF filter, is recommended because charge pump currents aredrawn through V
DD
.
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TYPICAL CHARACTERISTICS
0.5
1.5
2.0
2.5
3.0
0 2 4 6 8 10
I(GATE) − A
V − V
(GATE - GND)
1.0
0.0
T =125 C
J
o
T =85 C
J
o
T =25 C
J
o
T =-40 C
J
o
8.5
9.5
10.5
11.5
12.0
−40 −20 0 20 40 60 80 100 120
V(AC) − mV
T − JunctionT
Jemperature − C
o
11.0
10.0
9.0
8.0
R =Open
(RSET)
1.5
2.5
3.5
4.5
5.0
−40 −20 0 20 40 60 80 100 120
V(AC) − mV
T − JunctionT
Jemperature − C
o
4.0
3.0
2.0
1.0
T =125 C
J
o
T =25 C
J
o
T =-40 C
J
o
10
20
40
50
60
2 4 6 8 10 12 14 16 18
Delay − sm
V − V
DD
30
0
T =-40 C
J
o
T =125 C
J
o
T =25 C
J
o
0.5
1.0
2.0
2.5
3.0
2 4 6 8 10 12 14 16 18
I(VDD) −mA
V − V
DD
1.5
0.0
TPS2410
TPS2411
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.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
TPS2410 V
(AC)
REGULATION
VOLTAGE FAST TURNOFF THRESHOLD PULSED GATE SINKING CURRENTvs vs vsTEMPERATURE TEMPERATURE GATE VOLTAGE
Figure 2. Figure 3. Figure 4.
TURNON DELAY
vs V
DD
CURRENTV
DD
vs(POWER APPLIED UNTIL GATE IS V
DD
VOLTAGEACTIVE) (GATE SATURATED HIGH)
Figure 5. Figure 6.
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V (Right)
(GATE)
at5V/div
V (Left)
(GATE)
at5V/div
V (Left)
(AC)
at20mV/div
V (Left)
(STAT)
at10V/div
50ns/div
V(AC)
GATE
V(STAT)
V (Left)
(AC)
at10mV/div
V (Right)
(GATE)
at10V/div V (Left)
(GATE)
at10V/div
V (Right)
(IN)
at20mVac/div
500 μs/div
V(AC)
GATE
V(IN)
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)TYPICAL TURNOFF WITH TWO ORED DEVICES ACTIVE(V
DD
= 12 V, I
(LOAD)
= 5 A, IRL3713,TRANSIENT APPLIED TO LEFT SIDE)
Figure 7.
TYPICAL TURNOFF AND RECOVERY WITH TWO ORED DEVICES ACTIVE(V
DD
= 3 V, V
A
= 18 V, I
(LOAD)
= 5 A, IRL3713,TRANSIENT APPLIED TO LEFT SIDE)
Figure 8.
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V
at2V/div
(GATE)
I
at2A/div
(GATE)
Delay=70ns,V =1Vat113ns
(GATE)
V
at20mV/div
(AC)
20ns/div
V(AC)
GATE
I(GATE
TPS2410
TPS2411
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.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
TYPICAL CHARACTERISTICS (continued)TURNOFF TIME WITHC
(GATE)
= 10 nF and V
(AC)
= -20 mV, V
DD
= V
A
= 12 V
Figure 9.
TURNOFF TIME WITHC
(GATE)
= 10 nF, V
(AC)
= -20 mV, V
DD
= 5, V
A
= 1 V
Figure 10.
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APPLICATION INFORMATION
OVERVIEW
Gate
ON
Gate
OFF
1 0 m V
3 m V
Programmable
FastTurn-off
Threshold
Gnd
1 0 m V
3 m V
Programmable
FastTurn-off
Threshold
Active
Regulation
SlowTurn-off
Range
TPS2411
(SeeText)
TPS2410
(SeeText)
V +10V
(A)
V +V
(A) (T)
V(AC) V(AC)
V(GATE)
V(GATE)
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
www.ti.com
The TPS2410/11 is designed to allow output ORing in N+1 power supply applications (see Figure 12 ) andinput-power bus ORing in redundant source applications (see Figure 13 ). The TPS2410/11 and externalMOSFET emulate a discrete diode to perform this unidirectional power combining function. The advantage to thisemulation is lower forward voltage drop and the ability to tune operation.
The TPS2410 turns the MOSFET on with a linear control loop that regulates V
(AC)
to 10 mV as shown inFigure 11 . With the gate low, and V
(AC)
increasing to 10 mV, the amplifier drives GATE high with all availableoutput current until regulation is reached. The regulator controls V
(GATE)
to maintain V
(AC)
at 10 mV as long as theMOSFET r
DS(on)
× I
(DRAIN)
is less than this the regulated voltage. The regulator drives GATE high, turning theMOSFET fully ON when the r
DS(on)
× I
(DRAIN)
exceeds 10 mV, otherwise V
(GATE)
will be near V
(A)
plus theMOSFET gate threshold voltage. If the external circuits force V
(AC)
below 10 mV and above the programmed fastturnoff, GATE is slowly turned off. GATE is rapidly pulled to ground if V
(AC)
falls to the RSET programmed fastturn-off threshold.
The TPS2411 turns the MOSFET on and off like a comparator with hysteresis as shown in Figure 11 . GATE isdriven high when V
(AC)
exceeds 10 mV, and rapidly turned off if V
(AC)
falls to the RSET programmed fast turn-offthreshold.
System designs should account for the inherent delay between a TPS2410/11 circuit becoming forward biased,and the MOSFET actually turning ON. The delay is the result of the MOSFET gate capacitance charge fromground to its threshold voltage by the 270 µA gate current. If there are no additional sources holding the ORedrail voltage up, the MOSFET internal diode will conduct and maintain voltage on the ORed output, but there willbe some voltage droop. This condition is analogous to the power source being ORed in this case. The DC/DCconverter output voltage droops when its load increases from zero to a high value. Load sharing techniques thatkeep all ORed sources active solve this condition.
Figure 11. TPS2410/11 Operation
12 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2410 TPS2411
TPS2410 vs TPS2411 – MOSFET CONTROL METHODS
TPS2410
TPS2411
www.ti.com
.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
The operation of the two parts is summarized in Table 2 .
Table 2. Operation as a Function of V
AC
Turnoff Threshold
(1)
≤V
AC
≤10 mVV
(AC)
≤Turnoff Threshold
(1)
V
(AC)
> 10 mV(MOSFETV
(AC)
Forced < 10 mV
r
DS(on)
× I
LOAD
)≤10 mV
Weak GATE pull-downTPS2410 Strong GATE pull-down (OFF) V
(AC)
regulated to 10 mV GATE pulled high (ON)(OFF)TPS2411 Strong GATE pull-down (OFF) Depends on previous state GATE pulled high (ON)(Hysteresis region)
(1) Turnoff threshold is established by the value of RSET.
The TPS2410 control method yields several benefits. First, the low current GATE driver provides a gentle turn-onand turn-off for slowly rising and falling input voltage. Second, it reduces the tendency for on/off cycling of acomparator based solution at light loads. Third, it avoids reverse currents if the fast turn-off threshold is leftpositive. The drawback to this method is that the MOSFET appears to have a high resistance at light load whenthe regulation is active. A momentary output voltage droop occurs when a large step load is applied from alight-load condition. The TPS2410 is a better solution for a mid-rail bus that will be re-regulated.
The TPS2411 turns the MOSFET on if V
(AC)
is greater than 10 mV, and hard off when V
(AC)
is less than theRSET programmed threshold. There is no linear control range and slow turn-off. The disadvantage is that theturn-off threshold must be negative (unless a specified load is always present) permitting a continuous reversecurrent. Under a dynamic reverse voltage fault, the lower threshold voltage may permit a higher peak reversecurrent. There are a number of advantages to this control method. Step loads from a light load condition arehandled without a voltage droop beyond I × R. If the redundant converter fails, applications with redundantsynchronous converters may permit a small amount of reverse current at light load in order to assure that theMOSFET is all ready on. The TPS2411 is a better solution for low-voltage busses that will not be re-regulated,and that may see large load steps transients.
These applications recommendations are meant as a starting point, with the needs of specific implementationsover-riding them.
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS2410 TPS2411
N+1 POWER SUPPLY – TYPICAL CONNECTION
CommonBus
Concept
VDD
A
C
GND
GATE
Power Conversion Block
Input
Voltage
Power
Bus
Implementation
C(BYP)
BYP
DC/DC
Converter
DC/DC
Converter
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
www.ti.com
The N+1 power supply configuration shown in Figure 12 is used where multiple power supplies are paralleled foreither higher capacity, redundancy or both. If it takes N supplies to power the load, adding an extra, identical unitin parallel permits the load to continue operation in the event that any one of the N supplies fails. The suppliesare ORed together, rather than directly connected to the bus, to isolate the converter output from the bus when itis plugged-in or fails short. The TPS2410/11 with an external MOSFET emulates the function of the ORing diode.
It is possible for a malfunctioning converter in an ORed topology to create a bus overvoltage if the loading is lessthan the converter ’ s capacity (e.g. N = 1). The ORed topology shown cannot protect the bus from this condition,even if the ORing MOSFET can be turned off. One common solution is to use two MOSFETs in a back-to-backconfiguration to provide bidirectional blocking. See the section on BIDIRECTIONAL BLOCKING ANDPROTECTION OF C.
ORed supplies are usually designed to share power by various means, although the desired operation couldimplement an active and standby concept. Sharing approaches include both passive, or voltage droop, andactive methods. Not all of the output ORing devices may be active depending on the sharing control method, busloading, distribution resistences, and TPS2410/11 settings.
Figure 12. N+1 Power Supply Example
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Product Folder Link(s): TPS2410 TPS2411
INPUT ORing – TYPICAL CONNECTION
Optional Connection
Plug-In Unit
STAT
STAT
SYSTEM DESIGN AND BEHAVIOR WITH TRANSIENTS
TPS2410
TPS2411
www.ti.com
.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
Figure 13 shows how redundant buses may be ORed to a common point to achieve higher reliability. It ispossible to have both MOSFETs ON at once if the bus voltages are matched, or the combination of toleranceand regulation causes both TPS2410/11 circuits to see a forward voltage. The ORing MOSFET disconnects thelower-voltage bus, protecting the remaining bus from potential overload by a fault.
Figure 13. Example ORing of Input Power Buses
The power system, perhaps consisting of multiple supplies, interconnections, and loads, is unique for everyproduct. A power distribution has low impedance, and low loss, which yields high Q by its nature. While theaddition of lossy capacitors helps at low frequencies, their benefit at high frequencies is compromised byparasitics. Transient events with rise times in the 10-ns range may be caused by inserting or removing units, loadfluctuations, switched loads, supply fluctuations, power supply ripple, and shorts. These transients cause thedistribution to ring, creating a situation where ORing controllers may trip off unnecessarily. In particular, when anORing device turns off due to a reverse current fault, there is an abrupt interruption of the current, causing a fastringing event. Since this ringing occurs at the same point in the topology as the other ORing controllers, they arethe most likely to be effected.
The ability to operate in the presence of noise and transients is in direct conflict with the goal of precise ORingwith rapid response to actual faults. A fast response reduces peak stress on devices, reduces transients, andpromotes un-interrupted system operation. However, a control with small thresholds and high speed is mostlikely to be falsely tripped by transients that are not the result of a fault. The power distribution system should bedesigned to control the transient voltages seen by fast-responding devices such as ORing and hotswap devices.
The TPS2410 was designed with several features to help tune its speed and sensitivity to individual systems.The FLTR pin provides a convenient place to filter the bus voltage before it causes undesired tripping (see FastComparator Input Filtering – C
(FLTR)
). Some applications may find it possible to use RSET to advantage bysetting the reverse turn-off threshold more negative. Last, the STAT pin may be used to desensitize the turnoffthreshold of an on-line TPS2410 when a redundant TPS2410 has turned off. This is especially attractive in dualredundant systems (see Input ORing and STAT). Ultimately, the performance may have to be tuned to fit thecharacteristics of each particular system.
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS2410 TPS2411
RECOMMENDED OPERATING RANGE
TPS2410 REGULATION-LOOP STABILITY
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
www.ti.com
The maximum recommended bus voltage is lower than the absolute maximum voltage ratings on A, C, and V
DDsolely to provide margin for transients on the bus. Most power systems experience transient voltages above thenormal operating level. Short transients, or voltage spikes, may be clamped by the ORing MOSFET to an outputcapacitor and/or voltage rail depending on the system design. Transient protection, e.g. a TVS diode (transientvoltage suppressor, a type of Zener diode), may be required on the input or output if the system design does notinherently limit transient voltages below the TPS2410/11 absolute maximum ratings. If a TVS is required, it mustprotect to the absolute maximum ratings at the worst case clamping current. The TPS2410/11 will operateproperly up to the absolute maximum voltage ratings on A, C, and V
DD
.
The TPS2410 uses an internal linear error amplifier to keep the external MOSFET from saturating at light load.This feature has the benefits of setting a turn-off above 0 V, providing a soft turn-off for slowly decaying inputvoltages, and helps droop-sharing redundancy at light load.
Although the control loop has been designed to accommodate a wide range of applications, there are a fewguidelines to be followed to assure stability.•Select a MOSFET C
(ISS)
of 1 nF or greater•Use low ESR bulk capacitors on the output C terminal, typically greater than 100 µF with less than 50 m ΩESR
•Maintain some minimum operational load (e.g. 100 mA or more)
Symptoms of stability issues include V
(AC)
undershoot and possible fast turn-off on large-transient recovery, anda worst-case situation where the gate continually cycles on and off. These conditions are solved by following therules above. Loop stability should not be confused with tripping the fast comparator due to V
(AC)
tripping the gateoff.
Although not common, a condition may arise where the dc/dc converter transient response may cause the GATEto cycle on and off at light load. The converter experiences a load spike when GATE transitions from OFF to ONbecause the ORed bus capacitor voltage charges abruptly by as much as a diode drop. The load spike maycause the supply output to droop and overshoot, which can result in the ORed capacitor peak charging to theovershoot voltage. When the supply output settles to its regulated value, the ORed bus may be higher than thesource, causing the TPS2410/11 to turn the GATE off. While this may not actually cause a problem, itsoccurrence may be mitigated by control of the power supply transient characteristic and increasing its outputcapacitance while increasing the ORed load to capacitance ratio. Adjusting the TPS2410 turn-off threshold orusing STAT if possible to desensitize the redundant ORing device may help as well. Careful attention to layoutand charge-pump noise around the TPS2410/11 helps with noise margin.
The linear gate driver has a pull-up current of 290 µA and pull-down current of 3 mA typical.
16 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2410 TPS2411
MOSFET SELECTION AND R
(RSET)
-470.02
R(RSET) V - 0.00314
(OFF)
æ ö
ç ÷
=ç ÷
è ø
(2)
I(TURN_OFF) =- 1 A
V(THRESHOLD)
rDS(on)
-10mV
10mW
I(TURN_OFF) =
I(TURN_OFF) =
(3)
TPS2410
TPS2411
www.ti.com
.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
MOSFET selection criteria include voltage rating, voltage drop, power dissipation, size, and cost. The voltagerating consists of both the ability to withstand the rail voltage with expected transients, and the gate breakdownvoltage. The MOSFET gate rating should be the minimum of 12 V or the controlled rail voltage. Typically thisrequires a ± 20 V GATE voltage rating.
While r
DS(on)
is often chosen with the power dissipation, voltage drop, size and cost in mind, there are severalother factors to be concerned with in ORing applications. When using the TPS2410, the minimum voltage acrossthe device is 10 mV. A device that would have a lower voltage drop at full-load would be overspecified. Whenusing a TPS2411 or TPS2410 with RSET programmed to a negative voltage, the permitted static reverse currentis equal to the turn-off threshold divided by the r
DS(on)
. While this current may actually be desirable in somesystems, the amount may be controlled by selection of r
DS(on)
and RSET. The practical range of r
DS(on)
runs fromthe low milliohms to 40 m Ωfor a single MOSFET.
MOSFETs may be paralleled for lower voltage drop (power loss) at high current. For TPS2410 operation, oneshould plan for only one of the MOSFETs to carry current until the 10 mV regulation point is exceeded and theloop forces GATE fully ON. TPS2411 operation does not rely on linear range operation, so the MOSFETs are allON or OFF together except for short transitional times. Beyond the control issues, current sharing depends onthe resistance match including both the r
DS(on)
and the connection resistance.
The TPS2410 may be used without a resistor on RSET. In this case, the turnoff V
(AC)
threshold is about 3 mV.The TPS2411 may only be operated without an RSET programming resistor if the loading provides a higherV
(AC)
. A larger negative turnoff threshold reduces sensitivity to false tripping due to noise on the bus, but permitslarger static reverse current. Installing a resistor from RSET to ground creates a negative shift in the fast turn-offthreshold per Equation 2 .
To obtain a – 10 mV fast turnoff ( V
(A)
is less than V
(C)
by 10 mV ), R
(RSET)
= ( – 470.02/ ( – 0.01 – 0.00314) ) ≈35,700 Ω. If a 10 m Ωr
DS(on)
MOSFET was used, the reverse turnoff current is calculated as follows.
The sign indicates that the current is reverse, or flows from the MOSFET drain to source ( C to A ).
The turn-off speed of a MOSFET is influenced by the effective gate-source and gate-drain capacitance (C
ISS
).Since these capacitances vary a great deal between different vendor parts and technologies, they should beconsidered when selecting a MOSFET where the fastest turn-off is desired.
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS2410 TPS2411
GATE DRIVE, CHARGE PUMP AND C
(BYP)
FAST COMPARATOR INPUT FILTERING – C
(FLTR)
( ) æ ö
ç ÷
è ø
v2
t = - R × C × ln
DLY (FLTR) v -v
2 1
(4)
C(FLTR)
Source Load
ACFLTR
Fast
Comparator
Turn-on
Amplifier/
Comparator
v1
tDLY
time
Comparator Input
Bus Transient
VFLTR-A
v1tDLY
time
Comparator Input
Bus Transient
VF LTR -A
DtDLY
V(FLTR-A)
V(FLTR-A)
V2
V1
V1
V2
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
www.ti.com
Gate drive of 270 µA typical is generated by an internal charge pump and current limiter. A separate supply, V
DD
,is provided to avoid having the large charge pump currents interfere with voltage sensing by the A and C pins.The GATE drive voltage is referenced to V
(A)
as GATE will only driven high when V
(A)
> V
(C)
. The recommendedcapacitor on BYP (bypass) must be used in order to form a quiet supply for the internal high-speed comparator.V
(GATE)
must not exceed V
(BYP)
.
The FLTR (filter) pin enables a simple method of filtering the input to the fast turn-off comparator asdemonstrated in Figure 14 . To minimize the impact of a bus fault, the ORing controller turns off the externalMOSFET as fast as possible when a voltage reversal occurs. However, having a fast reaction increases thelikelihood that noise or non-fault transients may cause false triggering. Examples of such transients are ESD,EFT, RF induction, step loads, and insertion of high-inrush units. The effect of the filter on a time-domaintransient are illustrated by assuming a step input from positive to negative. The expression for the time to reach 0V across the fast comparator inputs follows, where the variables are defined in Figure 14 .
Figure 14 graphically illustrates that the external MOSFET is turned off after a longer delay for a small transientthan a large voltage reversal. For example, the delay from 10 mV forward to 10-mV reverse is about 52 ns (R =520 Ω, C = 150 pF), while the delay for a 100-mV reverse transient is 7 ns. It is unlikely that the transient in areal system is a step response, making exact calculations on the effect of the R-C filter to a specific transientdifficult.
The need for a C
(FLTR)
, and its value, is dependent on the electrical noise environment of the particular system. Ifthe electrical environment is understood, the need for the filter, or its value, is selected based on approximationsor simulations. If the system is not understood or does not exist when the TPS2410 circuit design is completed, itis recommended that a C
(FLTR)
of 100 pF be included in initial schematics. Evaluation of system performance mayallow removal of C
(FLTR)
. The tolerance of the internal resistance is about ± 25% including temperature variations.
Figure 14. Fast Comparator Input Filtering
18 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2410 TPS2411
UV, OV, AND PG
Logic
Supply
BasicSupply
Monitoring
GND
Monitored Input Supply
UV
OV PG
RA
RB
RC
To
Monitor
P/O
TPS2410
Logic
Supply
GND
UV
OV PG To
Monitor
P/O
TPS2410
Logic
Supply
OVusedasanEnable
TPS2410
TPS2411
www.ti.com
.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
The UV and OV inputs can be used in a several ways. These include voltage monitoring and forcing the passMOSFET off.
A voltage bus may be monitored for undervoltage with the UV pin, and overvoltage with the OV pin. Figure 15demonstrates a basic three resistor divider, however, two separate two resistor dividers may be used. PG is highif V
(UV)
exceeds the UV threshold, and V
(OV)
is below the OV threshold, else PG is low. Each of these inputs hasa 0.6-V threshold and 7 mV of hysteresis. Optionally, UV and OV may be independently disabled by connectingthem to ground, and PG may be left floating if not used. The state of PG is undefined until the internal UVLO issatisfied.
GATE is forced low if V
(OV)
exceeds 0.6 V. This allows OV to be used as an enable as shown in Figure 15 . Thiscan be used for testing purposes, or control of back-to-back MOSFETs to force an output off even though V
(AC)
isgreater than 10 mV.
Figure 15. UV, OV, AND PG
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS2410 TPS2411
V
DD
, BYP, and POWERING OPTIONS
VDD
A
C
GND
GATE
Input
Voltage
3.3V-18V
Common
Bus
CommonBusPowering
*OptionalFiltering
10*
VDD
A
C
GND
GATE
Input
Voltage
0.8V-18V
Common
Bus
SeparateBusPowering
*OptionalFiltering
5V
2200pF BYP
2200pF BYP
0.01 Fm
0.01 Fm
10*
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
www.ti.com
The separate V
DD
pin provides flexibility for operational power and controlled rail voltage. While the internalUVLO has been set to 2.5 V, the TPS2410/1 requires at least 3 V to generate the specified GATE drive voltage.Sufficient BYP voltage to run internal circuits occurs at V
DD
voltages between 2.5 V and 3 V. There are threechoices for power, A, C, or a separate supply, two of which are demonstrated in Figure 16 . One choice forvoltage rails over 3.3 V is to power from C, since it is typically the source of reliable power. Voltage rails below3.3 V, e.g. 2.5 V and below, should use a separate supply such as 5 V. A separate V
DD
supply can be used tocontrol voltages above it, for example 5 V powering V
DD
to control a 12-V bus.
V
DD
is the main source of power for the internal control circuits. The charge pump that powers BYP draws mostof its power from V
DD
. The input should be low impedance, making a bypass capacitor a preferred solution. A10- Ωseries resistor may be used to limit inrush current into the bypass capacitor, and to provide noise filteringfor the supply.
BYP is the interconnection point between a charge pump, V
(AC)
monitor amplifiers and comparators, and the gatedriver. C
(BYP)
must be used to filter the charge pump. A 2200 pF is recommended, but the value is not critical.
Figure 16. V
DD
Powering Examples
20 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2410 TPS2411
INPUT ORing AND STAT
OV
GND
STAT
PullLow
toReset
LogicRail
TPS2410
TPS2411
www.ti.com
.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
STAT provides information regarding the state of the MOSFET gate drive. STAT is pulled to V
DD
, through a46-k Ωinternal pullup, if GATE is being driven high and V
(GATE)
exceeds V
(A)
plus 0.4 V. The STAT pin may bedirectly connected to low-voltage logic by using the logic gate's input ESD clamp to control the voltage or byusing a much lower pullup resistor (e.g., 5 k Ω) to the logic supply voltage. STAT must be allowed to rise aboveV
DD
/2 to avoid effecting the reverse turn-off threshold.
Interconnecting STAT pins can be used to reduce the occurence of both MOSFETs turning off in topologies suchas Figure 13 that normally have both MOSFETs ON. This might occur when there is a noise transient on bothbuses due to fans cycling on and off, or an ac mains disturbance. If both MOSFETs are ON, and then an ORingcircuit turns OFF, the second ORing circuit's fast turnoff threshold is shifted negative by 157 mV from the RSETprogrammed value because STAT is pulled low. This reduces the probability that it too will turn off as the arrivalof the transient, and speed of both circuits, is unlikely to be matched. Maintaining at least one device ON avoidsboth a bus transient due to the current interruption, and momentary downstream hotswap overload when theORing recovers. The function of STAT is not limited to the topology of Figure 13 and may be used to dynamicallyshift the fast turnoff threshold. The internal circuit shown in the FUNCTIONAL BLOCK DIAGRAM will assist indesigning these applications.
Figure 17 shows how STAT and OV can be used to latch the TPS2410 off. This is useful when a systemoperation benefits from preventing a failed power module from repeatedly disturbing the bus, and may be used inconjunction with back-to-back MOSFETs. The OV pin must be help low until V
(GATE)
is 0.4 V above V
(A)
in orderto accomplish a reset.
Figure 17. Use of STAT and OV to Latch TPS2411 OFF
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS2410 TPS2411
BIDIRECTIONAL BLOCKING AND PROTECTION OF C
UV
OV
VDD
A
CGND
GATE
Power
Bus
BY P
1kW
SST270
Control
Switchable
Input
C(BYP)
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
www.ti.com
The TPS2410/11 may be used in applications where bidirectional blocking is desired. This may occur insituations where two different voltages are ORed together, and operation from the lower voltage is desired.Another important application allows isolation of a redundant unit that is generating too high an output voltage.There are two considerations, first is the selection of the V
DD
source, and second is protection of the C pin fromexcessive current. Figure 18 provides an example of this type of application.
V
DD
needs to have voltage applied when A is to be connected to the load. Connecting V
DD
to C only works whenvoltage on C is always present before A is connected. V
DD
may be connected to A, a separate supply, or havevoltage from A ORed with voltage from C. OV may be used to force GATE low, even when V
(A)
is greater thanV
(C)
, by driving OV to a voltage between 0.6 V and less than 5.25 V.
The C pin must be protected from excessive current if V
(A)
can exceed V
(C)
by more than 5.5 V. With a singleMOSFET, V
(C)
will never be more than a diode drop lower than V
(A)
. When V
(AC)
is greater than a diode drop, asmall current flows out of the C pin into the load. If V
(AC)
exceeds 5.5 V, a current limiting circuit should be usedto protect C. Figure 18 provides an example circuit. Inserting this protection circuit creates a small offset in theforward regulation and threshold voltage.
Figure 18. Bidirectional Blocking Example
22 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2410 TPS2411
ORing EXAMPLES
Input1
Input2
2200pF
Output
VDD
C
GATE
BYP
A
GND
2 20 0 pF
VDD
C
GATE
BYP
A
GND
STAT
Input1
Input2 Output
10kW
TPS2410
TPS2411
www.ti.com
.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
Applications with the TPS2410/11 are not limited to ORIng of identical sections. The TPS2410/11 and externalMOSFET form a general purpose function block. Figure 19 shows a circuit with ORing between a discrete diodeand a TPS2410/MOSFET section. This circuit can be used to combine two different voltages in cases where theoutput is reregulated, and the additional voltage drop in the Input 1 path is not a concern. An example is ORingof an ac adapter on Input 1 with a lower voltage on Input 2 Figure 20 shows an improved efficiency version of thefirst in which a P MOSFET replaces the simple diode. This circuit may not be useful in applications where Input 1may be shorted because the P MOSFET is not managed, permitting reverse current flow. Input 2 should be thelower of the two voltage rails. If Input 1 was the lower voltage rail and connected first, then Input 2 is connected,there will be a momentary reverse current in the P MOSFET. The reverse current occurs because the STATsignal will not go high until V
GATE
ramps above Input 2 (the higher voltage) by 0.4 V. The Input 1 to Input 2difference voltage momentarily appears across the PMOS device which is turned on until STAT switches high,causing a reverse current. The highest efficiency with the best fault tolerance is provided by twoTPS2410/MOSFET sections.
Figure 19. ORing Circuit Figure 20. P MOSFET Circuit
The TPS2410 may be a better choice in applications where inputs may be removed, causing an open-circuitinput. If the MOSFET was ON when the input is removed, V
AC
will be virtually zero. If the reverse turn-offthreshold is programmed negative, the TPS2410/11 will not pull GATE low. A system interruption could then becreated if a short is applied to the floating input. For example, if an ac adapter is first connected to the unit, andthen connected to the ac mains, the adapter's output capacitors will look like a momentary short to the unit. ATPS2410 with RSET open will turn the MOSFET OFF when the input goes open circuit.
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPS2410 TPS2411
SUMMARIZED DESIGN PROCEDURE
UV
OV
VDD
A
C
GND
GATE
R SET
FLTR
PG
FLTB
STAT
Input
Voltage
Common
Voltage
BY P
R SV D
Logic
Voltage
See
Text
M1
OptionalLogic
Interface
R(VDD)
10kW
10kW
C(FLTR)
C(BYP)
C(A)
C(VDD)
R(A)
R(B)
R(C)
R(RSET)
Layout Considerations
TPS2410
TPS2411
SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009 ..................................................................................................................................................
www.ti.com
The following is a summarized design procedure:1. Choose between the TPS2410 or 2411, see TPS2410 vs TPS2411 – MOSFET Control Methods2. Choose the V
DD
source. Table 3 provides a guide for where to connect V
DD
that covers most cases. V
DD
maybe directly connected to the supply, but an R
(VDD)
/ C
(VDD)
of 10 Ω/ 0.01 µF is recommended.
Table 3. V
DD
Connection Guide
V
A
< 3 V 3 V ≤V
A
≤3.5 V V
A
> 3.5 V
Bias Supply > 3 V V
A
or Bias Supply > 3 V. V
C
if always > 3 V V
C
, V
A
or Bias for special configurations
3. Noise voltage and impedance at the A pin should be kept low. C
(A)
may be required if there is noise on thebus, or A is not low impedance. If either of these is a concern, a C
(A)
of 0.01 µF or more may be required.4. Select C
(BYP)
as 2200 pF, X7R, 25-V or 50-V ceramic capacitor.5. If the noise and transient environment is not well known, design C
(FLTR)
in, then experimentally determine if itis required. Start with a 100 pF, X7R, 25-V or 50-V ceramic capacitor and adjust if necessary.6. Select M1 based on considerations of voltage drop, power dissipated, voltage ratings, and gate capacitance.See sections: MOSFET Selection and RSET and TPS2410 Regulation-Loop Stability.7. Select R
(RSET)
based on which MOSFET was chosen and reverse current considerations – see MOSFETSelection and RSET. If the noise and transient environment is not well known, make provision for R
(RSET)even when using the TPS2410.8. Configure the UV and OV inputs per the desired behavior – UV, OV, and PG. Calculate the resistor dividers.9. Add optional interface for PG, FLTB, and STAT as desired.10. Make sure to connect RSVD to ground.
Figure 21. Design Template
See Figure 21 for reference designations.1. The TPS2410/11, M1, and associated components should be used over a ground plane.2. The GND connection should be short with multiple vias to ground.3. C
(VDD)
should be adjacent to the V
DD
pin with a minimal ground connection length to the plane.4. The GATE connection should be short and wide (e.g., 0.025" minimum).5. The C pin should be Kelvin connected to M1.6. The A pin should be a short, wide, Kelvin connection to M1 and the bus.7. C
(BYP)
, C
(FLTR)
, and R
(RSET)
should be kept immediately adjacent to the TPS2410/11 with short leads.8. Do not run noisy signals adjacent to FLTR.
24 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2410 TPS2411
TPS2410
TPS2411
www.ti.com
.................................................................................................................................................. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
Revision History
Changes from Revision B (November, 2006) to Revision C .......................................................................................... Page
•Changed STAT pullup voltage typo ....................................................................................................................................... 5•Changed I/O entry and description of STAT .......................................................................................................................... 6•Changed STAT Detailed Description ..................................................................................................................................... 8•Changed figure to show STAT connection .......................................................................................................................... 15•Changed description of STAT interconnection .................................................................................................................... 21
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS2410 TPS2411
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2410PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2410PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2410PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2410PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2411PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2411PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2411PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2411PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jul-2011
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2410PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS2411PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2410PWR TSSOP PW 14 2000 367.0 367.0 35.0
TPS2411PWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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