MF633-04 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C62N33 Technical Manual S1C62N33 Technical Hardware/S1C62N33 Technical Software NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001 All rights reserved. PREFACE This part explains the function of the S1C62N33, the circuit configurations, and details the controlling method. II. S1C62N33 Technical Software This part explains the programming method of the S1C62N33. Software I. S1C62N33 Technical Hardware Hardware This manual is individualy described about the hardware and the software of the S1C62N33. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development tools C 60R08 S5U1 D1 1 00 Packing specification Version (1: Version 1 2) Tool type (D1: Development Tool 1) Corresponding model number (60R08: for S1C60R08) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products) 1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) 2: Actual versions are not written in the manuals. Comparison table between new and previous number S1C60 Family processors Previous No. E0C6001 E0C6002 E0C6003 E0C6004 E0C6005 E0C6006 E0C6007 E0C6008 E0C6009 E0C6011 E0C6013 E0C6014 E0C60R08 New No. S1C60N01 S1C60N02 S1C60N03 S1C60N04 S1C60N05 S1C60N06 S1C60N07 S1C60N08 S1C60N09 S1C60N11 S1C60N13 S1C60140 S1C60R08 S1C62 Family processors Previous No. E0C621A E0C6215 E0C621C E0C6S27 E0C6S37 E0C623A E0C623E E0C6S32 E0C6233 E0C6235 E0C623B E0C6244 E0C624A E0C6S46 New No. S1C621A0 S1C62150 S1C621C0 S1C6S2N7 S1C6S3N7 S1C6N3A0 S1C6N3E0 S1C6S3N2 S1C62N33 S1C62N35 S1C6N3B0 S1C62440 S1C624A0 S1C6S460 Previous No. E0C6247 E0C6248 E0C6S48 E0C624C E0C6251 E0C6256 E0C6292 E0C6262 E0C6266 E0C6274 E0C6281 E0C6282 E0C62M2 E0C62T3 New No. S1C62470 S1C62480 S1C6S480 S1C624C0 S1C62N51 S1C62560 S1C62920 S1C62N62 S1C62660 S1C62740 S1C62N81 S1C62N82 S1C62M20 S1C62T30 Comparison table between new and previous number of development tools Development tools for the S1C60/62 Family Previous No. ASM62 DEV6001 DEV6002 DEV6003 DEV6004 DEV6005 DEV6006 DEV6007 DEV6008 DEV6009 DEV6011 DEV60R08 DEV621A DEV621C DEV623B DEV6244 DEV624A DEV624C DEV6248 DEV6247 New No. S5U1C62000A S5U1C60N01D S5U1C60N02D S5U1C60N03D S5U1C60N04D S5U1C60N05D S5U1C60N06D S5U1C60N07D S5U1C60N08D S5U1C60N09D S5U1C60N11D S5U1C60R08D S5U1C621A0D S5U1C621C0D S5U1C623B0D S5U1C62440D S5U1C624A0D S5U1C624C0D S5U1C62480D S5U1C62470D Previous No. DEV6262 DEV6266 DEV6274 DEV6292 DEV62M2 DEV6233 DEV6235 DEV6251 DEV6256 DEV6281 DEV6282 DEV6S27 DEV6S32 DEV6S37 EVA6008 EVA6011 EVA621AR EVA621C EVA6237 EVA623A New No. S5U1C62620D S5U1C62660D S5U1C62740D S5U1C62920D S5U1C62M20D S5U1C62N33D S5U1C62N35D S5U1C62N51D S5U1C62560D S5U1C62N81D S5U1C62N82D S5U1C6S2N7D S5U1C6S3N2D S5U1C6S3N7D S5U1C60N08E S5U1C60N11E S5U1C621A0E2 S5U1C621C0E S5U1C62N37E S5U1C623A0E Previous No. EVA623B EVA623E EVA6247 EVA6248 EVA6251R EVA6256 EVA6262 EVA6266 EVA6274 EVA6281 EVA6282 EVA62M1 EVA62T3 EVA6S27 EVA6S32R ICE62R KIT6003 KIT6004 KIT6007 New No. S5U1C623B0E S5U1C623E0E S5U1C62470E S5U1C62480E S5U1C62N51E1 S5U1C62N56E S5U1C62620E S5U1C62660E S5U1C62740E S5U1C62N81E S5U1C62N82E S5U1C62M10E S5U1C62T30E S5U1C6S2N7E S5U1C6S3N2E2 S5U1C62000H S5U1C60N03K S5U1C60N04K S5U1C60N07K Hardware I. S1C62N33 Technical Hardware CONTENTS CONTENTS CHAPTER 2 OVERVIEW ........................................................................ I-1 1.1 Configuration .................................................................... I-1 1.2 Features ........................................................................... I-2 1.3 Block Diagram .................................................................. I-3 1.4 Pin Layout Diagram .......................................................... I-4 1.5 Pin Description ................................................................. I-5 POWER SUPPLY AND INITIAL RESET ................................. I-6 2.1 Power Supply ................................................................... I-6 2.2 Initial Reset ....................................................................... I-7 Oscillation detection circuit ....................................... I-8 Reset terminal (RESET) ............................................. I-8 Simultaneous high input to input ports (K00-K03) .... I-8 Watchdog timer ......................................................... I-9 Internal register at initial setting .............................. I-10 2.3 CHAPTER 3 Test Terminal (TEST) ...................................................... I-10 CPU, ROM, RAM ............................................................. I-11 3.1 CPU ................................................................................. I-11 3.2 ROM ................................................................................ I-11 3.3 RAM ................................................................................ I-12 S1C62N33 TECHNICAL HARDWARE EPSON I-i Hardware CHAPTER 1 CONTENTS CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ....................... I-13 4.1 Memory Map ................................................................... I-13 4.2 Resetting Watchdog Timer .............................................. I-19 Configuration of watchdog timer ............................... Mask option ............................................................. Control of watchdog timer ........................................ Programming note .................................................... 4.3 Oscillation Circuit ............................................................. I-21 OSC1 oscillation circuit ............................................ OSC3 oscillation circuit ............................................ Configuration of oscillation circuit ............................ Control of oscillation circuit ..................................... Programming notes .................................................. 4.4 I-26 I-27 I-29 I-30 I-32 Output Ports (R00-R03, R10-R13) ................................ I-34 Configuration of output ports ................................... Mask option ............................................................. Control of output ports ............................................. Programming note .................................................... 4.6 I-21 I-21 I-23 I-24 I-25 Input Ports (K00-K03, K10) ............................................ I-26 Configuration of input ports ..................................... Differential registers and interrupt function.............. Mask option ............................................................. Control of input ports ............................................... Programming notes .................................................. 4.5 I-19 I-19 I-20 I-20 I-34 I-35 I-38 I-40 I/O Ports (P00-P03, P10-P13) ....................................... I-41 Configuration of I/O ports ........................................ I-41 I/O control register and I/O mode ............................ I-42 Mask option ............................................................. I-42 Control of I/O ports .................................................. I-43 Programming notes .................................................. I-45 I-ii EPSON S1C62N33 TECHNICAL HARDWARE CONTENTS LCD Driver (COM0-COM3, SEG0-SEG39) ................... I-46 Configuration of LCD driver ...................................... Switching between dynamic and static drive ............. Mask option (segment allocation) .............................. Control of LCD driver ............................................... Programming notes .................................................. 4.8 Clock Timer ..................................................................... I-54 Configuration of clock timer ..................................... Interrupt function .................................................... Control of clock timer ............................................... Programming notes .................................................. 4.9 I-46 I-49 I-50 I-52 I-53 I-54 I-55 I-56 I-58 Stopwatch Counter .......................................................... I-59 Configuration of stopwatch counter .......................... Count-up pattern ..................................................... Interrupt function .................................................... Control of stopwatch counter ................................... Programming notes .................................................. I-59 I-60 I-61 I-62 I-65 4.10 Event Counter ................................................................. I-66 Configuration of event counter ................................. Operation of event counter ....................................... Mask option ............................................................. Control of event counter ........................................... Programming note .................................................... I-66 I-65 I-67 I-67 I-68 4.11 Analog Comparator ......................................................... I-69 Configuration of analog comparator .......................... Operation of analog comparator ............................... Control of analog comparator ................................... Programming notes .................................................. S1C62N33 TECHNICAL HARDWARE EPSON I-69 I-69 I-70 I-70 I-iii Hardware 4.7 CONTENTS 4.12 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function .............................. I-71 Configuration of SVD circuit ..................................... Heavy load protection function (S1C62L33) .............. Detection timing of SVD circuit ................................ Control of SVD circuit .............................................. Programing notes ..................................................... I-71 I-72 I-73 I-75 I-77 4.13 Serial Interface (SIN, SOUT, SCLK, SIOF) ..................... I-78 Configuration of serial interface ................................ Master mode and slave mode of serial interface ........ Data input/output and interrupt function ................ Mask option ............................................................. Control of serial interface ......................................... Programing notes ..................................................... I-78 I-79 I-81 I-85 I-86 I-90 4.14 Interrupt and HALT .......................................................... I-91 Interrupt factors ....................................................... Specific masks and factor flags for interrupt ............. Interrupt vectors ...................................................... Control of interrupt and HALT .................................. Programming notes .................................................. CHAPTER 5 CHAPTER 6 I-iv I-93 I-94 I-95 I-96 I-99 SUMMARY OF NOTES ..................................................... I-100 5.1 Notes for Low Current Consumption .............................. I-100 5.2 Summary of Notes by Function ...................................... I-101 DIAGRAM OF BASIC EXTERNAL CONNECTIONS ............................................ I-108 EPSON S1C62N33 TECHNICAL HARDWARE CONTENTS ELECTRICAL CHARACTERISTICS .................................... I-111 7.1 Absolute Maximum Rating ............................................. I-111 7.2 Recommended Operating Conditions ............................ I-112 7.3 DC Characteristics ......................................................... I-113 7.4 Analog Circuit Characteristics and Consumed Current .................................................. I-115 7.5 CHAPTER 8 CHAPTER 9 Oscillation Characteristics .............................................. I-121 PACKAGE ...................................................................... I-125 8.1 Plastic Package .............................................................. I-125 8.2 Ceramic Package for Test Samples ............................... I-126 PAD LAYOUT .................................................................. I-127 9.1 Diagram of Pad Layout ................................................... I-127 9.2 Pad Coordinates ............................................................. I-128 S1C62N33 TECHNICAL HARDWARE EPSON I-v Hardware CHAPTER 7 CHAPTER 1: OVERVIEW CHAPTER 1 OVERVIEW The S1C62N33 Series is a single-chip microcomputer made up of the 4-bit core CPU S1C6200, ROM (3,072 words, 12 bits to a word), RAM (256 words, 4 bits to a word) LCD driver circuit, analog comparator, event counter, serial interface, watchdog timer, and two types of time base counter. Because of its low-voltage operation and low power consumption, this series is ideal for a wide range of applications, and is especially suitable for battery-driven systems. 1.1 Configuration The S1C62N33 Series is configured as follows, depending on supply voltage and oscillation circuits. S1C62N33 TECHNICAL HARDWARE Model S1C62N33 S1C62L33 S1C62A33 Supply Voltage 3.0 V 1.5 V 3.0 V Oscillation OSC1 only OSC1 only OSC1 and OSC3 Circuits (Single Clock) (Single Clock) (Twin Clock) EPSON I-1 CHAPTER 1: OVERVIEW 1.2 Features S1C62N33 S1C62L33 OSC1 oscillation circuit Crystal oscillation circuit 32,768 Hz (Typ.) OSC3 oscillation circuit No setting S1C62A33 CR or ceramic oscillation circuit (selected by mask option) 500 kHz (Typ.) Instruction sets 108 types Instruction execution time 153 s, 214 s, 366 s (CLK = 32,768 Hz) (differs depending oninstruction) 10 s, 14 s, 24 s (CLK: CPU operation frequency) (CLK = 500 kHz) ROM capacity 3,072 words, 12 bits per word RAM capacity 256 words, 4 bits per word Input ports 5 bits (pull-down resistor can be added through mask option) Output ports 8 bits (BZ, BZ, FOUT outputs are available through mask option) Input/output ports 8 bits (pull-down resistor is added during input data read-out) Serial interface 1 port (serial 8 bits, clock synchronized) LCD driver Either 40 segments x 4 or 3 common (selected through mask option) V-3V 1/4 or 1/3 duty (regulated voltage circut and booster voltage circuit built-in) Time base counter Two types (timer and stopwatch) Watchdog timer Built-in (can be disabled through mask option) Event counter One 8-bit inputs Analog comparator Inverted input x 1, noninverted input x 1 Supply voltage detection circuit (SVD) 2.4 V 1.2 V External interrupt Input port interrupt; dual system Internal interrupt Time base counter interrupt; dual system 2.4 V Serial interface interrupt; single system Supply voltage Consumed CLK = 32,768 Hz current (when halted) (Typ. value) (when executed) CLK = 32,768 Hz CLK = 500 kHz (when executed) Form when shipped I-2 3.0 V (1.8-3.5 V) 1.5 V (0.9-1.7 V) 3.0 V (2.2-3.5 V) 1.5 A 1.0 A 2.0 A 6.0 A 3.0 A 8.0 A - - 135 A 100-pin QFP (plastic) or chip EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 1: OVERVIEW ROM 3,072 words x 12 bits OSC RESET OSC4 OSC3 OSC2 OSC1 1.3 Block Diagram System Reset Control Core CPU S1C6200 RAM 256 words x 4 bits COM0~3 SEG0~39 Interrupt Generator LCD Driver Input Port TEST VDD VL1~3 CA~CC K00~03, K10 Power Controller I/O Port P00~03, P10~13 Output Port R00~03, R10~13 Comparator AMPP AMPM VS1 VSS Timer SVD Stop Watch Event Counter Serial Interface SIN SOUT SCLK SIOF Fig. 1.3 Block diagram S1C62N33 TECHNICAL HARDWARE EPSON I-3 CHAPTER 1: OVERVIEW 1.4 Pin Layout Diagram 80 QFP5-100pin 51 81 50 Index 100 31 1 30 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Fig. 1.4 Pin layout diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 N.C. N.C. TEST N.C. N.C. SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SEG38 SEG39 N.C. AMPP N.C. AMPM K10 K03 K02 K01 K00 P03 P02 P01 P00 P13 P12 P11 P10 R03 R02 N.C. R01 R00 R12 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 N.C. N.C. N.C. N.C. R11 R10 R13 V SS RESET OSC4 OSC3 V S1 OSC2 OSC1 V DD V L3 V L2 V L1 CC CB CA COM3 COM2 COM1 COM0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SIOF SCLK N.C. N.C. N.C. SOUT SIN SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 N.C.=No Connection I-4 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 1: OVERVIEW 1.5 Pin Description Table 1.5 Pin description Pin Number Input/output VDD 65 (I) Power source positive terminal VSS 58 (I) Power source negative terminal VS1 62 - Constant voltage output terminal for oscillation VL1 68 - Constant voltage output terminal for LCD (approx. -1.05 V) VL2 67 - Booster output terminal for LCD (VL1 x 2) 66 - Booster output terminal for LCD (VL1 x 3) 69-71 - Booster condenser connector terminal Pin Name VL3 CA-CC Function OSC1 64 I Crystal oscillator input terminal OSC2 63 O Crystal oscillator output terminal OSC3 61 I *1 OSC4 60 O *2 32-36 I Input terminal P00-13 37-44 I/O R00-03 45, 46, 48, 49 O Output terminal R10 56 O Output terminal (Can output BZ through mask option.) R13 57 O Output terminal (Can output BZ through mask option.) R11 55 O Output terminal R12 50 O Output terminal (Can output FOUT through mask option.) AMPP 29 I Analog comparator noninverted input terminal AMPM 31 I Analog comparator inverted input terminal SEG0-39 6-27, 83-100 O LCD segment output terminal COM0-3 O LCD common output terminal K00-10 Input/output terminal (DC output available through mask option.) 72-75 SIN 82 I Serial interface input terminal SOUT 81 O Serial interface output terminal SCLK 77 I/O SIOF 76 O Serial interface output terminal RESET 59 I Initial setting input terminal TEST 3 I Test input terminal Serial interface clock input/output terminal *1 62N33/62L33 : Not connected 62A33 : CR or ceramic oscillation input terminal (Switchable through mask option.) *2 62N33/62L33 : Not connected 62A33 : CR or ceramic oscillation output terminal (Switchable through mask option.) S1C62N33 TECHNICAL HARDWARE EPSON I-5 CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply (*1) supplied to VDD through VSS, the S1C62N33 Series generates the necessary internal voltage with the regulated voltage circuit (<VS1> for oscillators, <VL1> for LCDs) and the voltage booster circuit (<VL2, VL3> for LCDs). Figure 2.1 shows the configuration of power supply. *1 Supply voltage: 62N33/62A33 .. 3 V, 62L33 .. 1.5 V Note - External loads cannot be driven by the regulated voltage and voltage booster circuit's output voltage. - See "7 ELECTRICAL CHARACTERISTICS" for voltage values. V DD Internal circuit VS1 V L1 External power supply V L2 V L3 CA CB CC Oscillation system regulated voltage circuit V S1 Oscillation circuit LCD system regulated voltage circuit OSC1-4 V L1 V L1 LCD system voltage booster circuit V L2 V L3 LCD driver circuit COM0-3 SEG0-39 V SS Fig. 2.1 Configuration of power supply I-6 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C62N33 Series circuits, initial reset must be executed. There are four ways of doing this. (1) Initial reset by the oscillation detection circuit (2) External initial reset by the RESET terminal (3) External initial reset by simultaneous high input to terminals K00-K03 (4) Initial reset by watchdog timer Figure 2.2 shows the configuration of the initial reset circuit. OSC1 OSC1 OSC2 Oscillation circuit K00 Vss Oscillation detection circuit Watchdog timer K01 Noise rejector Initial reset Time authorize circuit K02 K03 RESET Vss Fig. 2.2 Configuration of initial reset circuit S1C62N33 TECHNICAL HARDWARE EPSON I-7 CHAPTER 2: POWER SUPPLY AND INITIAL RESET Oscillation detection The oscillation detection circuit outputs the initial reset signal at power-on until the crystal oscillation circuit (OSC1) circuit begins oscillating, or when this crystal oscillation circuit (OSC1) halts oscillating for some reason. Reset terminal (RESET) Initial reset can be executed externally by setting the reset terminal to the high level. This high level must be maintained for at least 5 ms (when oscillating frequency is fosc1 = 32 kHz), because the initial reset circuit contains a noise rejector circuit. When the reset terminal goes low the CPU begins to operate. Note When oscillation is stopped, reset input from the reset terminal triggered by the noise reject circuit cannot be received. When oscillation is stopped, initialization of internal circuits is triggered by the oscillation detection circuit. Simultaneous high input to input ports (K00-K03) Table 2.2.1 Input port combinations I-8 Another way of executing initial reset externally is to input a high signal simultaneously to the input ports (K00-K03) selected with the mask option. The specified input port terminals must be kept high for at least 5 ms (when oscillating frequency is fosc1 = 32 kHz), because the initial reset circuit contains a noise rejector circuit. Table 2.2.1 shows the combinations of input ports (K00-K03) that can be selected with the mask option. A B Not used K00*K01 C D K00*K01*K02 K00*K01*K02*K03 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 2: POWER SUPPLY AND INITIAL RESET When, for instance, mask option D (K00*K01*K02*K03) is selected, initial reset is executed when the signals input to the four ports K00-K03 are all high at the same time. Furthermore, initial reset is also applied when key input, which includes the combination of input ports selected, is performed. Further, when the input time of the simultaneous HIGH input is tested and found to be the same or more than the defined time (1-3 sec), the time test circuit that performs initial reset can be selected with the mask option. If you use this function, make sure that the specified ports do not go high at the same time during ordinary operation. Note When oscillation is stopped, the reset triggered by the noise reject circuit which would normally take place when the input ports are simultaneously switched to HIGH cannot be received. Watchdog timer S1C62N33 TECHNICAL HARDWARE If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial reset signal. See "4.2 Resetting Watchdog Timer" for details. EPSON I-9 CHAPTER 2: POWER SUPPLY AND INITIAL RESET Internal register at initial setting Initial reset initializes the CPU as shown in the table below. Table 2.2.2 Initial values CPU Core Name Program counter step Signal PCS Number of Bits Setting Value 8 00H Program counter page New page pointer PCP NPP 4 4 1H 1H Stack pointer Index register IX SP IX 8 9 Undefined Undefined Index register IY Register pointer IY RP 9 4 Undefined Undefined General-purpose register A General-purpose register B A B 4 4 Undefined Undefined Interrupt flag Decimal flag I D 1 1 0 Undefined Zero flag Carry flag Z C 1 1 Undefined Undefined Peripheral Circuits Name RAM Segment data Other peripheral circuit Number of Bits Setting Value 256 x 4 Undefined 40 x 4 - Undefined *1 *1 See "4.1 Memory Map" 2.3 Test Terminal (TEST) This terminal is used when the IC load is being detected. During ordinary operation be certain to connect this terminal to VSS. I-10 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C62N33 Series employs the core CPU S1C6200 for the CPU, so that register configuration, instructions and so forth are virtually identical to those in other family processors using the S1C6200. Refer to "S1C6200/6200A Core CPU Manual" for details about the S1C6200. Note the following points with regard to the S1C62N33 Series: (1) The SLEEP operation is not assumed, so the SLP instruction cannot be used. (2) Because the ROM capacity is 3,072 words, bank bits are unnecessary and PCB and NBP are not used. (3) Since RAM is set for up to 1 page, only the subordinate 1 bit of the page section of the index register which specifies address is effective. (The 3 superordinate bits are ignored.) 3.2 ROM The built-in ROM, a mask ROM for loading the program, has a capacity of 3,072 steps, 12 bits each. The program area is 12 pages (0-11), each of 256 steps (00H-FFH). After initial reset, the program beginning address is page 1, step 00H. The interrupt vector is allocated to page 1, steps 01H-0FH. S1C62N33 TECHNICAL HARDWARE EPSON I-11 CHAPTER 3: CPU, ROM, RAM 00H step 0 page Program start address 01H step 1 page 2 page Interrupt vector area 3 page 4 page 5 page 0FH step 6 page 10H step 7 page 8 page 9 page 10 page 11 page FFH step Fig. 3.2 12 bits ROM configuration 3.3 RAM The RAM, a data memory storing a variety of data, has a capacity of 256 words, each of four bits. When programming, keep the following points in mind. (1) Part of the data memory can be used as stack area when saving subroutine calls and registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words of the stack area. (3) The data memory 000H-00FH is for the register pointers (RP), and is the addressable memory register area. (4) The data memory is split into three areas, 000H-06FH, 080H-09FH and 100H-16FH, so take care when allocating the data. (See "4.1 Memory Map" for details.) I-12 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C62N33 Series are memory mapped, and interfaced with the CPU. Thus, all the peripheral circuits can be controlled by using the memory operation command to access the I/O data memory in the memory map. The following sections describe how the peripheral circuits operation. 4.1 Memory Map Data memory of the S1C62N33 Series has an address space of 360 words, of which 48 words are allocated to display memory and 64 words to I/O data memory. Figures 4.1.1 and 4.1.2 present the overall memory maps of the S1C62N33 Series, and Tables 4.1(a)-(c) the peripheral circuits' (I/O space) memory maps. The I/O data memory in all units of the S1C62N33 Series is configured in the same manner at 070H-07FH, 170H-17FH and 0F0H-0FFH, 1F0H-1FFH. This makes it possible to access I/O data memory without switching data memory pages. S1C62N33 TECHNICAL HARDWARE EPSON I-13 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D E F High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 3 RAM (112 words x 4 bits) R/W 4 5 6 0 7 I/O data memory Tables 4.1(a), (b) 8 RAM (32 words x 4 bits) R/W 9 A B Unused area C D E F I/O data memory Table 4.1(c) 0 1 2 3 RAM (112 words x 4 bits) R/W 4 5 6 1 7 I/O data memory Tables 4.1(a), (b) 8 9 A Unused area B C D Fig. 4.1.1 Memory map I-14 E I/O data memory Table 4.1(c) F EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Address Low 0 Fig. 4.1.2 Memory map (segment area) Page 1 2 4 or C 0 3 4 5 6 7 8 9 A B C D E F High Segment data memory (40 words x 4 bits) 40H-6FH = R/W C0H-EFH = W 5 or D 6 or E Note (1) The I/O data memory registers of 070H-07FH, 170H-17FH and 0F0H-0FFH, 1F0H-1FFH are each linked. For instance, by switching the I/O data memory at 074H, data memory at 174H can by switched simultaneously. See Tables 4.1(a)-(c) for details of I/O data memory. (2) The mask option can be used to select whether to assign the overall area of segment data memory to 040H-06FH or 0C0H- 0EFH. When 040H-06FH is selected, read/write is enabled. When 0C0H-0EFH is selected, write only is enabled. If 040H-06FH is assigned, RAM is used as the segment area (48 words). (3) Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. S1C62N33 TECHNICAL HARDWARE EPSON I-15 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1(a) I/O memory map (70H-77H) Address *7 D3 TM3 70H SWL3 71H SWH3 72H K03 73H DFK03 74H EIK03 75H HVLD 76H R/W SCTRG 77H SIOF W R *1 *2 *3 *4 I-16 Register D2 D1 D0 Name TM3 TM2 TM1 TM0 TM2 TM1 R TM0 SWL3 SWL0 SWL2 SWL1 SWL2 SWL1 R SWL0 SWH3 SWH0 SWH2 SWH1 SWH2 SWH1 R SWH0 K03 K00 K02 K01 K02 K01 R K00 DFK03 DFK00 DFK02 DFK01 DFK02 DFK01 R/W DFK00 EIK03 EIK02 EIK01 EIK00 EIK02 EIK01 R/W EIK00 HVLD SVDDT EISWIT1 EISWIT0 SVDDT SVDON SVDON R EISWIT1 R/W W EISWIT0 SCTRG DFK10 EIK10 K10 SIOF EIK10 DFK10 R R/W K10 Init *1 0 0 0 0 0 0 0 0 0 0 0 0 *2 *2 *2 *2 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 *2 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON 1 Comment 0 Timer data (clock timer 2 Hz) Timer data (clock timer 4 Hz) Timer data (clock timer 8 Hz) Timer data (clock timer 16 Hz) MSB Stopwatch counter 1/100 sec (BCD) LSB MSB Stopwatch counter 1/10 sec (BCD) LSB High High High High Falling Falling Falling Falling Enable Enable Enable Enable Low Low Low Low Rising Rising Rising Rising Mask Mask Mask Mask Heavy load Normal Low voltage Normal On Off Enable Mask Enable Mask Trigger - Run Stop Enable Mask Falling Rising High Low Input port (K00-K03) Differential register (K00-K03) Interrupt mask register (K00-K03) Heavy load protection mode register SVD evaluation data (at read-out) SVD ON/OFF (at writing) Interrupt mask register (stopwatch 1 Hz) Interrupt mask register (stopwatch 10 Hz) Serial interface clock trigger SIOF Interrupt mask register (K10) Differential register (K10) Input port (K10) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1(b) I/O memory map (78H-7FH) Address *7 D3 CSDC Register D2 D1 D0 ETI8 ETI32 TI8 TI32 SWIT1 SWIT0 R01 R00 R11 R10 P01 P00 ETI2 78H R/W - TI2 79H R IK1 IK0 7AH R R03 R02 7BH R/W R13 R12 7CH R/W P03 P02 7DH R/W TMRST SWRUN SWRST IOC0 W R/W W R/W WDRST WD2 WD1 WD0 7EH 7FH W S1C62N33 TECHNICAL HARDWARE R Name CSDC ETI2 ETI8 ETI32 - TI2 TI8 TI32 IK1 IK0 SWIT1 SWIT0 R03 R02 R01 R00 R13 R12 R11 R10 P03 P02 P01 P00 TMRST SWRUN SWRST IOC0 WDRST WD2 WD1 WD0 Init *1 0 0 0 0 *2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *2 *2 *2 *2 Reset 0 Reset 0 Reset 0 0 0 EPSON 1 Static Enable Enable Enable 0 Dynamic Mask Mask Mask Yes Yes Yes Yes Yes Yes Yes High High High High High High High High High High High High Reset Run Reset Output Reset No No No No No No No Low Low Low Low Low Low Low Low Low Low Low Low - Stop - Input - Comment LCD drive switch Interrupt mask register (clock timer 2 Hz) Interrupt mask register (clock timer 8 Hz) Interrupt mask register (clock timer 32 Hz) Unused *5 Interrupt factor flag (clock timer 2 Hz) *4 Interrupt factor flag (clock timer 8 Hz) *4 Interrupt factor flag (clock timer 32 Hz) *4 Interrupt factor flag (K10) *4 Interrupt factor flag (K00-K03) *4 Interrupt factor flag (stopwatch 1 Hz) *4 Interrupt factor flag (stopwatch 10 Hz) *4 Output port (R00-R03) Output port (R13, BZ) *6 Output port (R12, FOUT) *6 Output port (R11) Output port (R10, BZ) *6 I/O port (P00-P03) Output latch reset at time of initial reset Clock timer reset *5 Stopwatch counter RUN/STOP Stopwatch counter reset *5 I/O control register 0 (P00-P03) Watchdog timer reset *5 Timer data (watchdog timer 1/4 Hz) Timer data (watchdog timer 1/2 Hz) Timer data (watchdog timer 1 Hz) I-17 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1(c) I/O memory map (F0H-F3H, F6H-F9H, FCH-FEH) D3 Register D2 D1 SD3 SD2 Address *7 SD1 F0H R/W SD7 SD6 SD5 F1H R/W SCS1 SCS0 SE2 F2H R/W - - - F3H R BZFQ - - F6H R/W - R - AMPDT F7H R EV03 EV02 EV01 F8H R EV07 EV06 EV05 F9H R - EVRUN - R R/W R P13 P12 P11 FCH FDH R/W - CLKCHG OSCC FEH R I-18 R/W D0 Name SD3 SD0 SD2 SD1 SD0 SD7 SD4 SD6 SD5 SD4 SCS1 EISIO SCS0 SE2 EISIO - ISIO - - ISIO BZFQ - - - - - AMPON - AMPDT R/W AMPON EV03 EV00 EV02 EV01 EV00 EV07 EV04 EV06 EV05 EV04 - EVRST EVRUN - W EVRST P13 P10 P12 P11 P10 - IOC1 CLKCHG OSCC IOC1 Init *1 1 *3 *3 *3 *3 *3 *3 *3 *3 *6 1 *6 1 Rising 0 Enable 0 *2 *2 *2 Yes 0 2 kHz 0 *2 *2 *2 *2 *2 +>1 On 0 0 0 0 0 0 0 0 0 *2 Run 0 *2 Reset Reset High *2 High *2 High *2 High *2 *2 OSC3 0 On 0 Output 0 EPSON 0 Comment Serial interface data register Low order (SD0-SD3) Serial interface data register High order (SD4-SD7) *6 *6 Falling Mask No 4 kHz ->+ Off Clock edge selection register (SCS0, SCS1) Clock edge selection register Interrupt mask register (serial interface) Unused *5 Unused *5 Unused *5 Interrupt factor flag (serial interface) *4 Buzzer frequency selection register Unused *5 Unused *5 Unused *5 Unused *5 Unused *5 Analog comparator data Analog comparator ON/OFF Event counter Low order (EV00-EV03) Event counter High order (EV04-EV07) Stop - Low Low Low Low OSC1 Off Input Unused *5 Event counter RUN/STOP Unused *5 Event counter reset *5 I/O port (P10-P13) Output latch reset at time of initial reset Unused *5 CPU clock switch OSC3 oscillator ON/OFF I/O control register 1 (P10-P13) S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer) 4.2 Resetting Watchdog Timer Configuration of watchdog timer Fig. 4.2 Watchdog timer block diagram The S1C62N33 Series incorporates a watchdog timer as the source oscillator for OSC1 (clock timer 2 Hz signal). The watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3 or 4 seconds, the initial reset signal is output automatically for the CPU. Figure 4.2 is the block diagram of the watchdog timer. OSC1 demultiplier (256 Hz) Clock timer TM0-TM3 2 Hz Watchdog timer WD0-WD2 Initial reset signal Watchdog timer reset signal The watchdog timer, configured of a three-bit binary counter (WD0-WD2), generates the initial reset signal internally by overflow of the MSB. Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. The watchdog timer operates in the halt mode. If the halt status continues for 3 or 4 seconds, the initial reset signal restarts operation. Mask option S1C62N33 TECHNICAL HARDWARE You can select whether or not to use the watchdog timer with the mask option. When "Not use" is chosen, there is no need to reset the watchdog timer. EPSON I-19 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer) Table 4.2 lists the watchdog timer's control bits and their addresses. Control of watchdog timer Table 4.2 Control bits of watchdog timer Address *7 D3 WDRST Register D2 D1 WD2 W WD1 R Comment D0 Name SR *1 WD0 WDRST Reset WD2 0 Timer data (watchdog timer 1/4 Hz) WD1 0 Timer data (watchdog timer 1/2 Hz) WD0 0 Timer data (watchdog timer 1 Hz) 1 0 Reset - Watchdog timer reset *5 7FH *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary WDRST: This is the bit for resetting the watchdog timer. Watchdog timer reset When "1" is written: Watchdog timer is reset (7FH*D3) When "0" is written: No operation Read-out: Always "0" When "1" is written to WDRST, the watchdog timer is reset, and the operation restarts immediately after this. When "0" is written to WDRST, no operation results. This bit is dedicated for writing, and is always "0" for readout. Programming note I-20 When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data (WD0-WD2) cannot be used for timer applications. EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3 Oscillation Circuit OSC1 oscillation circuit The S1C62N33 Series has a built-in crystal oscillation circuit. As an external element, the OSC1 oscillation circuit generates the operating clock for the CPU and peripheral circuitry by connecting the crystal oscillator (Typ. 32.768 kHz) and trimmer capacitor (5-25 pF). Figure 4.3.1 is the block diagram of the OSC1 oscillation circuit. V DD CGX OSC2 Fig. 4.3.1 OSC1 oscillation circuit RDX To CPU and peripheral circuits RFX X'tal OSC1 V DD C DX S1C62N33 Series As Figure 4.3.1 indicates, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) between terminals OSC1 and OSC2 to the trimmer capacitor (CGX) between terminals OSC1 and VDD. OSC3 oscillation circuit S1C62N33 TECHNICAL HARDWARE In the S1C62N33 Series, the S1C62A33 has twin clock specification. The mask option enables selection of either the CR or ceramic oscillation circuit (OSC3 oscillation circuit) as the CPU's subclock. Because the oscillation circuit itself is built-in, it provides the resistance as an external element when CR oscillation is selected, but when ceramic oscillation is selected both the ceramic oscillator and two capacitors (gate and drain capacitance) are required. Figure 4.3.2 is the block diagram of the OSC3 oscillation circuit. EPSON I-21 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) C CR OSC3 RCR To CPU (SIO) Oscillation circuit control signal OSC4 S1C62A33 VDD C GC Fig. 4.3.2 OSC3 oscillation circuit To CPU (SIO) RFC Ceramic CDC OSC3 OSC4 RDC Oscillation circuit control signal S1C62A33 As indicated in Figure 4.3.2, the CR oscillation circuit can be configured simply by connecting the resistor (RCR) between terminals OSC3 and OSC4 when CR oscillation is selected. When 82 k is used for RCR, the oscillation frequency is about 430 kHz. When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (Typ. 500 kHz) between terminals OSC3 and OSC4 to the two capacitors (CGC and CDC) located between terminals OSC3 and OSC4 and VDD. For both CGC and CDC, connect capacitors that are about 100 pF. To lower current consumption of the OSC3 oscillation circuit, oscillation can be stopped through the software. For the S1C62N33 and 62L33 (single clock specification), do not connect anything to terminals OSC3 and OSC4. I-22 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) Configuration of oscillation circuit The S1C62N33 and 62L33 have one oscillation circuit (OSC1), and the S1C62A33 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock the CPU and peripheral circuits. OSC3 is either a CR or ceramic oscillation circuit. When processing with the S1C62A33 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3. Figure 4.3.3 is the block diagram of this oscillation system. OSC1 oscillation circuit To peripheral circuit Clock switch OSC3 oscillation circuit CPU clock selection signal Fig. 4.3.3 Oscillation system To CPU (SIO) Oscillation circuit control signal For S1C62A33, selection of either OSC1 or OSC3 for the CPU's operating clock can be made through the software. S1C62N33 TECHNICAL HARDWARE EPSON I-23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) Control of oscillation Table 4.3 lists the control bits and their addresses for the oscillation circuit. circuit Table 4.3 Control bits of oscillation circuit and prescaler Address *7 D3 - R Register D2 D1 CLKCHG OSCC R/W SR *1 1 Comment 0 D0 Name IOC1 - *2 CLKCHG 0 OSC3 OSC1 CPU clock switch OSCC 0 ON OFF OSC3 oscillator ON/OFF IOC1 0 Output Input I/O control register 1 (P10-P13) Unused *5 FEH *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary OSCC: Controls oscillation ON/OFF for the OSC3 oscillation circuit. OSC3 oscillation control (S1C62A33 only.) (FEH*D1) When "1" is written: The OSC3 oscillation ON When "0" is written: The OSC3 oscillation OFF Read-out: Valid When it is necessary to operate the CPU of the S1C62A33 at high speed, set OSCC to "1". At other times, set it to "0" to lessen the current consumption. For the S1C62N33 and 62L33, keep OSCC set to "0". At initial reset, OSCC is set to "0". I-24 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) CLKCHG: The CPU's operation clock is selected with this register. The CPU's clock switch (S1C62A33 only.) (FEH*D2) When "1" is written: OSC3 clock is selected When "0" is written: OSC1 clock is selected Read-out: Valid When the S1C62N33's CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0". This register cannot be controlled for the S1C62N33 and 62L33, so that OSC1 is selected no matter what the set value. At initial reset, CLKCHG is set to "0". Programming notes (1) It takes at least 5 ms from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 ms have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction. S1C62N33 TECHNICAL HARDWARE EPSON I-25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4 Input Ports (K00-K03, K10) Configuration of input ports The S1C62N33 Series has five bits general-purpose input ports. Each of the input port terminals (K00-K03, K10) provides internal pull-down resistor. Pull-down resistor can be selected for each bit with the mask option. Figure 4.4.1 shows the configuration of input port. Interrupt request K Fig. 4.4.1 Data bus V DD Address Vss Configuration of input port Mask option Selection of "pull-down resistance enabled" with the mask option suits input from the push switch, key matrix, and so forth. When "pull-down resistance disabled" is selected, the port can be used for slide switch input and interfacing with other LSIs. Further, the input port terminal K10 is used as the input terminals for the event counter. (See "4.10 Event Counter" for details.) I-26 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) All five bits of the input ports (K00-K03, K10) provide the interrupt function. The conditions for issuing an interrupt can be set by the software. Further, whether to mask the interrupt function can be selected individually for all five bits by the software. Figure 4.4.2 shows the configuration of K00-K03 and K10. Differential registers and interrupt function K One for each terminal series Data bus Address Differential register (DFK) Noise rejector Address Interrupt factor flag (IK) Interrupt request Address Mask option (K00-K03, K10) Interrupt mask register (EIK) Fig. 4.4.2 Address Input interrupt circuit configuration (K00-K03, K10) The input interrupt timing for K00-K03 and K10 depends on the value set for the differential registers (DFK00-DFK03 and DFK10). Interrupt can be selected to occur at the rising or falling edge of the input. The interrupt mask registers (EIK00-EIK03, EIK10) enables the interrupt mask to be selected individually for K00-K03 and K10. However, whereas the interrupt function is enabled inside K00-K03, the interrupt occurs when the contents change from matching those of the differential register to non-matching contents. Interrupt for K10 can be generated by setting the same conditions individually. When the interrupt is generated, the interrupt factor flag (IK0 and IK1) is set to "1". Figure 4.4.3 shows an example of an interrupt for K00-K03. Note Writing to the interrupt mask registers (EIK00-EIK03, EIK10) can be done only in the DI status (interrupt flag = "0"). S1C62N33 TECHNICAL HARDWARE EPSON I-27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Interrupt mask register EIK03 EIK02 EIK01 EIK00 1 1 1 0 Differential register DFK03 DFK02 DFK01 DFK00 1 0 1 0 With the above setting, the interrupt for K00-K03 occurs in the following conditions. Input port (1) K03 1 K02 0 K01 1 K00 0 K01 1 K00 1 K01 1 K00 1 Interrupt generated (Initial value) (2) K03 1 K02 0 (3) K03 0 K02 0 K00 is masked, so the three bits Fig. 4.4.3 Example of interrupt of (4) K03 0 K02 1 of K01-K03 cease matching K01 1 K00 1 those of the differential register DFK01-DFK03, and an interrupt occurs. K00-K03 K00 is masked by the interrupt mask register (EIK00), so that an interrupt does not occur at (2). At (3), K03 changes to "0"; the data of the terminal that is interrupt enabled no longer matches the data of the differential register, so that interrupt occurs. As already explained, the condition for the interrupt to occur is the change in the port data and contents of the differential register from matching to nonmatching. Hence, in (4), when the nonmatching status changes to another nonmatching status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect the conditions for interrupt generation. I-28 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Mask option The contents that can be selected with the input port mask option are as follows: (1) Internal pull-down resistor can be selected for each of the five bits of the input ports (K00-K03, K10). When you have selected "pull-down resistor disabled", take care that the floating status does not occur for the input. Select "pull-down resistor enabled" for input ports that are not being used. (2) The input interrupt circuit contains a noise rejector for preventing interrupt occurring through noise. The mask option enables selection of whether to use the noise rejector for each separate terminal series. When "Use" is selected, a maximum delay of 1 ms occurs from the time interrupt condition is established until the interrupt factor flag (IK) is set to "1". S1C62N33 TECHNICAL HARDWARE EPSON I-29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Control of input ports Table 4.4 list the input ports control bits and their addresses. Table 4.4 Input port control bits Address *7 D3 Register D2 D1 D0 Name K03 K02 K00 K03 K01 SR *1 0 *2 High Low K02 *2 High Low K01 *2 High Low K00 *2 High Low DFK03 0 Falling Rising DFK02 0 Falling Rising DFK01 0 Falling Rising DFK00 0 Falling Rising EIK03 0 Enable Mask EIK02 0 Enable Mask EIK01 0 Enable Mask EIK00 0 Enable Mask K10 SCTRG SIOF - 0 Trigger Run - Stop Serial interface clock trigger SIOF R EIK10 0 Enable Mask Interrupt mask register (K10) DFK10 0 Falling Rising Differential register (K10) K10 *2 High Low Input port (K10) IK1 0 Yes No Interrupt factor flag (K10) *4 IK0 0 Yes No Interrupt factor flag (K00-K03) *4 SWIT1 0 Yes No Interrupt factor flag (stopwatch 1 Hz) *4 SWIT0 0 Yes No Interrupt factor flag (stopwatch 10 Hz) *4 R 73H DFK03 DFK02 DFK01 DFK00 R/W 74H EIK03 EIK02 EIK01 EIK00 R/W 75H SCTRG SIOF 77H EIK10 W R IK1 DFK10 R/W IK0 SWIT1 R Comment 1 SWIT0 Input port (K00-K03) Differential register (K00-K03) Interrupt mask register (K00-K03) 7AH *1 *2 *3 *4 I-30 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) K00-K03, K10: Input data of the input port terminals can be read out with Input port data these registers. (73H, 77H*D0) When "1" is read out: High level When "0" is read out: Low level Writing: Invalid The read-out is "1" when the terminal voltage of the five bits of the input ports (K00-K03, K10) goes high (VDD), and "0" when the voltage goes low (VSS). These bits are dedicated for read-out, so writing cannot be done. DFK00-DFK03, DFK10: Interrupt conditions can Differential registers When read out is "1": (74H, 77H*D1) When read out is "0": Read-out: be set with these registers. Falling edge Rising edge Valid The interrupt conditions can be set for the rising or falling edge of input for each of the five bits (K00-K03 and K10), through the differential registers (DFK00-DFK03 and DFK10). At initial reset, these registers are set to "0". EIK00-EIK03, EIK10: Masking the interrupt of the input port terminals can be Interrupt mask registers selected with these registers. (75H, 77H*D2) When "1" is written: Enable When "0" is written: Mask Read-out: Valid With these registers, masking of the input port bits can be selected for each of the five bits. Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). At initial reset, these registers are all set to "0". IK0, IK1: These flags indicate the occurrence of input interrupt. Interrupt factor flags When "1" is read out: Interrupt has occurred (7AH*D2 and D3) When "0" is read out: Interrupt has not occurred Writing: Invalid The interrupt factor flags IK0 and IK1 are associated with K00-K03 and K10, respectively. S1C62N33 TECHNICAL HARDWARE EPSON I-31 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) From the status of these flags, the software can decide whether an input interrupt has occurred. These flags are reset when the software reads them. Readout can be done only in the DI status (interrupt flag = "0"). At initial reset, these flags are set to "0". Programming notes (1) When input ports are changed from high to low by pulldown resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time of about 1 ms. (2) When "noise rejector circuit enable" is selected with the mask option, a maximum delay of 1 ms occurs from time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. For example, when performing a key scan with the key matrix, the key scan changes the input status to set the interrupt factor flag, so it has to be read out to reset it. However, if the interrupt factor flag is read out immediately after key scanning, the delay will cause the flag to be set after read-out, so that it will not be reset. (3) Input interrupt programing related precautions Port K input Active status Active status Differential register Falling edge interrupt Rising edge interrupt Mask register Fig. 4.4.4 Input interrupt timing I-32 Factor flag set Not set Factor flag set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flags are set at and , being the interrupt due to the falling edge and the interrupt due to the rising edge. EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status, the factor flag for input interrupt may be set. Therefore, when using the input interrupt, the active status of the input terminal implies input terminal = low status, when the falling edge interrupt is effected and input terminal = high status, when the rising edge interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of shown in Figure 4.4.4. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the timing of shown in Figure 4.4.4. In this case, when the mask registers cleared, then set, you should set the mask register, when the input terminal is in the low status. In addition, when the mask register = "1" and the content of the differential register is rewritten in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite the content of the differential register in the mask register = "0" status. (4) Read-out the interrupt factor flag (IK) only in the DI status (interrupt flag = "0"). Read-out during EI status will cause malfunction. (5) Writing to the interrupt mask registers (EIK) can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause malfunction. S1C62N33 TECHNICAL HARDWARE EPSON I-33 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5 Output Ports (R00-R03, R10-R13) Configuration of output ports The S1C62N33 Series has general output ports (4 bits x 2). Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output. Further, the mask option enables the output ports R10, R12, and R13 to be used as special output ports. Figure 4.5.1 shows the configuration of the output ports. Data bus VDD Register R Address VSS Fig. 4.5.1 Configuration of output ports I-34 Mask option EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) Mask option The mask option enables the following output port selection. (1) Output specifications of output ports Output specifications for the output ports (R00-R03, R10-R13) enable selection of either complementary output or Pch open drain output for each of the eight bits. However, even when Pch open drain output is selected, voltage exceeding source voltage must not be applied to the output port. (2) Special output In addition to the regular DC output, special output can be selected for the output ports R10, R12, and R13 as shown in Table 4.5.1. Figure 4.5.2 shows the structure of the output ports R10-R13. Table 4.5.1 Special output S1C62N33 TECHNICAL HARDWARE Pin Name When Special Output Selected R10 BZ R13 BZ (Only when R10 = BZ output is selected) R12 FOUT EPSON I-35 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) Data bus BZ Register (R10) R10 Register (R13) R13 (Without SW) Register (R11) R11 FOUT R12 Register (R12) Address (7CH) Mask option Fig. 4.5.2 Structure of output port R10-R13 I-36 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) BZ, BZ BZ and BZ are the buzzer signal output for driving the (R10, R13) piezoelectric buzzer. The buzzer signal frequency of 2 kHz or 4 kHz can be selected by software. Note When the BZ and BZ output signals are turned ON or OFF, a hazard can result. When DC output is set for the output port R10, the output port R13 cannot be set for BZ output. Figure 4.5.3 shows the output waveform for BZ and BZ. 0 1 0 Register "H" Fig. 4.5.3 Output waveform of BZ and BZ BZ output (R10 terminal) "L" BZ output (R13 terminal) "L" "H" FOUT When the output port R12 is set for FOUT output, it outputs (R12) the clock of fosc1 or the demultiplied fosc1. The clock frequency is selectable with the mask options, from the frequencies listed in Table 4.5.2. Table 4.5.2 FOUT clock frequency Setting Value Clock Frequency (Hz) fosc1 = 32,768 fosc1 / fosc1 / 1 2 32,768 16,384 fosc1 / fosc1 / 4 8 8,192 4,096 fosc1 / 16 fosc1 / 32 2,048 1,024 fosc1 / 64 fosc1 /128 512 256 Note A hazard may occur when the FOUT signal is turned ON or OFF. S1C62N33 TECHNICAL HARDWARE EPSON I-37 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) Table 4.5.3 lists the output ports' control bits and their addresses. Control of output ports Table 4.5.3 Control bits of output ports Address *7 D3 Register D2 D1 D0 Name R03 R02 R00 R03 R01 R/W SR *1 Comment 1 0 0 High Low R02 0 High Low R01 0 High Low R00 0 High Low R13 0 High Low Output port (R13, BZ) *6 R12 0 High Low Output port (R12, FOUT) *6 R11 0 High Low Output port (R11) R10 0 High Low Output port (R10, BZ) *6 BZFQ 0 2 kHz 4 kHz Buzzer frequency selection register - *2 Unused *5 - *2 Unused *5 - *2 Unused *5 7BH Output port (R00-R03) R13 R12 R11 R10 R/W 7CH BZFQ R/W - - R - F6H *1 *2 *3 *4 I-38 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00-R03, R10-R13 Sets the output data for the output ports. (when DC output): When "1" is written: High output Output port data When "0" is written: Low output (7BH, 7CH) Read-out: Valid The output port terminals output the data written in the corresponding registers (R00-R03, R10-R13) without changing it. When "1" is written in the register, the output port terminal goes high (VDD), and when "0" is written, the output port terminal goes low (VSS). At initial reset, all registers are set to "0". R10, R13 (when BZ and These bits control the output of the buzzer signals (BZ, BZ). BZ output is selected): When "1" is written: Buzzer signal is output Special output port data When "0" is written: Low level (DC) is output (7CH*D0 and D3) Read-out: Valid BZ is output from terminal R13. With the mask option, selection can be made perform this output control by R13, or to perform output control simultaneously with BZ by R10. * When R13 controls BZ output BZ output and BZ output can be controlled independently. BZ output is controlled by writing data to R10, and BZ output is controlled by writing data to R13. * When R10 controls BZ output BZ output and BZ output can be controlled simultaneously by writing data to R10 only. For this case, R13 can be used as a one-bit general register having both read and write functions, and data of this register exerts no affect on BZ output (output from the R13 pin). At initial reset, registers R10 and R13 are set to "0". S1C62N33 TECHNICAL HARDWARE EPSON I-39 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) BZFQ: Selects the frequency of the buzzer signal. Buzzer frequency When "1" is written: 2 kHz selection register When "0" is written: 4 kHz (F6H*D3) Read-out: Valid When "1" is written to register BZFQ, the frequency of the buzzer signal is set in 2 kHz, and in 4 kHz when "0" is written. At initial reset, BZFQ is set to "0" (4 kHz). R12 Controls the FOUT (clock) output. (when FOUT is selected): When "1" is written: Clock output Special output port data When "0" is written: Low level (DC) output (7CH*D2) Read-out: Valid FOUT output can be controlled by writing data to R12. At initial reset, this register is set to "0". Programming note I-40 When BZ, BZ and FOUT are selected with the mask option, a hazard may be observed in the output waveform when the data of the output register changes. EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6 I/O Ports (P00-P03, P10-P13) The S1C62N33 Series has general-purpose I/O ports (4 bits x 2). Figure 4.6 shows the configuration of the I/O ports. The four bits of each of the I/O ports P00-P03 and P10-P13 can be set to either input mode or output mode. Modes can be set by writing data to the I/O control register. Data bus Configuration of I/O ports Input control P Register Address Fig. 4.6 Configuration of I/O ports S1C62N33 TECHNICAL HARDWARE Address I/O control register EPSON V ss I-41 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) I/O control register and I/O mode Input or output mode can be set for the four bits of I/O port P00-P03 and I/O port P10-P13 by writing data into the corresponding I/O control register IOC0 and IOC1. To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port. However, the input line is pulled down when input data is read. The output mode is set when "1" is written to the I/O control register. When an I/O port set to output mode works as an output port, it outputs a high signal (VDD) when the port output data is "1", and a low signal (VSS) when the port output data is "0". At initial reset, the I/O control registers are set to "0", and the I/O port enters the input mode. Mask option The output specification during output mode (IOC = "1") of these I/O ports can be set with the mask option for either complementary output or Pch open drain output. This setting can be performed for each bit of each port. However, when Pch open drain output has been selected, voltage in excess of the power voltage must not be applied to the port. I-42 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) Table 4.6 lists the I/O ports' control bits and their addresses. Control of I/O ports Table 4.6 I/O port control bits Address *7 D3 Register D2 D1 D0 Name P03 P02 P00 P03 P01 R/W SR *1 1 0 *2 High Low P02 *2 High Low P01 *2 High Low P00 *2 High Low 7DH Comment I/O port (P00-P03) Output latch reset at time of initial reset TMRST SWRUN SWRST IOC0 TMRST Reset Reset - W R/W W R/W SWRUN 0 RUN STOP SWRST Reset Reset - IOC0 0 Output Input P13 *2 High Low P12 *2 High Low P11 *2 High Low P10 *2 High Low - *2 CLKCHG 0 OSC3 OSC1 CPU clock switch OSCC 0 ON OFF OSC3 oscillator ON/OFF IOC1 0 Output Input I/O control register 1 (P10-P13) Clock timer reset *5 Stopwatch counter RUN/STOP 7EH P13 P12 P11 P10 R/W FDH - CLKCHG R OSCC R/W IOC1 Stopwatch counter reset *5 I/O control register 0 (P00-P03) I/O port (P10-P13) Output latch reset at time of initial reset Unused *5 FEH *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read S1C62N33 TECHNICAL HARDWARE EPSON *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary I-43 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) P00-P03, P10-P13: I/O port data can be read and output data can be set I/O port data through these ports. (7DH, FDH) * When writing data When "1" is written: When "0" is written: High level Low level When an I/O port is set to the output mode, the written data is output unchanged from the I/O port terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written, the level goes low (VSS). Port data can be written also in the input mode. * When reading data out When "1" is read out: High level When "0" is read out: Low level The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage level being input to the port terminal can be read out; in the output mode the output voltage level can be read. When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal voltage is low (VSS) the data is "0". Further, the built-in pull-down resistance goes ON during read-out, so that the I/O port terminal is pulled down. Internal pull down resistors are only ON during readout and gate floating by means of an input control signal cannot occur even at times other than readout. Note - When the I/O port is set to the output mode and a low-impedance load is connected to the port terminal, the data written to the register may differ from the data read out. - When the I/O port is set to the input mode and a low-level voltage (VSS) is input, erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-down resistance load is greater than the read-out time. I-44 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) When the input data is being read out, the time that the input line is pulled down is equivalent to 1.5 cycles of the CPU system clock. However, the electric potential of the terminals must be settled within 0.5 cycles. If this condition cannot be fulfilled, some measure must be devised such as arranging pull-down resistance externally, or performing multiple read-outs. IOC0, IOC1: The input and output modes of the I/O ports can be set I/O control registers with these registers. (7EH*D0, FEH*D0) When "1" is written: Output mode When "0" is written: Input mode Read-out: Valid The input and output modes of the I/O ports are set in units of four bits. IOC0 sets the mode for P00-P03, and IOC1 sets the mode for P10-P13. Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and writing "0" induces the input mode. At initial reset, these two registers are set to "0", so the I/O ports are in the input mode. Programming notes (1) When the I/O port is being read out, the built-in pulldown resistance of the I/O port goes ON. Consequently, if data is read out while the CPU is running in the OSC3 oscillation circuit, data must be read out continuously for about 500 s. (2) When the I/O port is set to the output mode and the data register has been read, the terminal data instead of the register data can be read out. Because of this, if a lowimpedance load is connected and read-out performed, the value of the register and the read-out result may differ. S1C62N33 TECHNICAL HARDWARE EPSON I-45 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7 LCD Driver (COM0-COM3, SEG0-SEG39) Configuration of LCD The S1C62N33 Series has four common terminals and 40 segment terminals, so that it can drive an LCD with a maxidriver mum of 160 (40 x 4) segments. The power for driving the LCD is generated by the CPU internal circuit so that there is no need to apply power especially from outside. The driving method is 1/4 duty (or 1/3 duty with the mask option) dynamic drive depending on the four types of potential, VDD, VL1, VL2 and VL3. The frame frequency is fosc1/ 1,024 Hz for 1/4 duty, and fosc1/768 Hz for 1/3 duty. Figure 4.7.1 shows the drive waveform for 1/4 duty, and Figure 4.7.2 shows the drive waveform for 1/3 duty. Note Fosc1 indicates the oscillation frequency of the OSC1 oscillation circuit. I-46 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 -VDD -VL1 -VL2 -VL3 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0-39 COM2 Not lit Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0-39 Frame frequency Fig. 4.7.1 Drive waveform for 1/4 duty S1C62N33 TECHNICAL HARDWARE EPSON I-47 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 -VDD -VL1 -VL2 -VL3 LCD lighting status COM0 COM1 COM2 COM1 SEG0-39 COM2 Not lit Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0-39 Frame frequency Fig. 4.7.2 Drive waveform for 1/3 duty I-48 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Switching between dynamic and static drive The S1C62N33 Series provides software setting of the LCD static drive. This function enables easy adjustment (cadence adjustment) of the oscillation frequency of the OSC1 oscillation circuit (crystal oscillation circuit). The procedure for executing static drive of the LCD is as follows: Write "1" to register CSDC at address 78H*D3. Write the same value to all registers corresponding to COM0-COM3 of the segment memory. Note - Even when 1/3 duty is selected, COM3 is valid for static drive. However, the output frequency is the same as for the frame frequency. - For cadence adjustment, set the segment data so that all the LCDs light. Figure 4.7.3 shows the drive waveform for static drive. LCD lighting status -V DD -V L1 -V L2 -V L3 COM 0-3 COM0 COM1 COM2 COM3 SEG0-39 Frame frequency -V DD -V L1 -V L2 -V L3 Not lit Lit SEG 0-39 -V DD -V L1 -V L2 -V L3 Fig. 4.7.3 LCD static drive waveform S1C62N33 TECHNICAL HARDWARE EPSON I-49 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (1) Segment allocation Mask option (segment allocation) As shown in Figure 4.1.2, segment data of the S1C62N33 Series is decided depending on display data written to the segment data memory (write-only) at address 40H-6FH or C0H-EFH. The mask option enables the segment data memory to be allocated entirely to either 40H-6FH or C0H-EFH. The address and bits of the segment data memory can be made to correspond to the segment pins (SEG0- SEG39) in any form through the mask option. This makes design easy by increasing the degree of freedom with which the liquid crystal panel can be designed. Figure 4.7.4 shows an example of the relationship between the LCD segments (on the panel) and the segment data memory (when 40H-6FH is selected) for the case of 1/3 duty. Address Data Common 0 Common 1 Common 2 D3 D2 D1 D0 6AH d c b a 6BH p g f e 6CH d' c' b' a' 6DH p' g' f' e' SEG10 6A, D0 (a) 6A, D1 (b) 6D, D1 (f' ) SEG11 SEG12 Segment data memory allocation 6B, D1 (f) 6B, D2 (g) 6A, D2 (c) 6B, D0 (e) 6A, D3 (d) 6B, D3 (p) Pin address allocation a a' b f e g' c d SEG10 b' f' g c' e' p p' d' SEG11 SEG12 Common 0 Fig. 4.7.4 Common 1 Segment allocation Common 2 Example of LCD panel I-50 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (2) Drive duty With the mask option, either 1/4 or 1/3 duty can be selected for the LCD drive duty. Table 4.7.1 shows the differences in the number of segments depending on the selected duty. Table 4.7.1 Differences depending on selected duty Duty 1/4 1/3 Pins Used in Common Maximum Number of Segments Frame Frequency (when fosc1 = 32 kHz) COM0-COM3 COM0-COM2 160 (40 x 4) 120 (40 x 3) fosc1/1,024 (32 Hz) fosc1/768 (42.7 Hz) (3) Output specification The segment pins (SEG0-SEG39) are selected with the mask option in pairs for either segment signal output or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to COM0 of each segment pin is output. When DC output is selected, either complementary output or Pch open drain output can be selected for each pin with the mask option. Note The pin pairs are the combination of SEG2*n and SEG2*n + 1 (where n is an integer from 0 to 18). S1C62N33 TECHNICAL HARDWARE EPSON I-51 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Control of LCD driver Table 4.7.2 shows the LCD driver's control bits and their addresses. Figure 4.7.5 shows the segment data memory map. Table 4.7.2 Control bits of LCD driver Address *7 Register D2 D1 D3 CSDC ETI2 ETI8 D0 Name ETI32 CSDC R/W SR *1 Comment 1 0 0 Static Dynamic ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) LCD drive switch 78H *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D E F High 4 or C 0 *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary 5 or D 6 or E Segment data memory (40 words x 4 bits) 40H-6FH = R/W C0H-EFH = W Fig. 4.7.5 Segment data memory map I-52 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) CSDC: LCD drive switch (78H*D3) The LCD drive format can be selected with this switch. When "1" is written: When "0" is written: Read-out: Static drive Dynamic drive Valid At initial reset, dynamic drive (CSDC = "0") is selected. Segment data memory The LCD segments are lit or turned off depending on this (40H-6FH or C0H-EFH) data. When "1" is written: When "0" is written: Read-out: Lit Not lit Valid for 40H-6FH Undefined C0H-EFH By writing data into the segment data memory allocated to the LCD segment (on the panel), the segment can be lit or put out. At initial reset, the contents of the segment data memory are undefined. Programming notes (1) When 40H-6FH is selected for the segment data memory, the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the segment data memory by executing initial processing. (2) When C0H-EFH is selected for the segment data memory, that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). S1C62N33 TECHNICAL HARDWARE EPSON I-53 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8 Clock Timer Configuration of clock timer The S1C62N33 Series has a built-in clock timer as the source oscillator for OSC1 (crystal oscillator). The clock timer is configured of a seven-bit binary counter that serves as the input clock, a 256 kHz signal output by the prescaler. Data of the four high-order bits (16 Hz-2 Hz) can be read out by the software. Figure 4.8.1 is the block diagram for the clock timer. Data bus OSC1 oscillation circuit 256 Hz 128 Hz-32 Hz 16 Hz-2 Hz 32 Hz, 8 Hz, 2 Hz Fig. 4.8.1 Block diagram of clock timer Clock timer reset signal Interrupt control Interrupt request Ordinarily, this clock timer is used for all types of timing functions such as clocks. I-54 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz and 2 Hz signals. Software can set whether to mask any of these frequencies. Figure 4.8.2 is the timing chart of the clock timer. Interrupt function Address 70H Clock timer timing chart Register Frequency D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz 32 Hz interrupt request Fig. 4.8.2 Timing chart of clock timer 8 Hz interrupt request 2 Hz interrupt request As shown in Figure 4.8.2, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz). At this time, the corresponding interrupt factor flag (TI32, TI8, TI2) is set to "1". Selection of whether to mask the separate interrupts can be made with the interrupt mask registers (ETI32, ETI8, ETI2). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal. Note Perform writing to the interrupt mask registers (ETI32, ETI8, ETI2) and readout from the interrupt factor flags (TI32, TI8, TI2) only in the DI status (interrupt flag = "0"). S1C62N33 TECHNICAL HARDWARE EPSON I-55 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Table 4.8 shows the clock timer control bits and their addresses. Control of clock timer Table 4.8 Control bits of clock timer Address *7 D3 Register D2 D1 TM3 TM2 TM1 Name TM0 TM3 0 Timer data (clock timer 2 Hz) TM2 0 Timer data (clock timer 4 Hz) TM1 0 Timer data (clock timer 8 Hz) TM0 0 Timer data (clock timer 16 Hz) CSDC 0 Static Dynamic ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) - *2 TI2 0 Yes No Interrupt factor flag (clock timer 2 Hz) *4 TI8 0 Yes No Interrupt factor flag (clock timer 8 Hz) *4 TI32 0 Yes No Interrupt factor flag (clock timer 32 Hz) *4 R SR *1 Comment D0 1 0 70H CSDC ETI2 ETI8 ETI32 R/W LCD drive switch 78H - TI2 TI8 TI32 R Unused *5 79H TMRST SWRUN SWRST IOC0 TMRST Reset Reset - W R/W W R/W SWRUN 0 RUN STOP SWRST Reset Reset - IOC0 0 Output Input Clock timer reset *5 Stopwatch counter RUN/STOP 7EH *1 *2 *3 *4 I-56 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON Stopwatch counter reset *5 I/O control register 0 (P00-P03) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) TM0-TM3: The 16 Hz-2 Hz timer data of the clock timer can be read Timer data out with this register. These four bits are read-out only, and (70H) writing operations are invalid. At initial reset, the timer data is initialized to "0H". ETI32, ETI8, ETI2: These registers are used to select whether to mask the clock Interrupt mask registers timer interrupt. (78H*D0-D2) When "1" is written: Enabled When "0" is written: Masked Read-out: Valid The interrupt mask registers (ETI32, ETI8, ETI2) are used to select whether to mask the interrupt to the separate frequencies (32 Hz, 8 Hz, 2 Hz). Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). At initial reset, these registers are all set to "0". TI32, TI8, TI2: These flags indicate the status of the clock timer interrupt. Interrupt factor flags When "1" is read out: Interrupt has occurred (79H*D0-D2) When "0" is read out: Interrupt has not occurred Writing: Invalid The interrupt factor flags (TI32, TI8, TI2) correspond to the clock timer interrupts of the respective frequencies (32 Hz, 8 Hz, 2 Hz). The software can judge from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the signal. These flags can be reset through being read out by the software. Also, the flags can be read out only in the DI status (interrupt flag = "0"). At initial reset, these flags are set to "0". S1C62N33 TECHNICAL HARDWARE EPSON I-57 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) TMRST: This bit resets the clock timer. Clock timer reset When "1" is written: Clock timer reset (7EH*D3) When "0" is written: No operation Read-out: Always "0" The clock timer is reset by writing "1" to TMRST. The clock timer starts immediately after this. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" at read-out. Programming notes (1) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Consequently, perform flag read-out (reset the flag) as necessary at reset. (2) The input clock of the watchdog timer is the 2 Hz signal of the clock timer, so that the watchdog timer may be counted up at timer reset. (3) Read-out the interrupt factor flag (TI) only during the DI status (interrupt flag = "0"). Read-out during EI status will cause malfunction. (4) Writing to the interrupt mask register (ETI) can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause malfunction. I-58 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter) 4.9 Stopwatch Counter Configuration of stopwatch counter The S1C62N33 Series incorporates a 1/100 sec and 1/10 sec stopwatch counter. The stopwatch counter is configured of a two-stage, four-bit BCD counter serving as the input clock of an approximately 100 Hz signal (signal obtained by approximately demultiplying the 256 Hz signal output by the prescaler). Data can be read out four bits at a time by the software. Figure 4.9.1 is the block diagram of the stopwatch counter. Data bus OSC1 oscillation circuit Fig. 4.9.1 Block diagram of stopwatch counter 10 Hz 256 Hz SWL counter SWH counter 10 Hz, 1 Hz Stopwatch counter reset signal Stopwatch counter RUN/STOP signal Interrupt control Interrupt request The stopwatch counter can be used as a separate timer from the clock timer. In particular, digital watch stopwatch functions can be realized easily with software. S1C62N33 TECHNICAL HARDWARE EPSON I-59 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter) The stopwatch counter is configured of four-bit BCD counters SWL and SWH. The counter SWL, at the stage preceding the stopwatch counter, has an approximated 100 Hz signal for the input clock. It counts up every 1/100 sec, and generates an approximated 10 Hz signal. The counter SWH has an approximated 10 Hz signal generated by the counter SWL for the input clock. It count-up every 1/10 sec, and generated 1 Hz signal. Figure 4.9.2 shows the count-up pattern of the stopwatch counter. Count-up pattern SWH count up pattern SWH count value Count time (S) 0 1 26 256 2 3 4 5 6 7 8 9 0 26 25 25 26 26 25 25 26 26 256 256 256 256 256 256 256 256 256 26 x 6 + 25 x 4 = 1 (S) 256 256 1 Hz signal generation SWL count up pattern 1 SWL count value Count time (S) 0 1 3 256 2 3 4 5 6 7 8 9 0 2 3 2 3 2 3 2 3 2 256 256 256 256 256 256 256 256 256 25 256 (S) Approximate 10 Hz signal generation SWL count up pattern 2 SWL count value Count time (S) 0 1 2 3 4 5 6 7 8 9 0 3 3 3 2 3 2 3 2 3 2 256 256 256 256 256 256 256 256 256 256 26 (S) 256 Fig. 4.9.2 Count-up pattern of Approximate 10 Hz signal generation stopwatch counter SWL generates an approximated 10 Hz signal from the basic 256 Hz signal. The count-up intervals are 2/256 sec and 3/ 256 sec, so that finally two patterns are generated: 25/256 sec and 26/256 sec intervals. Consequently, these patterns do not amount to an accurate 1/100 sec. SWH counts the approximated 10 Hz signals generated by the 25/256 sec and 26/256 sec intervals in the ratio of 4:6, to generate a 1 Hz signal. The count-up intervals are 25/ 256 sec and 26/256 sec, which do not amount to an accurate 1/10 sec. I-60 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter) The 10 Hz (approximate 10 Hz) and 1 Hz interrupts can be generated through the overflow of stopwatch counters SWL and SWH respectively. Also, software can set whether to separately mask the frequencies described earlier. Figure 4.9.3 is the timing chart for the stopwatch counter. Interrupt function Address Stopwatch counter (SWL) timing chart Register D0 71H (1/100 sec BCD) D1 D2 D3 10 Hz interrupt request Address Register Stopwatch counter (SWH) timing chart D0 72H (1/10 sec BCD) Fig. 4.9.3 Timing chart for stopwatch counter D1 D2 D3 1 Hz interrupt request As shown in Figure 4.9.3, the interrupts are generated by the overflow of their respective counters ("9" changing to "0"). Also, at this time the corresponding interrupt factor flags (SWIT0, SWIT1) are set to "1". The respective interrupts can be masked separately through the interrupt mask registers (EISWIT0, EISWIT1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters. Note S1C62N33 TECHNICAL HARDWARE Perform writing to the interrupt mask registers (EISWIT0, EISWIT1) and readout from the interrupt factor flags (SWIT0, SWIT1) only in the DI status (interrupt flag = "0"). EPSON I-61 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter) Control of stopwatch Table 4.9.1 list the stopwatch counter control bits and their addresses. counter Table 4.9.1 Stopwatch counter control bits Address *7 D3 SWL3 Register D2 D1 SWL2 Name SWL0 SWL3 0 MSB SWL2 0 Stopwatch counter 1/100 sec (BCD) SWL1 0 SWL0 0 LSB SWH3 0 MSB SWH2 0 Stopwatch counter 1/10 sec (BCD) SWH1 0 SWH0 0 EISWIT1 EISWIT0 HVLD 0 R/W SVDDT SVDON 0 0 Low voltage EISWIT1 SWL1 R SR *1 1 0 71H SWH3 SWH2 SWH1 SWH0 R 72H HVLD R/W 76H IK1 SVDDT SVDON R W IK0 Comment D0 SWIT1 SWIT0 R LSB Heavy load Normal Heavy load protection mode register ON Normal OFF 0 Enable Mask EISWIT0 0 Enable Mask SVD evaluation data (at read-out) SVD ON/OFF (at writing) Interrupt mask register (stopwatch 1 Hz) Interrupt mask register (stopwatch 10 Hz) IK1 0 Yes No Interrupt factor flag (K10) *4 IK0 0 Yes No Interrupt factor flag (K00-K03) *4 SWIT1 0 Yes No Interrupt factor flag (stopwatch 1 Hz) *4 SWIT0 0 Yes No Interrupt factor flag (stopwatch 10 Hz) *4 7AH TMRST SWRUN SWRST IOC0 TMRST Reset Reset - W R/W W R/W SWRUN 0 RUN STOP SWRST Reset Reset - IOC0 0 Output Input Clock timer reset *5 Stopwatch counter RUN/STOP 7EH *1 *2 *3 *4 I-62 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON Stopwatch counter reset *5 I/O control register 0 (P00-P03) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter) SWL0-SWL3: Data (BCD) of the 1/100 sec column of the stopwatch counStopwatch counter ter can be read out. These four bits are read-only, and 1/100 sec (71H) cannot be used for writing operations. At initial reset, the counter data is set to "0H". SWH0-SWH3: Data (BCD) of the 1/10 sec column of the stopwatch counter Stopwatch counter can be read out. These four bits are read-only, and cannot 1/10 sec (72H) be used for writing operations. At initial reset, the counter data is set to "0H". EISWIT0, EISWIT1: These registers are used to select whether to mask the Interrupt mask register stopwatch counter interrupt. (76H*D0 and D1) When "1" is written: Enabled When "0" is written: Masked Read-out: Valid The interrupt mask registers (EISWIT0, EISWIT1) are used to separately select whether to mask the 10 Hz and 1 Hz interrupts. Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). At initial reset, these registers are both set to "0". SWIT0, SWIT1: These flags indicate the status of the stopwatch counter Interrupt factor flag interrupt. (7AH*D0 and D1) When "1" is read out: Interrupt has occurred When "0" is read out: Interrupt has not occurred Writing: Invalid The interrupt factor flags (SWIT0, SWIT1) correspond to the 10 Hz and 1 Hz interrupts respectively. With these flags, the software can judge whether a stopwatch counter interrupt has occurred. However, regardless of the interrupt mask register setting, these flags are set to "1" by the counter overflow. These flags are reset when read out by the software. Also, read-out is only possible in the DI status (interrupt flag = "0"). At initial reset, these flags are set to "0". S1C62N33 TECHNICAL HARDWARE EPSON I-63 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter) SWRST: This bit resets the stopwatch counter. Stopwatch counter reset When "1" is written: Stopwatch counter reset (7EH*D1) When "0" is written: No operation Read-out: Always "0" The stopwatch counter is reset when "1" is written to SWRST. When the stopwatch counter is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. This bit is write-only, and is always "0" at read-out. SWRUN: This bit controls RUN/STOP of the stopwatch counter. Stopwatch counter When "1" is written: RUN RUN/STOP When "0" is written: STOP (7EH*D2) Read-out: Valid The stopwatch counter enters the RUN status when "1" is written to SWRUN, and the STOP status when "0" is written. In the STOP status, the counter data is maintained until the next RUN status or resets counter. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. When the counter data is read out in the RUN status, correct read-out may be impossible because of the carry from the low-order bit (SWL) to the high-order bit (SWH). This occurs when read-out has extended over the SWL and SWH bits when the carry occurs. To prevent this, perform read out after entering the STOP status, and then return to the RUN status. Also, the duration of the STOP status must be within 976 s (256 Hz 1/4 cycle). At initial reset, this register is set to "0". I-64 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter) Programming notes (1) If counter data is read out in the RUN status, the counter must be made into the STOP status, and after data is read out the RUN status can be restored. If data is read out when a carry occurs, the data cannot be read correctly. Also, the processing above must be performed within the STOP interval of 976 s (256 Hz 1/4 cycle). (2) Read-out of the interrupt factor flag (SWIT) must be done only in the DI status (interrupt flag = "0"). Read-out during EI status will cause malfunction. (3) Writing to the interrupt mask registers (EISWIT) can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause malfunction. S1C62N33 TECHNICAL HARDWARE EPSON I-65 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) 4.10 Event Counter The S1C62N33 Series has an event counter that counts the clock signals input from outside. The event counter is configured of eight-bit binary counters (UP counters). The clock pulses are input through pins K02 and K03 of the input port. Figure 4.10.1 shows the configuration of the event counter. Input port K10 Noise rejector circuit Fig. 4.10.1 Configuration of Event counter RUN/STOP event counter Event counter reset Operation of event counter Interrupt request Data bus Configuration of event counter Event counter [EV00-EV07] The clock signal input from terminal K10 is input to the event counter via the noise rejector. The event counter increments when the clock signal is input, and the incremented data can be read out through the software. RUN and STOP of the event counter are performed by making the clock of the noise rejector ON and OFF. This is controlled by writing data to the EVRUN register. Figure 4.10.2 is the timing chart for the event counter. Noise Input of K10 terminal EVRUN TON STOP TOFF RUN TON2 TN TSTP Input of event counter Defined time Fig. 4.10.2 Timing chart of TON TOFF TN TSTP TON2 < 1.5 T 1.0 T 0.5 T 0.5 T 1.5 T CH CH CH CH CH + TSTP (Execution time) TCH = 1/fCH Through the mask option, f CH selects fosc 1/16 or fosc 1/128 for the clock frequency of the noise rejector event counter I-66 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) The clock frequency of the noise rejector can be selected as fosc1/16 or fosc1/128. Table 4.10.1 lists the defined time depending on the frequency selected. Mask option Table 4.10.1 Defined time depending on frequency selected Selection fosc1/16 fosc1/128 TON 0.74 5.86 TOFF 0.49 3.91 TN 0.24 1.95 TSTP 0.25 1.96 fosc1 = 32,768 Hz TN : Max value Others : Min value (Unit: ms) Table 4.10.2 shows the event counter control bits and their addresses. Control of event counter Table 4.10.2 Event counter control bits Address *7 D3 EV03 Register D2 D1 EV02 EV01 D0 Name EV00 EV03 0 EV02 0 EV01 0 EV00 0 EV07 0 EV06 0 EV05 0 EV04 0 R SR *1 1 Event counter low order (EV00-EV03) F8H EV07 EV06 EV05 EV04 R Event counter high order (EV04-EV07) F9H - EVRUN - EVRST - *2 R R/W R W EVRUN 0 - *2 EVRST Reset Comment 0 Unused *5 RUN STOP Event counter RUN/STOP FCH *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read S1C62N33 TECHNICAL HARDWARE EPSON Unused *5 Reset - Event counter reset *5 *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary I-67 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) EV00-EV03: The four low-order data bits of event counter are read out. Event counter Low-order These four bits are read-only, and cannot be used for writ(F8H) ing. At initial reset, event counter is set to "00H". EV04-EV07: The four high-order data bits of event counter are read out. Event counter High-order These four bits are read-only, and cannot be used for writ(F9H) ing. At initial reset, event counter is set to "00H". EVRST: This is the register for resetting event counter. Event counter reset When "1" is written: Event counter reset (FCH*D0) When "0" is written: No operation Read-out: Always "0" When "1" is written, event counter is reset and the data becomes "00H". When "0" is written, no operation is executed. This is a write-only bit, and is always "0" at read-out. EVRUN: This register controls the Event counter RUN/STOP When "1" is written: (FCH*D2) When "0" is written: Read-out: event counter RUN/STOP status. RUN STOP Valid When "1" is written, the event counter enters the RUN status and starts receiving the clock signal input. When "0" is written, the event counter enters the STOP status and the clock signal input is ignored. (However, input to the input port is valid.) At initial reset, this register is set to "0". Programming note I-68 To prevent erroneous reading of the event counter data, read out the counter data several times, compare it, and use the matching data as the result. EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator) 4.11 Analog Comparator Configuration of analog comparator The S1C62N33 Series incorporates an MOS input analog comparator. This analog comparator, which has two differential input terminals (inverted input terminal AMPM, noninverted input terminal AMPP), can be used for general purposes. Figure 4.11 shows the configuration of the analog comparator. VDD + AMPM - AMPDT Data bus AMPP Input control Power source AMPON control Fig. 4.11 Configuration of VSS analog comparator Operation of analog comparator Address The analog comparator is ON when the AMPON register is "1", and compares the input levels of the AMPP and AMPM terminals. The result of the comparison is read from the AMPDT register. It is "1" when AMPP (+) > AMPM (-) and "0" when AMPP (+) < AMPM (-). After the analog comparator goes ON it takes a maximum of 3 ms until the output stabilizes. S1C62N33 TECHNICAL HARDWARE EPSON I-69 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator) Control of analog comparator Table 4.11 lists the analog comparator control bits and their addresses. Table 4.11 Analog comparator control bits Address *7 D3 - Register D2 D1 - R AMPDT SR *1 Comment D0 Name AMPON - *2 Unused *5 R/W - *2 Unused *5 AMPDT 1 +>- ->+ Analog comparator data AMPON 0 ON OFF Analog comparator ON/OFF 1 0 F7H *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary AMPON: Switches the analog comparator ON and OFF. Analog comparator When "1" is written: The analog comparator goes ON ON/OFF (F7H*D0) When "0" is written: The analog comparator goes OFF Read-out: Valid The analog comparator goes ON when "1" is written to AMPON, and OFF when "0" is written. At initial reset, AMPON is set to "0". AMPDT: Reads out the output from the analog comparator. Analog comparator data When "1" is read out: AMPP (+) > AMPM (-) (F7H*D1) When "0" is read out: AMPP (+) < AMPM (-) Writing: Invalid AMPDT is "0" when the input level of the inverted input terminal (AMPM) is greater than the input level of the noninverted input terminal (AMPP); and "1" when smaller. At initial reset, AMPDT is set to "1". Programming notes (1) To reduce current consumption, set the analog comparator to OFF when it is not necessary. (2) After setting AMPON to "1", wait at least 3 ms for the operation of the analog comparator to stabilize before reading the output data of the analog cpmparator from AMPDT. I-70 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) 4.12 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function Configuration of SVD circuit The S1C62N33 Series has a built-in supply voltage detection (SVD) circuit, so that the software can find when the source voltage lowers. The configuration of the SVD circuit is shown in Figure 4.12. Turning the SVD operation ON/OFF is controlled through the software (HVLD, SVDON). Moreover, when a drop in source voltage (SVDDT = "1") is detected, SVD operation is periodically performed by the hardware until the source voltage is recovered (SVDDT = "0"). Because the power current consumption of the IC becomes big when the SVD operation is turned ON, set the SVD operation to OFF unless otherwise necessary. See "7 ELECTRICAL CHARACTERISTICS" for the evaluation voltage accuracy. VDD SVD circuit HVLD SVD sampling control Fig. 4.12 Configuration of SVD circuit S1C62N33 TECHNICAL HARDWARE Address 76H SVDON VSS Detection output EPSON Data bus Address 76H SVDDT I-71 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) Heavy load protection function (S1C62L33) Note that the heavy load protection function on the S1C62L33 is different from the S1C62N33. (1) In case of S1C62L33 The S1C62L33 has the heavy load protection function for when the battery load becomes heavy and the source voltage drops, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. In this mode, operation with a lower voltage than normal is possible. The normal mode changes to the heavy load protection mode in the following two cases: When the software changes the mode to the heavy load protection mode (HVLD = "1") When supply voltage drop (SVDDT = "1") in the SVD circuit is detected, the mode will automatically shift to the heavy load protection mode until the supply voltage is recovered (SVDDT = "0") In the heavy load protection mode, the internally regulated voltage is generated by the liquid crystal driver source output VL2 so as to operate the internal circuit. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. Also, when the SVD is to be turned on during operation in the heavy load protection mode, limit the ON time to 10 ms per second of operation time. (2) In case of S1C62N33/62A33 The S1C62N33/62A33 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. Compared with the normal operation mode, this mode can reduce the output voltage variation of the constant voltage/booster voltage circuit of the LCD system. The normal mode changes to the heavy load protection mode in the following case: I-72 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) When the software changes the mode to the heavy load protection mode (HVLD = "1") The heavy load protection mode switches the constant voltage circuit of the LCD system to the high-stability mode from the low current consumption mode. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. Detection timing of SVD circuit This section explains the timing for when the SVD circuit writes the result of the source voltage detection to the SVDDT latch. Turning the SVD operation ON/OFF is controlled through the software (HVLD, SVDON). Moreover, when a drop in source voltage (SVDON = "1") is detected, SVD operation is periodically performed by the hardware until the source voltage is recovered (SVDON = "0"). The result of the source voltage detection is written to the SVDDT latch by the SVD circuit, and this data can be read out by the software to find the status of the source voltage. There are three methods, explained below, for executing the detection operation of the SVD circuit. (1) Sampling with HVLD set to "1" When HVLD is set to "1" and SVD sampling executed, the detection results can be written to the SVDDT latch in the following two timings. Immediately after the time for one instruction cycle has ended immediately after HVLD = "1" Immediately after sampling in the 2 Hz cycle output by the clock timer while HVLD = "1" Consequently, the SVDDT latch data is loaded immediately after HVLD has been set to "1", and at the same time the new detection result is written in 2 Hz cycles. To obtain a stable SVD detection result, the SVD circuit must be set to ON with at least 100 s. Consequently, when the CPU system clock is fosc3 in S1C62A33, the detection result at the timing in above may be invalid or incorrect. (When performing SVD detection using the timing in , be sure that the CPU system clock is fosc1.) S1C62N33 TECHNICAL HARDWARE EPSON I-73 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) (2) Sampling with SVDON set to "1" When SVDON is set to "1", SVD detection is executed. As soon as SVDON is reset to "0" the detection result is loaded to the SVDDT latch. To obtain a stable SVD detection result, the SVD circuit must be set to ON with at least 100 s. Hence, to obtain the SVD detection result, follow the programming sequence below. 0. Set HVLD to "1" (only when the CPU system clock is fosc3 in S1C62A33) 1. Set SVDON to "1" 2. Maintain at 100 s minimum 3. Set SVDON to "0" 4. Read out SVDDT 5. Set HVLD to "0" (only when the CPU system clock is fosc3 in S1C62A33) However, when a crystal oscillation clock (fosc1) is selected for the CPU system clock in S1C62N33, S1C62L33, and S1C62A33, the instruction cycles are long enough, so that there is no need for concern about maintaining 100 s for the SVDON = "1" with the software. (3) Sampling by hardware when SVDDT latch is set to "1" When SVDDT latch is set to "1", the detection results can be written to the SVDDT latch in the following two timings (same as that sampling with HVLD set to "1"). Immediately after the time for one instruction cycle has ended immediately after SVDDT = "1" Immediately after sampling in the 2 Hz cycle output by the clock timer while SVDDT = "1" Consequently, the SVDDT latch data is loaded immediately after SVDDT latch has been set to "1", and at the same time the new detection result is written in 2 Hz cycles. To obtain a stable SVD detection result, the SVD circuit must be set to ON with at least 100 s. When the CPU system clock is fosc3 in S1C62A33, the detection result at the timing in above may be invalid or incorrect. I-74 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) Table 4.12 shows the SVD circuit's control bits and their addresses. Control of SVD circuit Table 4.12 Control bits of SVD circuit Address *7 D3 HVLD R/W 76H *1 *2 *3 *4 Register D2 D1 SVDDT SVDON R W D0 Name SR *1 0 Heavy load Normal Heavy load protection mode register SVD evaluation data (at read-out) SVD ON/OFF (at writing) Interrupt mask register (stopwatch 1 Hz) Interrupt mask register (stopwatch 10 Hz) EISWIT1 EISWIT0 HVLD 0 R/W SVDDT SVDON 0 0 Low voltage ON Normal OFF EISWIT1 0 Enable Mask EISWIT0 0 Enable Mask Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read HVLD: Heavy load protection mode (76H*D3) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary When "1" is written: When "0" is written: Read-out: Comment 1 Heavy load protection mode is set Heavy load protection mode is released Valid When HVLD is set to "1", the IC operating status enters the heavy load protection mode and at the same time the supply voltage detection of the SVD circuit is controlled (ON/OFF). When HVLD is set to "1", sampling control is executed for the SVD circuit ON time. There are two types of sampling time, as follows: (1) The time of one instruction cycle immediately after HVLD = "1" (2) Sampling at cycles of 2 Hz output by the clock timer while HVLD = "1" The SVD circuit must be made ON with at least 100 s for the SVD circuit to respond. Hence, when the CPU system clock is fosc3 in S1C62A33, the detection result at the timing in (1) above may be invalid or incorrect. (When performing SVD detection using the timing in (1), be sure that the CPU system clock is fosc1.) S1C62N33 TECHNICAL HARDWARE EPSON I-75 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) When SVD sampling is done with HVLD set to "1", the results are written to the SVDDT latch in the timing as follows: (1) As soon as the time has elapsed for one instruction cycle immediately following HVLD = "1" (2) Immediately on completion of sampling at cycles of 2 Hz output by the clock timer while HVLD = "1" Consequently, the SVDDT latch data is written immediately after HVLD is set to "1", and at the same time the new detection result is written in 2 Hz cycles. SVDON/SVDDT: SVD detection/SVD data (76H*D2) When "0" is written: SVD detection OFF When "1" is written: SVD detection ON When "0" is read out: Source voltage (VDD-VSS) is higher than SVD set value When "1" is read out: Source voltage (VDD-VSS) is lower than SVD set value Note that the function of this bit when written is different to when read out. When this bit is written to, ON/OFF of the SVD detection operation is controlled; when this bit is read out, the result of the SVD detection (contents of SVDDT latch) is obtained. Appreciable current is consumed during operation of SVD detection, so keep SVD detection OFF except when necessary. When SVDON is set to "1", SVD detection is executed. As soon as SVDON is reset to "0" the detection result is loaded to the SVDDT latch. To obtain a stable SVD detection result, the SVD circuit must be set to ON with at least 100 s. Hence, to obtain the SVD detection result, follow the programming sequence below. 0. Set HVLD to "1" (only when the CPU system clock is fosc3 in S1C62A33) 1. Set SVDON to "1" 2. Maintain at 100 s minimum 3. Set SVDON to "0" 4. Read out SVDDT 5. Set HVLD to "0" (only when the CPU system clock is fosc3 in S1C62A33) However, when a crystal oscillation clock (fosc1) is selected for the CPU system clock in S1C62N33, S1C62L33, and S1C62A33, the instruction cycles are long enough, so that there is no need for concern about maintaining 100 s for the SVDON = "1" with the software. I-76 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) Programming notes (1) It takes 100 s from the time the SVD circuit goes ON until a stable result is obtained. For this reason, keep the following software notes in mind: When the CPU system clock is fosc1 1. When detection is done at HVLD After writing "1" on HVLD, read the SVDDT after 1 instruction has passed. 2. When detection is done at SVDON After writing "1" on SVDON, write "0" after at least 100 s has lapsed (possible with the next instruction) and then read the SVDDT. When the CPU system clock is fosc3 (in case of S1C62A33 only) 1. When detection is done at HVLD After writing "1" on HVLD, read the SVDDT after 0.6 sec has passed. (HVLD holds "1" for at least 0.6 sec) 2. When detection is done at SVDON Before writing "1" on SVDON, write "1" on HVLD first; after at least 100 s has lapsed after writing "1" on SVDON, write "0" on SVDON and then read the SVDDT. (2) SVDON resides in the same bit at the same address as SVDDT, and one or the other is selected by write or read operation. When writing a "1" to SVDON use the OR command, and when writing a "0" use the AND command. No other commands should be used for this purpose. (3) Select one of the following software processing to return to the normal mode after a heavy load has been driven in the heavy load protection mode (S1C62L33). After heavy load drive is completed, return to the normal mode after at least one second has elapsed. After heavy load drive is completed, switch SVD ON and OFF (at least 100 s is necessary for the ON status) and then return to the normal mode. The S1C62N33/62A33 returns to the normal mode after driving a heavy load without special software processing. (4) When the SVD is to be turned on during operation in the heavy load protection mode, limit the ON time to 10 ms per second of operation time. S1C62N33 TECHNICAL HARDWARE EPSON I-77 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.13 Serial Interface (SIN, SOUT, SCLK, SIOF) Configuration of serial interface The S1C62N33 has a synchronous clock type 8 bits serial interface built-in. The configuration of the serial interface is shown in Figure 4.13.1. The CPU, via the 8 bits shift register, can read the serial input data from the SIN terminal. Moreover, via the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT terminal. The synchronous clock for serial data input/output may be set by selecting by software any one of 3 types of master mode (internal clock mode: when the S1C62N33 is to be the master for serial input/output) and a type of slave mode (external clock mode: when the S1C62N33 is to be the slave for serial input/output). Also, when the serial interface is used at slave mode, SIOF signal which indicates whether or not the serial interface is available to transmit or receive output to output port SIOF. SD0-SD7 SIN Shift register (8 bits) SCS0 SCS1 Serial clock selector SOUT Output latch SEN Serial clock counter Serial interface interrupt control circuit ISIO SCLK Serial clock generator System clock EISIO Serial interface activating circuit Fig. 4.13.1 Configuration of SIOF SCTRG serial interface I-78 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Master mode and slave mode of serial interface Table 4.13.1 Synchronous clock selection The serial interface of the S1C62N33 has two types of operation mode: master mode and slave mode. In the master mode, it uses an internal clock as synchronous clock of the built-in shift register, generates this internal clock at the SCLK terminal and controls the external (slave side) serial device. In the slave mode, the synchronous clock output from the external (master side) serial device is input from the SCLK terminal and uses it as the synchronous clock to the builtin shift register. The master mode and slave mode are selected by writing data to registers SCS1 and SCS0 (address F2H*D2, D3). When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in Table 4.13.1. SCS1 0 0 1 1 SCS0 0 1 0 1 Mode Master mode Slave mode Synchronous Clock CLK CLK/2 CLK/4 External clock CLK: system clock At initial reset, the slave mode (external clock mode) is selected. Moreover, the synchronous clock, along with the input /output of the 8 bits serial data, is controlled as follows: * At master mode, after output of 8 clocks from the SCLK terminal, clock output is automatically suspended and SCLK terminal is fixed at low level. * At slave mode, after input of 8 clocks to the SCLK terminal, subsequent clock inputs are masked. Note When using the serial interface in the master mode, CPU system clock is used as the synchronous clock. Accordingly, when the serial interface is operating, system clock switching (fosc1 fosc3) should not be performed. S1C62N33 TECHNICAL HARDWARE EPSON I-79 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) A sample basic serial input/output portion connection is shown in Figure 4.13.2. S1C62N33 External serial device SCLK CLK SOUT SOUT SIN SIN Input terminal READY a. Master mode S1C62N33 Fig. 4.13.2 Sample basic connection of External serial device SCLK CLK SOUT SOUT SIN SIN SIOF Input terminal serial input/output section b. Slave mode I-80 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Data input/output and interrupt function The serial interface of S1C62N33 can input/output data via the internal 8 bits shift register. The shift register operates by synchronizing with either the synchronous clock output from SCLK terminal (master mode), or the synchronous clock input to SCLK (slave mode). The serial interface generates interrupt on completion of the 8 bits serial data input/output. Detection of serial data input/output is done by the counting of the synchronous clock (SCLK); the clock completes input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates interrupt. The serial data input/output procedure data is explained below: (1) Serial data output procedure and interrupt The S1C62N33 serial interface is capable of outputting parallel data as serial data, in units of 8 bits. By setting the parallel data to 4 bits registers SD0-SD3 (address F0H) and SD4-SD7 (address F1H) individually and writing "1" to SCTRG bit (address 77H*D3), it synchronizes with the synchronous clock and serial data is output at the SOUT terminal. The synchronous clock used here is as follows: in the master mode, internal clock which is output to the SCLK terminal while in the slave mode, external clock which is input from the SCLK terminal. The serial output of the SOUT termina changes with the rising edge of the clock that is input or output from the SCLK terminal. The serial data to the built-in shift register is shifted with the rising edge of the SCLK signal when SE2 bit (address F2H*D1) is "1" and is shifted with the falling edge of the SCLK signal when SE2 bit (address F2H*D1) is "0". When the output of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO (address F3H*D0) is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIO (address F2H*D0). S1C62N33 TECHNICAL HARDWARE EPSON I-81 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (2) Serial data input procedure and interrupt The S1C62N33 serial interface is capable of inputting serial data as parallel data, in units of 8 bits. The serial data is input from the SIN terminal, synchronizes with the synchronous clock, and is sequentially read in the 8 bits shift register. As in the above item (1), the synchronous clock used here is as follows: in the master mode, internal clock which is output to the SCLK terminal while in the slave mode, external clock which is input from the SCLK terminal. The serial data to the built-in shift register is read with the rising edge of the SCLK signal when SE2 bit is "1" and is read with the falling edge of the SCLK signal when SE2 bit is "0". Moreover, the shift register is sequentially shifted as the data is fetched. When the input of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is set to "1" after input of the 8 bits data. The data input in the shift register can be read from data registers SD0-SD7 by software. I-82 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (3) Serial data input/output permutation S1C62N33 allows the input/output permutation of serial data to be selected by mask option as to either LSB first or MSB first. The block diagram showing input/output permutation in case of LSB first and MSB first is provided in Figure 4.13.3. SIN Address F1H Address F0H SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Output latch SOUT Output latch SOUT (In case of LSB first) Fig. 4.13.3 Serial data input/output permutation SIN Address F0H Address F1H SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 (In case of MSB first) (4) SIOF signal When the S1C62N33 serial interface is used in the slave mode (external clock mode), SIOF is used to indicate whether the internal serial interface is available to transmit or receive data for the master side (external) serial device. SIOF signal becomes "1" (high) when the S1C62N33 serial interface becomes available to transmit or receive data; normally, it is at "0" (low). SIOF signal changes from "0" to "1" immediately after "1" is written to SCTRG and returns from "1" to "0" when eight synchronous clock has been counted. S1C62N33 TECHNICAL HARDWARE EPSON I-83 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (5) Timing chart The S1C62N33 serial interface timing chart is shown in Figure 4.13.4. SCTRG SCLK SIN 8-BIT SHIFT REGISTER SOUT ISIO SIOF a. Timing chart, SE2 = "1" SCTRG SCLK SIN 8-BIT SHIFT REGISTER SOUT ISIO SIOF b. Timing chart, SE2 = "0" Fig. 4.13.4 Serial interface timing chart I-84 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Mask option The serial interface may be selected for the following by mask option. (1) Whether or not the SIN terminal will use built-in pull down resistor may be selected. If the use of no pull down resistor is selected, take care that floating state does not occur at the SIN terminal. When the SIN terminal is not used, the use of pull down resistor should be selected. (2) Either complementary output or P channel (Pch) open drain as output specification for the SOUT terminal may be selected. However, even if Pch open drain has been selected, application of voltage exceeding power source voltage to the SOUT terminal will be prohibited. (3) Whether or not the SCLK terminal will use pull down resistor which is turned ON during input mode (external clock) may be selected. If the use of no pull down resistor is selected, take care that floating state does not occur at the SCLK terminal during input mode. Normally, the use of pull down resistor should be selected. (4) As output specification during output mode, either complementary output or P channel (Pch) open drain output may be selected for the SCLK terminal. (5) Positive or negative logic can be selected for the signal logic of the SCLK pin (SCLK or SCLK). However, keep in mind that only pull-down resistance can be set for the input mode (pull-up resistance is not built-in). (6) LSB first or MSB first as input/output permutation of serial data may be selected. S1C62N33 TECHNICAL HARDWARE EPSON I-85 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Table 4.13.2 lists the serial interface control bits and their addresses. Control of serial interface Table 4.13.2 Control registers of serial interface Address *7 D3 Register D2 D1 SD3 SD2 SD1 Name SR *1 SD0 SD3 x *3 SD2 x *3 SD1 x *3 SD0 x *3 SD7 x *3 SD6 x *3 SD5 x *3 SD4 x *3 SCS1 1 *6 *6 SCS0 1 *6 *6 SE2 0 Rising Falling Clock edge selection register EISIO 0 Enable Mask Interrupt mask register (serial interface) - *2 Unused *5 - *2 Unused *5 - *2 Unused *5 ISIO 0 Yes No K10 SCTRG SIOF - 0 Trigger RUN - STOP Serial interface clock trigger SIOF R EIK10 0 Enable Mask Interrupt mask register (K10) DFK10 0 Falling Rising Input comparison register (K10) K10 *2 High Low R/W F0H SD7 SD6 SD5 SD4 R/W 1 0 Serial interface data regsiter Low order (SD0-SD3) Serial interface data regsiter High order (SD4-SD7) F1H SCS1 SCS0 SE2 Comment D0 EISIO R/W Clock mode selection register (SCS0, SCS1) F2H - - - ISIO R F3H SCTRG SIOF 77H *1 *2 *3 *4 I-86 W R EIK10 DFK10 R/W Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON Interrupt factor flag (serial interface) *4 Input port (K10) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SD0-SD3, SD4-SD7: These registers are used for writing and reading serial data. Serial interface data registers * During writing operation (F0H, F1H) When "1" is written: High level When "0" is written: Low level Writes serial data will be output to SOUT terminal. From the SOUT terminal, the data converted to serial data as high (VDD) level bit for bits set at "1" and as low (VSS) level bit for bits set at "0". * During reading operation When "1" is read out: High level When "0" is read out: Low level The serial data input from the SIN terminal can be read by this register. The data converted to parallel data, as high (VDD) level bit "1" and as low (VSS) level bit "0" input from SIN terminal. Perform data reading only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). At initial reset, these registers will be undefined. SCS1, SCS0: Selects the synchronous clock for the serial interface Clock mode selection (SCLK). register (F2H*D3, D2) Table 4.13.3 Synchronous clock selection SCS1 0 0 1 1 SCS0 0 1 0 1 Mode Master mode Slave mode Synchronous Clock CLK CLK/2 CLK/4 External clock CLK: system clock Synchronous clock (SCLK) is selected from among the above 4 types: 3 types of internal clock and external clock. At initial reset, external clock is selected. S1C62N33 TECHNICAL HARDWARE EPSON I-87 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SE2: Selects the timing for reading in the serial data input. Clock edge selection When "1" is written: Rising edge of SCLK register When "0" is written: Falling edge of SCLK (F2H*D1) Read-out: Valid Selects whether the fetching for the serial input data to registers (SD0-SD7) at the rising edge (at "1" writing) or falling edge (at "0" writing) of the SCLK signal. Pay attention if the synchtonous clock goes into reverse phase (SCLK SCLK) through the mask option. SCLK rising = SCLK falling, SCLK falling = SCLK rising When the internal clock is selected as the synchronous clock (SCLK), a hazard occurs in the synchronous clock (SCLK) when data is written to register SE2. The input data fetching timing may be selected but output timing for output data is fixed at SCLK rising edge. At initial reset, falling edge of SCLK (SE2 = "0") is selected. EISIO: This is the interrupt mask register of the serial interface. Interrupt mask register When "1" is written: Enabled (F2H*D0) When "0" is written: Masked Read-out: Valid At initial reset, this register is set to "0" (mask). ISIO: This is the interrupt factor flag of the serial interface. Interrupt factor flag When "1" is read out: Interrupt has occurred (F3H*D0) When "0" is read out: Interrupt has not occurred Writing: Invalid From the status of this flag, the software can decide whether the serial interface interrupt. The interrupt factor flag is reset when it has been read out. Note, however, that even if the interrupt is masked, this flag will be set to "1" after the 8 bits data input/output. Be sure that the interrupt factor flag reading is done with the interrupt in the DI status (interrupt flag = "0"). At initial reset, this flag is set to "0". I-88 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SCTRG: This is a trigger to start input/output of synchronous clock. Clock trigger When "1" is written: Trigger (77H*D3) When "0" is written: No operation Read-out: SIOF When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK) input/output is started. As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from perfoming trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. SCTRG resides in the same bit at the same address as SIOF, and one or the other is selected by write or read operation. When writing a "1" to SCTRG use the OR command, and when writing a "0" use the AND command. No other commands should be used for this purpose. SIOF: Indicates the running status of the serial interface. Serial interface running When "1" is read out: RUN status status When "0" is read out: STOP status (77H*D3) Writing: SCTRG The RUN status is indicated from immediatery after "1" is written to SCTRG bit through to the end of serial data input/output. S1C62N33 TECHNICAL HARDWARE EPSON I-89 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Programming notes (1) If the bit data of SE2 changes while SCLK is in the master mode, a hazard will be output to the SCLK pin. If this poses a problem for the system, be sure to set the SCLK to the external clock if the bit data of SE2 is to be changed. (2) Be sure that read-out of the interrupt factor flag (ISIO) is done only when the serial port is in the STOP status (SIOF = "0") and the DI status (interrupt flag = "0"). If read-out is performed while the serial data is in the RUN status (during input or output), the data input or output will be suspended and the initial status resumed. Readout during the EI status (interrupt flag = "1") causes malfunctioning. (3) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fosc1 fosc3) while the serial interface is operating. (4) Perform data writing/reading to data registers SD0-SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). (5) As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. (6) Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause malfunction. (7) SCTRG resides in the same bit at the same address as SIOF, and one or the other is selected by write or read operation. When writing a "1" to SCTRG use the OR command, and when writing a "0" use the AND command. No other commands should be used for this purpose. I-90 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14 Interrupt and HALT The S1C62N33 Series provides the following interrupt settings, each of which is maskable. External interrupt: Internal interrupt: Input interrupt (two) Timer interrupt (three) Stopwatch interrupt (two) Serial interface interrupt (one) To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask registers must be set to "1" (enable). When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are inhibited. When a HALT instruction is input the CPU operating clock stops, and the CPU enters the HALT status. The CPU is reactivated from the HALT status when an interrupt request occurs. If reactivation is not caused by an interrupt request, initial reset by the watchdog timer causes reactivates the CPU (when the watchdog timer is enabled). Figure 4.14 shows the configuration of the interrupt circuit. S1C62N33 TECHNICAL HARDWARE EPSON I-91 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) SWIT1 EISWIT1 SWIT0 EISWIT0 Interrupt vector TI2 ETI2 (MSB) TI8 Program counter (four low-order bits) ETI8 TI32 ETI32 (LSB) K00 DFK00 EIK00 INT (interrupt request) K01 DFK01 EIK01 IK0 K02 Interrupt flag DFK02 EIK02 K03 DFK03 EIK03 K10 DFK10 Interrupt factor flag IK1 EIK10 Interrupt mask register Differential register ISIO EISIO Fig. 4.14 Configuration of interrupt circuit I-92 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.14.1 shows the factors for generating interrupt requests. Interrupt factors The interrupt flags are set to "1" depending on the corresponding interrupt factors. The CPU operation is interrupted when any of the conditions below set an interrupt factor flag to "1". * The corresponding mask register is "1" (enabled) * The interrupt flag is "1" (EI) The interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read out. At initial reset, the interrupt factor flags are reset to "0". Note Read the interrupt factor flags only in the DI status (interrupt flag = "0"). A malfunction could result from read-out during the EI status (interrupt flag = "1"). Table 4.14.1 Interrupt factors Interrupt Factor Interrupt Factor Flag (79H D2) Clock timer 2 Hz falling edge TI2 Clock timer 8 Hz falling edge TI8 (79H D1) Clock timer 32 Hz falling edge TI32 (79H D0) Stopwatch counter SWIT1 (7AH D1) SWIT0 (7AH D0) IK0 (7AH D2) IK1 (7AH D3) ISIO (F3H D0) 1 Hz falling edge Stopwatch counter 10 Hz falling edge Input data (K00-K03) Rising or falling edge Input data (K10) Rising or falling edge Serial interface Data (8 bits) input/output has completed S1C62N33 TECHNICAL HARDWARE EPSON I-93 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Specific masks and factor flags for interrupt The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is written to them, and masked (interrupt inhibited) when "0" is written to them. At initial reset, the interrupt mask register is set to "0". Table 4.14.2 shows the correspondence between interrupt mask registers and interrupt factor flags. Note Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). A malfunction could result from writing during the EI status. Table 4.14.2 Interrupt mask registers and interrupt factor flags Interrupt Mask Register Interrupt Factor Flag ETI2 (78H D2) TI2 (79H D2) ETI8 (78H D1) TI8 (79H D1) ETI32 (78H D0) TI32 (79H D0) EISWIT1 (76H D1) SWIT1 (7AH D1) EISWIT0 (76H D0) SWIT0 (7AH D0) EISIO (F2H D0) ISIO (F3H D0) EIK03 (75H D3) EIK02 (75H D2) EIK01 (75H D1) IK0 (7AH D2) EIK00 (75H D0) EIK10 (77H D2) IK1 (7AH D3) * There is an interrupt mask register for each pin of the input ports. I-94 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is terminated, the interrupt processing is executed in the following order. Interrupt vectors The address data (value of program counter) of the program to be executed next is saved in the stack area (RAM). The interrupt request causes the value of the interrupt vector (page 1, 01H-0FH) to be set in the program counter. The program at the specified address is executed (execution of interrupt processing routine by software). Table 4.14.3 shows the correspondence of interrupt requests and interrupt vectors. Note The processing in and above take 12 cycles of the CPU system clock. Table 4.14.3 Interrupt request and PC Value PCS3 1 Stopwatch interrupt Enabled 0 Stopwatch interrupt Masked 1 Timer interrupt Enabled 0 Timer interrupt Masked 1 Input (K00-K03, K10) interrupt Enabled 0 Input (K00-K03, K10) interrupt Masked 1 Serial interface interrupt Enabled 0 Serial interface interrupt Masked interrupt vectors PCS2 PCS1 PCS0 Interrupt Request The four low-order bits of the program counter are indirectly addressed through the interrupt request. S1C62N33 TECHNICAL HARDWARE EPSON I-95 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Tables 4.14.4(a) and (b) show the interrupt control bits and their addresses. Control of interrupt and HALT Table 4.14.4(a) Interrupt control bits (1) Address *7 D3 DFK03 Register D2 D1 DFK02 DFK01 D0 Name DFK00 DFK03 R/W SR *1 0 0 Falling Rising DFK02 0 Falling Rising DFK01 0 Falling Rising DFK00 0 Falling Rising EIK03 0 Enable Mask EIK02 0 Enable Mask EIK01 0 Enable Mask EIK00 0 Enable Mask HVLD 0 Heavy load Normal Heavy load protection mode register SVD evaluation data (at read-out) SVD ON/OFF (at writing) Interrupt mask register (stopwatch 1 Hz) Interrupt mask register (stopwatch 10 Hz) 74H EIK03 EIK02 EIK01 EIK00 R/W 75H HVLD R/W 76H 77H *1 *2 *3 *4 I-96 SCTRG SIOF W R SVDDT SVDON R W EIK10 EISWIT1 EISWIT0 R/W Differential register (K00-K03) Interrupt mask register (K00-K03) SVDDT SVDON 0 0 Low voltage ON Normal OFF EISWIT1 0 Enable Mask EISWIT0 0 Enable Mask K10 SCTRG SIOF - 0 Trigger Run - Stop Serial interface clock trigger SIOF R EIK10 0 Enable Mask Interrupt mask register (K10) DFK10 0 Falling Rising Differential register (K10) K10 *2 High Low R/W DFK10 Comment 1 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON Input port (K10) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.14.4(b) Interrupt control bits (2) Address *7 D3 CSDC Register D2 D1 ETI2 ETI8 D0 Name ETI32 CSDC R/W SR *1 Comment 1 0 0 Static Dynamic ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) - *2 TI2 0 Yes No Interrupt factor flag (clock timer 2 Hz) *4 TI8 0 Yes No Interrupt factor flag (clock timer 8 Hz) *4 TI32 0 Yes No Interrupt factor flag (clock timer 32 Hz) *4 IK1 0 Yes No Interrupt factor flag (K10) *4 IK0 0 Yes No Interrupt factor flag (K00-K03) *4 SWIT1 0 Yes No Interrupt factor flag (stopwatch 1 Hz) *4 SWIT0 0 Yes No Interrupt factor flag (stopwatch 10 Hz) *4 SCS1 1 *6 *6 SCS0 1 *6 *6 SE2 0 Rising Falling Clock edge selection register EISIO 0 Enable Mask Interrupt mask register (serial interface) - *2 Unused *5 - *2 Unused *5 - *2 Unused *5 ISIO 0 LCD drive switch 78H - TI2 TI8 TI32 R Unused *5 79H IK1 IK0 SWIT1 SWIT0 R 7AH SCS1 SCS0 SE2 EISIO R/W Clock edge selection register (SCS0, SCS1) F2H - - - R ISIO F3H *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read S1C62N33 TECHNICAL HARDWARE EPSON Yes No Interrupt factor flag (serial interface) *4 *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary I-97 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) - ETI32, ETI8, ETI2: Interrupt mask registers (78H*D0-D2) - TI32, TI8, TI2: Interrupt factor flags (79H*D0-D2) See "Control of clock timer". - EISWIT0, EISWIT1: Interrupt mask registers (76H*D0, D1) - SWIT0, SWIT1: Interrupt factor flags (7AH*D0, D1) See "Control of stopwatch counter". - EISIO: Interrupt mask register (F2H*D0) - ISIO: Interrupt factor flag (F3H*D0) See "Control of serial interface". - DFK00-DFK03: Differential registers (74H) - EIK00-EIK03: Interrupt mask registers (75H) - IK0: Interrupt factor flag (7AH*D2) See "Control of input ports". - DFK10: Differential register (77H*D1) - EIK10: Interrupt mask register (77H*D2) - IK1: Interrupt factor flag (7AH*D3) See "Control of input ports". I-98 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Programming notes (1) When the interrupt mask register (EIK) is set to "0", the interrupt factor flag (IK) of the input port cannot be set even though the pin status of the input port has changed. (2) The interrupt factor flags of the clock timer and stopwatch counter (TI, SWIT) are set when the timing condition is established, even if the interrupt mask registers (ETI, EISWIT) are set to "0". (3) Read out the interrupt factor flags only in the DI status (interrupt flag = "0"). If read-out is performed in the EI status a malfunction will result. (4) Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause malfunction. S1C62N33 TECHNICAL HARDWARE EPSON I-99 CHAPTER 5: SUMMARY OF NOTES CHAPTER 5 SUMMARY OF NOTES 5.1 Notes for Low Current Consumption The S1C62N33 Series contains control registers for each of the circuits so that current consumption can be lowered. These control registers lower the current consumption through programs that operate the circuits at the minimum levels. The following text explains the circuits that can control operation and their control registers. Refer to these when putting programs together. Table 5.1 Circuits and control registers Circuits (and Items) Control Registers Order of Consumed Current CPU HALT instruction See electrical characteristics (Chapter 7) CPU operation frequency CLKCHG, OSCC See electrical characteristics (Chapter 7) Heavy load protection mode HVLD See electrical characteristics (Chapter 7) SVD circuit HVLD, SVDON Several tens A Analog comparator AMPON Several tens A (SMC62A33) Below are the circuit statuses at initial reset. CPU: Operating status CPU operating frequency: Low speed side (CLKCHG = "0"), OSC3 oscillation circuit stop status (OSCC = "0") Heavy load protection mode: Normal operating mode (HVLD = "0") SVD circuit: OFF status (HVLD = "0", SVDON = "0") Analog comparator: OFF status (AMPON = "0") Also, be careful about panel selection because the current consumption can differ by the order of several A on account of the LCD panel characteristics. I-100 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 5: SUMMARY OF NOTES 5.2 Summary of Notes by Function Here, the cautionary notes are summed up by function category. Keep these notes well in mind when programming. Memory Memory is not mounted in unused area within the memory map and in memory area not indicated in this manual. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. Reset terminal When oscillation is stopped, reset input from the reset terminal triggered by the noise reject circuit cannot be received. When oscillation is stopped, initialization of internal circuits is triggered by the oscillation detection circuit. Watchdog timer When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data (WD0-WD2) cannot be used for timer applications. Oscillation circuit (1) It takes at least 5 ms from the time the OSC3 oscillation circuit starts operating until the oscillation stabilizes. and prescaler Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 ms have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (2) When switching the clock from OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction. Input port (1) When input ports are changed from high to low by pulldown resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time of about 1 ms. S1C62N33 TECHNICAL HARDWARE EPSON I-101 CHAPTER 5: SUMMARY OF NOTES (2) When "noise rejector circuit enable" is selected with the mask option, a maximum delay of 1 ms occurs from the time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. For example, immediately after performing a key scan with the key matrix, the flag will not be reset because the delay in the interrupt factor flag read-out means the flag is set after read-out. (The key scan changes the input status and the interrupt factor flag is set, necessitating read-out to reset the flag.) (3) Input interrupt programing related precautions Port K input Active status Active status Differential register Falling edge interrupt Rising edge interrupt Mask register Fig. 5.2.1 Input interrupt timing Factor flag set Not set Factor flag set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flags are set at and , being the interrupt due to the falling edge and the interrupt due to the rising edge. When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status, the factor flag for input interrupt may be set. Therefore, when using the input interrupt, the active status of the input terminal implies input terminal = low status, when the falling edge interrupt is effected and input terminal = high status, when the rising edge interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of shown in Figure 5.2.1. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. I-102 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 5: SUMMARY OF NOTES Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the timing of shown in Figure 5.2.1. In this case, when the mask registers cleared, then set, you should set the mask register, when the input terminal is in the low status. In addition, when the mask register = "1" and the content of the differential register is rewritten in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite the content of the differential register in the mask register = "0" status. (4) Read-out the interrupt factor flag (IK) only in the DI status (interrupt flag = "0"). Read-out during EI status will cause malfunction. (5) Writing to the interrupt mask registers (EIK) can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause malfunction. (6) When oscillation is stopped, the reset triggered by the noise reject circuit which would normally take place when the input ports are simultaneously switched to HIGH cannot be received. Output port When BZ, BZ and FOUT are selected with the mask option, a hazard may be observed in the output waveform when the data of the output register changes. I/O port (1) When the I/O port is being read out, the in-built pulldown resistance of the I/O port goes ON. Consequently, if data is read out while the CPU is running in the OSC3 oscillation circuit, data must be read out continuously for about 500 s. S1C62N33 TECHNICAL HARDWARE EPSON I-103 CHAPTER 5: SUMMARY OF NOTES (2) When the I/O port is set to the output mode and the data register has been read, the terminal data instead of the register data can be read out. Because of this, if a lowimpedance load is connected and read-out performed, the value of the register and the read-out result may differ. LCD driver (1) When 40H-6FH is selected for the segment data memory, the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the segment data memory by executing initial processing. (2) When C0H-EFH is selected for the segment data memory, that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). Clock timer (1) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Consequently, perform flag read-out (reset the flag) as necessary at reset. (2) The input clock of the watchdog timer is the 2 Hz signal of the clock timer, so that the watchdog timer may be counted up at timer reset. (3) Read-out the interrupt factor flag (TI) only during the DI status (interrupt flag = "0"). Read-out during EI status will cause malfunction. (4) Writing to the interrupt mask registers (ETI) can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause malfunction. Stopwatch counter (1) If counter data is read out in the RUN status, the counter must be made into the STOP status, and after data is read out the RUN status can be restored. If data is read out when a carry occurs, the data cannot be read correctly. Also, the processing above must be performed within the STOP interval of 976 s (256 Hz 1/4 cycle). (2) Read-out of the interrupt factor flag (SWIT) must be done only in the DI status (interrupt flag = "0"). Read-out during EI status will cause malfunction. I-104 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 5: SUMMARY OF NOTES (3) Writing to the interrupt mask registers (EISWIT) can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause malfunction. Event counter To prevent erroneous reading of the event counter data, read out the counter data several times, compare it, and use the matching data as the result. Analog comparator (1) To reduce current consumption, set the analog comparator to OFF when it is not necessary. (2) After setting AMPON to "1", wait at least 3 ms for the operation of the analog comparator to stabilize before reading the output data of the analog cpmparator from AMPDT. Supply voltage detection (1) It takes 100 s from the time the SVD circuit goes ON until a stable result is obtained. For this reason, keep the (SVD) circuit and heavy following software notes in mind: load protection function When the CPU system clock is fosc1 1. When detection is done at HVLD After writing "1" on HVLD, read the SVDDT after 1 instruction has passed. 2. When detection is done at SVDON After writing "1" on SVDON, write "0" after at least 100 s has lapsed (possible with the next instruction) and then read the SVDDT. When the CPU system clock is fosc3 (in case of S1C62A33 only) 1. When detection is done at HVLD After writing "1" on HVLD, read the SVDDT after 0.6 sec has passed. (HVLD holds "1" for at least 0.6 sec) 2. When detection is done at SVDON Before writing "1" on SVDON, write "1" on HVLD first; after at least 100 s has lapsed after writing "1" on SVDON, write "0" on SVDON and then read the SVDDT. S1C62N33 TECHNICAL HARDWARE EPSON I-105 CHAPTER 5: SUMMARY OF NOTES (2) SVDON resides in the same bit at the same address as SVDDT, and one or the other is selected by write or read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth) cannot be used for SVDON control. (3) Select one of the following software processing to return to the normal mode after a heavy load has been driven in the heavy load protection mode. After heavy load drive is completed, return to the normal mode after at least one second has elapsed. After heavy load drive is completed, switch SVD ON and OFF (at least 100 s is necessary for the ON status) and then return to the normal mode. (4) When the SVD is to be turned on during operation in the heavy load protection mode, limit the ON time to 10 ms per second of operation time. Serial interface (1) If the bit data of SE2 changes while SCLK is in the master mode, a hazard will be output to the SCLK pin. If this poses a problem for the system, be sure to set the SCLK to the external clock if the bit data of SE2 is to be changed. (2) Be sure that read-out of the interrupt factor flag (ISIO) is done only when the serial port is in the STOP status (SIOF = "0") and the DI status (interrupt flag = "0"). If read-out is performed while the serial data is in the RUN status (during input or output), the data input or output will be suspended and the initial status resumed. Readout during the EI status (interrupt flag = "1") causes malfunctioning. (3) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fosc1 fosc3) while the serial interface is operating. (4) Perform data writing/reading to data registers SD0-SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). I-106 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 5: SUMMARY OF NOTES (5) As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. (6) Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause malfunction. (7) SCTRG resides in the same bit at the same address as SIOF, and one or the other is selected by write or read operation. When writing a "1" to SCTRG use the OR command, and when writing a "0" use the AND command. No other commands should be used for this purpose. Interrupt and HALT (1) When the interrupt mask register (EIK) is set to "0", the interrupt factor flag (IK) of the input port cannot be set even though the pin status of the input port has changed. (2) The interrupt factor flags of the clock timer and stopwatch counter (TI, SWIT) are set when the timing condition is established, even if the interrupt mask registers (ETI, EISWIT) are set to "0". (3) Read-out the interrupt factor flags only in the DI status (interrupt flag = "0"). If read-out is performed in the EI status a malfunction will result. (4) Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause malfunction. S1C62N33 TECHNICAL HARDWARE EPSON I-107 CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS DIAGRAM OF BASIC EXTERNAL CONNECTIONS CHAPTER 6 S1C62N33 and S1C62L33 I/O O I I/O O * SOUT * SCLK * SIN * SIOF * P00 * P03 * P10 * P13 * K00 * K03 * K10 I S1C 62N33/62L33 * R10(BZ) * R13(BZ) * R11 * AMPP * AMPM * R00 * R03 Note I-108 C1 C2 C3 C4 C5 C GX X'tal * OSC2 * VS1 * OSC3 * OSC4 1.5V (S1C62L33) or 3.0V (S1C62N33) C6 N.C N.C Crystal oscillator Trimmer capacitor + * TEST * VSS CP Piezo LAMP X'tal CGX C1 C2 C3 C4 C5 C6 CP * CC * CB * CA * V L1 * V L2 * V L3 * V DD * OSC1 * RESET * R12(FOUT) O * SEG0 * SEG39 * COM0 * COM3 LCD panel 32,768 Hz, CI (MAX) = 35 k 5-25pF 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 F The above table is simply an example, and is not guaranteed to work. EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS S1C62A33 I/O O I I/O O S1C62A33 * CC * CB * CA * VL1 * VL2 * VL3 * VDD * OSC1 C1 C2 C3 C4 C5 CGX X'tal * OSC2 * VS1 * OSC3 * R10(BZ) * R13(BZ) * R11 * R12(FOUT) O * R00 * R03 * AMPP * AMPM * SOUT * SCLK * SIN * SIOF * P00 * P03 * P10 * P13 * K00 * K03 * K10 I * SEG0 * SEG39 * COM0 * COM3 LCD panel * OSC4 * RESET * TEST * VSS C6 R CR C GC *2 CR *1 CDC 3.0V + CP *1 Ceramic oscillation *2 CR oscillation Note Crystal oscillator Trimmer capacitor Ceramic oscillator Gate capacitance Drain capacitance Resistance for CR oscillation Piezo LAMP X'tal CGX CR CGC CDC RCR C1 C2 C3 C4 C5 C6 CP 32,768 Hz, CI (MAX)=35 k 5-25 pF 500 kHz 100 pF 100 pF 82 k 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 F The above table is simply an example, and is not guaranteed to work. S1C62N33 TECHNICAL HARDWARE EPSON I-109 CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS When the piezoelectric buzzer is driven directly S1C62N33 Series R10 (BZ) R13 (BZ) RA1 RA2 Piezo RA1 RA2 I-110 Protection resistance 100 Protection resistance 100 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 7: ELECTRICAL CHARACTERISTICS CHAPTER 7 ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Rating S1C62N33 and S1C62A33 (VDD = 0 V) Item Code Rated Value Unit VSS -5.0 to 0.5 V Input voltage (1) VI VSS-0.3 to 0.5 V Input voltage (2) VIOSC VS1-0.3 to 0.5 V Permissible total output current IVSS 10 mA Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Soldered temperature, time Tsol 260C, 10 sec (lead section) - PD 250 mW Supply voltage *2 Permitted loss *1 S1C62L33 (VDD = 0 V) Item Supply voltage Input voltage (1) Input voltage (2) Code Rated Value Unit VSS -2.0 to 0.5 V VI VSS-0.3 to 0.5 V VIOSC VS1-0.3 to 0.5 V Permissible total output current IVSS 10 mA Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Soldered temperature, time Tsol 260C, 10 sec (lead section) - PD 250 mW *2 Permitted loss *1 *1 For 100-pin plastic package *2 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is drawn in). S1C62N33 TECHNICAL HARDWARE EPSON I-111 CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.2 Recommended Operating Conditions S1C62N33 (Ta = -20-70C) Item Supply voltage Oscillation frequency Code Condition Min. Typ. Max. Unit VSS VDD = 0V -3.5 -3.0 -1.8 V - 32,768 - Hz Min. Typ. Max. Unit -1.7 -1.5 -1.1 V VDD = 0V software *1 controllable -1.7 -1.5 -0.9 -1.7 -1.5 -1.2 V - 32,768 - Hz fosc1 S1C62L33 (Ta = -20-70C) Item Supply voltage Code VSS Condition VDD = 0V *2 V VDD = 0V When use the analog comparator Oscillation frequency fosc1 S1C62A33 (Ta = -20-70C) Item Supply voltage Code Condition Min. Typ. Max. Unit VSS VDD = 0V -3.5 -3.0 -2.2 V - 32,768 - Hz 50 500 600 kHz Oscillation frequency (1) fosc1 Oscillation frequency (2) fosc3 duty 505% *1 When switching to heavy load protection mode. (See Section 4.12 for details.) Note, however, that the ON time for SVD in the heavy load protection must be limited to 10 ms per second of operation time. *2 The possibility of LCD panel display differs depending on the characteristics of the LCD panel. I-112 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.3 DC Characteristics S1C62N33 and S1C62A33 (VDD=0V, VSS=-3V, fosc1=32,768Hz, Ta=25C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1F) Item Code High-level input voltage (1) VIH1 High-level input voltage (2) VIH2 Low-level input voltage (1) VIL1 Low-level input voltage (2) VIL2 High-level input current (1) IIH1 VIH = 0V Condition K00-03*10 SIN, SCLK P00-03*10-13 Max. Unit 0.2* VSS 0 V 0.1* VSS 0 V RESET, TEST VSS 0.8* VSS V VSS 0.9* VSS V 0 0.5 A 4 16 A 25 100 A 0 A -1.8 mA -0.9 mA K00-03*10 P00-03*10-13 Min. RESET, TEST K00-03*10 SIN, SCLK No pull-down resistance High-level input current (2) IIH2 VIH = 0V High-level input current (3) IIH3 VIH = 0V Low-level input current IIL Typ. P00-03*10-13 AMPP, AMPM K00-03*10 Has pull-down resistance Has pull-down resistance VIL = VSS P00-03*10-13 RESET, TEST K00-03*10, SIN -0.5 P00-03*10-13, SCLK AMPP, AMPM RESET, TEST High-level output current (1) IOH1 VOH1 = 0.1*VSS High-level IOH2 VOH2 = 0.1*VSS output current (2) Low-level IOL1 VOL1 = 0.9*VSS output current (1) Low-level output current (2) Common output current IOL2 VOL2 = 0.9*VSS IOH3 VOH3 = -0.05V IOL3 VOL3 = VL3+0.05V Segment output current IOH4 VOH4 = -0.05V (at LCD output) R13 R00-03*12 SOUT, SIOF P00-03*10-13, SCLK R10 R11 R13 R00-03*12 SOUT, SIOF P00-03*10-13, SCLK COM0-3 mA 3.0 mA -3 A A -3 A A -200 A A 3 3 SEG0-39 IOL5 VOL5 = 0.9*VSS S1C62N33 TECHNICAL HARDWARE 6.0 SEG0-39 IOL4 VOL4 = VL3+0.05V Segment output current IOH5 VOH5 = 0.1*VSS (at DC output) R10 R11 EPSON 200 I-113 CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C62L33 (VDD=0V, VSS=-1.5V, fosc1=32,768Hz, Ta=25C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1F) Item Code High-level input voltage (1) VIH1 High-level input voltage (2) VIH2 Low-level input voltage (1) VIL1 Low-level input voltage (2) VIL2 High-level input current (1) IIH1 VIH = 0V Condition K00-03*10 SIN, SCLK P00-03*10-13 Max. Unit 0.2* VSS 0 V 0.1* VSS 0 V RESET, TEST VSS 0.8* VSS V VSS 0.9* VSS V 0 0.5 A 2 10 A 12 60 A 0 A -300 A -150 A K00-03*10 P00-03*10-13 Min. RESET, TEST K00-03*10 SIN, SCLK No pull-down resistance High-level input current (2) IIH2 VIH = 0V High-level input current (3) IIH3 VIH = 0V Low-level input current IIL Typ. P00-03*10-13 AMPP, AMPM K00-03*10 Has pull-down resistance Has pull-down resistance VIL = VSS P00-03*10-13 RESET, TEST K00-03*10, SIN -0.5 P00-03*10-13, SCLK AMPP, AMPM RESET, TEST High-level output current (1) IOH1 VOH1 = 0.1*VSS High-level IOH2 VOH2 = 0.1*VSS output current (2) Low-level IOL1 VOL1 = 0.9*VSS output current (1) Low-level output current (2) Common output current IOL2 IOH3 IOL3 I-114 SEG0-39 IOL4 VOL4 = VL3+0.05V Segment output current IOH5 VOH5 = 0.1*VSS (at DC output) R13 R00-03*12 SOUT, SIOF P00-03*10-13, SCLK R10 1,400 R11 R13 R00-03*12 VOL2 = 0.9*VSS 700 SOUT, SIOF P00-03*10-13, SCLK VOH3 = -0.05V COM0-3 VOL3 = VL3+0.05V 3 Segment output current IOH4 VOH4 = -0.05V (at LCD output) R10 R11 A A -3 A A -3 A A -100 A A 3 SEG0-39 IOL5 VOL5 = 0.9*VSS EPSON 100 S1C62N33 TECHNICAL HARDWARE CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.4 Analog Circuit Characteristics and Consumed Current S1C62N33 (Always in operating mode) (VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1F) Item Internal voltage Code VL1 Condition Min. Typ. Max. Unit Connects a 1M load resistance -1.15 -1.05 -0.95 V 2*VL1 -0.1 2*VL1 x 0.9 V 3*VL1 -0.1 3*VL1 x 0.9 V -2.25 100 V s VDD-0.9 V 10 mV 3 ms 4.0 10.0 A A between VDD and VL1 (No panel load) VL2 Connects a 1M load resistance between VDD and VL2 (No panel load) VL3 Connects a 1M load resistance between VDD and VL3 (No panel load) SVD voltage SVD circuit response time VSVD TSVD input voltage VIP VIM Analog comparator VOF Analog comparator -2.55 Noninverted input (AMPP) -2.40 VSS+0.3 Inverted input (AMPM) offset voltage Analog comparator TAMP VIP = -1.5V response time Consumed current VIM = VIP15mV IOP During HALT No panel load During operation*1 1.5 6.0 *1 The SVD circuit and analog comparator are in the OFF status. S1C62N33 TECHNICAL HARDWARE EPSON I-115 CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C62N33 (Heavy load protection mode) (VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1F) Item Internal voltage Code VL1 Condition Min. Typ. Max. Unit Connects a 1M load resistance -1.15 -1.05 -0.95 V 2*VL1 -0.1 2*VL1 x 0.9 V 3*VL1 -0.1 3*VL1 x 0.9 V -2.25 100 V s VDD-0.9 V 10 mV 3 ms 34.0 40.0 A A between VDD and VL1 (No panel load) VL2 Connects a 1M load resistance between VDD and VL2 (No panel load) VL3 Connects a 1M load resistance between VDD and VL3 (No panel load) SVD voltage SVD circuit response time VSVD TSVD input voltage VIP VIM Analog comparator VOF Analog comparator -2.55 Noninverted input (AMPP) -2.40 VSS+0.3 Inverted input (AMPM) offset voltage Analog comparator TAMP VIP = -1.5V response time Consumed current VIM = VIP15mV IOP During HALT No panel load *1 During operation 11.2 14.5 *1 The SVD circuit is on status (HVLD = "1", SVDON = "0"). The analog comparator is in the OFF status. I-116 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C62L33 (Always in operating mode) (VDD=0V, VSS=-1.5V, fosc1=32,768Hz, CG=25pF, Ta=25C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1F) Item Internal voltage Code VL1 Condition Min. Typ. Max. Unit Connects a 1M load resistance -1.15 -1.05 -0.95 V 2*VL1 -0.1 2*VL1 x 0.9 V 3*VL1 -0.1 3*VL1 x 0.9 V -1.10 100 V s VDD-0.9 V 20 mV 3 ms 3.0 8.0 A A between VDD and VL1 (No panel load) VL2 Connects a 1M load resistance between VDD and VL2 (No panel load) VL3 Connects a 1M load resistance between VDD and VL3 (No panel load) SVD voltage SVD circuit response time VSVD TSVD input voltage VIP VIM Analog comparator VOF Analog comparator -1.30 Noninverted input (AMPP) -1.20 VSS+0.3 Inverted input (AMPM) offset voltage Analog comparator TAMP VIP = -1.1V response time Consumed current VIM = VIP30mV IOP During HALT During No panel load operation*1 1.0 3.0 *1 The SVD circuit and analog comparator are in the OFF status. S1C62N33 TECHNICAL HARDWARE EPSON I-117 CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C62L33 (Heavy load protection mode) (VDD=0V, VSS=-1.5V, fosc1=32,768Hz, CG=25pF, Ta=25C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1F) Item Internal voltage Code VL1 Condition Min. Typ. Max. Unit Connects a 1M load resistance -1.15 -1.05 -0.95 V between VDD and VL1 (No panel load) VL2 VL3 Connects a 1M load resistance 2*VL1 2*VL1 V between VDD and VL2 (No panel load) -0.1 3*VL1 x 0.85 3*VL1 V x 0.85 -1.10 V 100 VDD-0.9 s V 20 mV 3 ms 2.0 7.0 A 8.0 18.0 A Connects a 1M load resistance between VDD and VL3 (No panel load) SVD voltage VSVD SVD circuit response time TSVD VIP Noninverted input (AMPP) Analog comparator input voltage Analog comparator VIM VOF -0.1 -1.30 -1.20 VSS+0.3 Inverted input (AMPM) offset voltage Analog comparator TAMP VIP = -1.1V response time Consumed current IOP VIM = VIP30mV During HALT *1 During No panel load operation*1 *1 The SVD circuit is on status (HVLD = "1", SVDON = "0"). The analog comparator is in the OFF status. I-118 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C62A33 (Always in operating mode) (VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1F) Item Internal voltage Code VL1 Condition Min. Typ. Max. Unit Connects a 1M load resistance -1.15 -1.05 -0.95 V between VDD and VL1 (No panel load) VL2 VL3 Connects a 1M load resistance 2*VL1 2*VL1 V between VDD and VL2 (No panel load) -0.1 3*VL1 x 0.9 3*VL1 V x 0.9 -2.25 V 100 VDD-0.9 s V 10 mV 3 ms Connects a 1M load resistance between VDD and VL3 (No panel load) SVD voltage VSVD SVD circuit response time TSVD VIP Noninverted input (AMPP) Analog comparator input voltage Analog comparator VIM VOF -0.1 -2.55 -2.40 VSS+0.3 Inverted input (AMPM) offset voltage Analog comparator TAMP VIP = -1.5V response time Consumed current IOP VIM = VIP15mV During HALT *1 No panel load 2.0 5.0 A During operation OSCC = "0" During operation No panel load 8.0 135 15.0 300 A A at 500 kHz*1 *1 The SVD circuit and analog comparator are in the OFF status. S1C62N33 TECHNICAL HARDWARE EPSON I-119 CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C62A33 (Heavy load protection mode) (VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1F) Item Internal voltage Code VL1 Condition Min. Typ. Max. Unit Connects a 1M load resistance -1.15 -1.05 -0.95 V between VDD and VL1 (No panel load) VL2 VL3 Connects a 1M load resistance 2*VL1 2*VL1 V between VDD and VL2 (No panel load) -0.1 3*VL1 x 0.9 3*VL1 V x 0.9 -2.25 V 100 VDD-0.9 s V 10 mV 3 ms Connects a 1M load resistance between VDD and VL3 (No panel load) SVD voltage VSVD SVD circuit response time TSVD VIP Noninverted input (AMPP) Analog comparator input voltage Analog comparator VIM VOF -0.1 -2.55 -2.40 VSS+0.3 Inverted input (AMPM) offset voltage Analog comparator TAMP VIP = -1.5V response time Consumed current IOP VIM = VIP15mV During HALT *1 No panel load 11.5 35.0 A During operation OSCC = "0" During operation No panel load 16.0 130 45.0 330 A A at 500 kHz*1 *1 The SVD circuit is on status (HVLD = "1", SVDON = "0"). The analog comparator is in the OFF status. I-120 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.5 Oscillation Characteristics The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values. S1C62N33 If no special requirement VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C Item Code Oscillation start Vsta voltage (VSS) Oscillation stop Vstp voltage (VSS) Built-in capacitance CD (drain) Frequency/voltage f/V deviation Frequency/IC f/IC deviation Frequency adjustment f/CG range Harmonic oscillation Vhho start voltage (VSS) Permitted leak Rleak resistance S1C62N33 TECHNICAL HARDWARE Condition Tsta 5sec Min. -1.8 Tstp 10sec -1.8 Typ. VSS = -1.8 to -3.5V -10 35 pF 5 ppm 10 ppm 45 ppm -3.5 Between OSC1 and VDD, VSS EPSON 200 Unit V V 18 Including incidental capacitance inside IC CG = 5 to 25pF Max. V M I-121 CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C62L33 If no special requirement VDD=0V, VSS=-1.5V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C *1 Parentheses indicate value for operation in heavy load protection mode. Item Code Oscillation start Vsta voltage (VSS) Oscillation stop Vstp voltage (VSS) Built-in capacitance CD (drain) Frequency/voltage f/V deviation Frequency/IC f/IC deviation Frequency adjustment f/CG range Harmonic oscillation Vhho start voltage (VSS) Permitted leak Rleak resistance Condition Tsta 5sec Tstp 10sec Min. -1.1 Typ. -1.1 (-0.9)*1 VSS = -1.1 to -1.7V (-0.9)*1 -10 35 pF 5 ppm 10 ppm 45 ppm -1.7 Between OSC1 and VDD, VSS 200 Unit V V 18 Including incidental capacitance inside IC CG = 5 to 25pF Max. V M Note, however, that the ON time for SVD must be limited to 10 ms per second of operation time. I-122 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C62A33 OSC1, 2 If no special requirement VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C Item Code Oscillation start Vsta voltage (VSS) Oscillation stop Vstp voltage (VSS) Built-in capacitance CD (drain) Frequency/voltage f/V deviation Frequency/IC f/IC deviation Frequency adjustment f/CG range Harmonic oscillation Vhho start voltage (VSS) Permitted leak Rleak resistance S1C62N33 TECHNICAL HARDWARE Condition Tsta 5sec Min. -2.2 Tstp 10sec -2.2 Typ. VSS = -2.2 to -3.5V -10 35 pF 5 ppm 10 ppm 45 ppm -3.5 Between OSC1 and VDD, VSS EPSON 200 Unit V V 18 Including incidental capacitance inside IC CG = 5 to 25pF Max. V M I-123 CHAPTER 7: ELECTRICAL CHARACTERISTICS OSC3, OSC4 (for CR oscillation circuit) If no special requirement VDD=0V, VSS=-3.0V, RCR=82k, Ta=25C Item Code Condition Min. Typ. Max. 430 kHz 30 Oscillation frequency fosc3 -30 Oscillation start voltage Vsta -2.2 Oscillation start time Tsta Oscillation stop voltage Vstp Unit % V VSS = -2.2 to -3.5V 3 -2.2 ms V OSC3, OSC4 (for ceramic oscillation circuit) If no special requirement VDD=0V, VSS=-3.0V, ceramic oscillation: 500kHz CGC=CDC=100pF, Ta=25C Item I-124 Code Oscillation start voltage Vsta Oscillation start time Tsta Oscillation stop voltage Vstp Condition Min. Typ. Max. -2.2 VSS = -2.2 to -3.5V EPSON V 5 -2.2 Unit ms V S1C62N33 TECHNICAL HARDWARE CHAPTER 8: PACKAGE CHAPTER 8 PACKAGE 8.1 Plastic Package QFP5-100pin (Unit: mm) 25.6 0.4 20.0 0.1 80 51 14.0 0.4 0.1 50 19.6 81 Index 100 31 0.65 0.1 0.30 0.1 30 2.7 0.1 0.15 0.05 1 0~12 1.5 0.3 2.8 S1C62N33 TECHNICAL HARDWARE EPSON I-125 CHAPTER 8: PACKAGE 8.2 Ceramic Package for Test Samples (Unit: mm) 26.8 20.0 51 50 100 31 14.0 81 30 0.4 0.76 0.30 0.95 0.65 0.8 1 20.9 80 Grass Note The ceramic package is fixed in this form regardless selecting of the plastic package form. I-126 EPSON S1C62N33 TECHNICAL HARDWARE CHAPTER 9: PAD LAYOUT CHAPTER 9 PAD LAYOUT 9.1 Diagram of Pad Layout 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 86 21 85 22 84 23 83 24 82 25 81 26 80 27 79 Y 28 78 29 4.77 mm 77 30 76 31 (0, 0) 32 X 75 74 33 73 34 72 35 71 36 70 37 69 38 68 39 67 40 66 41 65 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 DIE No. 4.31 mm Chip thickness: 400m Pad opening: 95m S1C62N33 TECHNICAL HARDWARE EPSON I-127 CHAPTER 9: PAD LAYOUT 9.2 Pad Coordinates (Unit : m) Pad No. Pad Name X Y Pad No. Pad Name X Y 1 AMPP 1,990 2,220 31 VDD -1,990 2 AMPM 1,765 2,220 32 VL3 3 K10 1,560 2,220 33 VL2 4 K03 1,400 2,220 34 5 K02 1,240 2,220 6 K01 1,080 2,220 7 K00 920 8 P03 9 P02 10 Pad No. Pad Name X Y 76 61 SEG15 1,198 -2,220 -1,990 -84 62 SEG16 1,358 -2,220 -1,990 -244 63 SEG17 1,518 -2,220 VL1 -1,990 -404 64 TEST 1,990 -2,005 35 CC -1,990 -564 65 SEG18 1,990 -1,559 36 CB -1,990 -724 66 SEG19 1,990 -1,399 2,220 37 CA -1,990 -884 67 SEG20 1,990 -1,239 630 2,220 38 COM3 -1,990 -1,070 68 SEG21 1,990 -1,079 470 2,220 39 COM2 -1,990 -1,230 69 SEG22 1,990 -919 P01 310 2,220 40 COM1 -1,990 -1,390 70 SEG23 1,990 -759 11 P00 150 2,220 41 COM0 -1,990 -1,590 71 SEG24 1,990 -599 12 P13 -50 2,220 42 SIOF -1,990 -1,750 72 SEG25 1,990 -439 13 P12 -210 2,220 43 SCLK -1,990 -2,010 73 SEG26 1,990 -279 14 P11 -370 2,220 44 SOUT -1,589 -2,220 74 SEG27 1,990 -119 15 P10 -530 2,220 45 SIN -1,428 -2,220 75 SEG28 1,990 41 16 R03 -738 2,220 46 SEG0 -1,202 -2,220 76 SEG29 1,990 201 17 R02 -898 2,220 47 SEG1 -1,042 -2,220 77 SEG30 1,990 361 18 R01 -1,058 2,220 48 SEG2 -882 -2,220 78 SEG31 1,990 521 19 R00 -1,218 2,220 49 SEG3 -722 -2,220 79 SEG32 1,990 681 20 R12 -1,426 2,220 50 SEG4 -562 -2,220 80 SEG33 1,990 841 21 R11 -1,990 1,780 51 SEG5 -402 -2,220 81 SEG34 1,990 1,001 22 R10 -1,990 1,620 52 SEG6 -242 -2,220 82 SEG35 1,990 1,161 23 R13 -1,990 1,460 53 SEG7 -82 -2,220 83 SEG36 1,990 1,377 24 VSS -1,990 1,291 54 SEG8 78 -2,220 84 SEG37 1,990 1,537 25 RESET -1,990 1,036 55 SEG9 238 -2,220 85 SEG38 1,990 1,697 26 OSC4 -1,990 876 56 SEG10 398 -2,220 86 SEG39 1,990 1,857 27 OSC3 -1,990 716 57 SEG11 558 -2,220 28 VS1 -1,990 556 58 SEG12 718 -2,220 29 OSC2 -1,990 396 59 SEG13 878 -2,220 30 OSC1 -1,990 236 60 SEG14 1,038 -2,220 Chip size X : 4.31 (mm) Y : 4.77 (mm) I-128 EPSON S1C62N33 TECHNICAL HARDWARE Software II. S1C62N33 Technical Software CONTENTS CONTENTS CHAPTER 1 BLOCK DIAGRAM .......................................................... II-1 CHAPTER 2 PROGRAM MEMORY ..................................................... II-2 CHAPTER 4 Program Memory Map .................................................... II-2 2.2 Programming Notes ....................................................... II-3 DATA MEMORY .............................................................. II-4 3.1 Data Memory Map .......................................................... II-4 3.2 RAM Map ....................................................................... II-6 3.3 Programming Notes ....................................................... II-6 3.4 I/O Memory Map ............................................................. II-7 INTERRUPT AND HALT .................................................... II-10 4.1 Control of Interrupt and HALT ....................................... II-10 4.2 Generation of Interrupt .................................................. II-13 4.3 Example of Main Routine: Entering HALT and waiting for reactivation by interrupt ......................... II-14 CHAPTER 5 4.4 Interrupt Vector Map ...................................................... II-15 4.5 Example of Interrupt Vector Processing ........................ II-16 4.6 Programming Notes ...................................................... II-19 PERIPHERAL CIRCUITS ................................................... II-20 5.1 Watchdog Timer ............................................................ II-20 Watchdog timer memory map ................................. II-20 Example of reset processing for watchdog timer ..... II-21 Programming note .................................................. II-22 S1C62N33 TECHNICAL SOFTWARE EPSON II-i Software CHAPTER 3 2.1 CONTENTS 5.2 OSC3 ............................................................................. II-23 OSC3 memory map ................................................ II-23 Example of using OSC3 .......................................... II-24 Programming notes ................................................ II-25 5.3 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function ............................ II-26 SVD circuit memory map ....................................... Example of finding supply voltage using SVD circuit Example of using heavy load protection function .... Programming notes ................................................ 5.4 II-26 II-26 II-31 II-36 Output Ports (R00-R03, R10-R13) .............................. II-38 Output port memory map ....................................... II-38 Example of using output ports ............................... II-40 Programming note .................................................. II-46 5.5 LCD Driver ..................................................................... II-47 Segment data memory map .................................... Example of control program for LCD segment output ......................................... LCD driver memory map ........................................ Example of switching LCD drive ............................. Programming notes ................................................ 5.6 II-48 II-55 II-55 II-57 Clock Timer ................................................................... II-58 Clock timer memory map ....................................... Example of using clock timer ................................. Timer interrupt memory map ................................. Clock timer timing chart ........................................ Example of using timer interrupt ............................ Programming notes ................................................ 5.7 II-47 II-58 II-59 II-62 II-63 II-63 II-68 Input Ports (K00-K03, K10) .......................................... II-69 Input port memory map ......................................... II-69 Example of using input ports ................................. II-71 Programming notes ................................................ II-80 5.8 I/O Ports ........................................................................ II-82 I/O port memory map ............................................ II-82 Example of program for I/O ports ........................... II-83 Programming notes ................................................ II-86 II-ii EPSON S1C62N33 TECHNICAL SOFTWARE CONTENTS 5.9 Stopwatch Counter ........................................................ II-87 Stopwatch counter memory map ............................ Example of program for stopwatch counter ............ Stopwatch interrupt memory map .......................... Stopwatch counter timing chart ............................. Example of program for stopwatch interrupt .......... Programming notes ................................................ II-87 II-88 II-90 II-91 II-92 II-96 5.10 Event Counter ............................................................... II-97 Event counter memory map ................................... II-97 Example of program for event counter .................... II-98 Programming note .................................................. II-99 Analog comparator memory map ........................... II-100 Example of program for analog comparator ........... II-100 Programming notes ............................................... II-101 5.12 Serial Interface (SIN, SOUT, SCLK, SIOF) .................. II-102 Serial interface memory map ................................. II-102 Example of program for serial interface ................. II-106 Programming notes ............................................... II-109 CHAPTER 6 INITIAL RESET ................................................................ II-110 6.1 Internal Status at Initial Reset ...................................... II-110 6.2 Example of Initialize Program ....................................... II-111 CHAPTER 7 SUMMARY OF NOTES ................................................... II-113 CHAPTER 8 CPU ............................................................................... II-121 APPENDIX 8.1 S1C62N33 Restrictions ................................................ II-121 8.2 Instruction Set .............................................................. II-121 * Table of cross assembler pseudo-instructions .................. II-127 * Table of ICE commands ................................................... II-128 S1C62N33 TECHNICAL SOFTWARE EPSON II-iii Software 5.11 Analog Comparator ...................................................... II-100 CHAPTER 1: BLOCK DIAGRAM ROM 3,072 words x 12 bits OSC RESET OSC4 OSC3 OSC2 BLOCK DIAGRAM OSC1 CHAPTER 1 System Reset Control Core CPU S1C6200 RAM 256 words x 4 bits COM0~3 SEG0~39 Interrupt Generator LCD Driver Input Port K00~03, K10 TEST VDD I/O Port P00~03, P10~13 Output Port R00~03, R10~13 Comparator AMPP AMPM VL1~3 CA~CC Power Controller VS1 VSS Timer SVD Stop Watch Event Counter Serial Interface SIN SOUT SCLK SIOF Fig. 1 Block diagram S1C62N33 TECHNICAL SOFTWARE EPSON II-1 CHAPTER 2: PROGRAM MEMORY CHAPTER 2 PROGRAM MEMORY The S1C62N33 Series has a mask ROM of 3,072 steps x 12 bits, for storing programs. Address space for program memory is configured of one bank of 12 pages x 256 steps. 2.1 Program Memory Map 00H step 0 page Program start address 01H step 1 page 2 page Interrupt vector area 3 page 4 page 5 page 0FH step 6 page 10H step 7 page 8 page 9 page 10 page 11 page FFH step Fig. 2.1 Program memory map 12 bits After initial reset, the program start address is page 1, step 00H; interrupt vectors can be allocated to page 1, steps 01H-0FH. II-2 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 2: PROGRAM MEMORY 2.2 Programming Notes (1) To use a branch instruction such as "JP" to branch outside the page of that instruction, the page to branch to must first be set with the "PSET" instruction; then the branch instruction can be executed. Be sure to execute the branch instruction as the step immediately following "PSET". (2) Immediately after the "PSET" instruction mentioned in above item (1), it will automatically be DI state until execution of the branch instruction is completed. (3) When moving from the last step of one page to the top step of the next page, there is no need to execute branch instructions such as "PSET" and "JP". (4) With just the one instruction "CALZ", subroutines on page 0 can be called from any page without using "PSET". Programming can be done efficiently if universal subroutines are located on page 0. (5) If the "PSET" instruction is executed immediately before "CALZ", "CALZ" will have priority and data set with "PSET" will be ignored. (6) The program memory can be used as a data table through the table look-up instruction. For details of the instructions, refer to "S1C6200/6200A Core CPU Manual". S1C62N33 TECHNICAL SOFTWARE EPSON II-3 CHAPTER 3: DATA MEMORY CHAPTER 3 DATA MEMORY The S1C62N33 Series has a general-purpose RAM (256 words x 4 bits ), I/O memory for controlling the internal peripheral circuits (64 words x 4 bits), and the optionally selectable segment memory (48 words x 4 bits). All these are allocated to the data memory addresses on page 0 and page 1. 3.1 Data Memory Map Data memory of the S1C62N33 Series has an address space of 360 words, of which 48 words are allocated to display memory and 64 words to I/O data memory. Figure 3.1 present the overall memory maps of the S1C62N33 Series, and Tables 3.4 (a)-(c) the peripheral circuits' (I/O space) memory maps. The I/O data memory in all units of the S1C62N33 Series is configured in the same manner at 070H-07FH, 170H-17FH and 0F0H-0FFH, 1F0H-1FFH. This makes it possible to access I/O data memory without switching data memory pages. II-4 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 3: DATA MEMORY Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D E F High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 3 RAM (112 words x 4 bits) R/W 4 5 6 0 7 I/O data memory Tables 3.4(a), (b) 8 RAM (32 words x 4 bits) R/W 9 A B Unused area C D E F I/O data memory Table 3.4(c) 0 1 2 3 RAM (112 words x 4 bits) R/W 4 5 6 1 7 I/O data memory Tables 3.4(a), (b) 8 9 A Unused area B C Fig. 3.1 Data memory map D E I/O data memory Table 3.4(c) F Note (1) The I/O data memory registers of 070H-07FH, 170H-17FH and 0F0H-0FFH, 1F0H-1FFH are each linked. For instance, by switching the I/O data memory at 074H, data memory at 174H can by switched simultaneously. See Tables 3.4(a)-(c) for details of I/O data memory. (2) The mask option can be used to select whether to assign the overall area of segment data memory to 040H-06FH or 0C0H- 0EFH. When 040H-06FH is selected, read/write is enabled. When 0C0H-0EFH is selected, write only is enabled. If 040H-06FH is assigned, RAM is used as the segment area (48 words). (3) Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. S1C62N33 TECHNICAL SOFTWARE EPSON II-5 CHAPTER 3: DATA MEMORY 3.2 RAM Map Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D E F High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 0 3 4 5 6 0 1 Fig. 3.2 RAM map 8 9 0 1 2 3 4 5 6 Addresses 000H-00FH are the memory register area that can be addressed with the register pointer (RP). Note Addresses 040H-06FH can be allocated to segment memory by option selection. With this selection, 48 words of RAM can be used as segment area. 3.3 Programming Notes (1) Part of the data memory is used as stack area for subroutine calls and register storage, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words of the stack area. (3) When addresses 040H-06FH have been allocated as segment memory by option selection, 48 words of RAM can be used as segment area. II-6 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 3: DATA MEMORY 3.4 I/O Memory Map Table 3.4(a) I/O data memory map (70H-77H) Address *7 D3 TM3 70H SWL3 71H SWH3 72H K03 73H DFK03 74H EIK03 75H HVLD 76H R/W SCTRG 77H SIOF W R *1 *2 *3 *4 Register D2 D1 D0 Name TM3 TM2 TM1 TM0 TM2 TM1 R TM0 SWL3 SWL0 SWL2 SWL1 SWL2 SWL1 R SWL0 SWH3 SWH0 SWH2 SWH1 SWH2 SWH1 R SWH0 K03 K00 K02 K01 K02 K01 R K00 DFK03 DFK00 DFK02 DFK01 DFK02 DFK01 R/W DFK00 EIK03 EIK02 EIK01 EIK00 EIK02 EIK01 R/W EIK00 HVLD SVDDT EISWIT1 EISWIT0 SVDDT SVDON SVDON R EISWIT1 R/W W EISWIT0 SCTRG EIK10 DFK10 K10 SIOF EIK10 DFK10 R R/W K10 Init *1 0 0 0 0 0 0 0 0 0 0 0 0 *2 *2 *2 *2 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 *2 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read S1C62N33 TECHNICAL SOFTWARE EPSON 1 Comment 0 Timer data (clock timer 2 Hz) Timer data (clock timer 4 Hz) Timer data (clock timer 8 Hz) Timer data (clock timer 16 Hz) MSB Stopwatch counter 1/100 sec (BCD) LSB MSB Stopwatch counter 1/10 sec (BCD) LSB High High High High Falling Falling Falling Falling Enable Enable Enable Enable Low Low Low Low Rising Rising Rising Rising Mask Mask Mask Mask Heavy load Normal Low voltage Normal On Off Enable Mask Enable Mask Trigger - Run Stop Enable Mask Falling Rising High Low Input port (K00-K03) Differential register (K00-K03) Interrupt mask register (K00-K03) Heavy load protection mode register SVD evaluation data (at read-out) SVD ON/OFF (at writing) Interrupt mask register (stopwatch 1 Hz) Interrupt mask register (stopwatch 10 Hz) Serial interface clock trigger SIOF Interrupt mask register (K10) Differential register (K10) Input port (K10) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary II-7 CHAPTER 3: DATA MEMORY Table 3.4(b) I/O data memory map (78H-7FH) Address *7 D3 CSDC Register D2 D1 D0 ETI8 ETI32 TI8 TI32 SWIT1 SWIT0 R01 R00 R11 R10 P01 P00 ETI2 78H R/W - TI2 79H R IK1 IK0 7AH R R03 R02 7BH R/W R13 R12 7CH R/W P03 P02 7DH R/W TMRST SWRUN SWRST IOC0 W R/W W R/W WDRST WD2 WD1 WD0 7EH 7FH W II-8 R Name CSDC ETI2 ETI8 ETI32 - TI2 TI8 TI32 IK1 IK0 SWIT1 SWIT0 R03 R02 R01 R00 R13 R12 R11 R10 P03 P02 P01 P00 TMRST SWRUN SWRST IOC0 WDRST WD2 WD1 WD0 Init *1 0 0 0 0 *2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *2 *2 *2 *2 Reset 0 Reset 0 Reset 0 0 0 EPSON 1 Static Enable Enable Enable 0 Dynamic Mask Mask Mask Yes Yes Yes Yes Yes Yes Yes High High High High High High High High High High High High Reset Run Reset Output Reset No No No No No No No Low Low Low Low Low Low Low Low Low Low Low Low - Stop - Input - Comment LCD drive switch Interrupt mask register (clock timer 2 Hz) Interrupt mask register (clock timer 8 Hz) Interrupt mask register (clock timer 32 Hz) Unused *5 Interrupt factor flag (clock timer 2 Hz) *4 Interrupt factor flag (clock timer 8 Hz) *4 Interrupt factor flag (clock timer 32 Hz) *4 Interrupt factor flag (K10) *4 Interrupt factor flag (K00-K03) *4 Interrupt factor flag (stopwatch 1 Hz) *4 Interrupt factor flag (stopwatch 10 Hz) *4 Output port (R00-R03) Output port (R13, BZ) *6 Output port (R12, FOUT) *6 Output port (R11) Output port (R10, BZ) *6 I/O port (P00-P03) Output latch reset at time of initial reset Clock timer reset *5 Stopwatch counter RUN/STOP Stopwatch counter reset *5 I/O control register 0 (P00-P03) Watchdog timer reset *5 Timer data (watchdog timer 1/4 Hz) Timer data (watchdog timer 1/2 Hz) Timer data (watchdog timer 1 Hz) S1C62N33 TECHNICAL SOFTWARE CHAPTER 3: DATA MEMORY Table 3.4(c) I/O data memory map (F0H-F3H, F6H-F9H, FCH-FEH) D3 Register D2 D1 SD3 SD2 Address *7 SD1 F0H R/W SD7 SD6 SD5 F1H R/W SCS1 SCS0 SE2 F2H R/W - - - F3H R BZFQ - - F6H R/W - R - AMPDT F7H R EV03 EV02 EV01 F8H R EV07 EV06 EV05 F9H R - EVRUN - R R/W R P13 P12 P11 FCH FDH R/W - CLKCHG OSCC FEH R S1C62N33 TECHNICAL SOFTWARE R/W D0 Name SD3 SD0 SD2 SD1 SD0 SD7 SD4 SD6 SD5 SD4 SCS1 EISIO SCS0 SE2 EISIO - ISIO - - ISIO BZFQ - - - - - AMPON - AMPDT R/W AMPON EV03 EV00 EV02 EV01 EV00 EV07 EV04 EV06 EV05 EV04 - EVRST EVRUN - W EVRST P13 P10 P12 P11 P10 - IOC1 CLKCHG OSCC IOC1 Init *1 1 *3 *3 *3 *3 *3 *3 *3 *3 *6 1 *6 1 Rising 0 Enable 0 *2 *2 *2 Yes 0 2 kHz 0 *2 *2 *2 *2 *2 +>1 On 0 0 0 0 0 0 0 0 0 *2 Run 0 *2 Reset Reset High *2 High *2 High *2 High *2 *2 OSC3 0 On 0 Output 0 EPSON 0 Comment Serial interface data register Low order (SD0-SD3) Serial interface data register High order (SD4-SD7) *6 *6 Falling Mask No 4 kHz ->+ Off Clock edge selection register (SCS0, SCS1) Clock edge selection register Interrupt mask register (serial interface) Unused *5 Unused *5 Unused *5 Interrupt factor flag (serial interface) *4 Buzzer frequency selection register Unused *5 Unused *5 Unused *5 Unused *5 Unused *5 Analog comparator data Analog comparator ON/OFF Event counter Low order (EV00-EV03) Event counter High order (EV04-EV07) Stop - Low Low Low Low OSC1 Off Input Unused *5 Event counter RUN/STOP Unused *5 Event counter reset *5 I/O port (P10-P13) Output latch reset at time of initial reset Unused *5 CPU clock switch OSC3 oscillator ON/OFF I/O control register 1 (P10-P13) II-9 CHAPTER 4: INTERRUPT AND HALT CHAPTER 4 INTERRUPT AND HALT The S1C62N33 Series provides the following interrupt settings, each of which is maskable. External interrupts: Internal interrupts: Input interrupts (two) Timer interrupt (three) Stopwatch interrupt (two) Serial interface interrupt (one) When a HALT instruction is input the CPU operating clock stops, and the CPU enters the HALT status. The CPU is reactivated from the HALT status when an interrupt request occurs. II-10 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 4: INTERRUPT AND HALT 4.1 Control of Interrupt and HALT Table 4.1(a) I/O data memory map (interrupt 1) Address *7 D3 DFK03 Register D2 D1 D0 Name DFK00 DFK03 SR *1 0 0 Falling Rising DFK02 0 Falling Rising DFK01 0 Falling Rising DFK00 0 Falling Rising EIK03 0 Enable Mask EIK02 0 Enable Mask EIK01 0 Enable Mask EIK00 0 Enable Mask EISWIT1 EISWIT0 HVLD 0 Heavy load Normal Heavy load protection mode register R/W SVDDT SVDON 0 0 Low voltage ON Normal OFF EISWIT1 0 Enable Mask EISWIT0 0 Enable Mask SVD evaluation data (at read-out) SVD ON/OFF (at writing) Interrupt mask register (stopwatch 1 Hz) Interrupt mask register (stopwatch 10 Hz) K10 SCTRG SIOF - 0 Trigger Run - Stop Serial interface clock trigger SIOF R EIK10 0 Enable Mask Interrupt mask register (K10) DFK10 0 Falling Rising Differential register (K10) K10 *2 High Low DFK02 DFK01 R/W 74H EIK03 EIK02 EIK01 EIK00 R/W 75H HVLD R/W 76H 77H *1 *2 *3 *4 SCTRG SIOF W R SVDDT SVDON R W Comment 1 EIK10 DFK10 R/W Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read S1C62N33 TECHNICAL SOFTWARE EPSON Differential register (K00-K03) Interrupt mask register (K00-K03) Input port (K10) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary II-11 CHAPTER 4: INTERRUPT AND HALT Table 4.1(b) I/O data memory map (interrupt 2) Address *7 D3 CSDC Register D2 D1 ETI2 ETI8 D0 Name ETI32 CSDC R/W SR *1 Comment 1 0 0 Static Dynamic ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) - *2 TI2 0 Yes No Interrupt factor flag (clock timer 2 Hz) *4 TI8 0 Yes No Interrupt factor flag (clock timer 8 Hz) *4 TI32 0 Yes No Interrupt factor flag (clock timer 32 Hz) *4 IK1 0 Yes No Interrupt factor flag (K10) *4 IK0 0 Yes No Interrupt factor flag (K00-K03) *4 SWIT1 0 Yes No Interrupt factor flag (stopwatch 1 Hz) *4 SWIT0 0 Yes No Interrupt factor flag (stopwatch 10 Hz) *4 SCS1 1 *6 *6 SCS0 1 *6 *6 SE2 0 Rising Falling Clock edge selection register EISIO 0 Enable Mask Interrupt mask register (serial interface) - *2 Unused *5 - *2 Unused *5 - *2 Unused *5 ISIO 0 LCD drive switch 78H - TI2 TI8 TI32 R Unused *5 79H IK1 IK0 SWIT1 SWIT0 R 7AH SCS1 SCS0 SE2 EISIO R/W Clock edge selection register (SCS0, SCS1) F2H - - - R ISIO F3H *1 *2 *3 *4 II-12 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON Yes No Interrupt factor flag (serial interface) *4 *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL SOFTWARE CHAPTER 4: INTERRUPT AND HALT 4.2 Generation of Interrupt Table 4.2 Interrupt factors Interrupt Factor Clock timer 2 Hz falling edge T2Hz Clock timer 8 Hz falling edge T8Hz Clock timer 32 Hz falling edge T32Hz Stopwatch counter SWT1Hz 1 Hz falling edge Stopwatch counter SWT10Hz 10 Hz falling edge Serial interface SIO Data (8 bits) input/output has completed Input data (K00-K03) K0 Change from match to mismatch of differential register data and port register data Input data (K10) K1 Rising or falling edge Interrupt Mask Register Interrupt Factor Flag ETI2 (78H*D2) ETI8 (78H*D1) ETI32 (78H*D0) EISWIT1 (76H*D1) TI2 TI8 TI32 SWIT1 (79H*D2) (79H*D1) (79H*D0) (7AH*D1) EISWIT0 (76H*D0) SWIT0 (7AH*D0) EISIO (F2H*D0) ISIO (F3H*D0) EIK03 EIK02 EIK01 (75H*D3) (75H*D2) (75H*D1) IK0 (7AH*D2) EIK00 EIK10 (75H*D0) (77H*D2) IK1 (7AH*D3) The CPU operation is interrupted when any of the conditions below sets an interrupt factor flag to "1". * The corresponding interrupt mask register is "1" (enabled) * The interrupt flag is "1" (EI) The interrupt flag is set to "1" depending on the corresponding interrupt factor. The interrupt factor flag is a read-only register, and is reset to "0" when the register data is read out. Note - Write to the interrupt mask registers only in the DI status (interrupt flag = "0"). An error could result from writing during the EI status. - Even when the interrupt mask registers (ETI, EISWIT) are set to "0", the interrupt factor flags (TI, SWIT) of the clock timer and stopwatch counter can be set when the timing conditions are established. - Read the interrupt factor flags only in the DI status (interrupt flag = "0"). An error could result from reading out during the EI status. S1C62N33 TECHNICAL SOFTWARE EPSON II-13 CHAPTER 4: INTERRUPT AND HALT 4.3 Example of Main Routine: Entering HALT and waiting for reactivation by interrupt Specifications This main routine enables K00-K03 input interrupt and 2 Hz timer interrupt, after which it enters the HALT status to wait for reactivation by interrupts. At every loop, the EI instruction enables an interrupt after execution of the display routine "DS" (of the watch or whatever the application happens to be). Program ; MAINLP: LD LD LD LD X,75H MX,1111B X,78H MX,0100B ; Enable K00-K03 input interrupt ; ; Enable 2 Hz timer interrupt ; CALL EI HALT JP DS ; Execute display processing "DS" ; Enable interrupts ; Enter HALT ; Interrupts' return address: Back to "MAINLP" MAINLP This routine assumes that "DS" has been prepared separately. Notes 1. This program example is one to follow the initialize program. Even without executing the DI instruction, writing to interrupt mask registers is done in the DI status. 2. When an interrupt is generated, the DI status (interrupt flag = "0") comes into effect automatically, so the EI instruction is necessary for each loop. II-14 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 4: INTERRUPT AND HALT 4.4 Interrupt Vector Map Table 4.4 Interrupt vector map Page 1 Step Interrupt Vector 00H Initial reset 01H Generation of Serial interface interrupt (ISIO) 02H Generation of input port interrupt (INTK0 or INTK1) 03H 04H Generation of ISIO and (INTK0 or INTK1) Generation of timer interrupt (TINT) 05H Generation of ISIO and TINT 06H 07H Generation of (INTK0 or INTK1) and TINT Generation of ISIO, (INTK0 or INTK1) and TINT 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Generation of stopwatch interrupt (SWINTT) Generation of ISIO and SWINTT Generation of (INTK0 or INTK1) and SWINTT Generation of ISIO, (INTK0 or INTK1) and SWINTT Generation of TINT and SWINTT Generation of ISIO, TINT and SWINTT Generation of (INTK0 or INTK1), TINT and SWINTT Generation of all interrupts Addresses (start addresses of interrupt processing routines) to jump to are written into the addresses available for interrupt vector allocation. S1C62N33 TECHNICAL SOFTWARE EPSON II-15 CHAPTER 4: INTERRUPT AND HALT 4.5 Example of Interrupt Vector Processing Specifications When interrupts having different vectors occur simultaneously, they are processed in the specified order of priority. Because of this, it is convenient to process all interrupts with the one interrupt routine "IN". Interrupt vectors ORG 101H ; Vector leading address JP JP JP JP JP JP JP JP JP JP JP JP JP JP JP IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN ; Generation of Serial interface interrupt (ISIO) ; Generation of input port interrupt (INTK0 or INTK1) ; Generation of ISIO and (INTK0 or INTK1) ; Generation of timer interrupt (TINT) ; Generation of ISIO and TINT ; Generation of (INTK0 or INTK1) and TINT ; Generation of ISIO, (INTK0 or INTK1) and TINT ; Generation of stopwatch interrupt (SWINTT) ; Generation of ISIO and SWINTT ; Generation of (INTK0 or INTK1) and SWINTT ; Generation of ISIO, (INTK0 or INTK1) and SWINTT ; Generation of TINT and SWINTT ; Generation of ISIO, TINT and SWINTT ; Generation of (INTK0 or INTK1), TINT and SWINTT ; Generation of all interrupts ; Interrupt routine Table 4.5 Order of interrupt priority in program example II-16 Table 4.5 lists the order of priority for processing interrupts. Values of registers X, Y, A, B and F are retained in stack. Priority 1 2 3 4 5 6 7 8 EPSON Interrupt Factor Stopwatch 10 Hz Stopwatch 1 Hz Serial interface K00-K03 input ports K10 input port Clock timer 32 Hz Clock timer 8 Hz Clock timer 2 Hz S1C62N33 TECHNICAL SOFTWARE CHAPTER 4: INTERRUPT AND HALT YIKSTB EQU H YTIB ; ; IN: EQU H ; Buffer address for factor flags of input interrupts ; and stopwatch interrupts ; Buffer address for timer interrupt factor flags PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH XH XL XP YH YL YP A B F ; Store the value of X register to stack ; ; ; Store the value of Y register to stack ; ; ; Store the value of A register to stack ; Store the value of B register to stack ; Store the value of F register to stack LD LD LD LD LD OR AND X,7AH Y,YIKSTB MY,MX X,76H A,MX A,1100B MY,A ; Reset and store ; input interrupt and stopwatch interrupt factor flags ; in the buffer ; Mask the stopwatch interrupt factor flags ; ; ; by the value of the stopwatch interrupt mask register FAN JP CALL MY,0001B Z,INSIT1 STI0 ; If the ST10Hz interrupt factor flag is set ; and enabled ; then execute ST10Hz interrupt processing "SIT0" LD FAN JP CALL Y,YIKSTB MY,0010B Z,INSIO SIT1 ; If the ST1Hz interrupt factor flag is set ; and enabled ; ; then execute ST1Hz interrupt processing "SIT1" LD LD FAN JP CALL Y,0F3H A,MX A,0001B Z,INK0 ISIO ; Reset and store ; serial interface interrupt factor flag in the A register ; If the serial interface interrupt factor flag is set ; ; then execute serial interface interrupt processing "ISIO" LD FAN JP CALL Y,YIKSTB MY,0100B Z,INK1 IK0 ; If the K0 interrupt factor flag is set ; ; ; then execute K0 interrupt processing "IK0" ; ; ; INSIT1: ; INSIO: ; INK0: S1C62N33 TECHNICAL SOFTWARE EPSON II-17 CHAPTER 4: INTERRUPT AND HALT ; INK1: ; INTI: LD FAN JP CALL Y,YIKSTB MY,1000B Z,INTI IK1 ; If the K1 interrupt factor flag is set ; ; ; then execute K1 interrupt processing "IK1" LD LD LD LD AND X,79H Y,YETI MY,MX X,78H MY,MX ; Reset and store ; the timer interrupt factor flags ; in the buffer ; Mask the timer interrupt factor flag ; by the value of the timer interrupt mask register FAN JP CALL MY,0001B Z,INTI8 TI32 ; If the T32Hz interrupt factor flag is set ; and enabled ; then execute T32Hz interrupt processing "TI32" LD FAN JP CALL Y,YTIB MY,0010B Z,INTI2 TI8 ; If the T8Hz interrupt factor flag is set ; and enabled ; ; then execute T8Hz interrupt processing "TI8" LD FAN JP CALL Y,YTIB MY,0100B Z,INRT TI2 ; If the TI2Hz interrupt factor flag is set ; and enabled ; ; then execute T2Hz interrupt processing "TI2" POP POP POP POP POP POP POP POP POP RET F B A YP YL YH XP XL XH ; Return the value of F register from stack ; Return the value of B register from stack ; Return the value of A register from stack ; Return the value of Y register from stack ; ; ; Return the value of X register from stack ; ; ; Return to parent routine ; ; INTI8: ; INTI2: ; INRT: Addresses of buffers IKSTB and TIB can be set anywhere in RAM. This routine assumes that processing routines "SIT0", "SIT1", "ISIO", "IK0", "IK1", "TI32", "TI8" and "TI2" have been prepared separately for each of the interrupts. II-18 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 4: INTERRUPT AND HALT 4.6 Programming Notes (1) Write to the interrupt mask registers only in the DI status (interrupt flag = "0"). Writing in the EI status can cause an error. (2) Even when the interrupt mask registers (ETI, EISWIT) are set to "0", the interrupt factor flags (TI, SWIT) of the clock timer and stopwatch counter can be set when the timing conditions are established. (3) When an interrupt is generated, three words of RAM are used; also, it takes 12 cycles of the CPU system clock until the value of the interrupt vector is set in the program counter. (4) When an interrupt occurs, the DI status (interrupt flag = "0") comes into effect automatically. (5) Read the interrupt factor flags only in the DI status (interrupt flag = "0"). Reading out in the EI status can cause an error. S1C62N33 TECHNICAL SOFTWARE EPSON II-19 CHAPTER 5: PERIPHERAL CIRCUITS (Watchdog Timer) CHAPTER 5 PERIPHERAL CIRCUITS Peripheral circuits of the S1C62N33 Series, such as the timer and I/O, are interfaced with the CPU by memory mapped I/O format. This means that all peripheral circuits can be controlled by accessing the memory map's I/O memory or segment memory with memory operation instructions. This chapter details how to control the peripheral circuits. 5.1 Watchdog Timer The S1C62N33 Series incorporates a watchdog timer. If the watchdog timer reset is not executed by the software in at least 3-4 seconds, the initial reset signal is output automatically for the CPU. You can select whether or not to use the watchdog timer with the mask option. When "Not use" is chosen, there is no need to reset the watchdog timer. Watchdog timer memory map Table 5.1 I/O data memory map (watchdog timer) Address *7 D3 WDRST W Register D2 D1 WD2 WD1 R Comment D0 Name SR *1 WD0 WDRST Reset WD2 0 Timer data (watchdog timer 1/4 Hz) WD1 0 Timer data (watchdog timer 1/2 Hz) WD0 0 Timer data (watchdog timer 1 Hz) 1 0 Reset - Watchdog timer reset *5 7FH *1 *2 *3 *4 II-20 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (WATCHDOG TIMER) WDRST: This is the bit for resetting the watchdog timer. Watchdog timer reset When "1" is written: Watchdog timer is reset. (7FH.D3) When "0" is written: No operation Read-out: Always "0" When the watchdog timer is used for the reset function, the software must reset the watchdog timer within 3 seconds. Operation restarts immediately after the watchdog timer is reset. Ordinarily, this routine is incorporated where periodic processing takes place, such as in the timer interrupt rou- Example of reset processing for watchdog timer tine, to detect program overrun, for instance when the watchdog timer processing is bypassed. Note In this case, timer data (WD0-WD2) cannot be used for timer applications. The watchdog timer operates in the halt mode. If the halt status continues for 3-4 seconds, the initial reset signal restarts operation. Specifications When the timing flag ("0.5 sec flag") is set in the T2Hz interrupt processing routine "TI2", the watchdog timer will be reset every second. When the routine "basic timer 'CK'" for the timer is executed every second on the second, the watchdog timer will be reset every second on the half-second. n sec n.5 sec (n+1) sec (n+1).5 sec Time "CK" is executed Fig. 5.1 Timing chart S1C62N33 TECHNICAL SOFTWARE "CK" is executed Watchdog timer is reset EPSON Watchdog timer is reset II-21 CHAPTER 5: PERIPHERAL CIRCUITS (Watchdog Timer) Program XTISF YFTM ; ; TI2: EQU EQU 0001B H ; 0.5 sec flag (TISF) ; Address for timing flag set LD FAN JP X,YFTM MX,XTISF NZ,TI21 ; TISF = "0" or "1"? ; ; OR LD LD RET AND CALL MX,XTISF X,7FH MX,0001B ; TISF = "0": Set the TIS flag ; Reset the watchdog timer ; ; Returns to parent routine ; TISF = "1": Reset the TIS flag ; Execute the basic timer "CK" ; TI21: MX,XTISF XOR 0FH CK ; RET ; Returns to parent routine The address for the timing flag set FTM can be set anywhere in RAM. Further, this routine assumes that a timer subroutine has been prepared separately to make 1 second the unit for the routine "basic timer 'CK'". (See page 63, "Example of using timer interrupt" for how to make "basic timer 'CK'".) Programming note II-22 When the watchdog timer is used for the reset function, the software must reset the watchdog timer within 3 seconds. In this case, timer data (WD0-WD2) cannot be used for timer applications. EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (OSC3) 5.2 OSC3 S1C62A33 has two built-in oscillation circuits (OSC1 and OSC3). When processing of S1C63A33 requires high-speed operations, the CPU's operating clock should be switched from OSC1 to OSC3. OSC3 memory map Table 5.2 I/O data memory map (OSC3) Address *7 D3 - Register D2 D1 CLKCHG R OSCC R/W SR *1 1 Comment 0 D0 Name IOC1 - *2 CLKCHG 0 OSC3 OSC1 CPU clock switch *6 OSCC 0 ON OFF OSC3 oscillator ON/OFF IOC1 0 Output Input I/O control register 1 (P10-P13) Unused *5 FEH *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary CLKCHG: The CPU's operation clock is selected with this register The CPU's clock switch (S1C62N33 only). (FEH.D2) When "1" is written: OSC3 is selected When "0" is written: OSC1 is selected Read-out: Available This register cannot be controlled for S1C62N33/62L33, so that OSC1 is selected regardless of the set value. S1C62N33 TECHNICAL SOFTWARE EPSON II-23 CHAPTER 5: PERIPHERAL CIRCUITS (OSC3) Example of using OSC3 Note To lessen current consumption, keep OSC3 oscillation OFF except when the CPU must be run at high speed. Also, with S1C62N33/ 62L33, keep OSCC fixed to "0". (1) Switching from OSC1 to OSC3 Specifications This subroutine first sets OSC3 to ON, and then, after about 5 ms, switches the CPU clock to OSC3. Program OS3: LD OR X,0FEH MX,0010B ; Set OSC3 to ON A,0EH A,0FH NZ,OS3DLLP ; Delay of 5.28 ms: preparation Loop for delay ; ; MX,0100B ; Switche the CPU clock to OSC3 ; Return to parent routine ; LD OS3DLLP: ADD JP ; OR RET Note II-24 A 5.28 ms delay is specified before switching to OSC3, to allow time for the oscillation circuit to stabilize. EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (OSC3) (2) Switching from OSC3 to OSC1 This subroutine switches the CPU clock to OSC1, and then sets OSC3 to OFF. Specifications Program OS1: LD AND X,0FEH MX,1011B ; Switche the CPU clock to OSC1 ; AND RET MX,1101B ; Set OSC3 to OFF ; Return to parent routine ; Note Programming notes To prevent an error, first switch OSC1, and then set OSC3 to OFF in the next step. (1) It takes at least 5 ms from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 ms have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (2) When switching the clock from OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. (3) To lessen current consumption, keep OSC3 oscillation OFF except when the CPU must be run at high speed. Also, with S1C62N33/62L33, keep OSCC fixed to "0". S1C62N33 TECHNICAL SOFTWARE EPSON II-25 CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) 5.3 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function The S1C62N33 Series has a built-in supply voltage detection (SVD) circuit, so that the software can find when the source voltage lowers. S1C62L33 has a heavy load protection function for when the battery load becomes heavy and the source voltage drops. *1 Initial value following initial reset *5 Always SVD circuit memory map Table 5.3 I/O data memory map (SVD circuit and heavy load protection function) Address *7 D3 HVLD R/W 76H "0" *2 *3 *4 Register D2 D1 SVDDT SVDON R W D0 Name SR *1 0 Heavy load Normal Heavy load protection mode register SVD evaluation data (at read-out) SVD ON/OFF (at writing) Interrupt mask register (stopwatch 1 Hz) Interrupt mask register (stopwatch 10 Hz) EISWIT1 EISWIT0 HVLD 0 R/W SVDDT SVDON 0 0 Low voltage ON Normal OFF EISWIT1 0 Enable Mask EISWIT0 0 Enable Mask when being read Not set in the circuit Undefined Reset (0) immediately after being read Comment 1 *6 Refer to main manual *7 Page switching in I/O memory is not necessary To obtain the SVD detection result, follow the programming Example of finding sequence below. supply voltage using 0. Set HVLD to "1" (only when the CPU system clock is SVD circuit fosc3 in S1C62A33) 1. 2. 3. 4. 5. II-26 Set SVDON to "1" Maintain at 100 s minimum Set SVDON to "0" Read out SVDDT Set HVLD to "0" (only when the CPU system clock is fosc3 in S1C62A33) EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) When HVLD is set to "1" or low voltage is detected by the SVD, the HVLD circuit is turned ON. At the same time the SVD circuit is switched ON and OFF. At this time, sampling control is executed for the SVD circuit ON time. There are two types of sampling time, as follows: The time of one instruction cycle immediately after the HVLD circuit is turned ON. Sampling at cycles of 2 Hz output by the clock timer while HVLD circuit ON time. When the CPU system clock is fosc3 in S1C62A33, the detection result at the timing in above may be invalid or incorrect. When performing SVD detection using the timing in , be sure that the CPU system clock is fosc1. Note Appreciable current is consumed during operation of SVD detection, so keep SVD detection OFF except when necessary. (1) For OSC1 using SVDON Specifications When the CPU clock is OSC1, the timing flag ("0.5 sec flag") is set in the T2Hz interrupt processing routine "TI2", so that the supply voltage is detected every second. Every second on the second the timer routine "basic timer 'CK'" is executed, to turn SVD ON or OFF every second on the half second. If the detection result indicates that the voltage is low, the separately prepared low voltage display routine "DSSVD" is executed. n sec n.5 sec (n+1) sec (n+1).5 sec Time "CK" is executed Fig. 5.3.1 Timing chart S1C62N33 TECHNICAL SOFTWARE "CK" is executed Supply voltage is detected EPSON Supply voltage is detected II-27 CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Program XTISF YFTM ; ; TI2: EQU EQU 0001B H ; 0.5 sec flag (TISF) ; Address for timing flag set LD FAN JP X,YFTM MX,XTISF NZ,TI21 ; TISF = "0" or "1"? ; ; OR LD OR AND FAN JP CALL MX,XTISF X,76H MX,0100B MX,1011B MX,0100B Z,TI2RT DSSVD ; TISF = "0": Set the TIS flag Detect: SVD ON ; ; SVD OFF ; If result is "1" (low voltage) ; ; then execute display routine "DSSVD" ; ; ; TI2RT: RET TI21: AND CALL ; RET Return to parent routine ; MX,XTISF XOR 0FH ; TISF = "1": Reset the TIS flag Execute the basic timer "CK" CK ; ; Return to parent routine The address for the timing flag set FTM can be set anywhere in RAM. This routine assumes that a timer subroutine has been prepared separately to make 1 second the unit for the routine "basic timer 'CK'". (See page 63, "Example of using timer interrupt" for how to make "basic timer 'CK'".) Timing chart of SVD operation Criteria voltage (1.2 V) Source voltage 1 sec SVDON register SVDDT register II-28 Fig. 5.3.2 Timing chart of HVLD circuit SVD operation SVD circuit 0.5 sec EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) (2) For OSC3 using HVLD Specifications When the CPU clock is OSC3, the supply voltage is detected every second, just as for (1). However, the method of detection is through the ON and OFF status of HVLD. Program When the CPU clock is OSC3, detection must be performed after switching the CPU clock to OSC1. XTISF YFTM ; ; TI2: EQU EQU 0001B H ; 0.5 sec flag (TISF) ; Address for timing flag set LD FAN JP X,YFTM MX,XTISF NZ,TI21 ; TISF = "0" or "1"? ; ; OR LD LD AND OR AND OR FAN JP CALL MX,XTISF X,76H Y,0FEH MY,1011B MX,1000B MX,0011B MY,0100B MX,0100B Z,TI2RT DSSVD ; TISF = "0": Set the TIS flag Detect: Preparation ; Switch the CPU's operating clock OSC1 ; ; HVLD ON ; HVLD OFF ; Return the CPU's operating clock to OSC3 ; If the result is "1" (low voltage) ; ; then execute display routine "DSSVD" ; ; ; TI2RT: RET TI21: AND CALL ; RET Return to parent routine ; MX,XTISF XOR 0FH ; TISF = "1": Reset the TIS flag Execute the basic timer "CK" CK ; Note S1C62N33 TECHNICAL SOFTWARE ; Return to parent routine SVDON is fixed to "0" when the HVLD is turnd OFF, because SVDON risides in the same bits at the same address as SVDDT, and one or the other is selected by write or read operation. EPSON II-29 CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) (3) For S1C62L33 using HVLD Specifications S1C62L33 uses HVLD to detect supply voltage. The other conditions are the same as for (1) and (2). However, the CPU of S1C62L33 does not use OSC3 for the clock. Program S1C62L33 has a heavy load protection function, so do not use HVLD to detect supply voltage in the heavy load protection mode. (See the following sections for the heavy load protection function.) XTISF YFTM ; ; TI2: EQU EQU 0001B H ; 0.5 sec flag (TISF) ; Address for timing flag set LD FAN JP X,YFTM MX,XTISF NZ,TI21 ; TISF = "0" or "1"? ; ; OR LD FAN JP MX,XTISF X,76H MX,1000B NZ,TI2DSB ; TISF = "0": Set the TIS flag ; If HVLD is OFF ; ; MX,1000B MX,0011B MX,0100B Z,TI2RT DSSVD ; ; ; ; ; ; ; OR AND TI2DSB: FAN JP CALL ; TI2RT: RET TI21: AND CALL ; RET Note II-30 then detect: HVLD ON HVLD OFF If the result is "1" (low voltage) then execute display routine "DSSVD" ; Return to parent routine MX,XTISF XOR 0FH ; TISF = "1": Reset the TIS flag CK ; Execute the basic timer "CK" ; Return to parent routine When the HVLD is turned OFF, SVDON is fixed to "0". EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Example of using heavy load protection function Note that the heavy load protection function on the S1C62L33 is different from the S1C62N33. (1) In case of S1C62L33 The S1C62L33 has the heavy load protection function for when the battery load becomes heavy and the source voltage drops, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. In this mode, operation with a lower voltage than normal is possible. The normal mode changes to the heavy load protection mode in the following two cases: When the software changes the mode to the heavy load protection mode (HVLD = "1") When supply voltage drop (SVDDT = "1") in the SVD circuit is detected, the mode will automatically shift to the heavy load protection mode until the supply voltage is recovered (SVDDT = "0") In the heavy load protection mode, the internally regulated voltage is generated by the liquid crystal driver source output VL2 so as to operate the internal circuit. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. Also, when the SVD is to be turned on during operation in the heavy load protection mode, limit the ON time to 10 ms per second of operation time. (2) In case of S1C62N33/62A33 This function can be used when the "Use" is selected by the mask option for the heavy load protection function. The S1C62N33/62A33 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. Compared with the normal operation mode, this mode can reduce the output voltage variation of the constant voltage/booster voltage circuit of the LCD system. S1C62N33 TECHNICAL SOFTWARE EPSON II-31 CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) The normal mode changes to the heavy load protection mode in the following case: When the software changes the mode to the heavy load protection mode (HVLD = "1") The heavy load protection mode switches the constant voltage circuit of the LCD system to the high-stability mode from the low current consumption mode. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. (1) Control of heavy load protection function using flag (S1C62L33) Specifications When heavy load protection mode is set, this will be routine "HLONBZ" which switches BZ ON, routine "BZOF" which switches BZ OFF, and 2 Hz interrupt routine "TI2" which controls 1-second waiting release. This routine employs the heavy load protection mode release flag HLOFF, which recognizes termination of heavy load drive, and the heavy load protection mode release delay flag HLOFDLF, which takes the timing of a 1-second wait. Setting heavy load protection mode XHLOF XHLOFDL XNOTHL YFHL ; ; HLONBZ: EQU EQU EQU EQU 1000B 0100B 0011B H ; Heavy load protection mode release flag ; Heavy load protection mode release delay flag ; ; Address of heavy load protection function related flag set LD OR LD AND LD OR RET X,76H MX,1000B X,YFHL MX,XNOTHL X,7CH MX,0001B ; Set heavy load protection mode ; ; Reset flags related to heavy load protection ; ; Switch BZ ON ; ; Return to parent routine This routine assumes that the addresses of the flag set related to heavy load protection functions together with the 0.5 sec flag are allocated suitably in RAM as the addresses of the timing flag set. II-32 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Release of heavy load protection mode When the heavy load drive terminates, the heavy load protection mode release flag is set, the heavy load protection mode delay flag is set and reset with the 1-second timer during the T2Hz interrupt processing routine, the heavy load protection mode is released. n sec n.5 sec (n+1) sec (n+1).5 sec Time "CK" is executed ; ; TI2: "CK" is executed Heavy load drive terminates (HLOF flag is set) Fig. 5.3.3 Timing chart XTISF XHLOFF XHLOFDL XNOTHL YFTM YFHL ; ; BZOF: HLOFDL flag is set Heavy load protection mode is released (Two flags are reset) EQU EQU EQU EQU EQU EQU 0001B 1000B 0100B 1100B H H ; 0.5 sec flag (TISF) ; High load protection mode release flag (HLOFF) ; High load protection mode release delay flag (HLOFDLF) ; ; Address of timing flag set ; Address of heavy load protection flag set LD AND LD OR RET X,7CH MX,1110B X,YFHL MX,XHLOF ; Stop BZ ; ; Set the HLOF flag ; ; Return to parent routine LD FAN JP ; OR FAN JP FAN JP X,YFTM MX,XTISF NZ,TI21 ; TISF = "0" or "1"? ; ; MX,XTISF MX,XHLOFDL Z,TI2RT MX,XHLOFDL NZ,TI2HLO ; TISF = "0": Set the TIS flag If the HLOF flag is set ; ; then HLOFDLF = "0" or "1"? ; ; OR RET MX,XHLOFDL ; ; ; S1C62N33 TECHNICAL SOFTWARE EPSON HLOFDLF = "0": Set the HLOFDL flag Return to parent routine II-33 CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) TI2HLO: ; TI2RT: TI21: AND MX,XNOTHL ; HLOFDLF = "1": Reset heavy load protection ; flag set ; Release heavy load protection mode ; and fix SVDON to "0" LD AND X,76H MX,0011B RET AND CALL ; Return to parent routine MX,XTISF XOR 0FH ; TISF = "1": Reset the TIS flag CK ; Execute basic timer "CK" ; RET ; Return to parent routine See page 40, "Example of using output ports" for details on BZ control. 1. When the heavy load protection mode is set, the heavy load protection flags must be reset. Notes 2. SVD is fixed to "0" when the heavy load protection mode is released, because the SVDON result is not fed back to SVDON through the AND instruction. (2) Method without using flags (S1C62L33) Specifications When heavy load protection mode is set, this will be routine "HLONBZ" which switches BZ ON and routine "BZHLOF" which stop BZ then releases the heavy load protection mode. Note, however, that unlike item (1) above, it does not use flags. Program SVDON is used to release the heavy load protection mode without using flags. After the heavy load drive terminates, the SVD is set ON and OFF, and then the heavy load protection mode is released. HLONBZ: ; ; BZHLOF: II-34 LD OR LD OR RET X,76H MX,1000B X,7CH MX,0001B ; Set the heavy load protection mode ; ; Switch BZ ON ; ; Return to parent routine LD AND LD X,7CH MX,1110B X,76H ; Stop BZ ; ; SVD ON EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) OR AND AND MX,0100B MX,1011B MX,0011B ; OFF ; ; Release the heavy load protection mode ; and fix SVDON to "0" ; Return to parent routine RET SVD is fixed to "0" when the heavy load protection mode is released, because the SVDON result is not fed back to SVDON through the AND instruction. Note Timing chart of heavy load protection mode operation Criteria voltage (1.2 V) Source voltage HVLD register HVLD circuit BZ output SVDON register 0.5 sec Fig. 5.3.4 Timing chart SVD circuit of HVLD operation SVDDT register (3) Control of heavy load protection (for S1C62N33/62A33) Specifications When the heavy load protection function is selected for the S1C62N33 or S1C62A33 by the mask option setting, the "HLBZ10" routine sets the heavy load protection mode and outputs the BZ signal for 10 ms, then, it releases the heavy load protection mode. However, the OSC1 clock (32.768 kHz) must be set for the CPU operating clock. 10 ms BZ Fig. 5.3.5 Timing chart S1C62N33 TECHNICAL SOFTWARE HVLD EPSON II-35 CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Program HLBZ10: LD OR LD OR X,76H MX,1000B Y,7CH MY,1000B ;Set the heavy losd protection mode ; ;Switch BZ ON ; CALL ST10MS ;10 ms soft timer call AND AND MY,0111B MX,0111B ;Switch BZ OFF ;Release the heavy load protection mode A,0H ;10 ms soft timer subroutine ;Reset the decimal flag ;Loop for 10 ms ;(7+7+5) clock x 16 ; ; ; ; ; ; ST10MS: LD RDF ST10MS1: NOP7 ADD JP RET Note Programming notes A,0FH NZ,ST10MS1 The heavy load protection mode can be released immediately after driving the heavy load (BZ output). To reduce current consumption, release the heavy load protection mode unless otherwise necessary. (1) It takes 100 s from the time the SVD circuit goes ON until a stable result is obtained. For this reason, keep the following software notes in mind: When the CPU system clock is fosc1 1. When detection is done at HVLD After writing "1" on HVLD, read the SVDDT after 1 instruction has passed. 2. When detection is done at SVDON After writing "1" on SVDON, write "0" after at least 100 s has lapsed (possible with the next instruction) and then read the SVDDT. When the CPU system clock is fosc3 (in case of S1C62A33 only) 1. When detection is done at HVLD After writing "1" on HVLD, read the SVDDT after 0.6 sec has passed. (HVLD holds "1" for at least 0.6 sec) II-36 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) 2. When detection is done at SVDON Before writing "1" on SVDON, write "1" on HVLD first; after at least 100 s has lapsed after writing "1" on SVDON, write "0" on SVDON and then read the SVDDT. (2) To reduce current consumption, set the SVD operation to OFF unless otherwise necessary. (3) SVDON resides in the same bit at the same address as SVDDT, and one or the other is selected by write or read operation. When writing a "1" to SVDON use the OR command, and when writing a "0" use the AND command. No other commands should be used for this purpose. (4) Select one of the following software processing to return to the normal mode after a heavy load has been driven in the heavy load protection mode (S1C62L33). After heavy load drive is completed, return to the normal mode after at least one second has elapsed. After heavy load drive is completed, switch SVD ON and OFF (at least 100 s is necessary for the ON status) and then return to the normal mode. The S1C62N33/62A33 returns to the normal mode after driving a heavy load without special software processing. (5) To reduce current consumption, be careful not to set the heavy load protection mode with the software unless otherwise necessary. (6) When the SVD is to be turned on during operation in the heavy load protection mode, limit the ON time to 10 ms per second of operation time. S1C62N33 TECHNICAL SOFTWARE EPSON II-37 CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports) 5.4 Output Ports (R00-R03, R10-R13) The S1C62N33 Series reserves eight bits (4 bits x 2) for general output ports. The output ports R10-R13 can be used as special output ports. Output port memory map Table 5.4 I/O data memory map (output ports) Address *7 D3 Register D2 D1 D0 Name R03 R02 R00 R03 R01 R/W SR *1 Comment 1 0 0 High Low R02 0 High Low R01 0 High Low R00 0 High Low R13 0 High Low Output port (R13, BZ) *6 R12 0 High Low Output port (R12, FOUT) *6 R11 0 High Low Output port (R11) R10 0 High Low Output port (R10, BZ) *6 BZFQ 0 2 kHz 4 kHz Buzzer frequency selection register - *2 Unused *5 - *2 Unused *5 - *2 Unused *5 7BH Output port (R00-R03) R13 R12 R11 R10 R/W 7CH BZFQ R/W - - R - F6H *1 *2 *3 *4 II-38 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports) The following explanations cover the control registers when special output has been selected for R10, R12, and R13. R10, R13 These bits control the output of the buzzer signals (BZ, BZ). (when BZ and BZ output is When "1" is written: Buzzer signal is output selected): When "0" is written: Low level (DC) is output Special output ports Read-out: Available data (7CH.D0 and D3) BZ is output from pin R13. The mask option supports selection of output control by R13, or output control by R10 simultaneously with BZ. * When R13 controls BZ output BZ output and BZ output can be controlled independently. BZ output is controlled by writing data to R10, and BZ output is controlled by writing data to R13. * When R10 controls BZ output BZ output and BZ output can be controlled simultaneously by writing data to R10 only. For this case, R13 can be used as a one-bit general register having both read and write functions, and data of this register exerts no affect on BZ output (output from pin R13). R12 Controls the FOUT (clock) output. (when FOUT is selected): When "1" is written: Clock output Special output port When "0" is written: Low level (DC) output data Read-out: Available (7CH.D2) S1C62N33 TECHNICAL SOFTWARE EPSON II-39 CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports) Example of using output ports (1) Writing and reading to output ports Specifications Register R13 control for pin R13 has been selected by mask option. First, the immediate value "0010B" is output to the output ports R00-R03. The value of RAM, OUTB is output to output ports R10-R13. Figure 5.4.1 indicates the correspondence of write data and output ports. RAM, OUTB D3 D2 D1 D0 Immediate value 0 0 1 0 R13 register R13 R12 register R12 R11 register R11 R10 register R10 Fig. 5.4.1 R03 register R03: Becomes low output Correspondence of write data and R02 register R02: Becomes low output R01 register R01: Becomes high output output ports R00 register R00: Becomes low output Then, the status of the (outputting) pins of output ports R00-R03 is read into B register, and the status of the pins of output ports R10-R13 is read into RAM, DTB. II-40 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports) Program YOUTB YDTB ; ; EQU EQU H H LD LD X,7BH ; Output (write) the immediate value "0010B" to R00-R03 MX,0010B ; LD LD LD X,7CH Y,YOUTB MY,MX ; Output (write) the value of RAM, OUTB to R10-R13 ; LD LD X,7BH B,MX ; Read the value of R00-R03 (being output) to B register ; LD LD LD X,7CH Y,YDTB MY,MX ; Read the value of R10-R13 (being output) to RAM, DTB ; ; ; Buffer address of data to be output to R10-R13 ; Buffer address of data ; ; ; Addresses for RAM, OUTB and DTB are allocated appropriately. S1C62N33 TECHNICAL SOFTWARE EPSON II-41 CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports) (2) Operation of output ports by separate bits Specifications This routine uses the read-out capability of the output port control registers, to control output for separate bits with the memory arithmetic instructions. First, "1" is written to registers R00 and R03 by the OR instruction, and then "0" is written to register R01 by the AND instruction. The result of the output to ports R00-R03 is shown in Figure 5.4.2. I/O memory R03 R02 R01 R00 Set to "1" No change Fig. 5.4.2 Output result Program II-42 LD OR AND R02: No change Set to "0" R01: Becomes low output Set to "1" R00: Becomes high output X,7BH MX,1001B MX,1101B EPSON R03: Becomes high output ; Make R00 and R03 outputs high ; ; Make R01 output low S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports) (3) Scanning for key input by ports R00-R03 The key matrix is shown in Figure 5.4.3. This is the scanning subroutine, "KYSC", to specify the key that has been made high input. Specifications Kxx R03 R02 R01 Fig. 5.4.3 Key matrix (Kxx x R00-R03) "KYSC" first brings R00 to high output and the other ports to low output, and then executes "KYIN" to judge whether an entry has been made to the key connected to R00. Regardless of the result of evaluation, the high output pin is shifted to the left and the key connected to the next pin is evaluated. This processing is repeated up to R03. Program KYSC: LD LD ; KYSCLP: CALL LD ADD JP RET R00 X,7BH ; Make R00 only high output MX,0001B ; KYIN ; Scanning loop: Execute key input evaluation processing "KYIN" X,7BH ; Shift high output to left MX,MX ; NZ,KYSCLP ; Continue until R00-R03 are all low ; Return to parent routine This routine assumes that the key input evaluation processing routine "KYIN" has been prepared separately. S1C62N33 TECHNICAL SOFTWARE EPSON II-43 CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports) (4) Control of BZ (when R13 is R10 control) Specifications This is the subroutine to switch BZ and BZ ON and OFF when R13 has become R10 control. In subroutine "BZ4", BZ output is switched ON after the BZ frequency is set to 4 kHz. In subroutine "BZ2", BZ output is switched ON after the BZ frequency is set to 2 kHz. In subroutine "BZOF", BZ output is switched OFF. Program Note II-44 BZ4: LD LD LD OR RET X,0F6H MX,0000B X,7CH MX,0001B ; Set BZ frequency to 4 kHz ; ; Make R10 and R13 high output ; ; Return to parent routine BZ2: LD LD LD OR RET X,0F6H MX,1000B X,7CH MX,0001B ; Set BZ frequency to 2 kHz ; ; Make R10 and R13 high output ; ; Returns to parent routine BZOF: LD AND RET X,7CH MX,1110B ; Make R10 and R13 low output ; ; Return to parent routine None of these routines affects registers R11-R13 (output pins R11 and R12). EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports) (5) Control of BZ frequency (when R13 is R10 control) Specifications This subroutine, "BZ", uses the BZ frequency control to sound BZ at 4 kHz when the value of the second counter is implemented in even time, and at 2 kHz for odd time. Program The second counter is the seconds column BCD data in the timer program. This routine assumes that the start address of the seconds data (that is, the memory address of the 1second column BCD data) is defined in "YCKS", the symbol indicating the address. (In the program example, " 0H".) The value of the second counter is judged to be even time (that is, even seconds) or odd time (that is, odd seconds) depending on whether the D0 data in the BCD data is "0" or "1". Branching is done depending on this evaluation, and the BZ is sounded after "0" or "1" is written to the BZFQ register. YCKS ; ; BZ: EQU ; Start address of second counter 0H LD LD FAN JP X,0F6H Y,YCKS MY,0001B NZ,BZ0D ; Store the I/O memory BZFQ in the X register ; Is the value of the second counter even or odd? ; ; LD JP LD MX,0000B BZON MX,1000B ; Even: Make BZFQ = "0" ; ; Odd: Make BZFQ = "1" LD OR RET X,7CH MX,0001B ; Output BZ ; ; Return to parent routine ; BZ0D: ; BZON: S1C62N33 TECHNICAL SOFTWARE EPSON II-45 CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports) Note In this program example, the BZ frequency is changed (according to even seconds or odd seconds) only when "BZ" is called and executed. For instance, if "BZ" is executed at even seconds and the BZ frequency is set to 4 kHz, then the BZ frequency will still be 4 kHz, even if the second counter advances and becomes odd seconds. As long as "BZ" is not executed again, the frequency will not change to 2 kHz. Programming note When BZ has been selected by the output application for pin R13, the mask option decides whether output is controlled by register R13, or by register R10 simultaneously with BZ. In particular, when BZ output is under R10 control, register R13 can be used as a 1-bit general register for read/write. Data in this register has no affect on BZ output (output of pin R13). II-46 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) 5.5 LCD Driver The S1C62N33 Series has four common pins and 40 segment pins, so that it can drive an LCD with up to 160 (40 x 4) segments. The driving method is 1/4 duty (or 1/3 duty with the mask option) dynamic drive. Further, the S1C62N33 Series provides software setting of the LCD static drive. Segment data memory map Address Low 0 Page Fig. 5.5.1 Segment data memory map 1 2 3 4 or C 0 4 5 6 7 8 9 A B C D E F High Segment data memory (40 words x 4 bits) 40H-6FH = R/W C0H-EFH = W 5 or D 6 or E Segment data memory The LCD segments are lit or turned off depending on this (40H-6FH or C0H-EFH) data. When "1" is written: When "0" is written: Read-out: Lit Not lit Available for 40H-6FH Undefined for C0H-EFH At initial reset, the contents of the segment data memory are undefined. Note - When 40H-6FH is selected for the segment data memory, the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the segment data memory by executing initial processing. - When C0H-EFH is selected for the segment data memory, that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). - Data output from segment pins selected as DC output will be the data corresponding to the COM0 pins. S1C62N33 TECHNICAL SOFTWARE EPSON II-47 CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) Example of control program for LCD segment output (1) Generation of 16-segment character Specifications This is the subroutine "DSCG", which uses the table lookup instruction to generate characters corresponding to the values of A and B registers, by writing to the A and B registers. Segment data memory assignment table Address Data D3 D2 D1 D0 - h l - c g k o b f j n a e i m (n+0)H (n+1)H (n+2)H (n+3)H Pin address assignment table SEG(0+4*n) SEG(1+4*n) SEG(2+4*n) SEG(3+4*n) Common 0 Common 1 Common 2 Common 3 (b) (g) (h) (d) (a) (f) (i) (c) (o) (e) (j) (m) (p) (l) (k) (n) SEG SEG (2+4*n) (0+4*n) d b h g c Common0 Common1 Common2 Common3 i m j k l o p SEG SEG (3+4*n) (1+4*n) Example of LCD panel II-48 a e n Fig. 5.5.2 f EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) The mask options are selected as below for the segment assignment to correspond with the LCD panel shown in Figure 5.5.2. * The drive duty is made 1/4 duty. * Of the 40 segment pins, one consecutive group of four pins (SEG0 + 4*n through SEG3 + 4*n, where n is 0 to 9) lights one LCD figure (16 segments). (See the pin address assignment table.) As a result, a group of four consecutive words in the segment memory address can control one LCD figure. (See the segment data memory assignment table.) The segment data memory area can be either 40H-6FH or C0H-EFH. In the two assignment tables, the addresses of one set of four words begin from the lowest value, as (n + 0), (n + 1), (n + 2), (n + 3). The relationship between the values of the A and B registers and the characters generated is as follows: * When the B register is "0", the value (hexadecimal) of the A register corresponds to a numeral from "0" through "F" (hexadecimal). * When the B register is "1" and A register is "0", this corresponds to " " (single-figure space). When the table is expanded, it corresponds to the character added to the A register in hexadecimal order. B=0 Value of A 0 1 2 3 4 5 6 9 A B C D E F 7 8 Character B=1 Value of A Fig. 5.5.3 Diagram of characters Character S1C62N33 TECHNICAL SOFTWARE Value of A 0 Character EPSON II-49 CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) Table look-up "DSCG" converts the address of the steps for writing into segment data memory the characters in the data table that correspond to the values of registers A and B (which have been set by the parent routine). Then it jumps to this address with the JPBA instruction. The PSET instruction is inserted immediately before the first half of the JPBA instruction, so that the table look-up is on the same page as the parent routine, and the data table part is on a different page. DSCG: Data table ADD ADC PSET JPBA A,A B,B DSCGTB ; Set to jump to A and B ; ; Jump to table and form subroutine ; The data table begins at the start address of the page in which it is placed. The segment memory can be written to in such a way that numerals "0" to "9" and letters "A" to "F" and " " (single-figure space) can be displayed. A character can be generated by combining LBPX instruction and RETD instruction. Further, expansion from " " (single-figure space) can be done according to the rule below for setting the values of the A and B registers. II-50 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) ORG ; DSCGTB LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD LBPX RETD S1C62N33 TECHNICAL SOFTWARE x00H ; Start address of table MX,10000111B 01111000B MX,01000001B 00000100B MX,00010011B 00100010B MX,00010011B 01100001B MX,01010100B 00000101B MX,00010110B 01100001B MX,00010110B 01110001B MX,00100110B 00010111B MX,00010111B 01110001B MX,00010111B 01000001B MX,00110001B 01000010B MX,01010011B 01100100B MX,00000110B 00110000B MX,01000011B 01100100B MX,00010110B 01100001B MX,00010110B 00010001B MX,00000000B ; Generate "0" (write to segment memory) ; , Return to parent routine ; Generate "1" (write to segment memory) ; , Return to parent routine ; Generate "2" (write to segment memory) ; , Return to parent routine ; Generate "3" (write to segment memory) ; , Return to parent routine ; Generate "4" (write to segment memory) ; , Return to parent routine ; Generate "5" (write to segment memory) ; , Return to parent routine ; Generate "6" (write to segment memory) ; , Return to parent routine ; Generate "7" (write to segment memory) ; , Return to parent routine ; Generate "8" (write to segment memory) ; , Return to parent routine ; Generate "9" (write to segment memory) ; , Return to parent routine ; Generate "A" (write to segment memory) ; , Return to parent routine ; Generate "B" (write to segment memory) ; , Return to parent routine ; Generate "C" (write to segment memory) ; , Return to parent routine ; Generate "D" (write to segment memory) ; , Return to parent routine ; Generate "E" (write to segment memory) ; , Return to parent routine ; Generate "F" (write to segment memory) ; , Return to parent routine ; Generate " " (single-space figure) (write to segment memory) ; ; , Return to parent routine 00000000B EPSON II-51 CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) (2) When segment memory is assigned to C0H-EFH Specifications This application example, in which the assignment shown in (1) is made to the segment data memory area C0H-EFH, is the "column display routine 'DSSG'" and the "apostrophe and period display routine 'DSSGA'". Both assume, as in (1), that eight columns of the LCD panel are to be used. The SEG (0 + 4*n) pin for the LCD's first column is assigned to segment memory C0H, and the remaining 31 pins are assigned in order. The pin assignment for the apostrophe and period assignments are not shown in (1). They are assigned in the manner shown in Figure 5.5.4. Segment data memory assignment table Data Address E0H E1H E2H E3H D3 D2 D1 D0 A3 A7 P3 P7 A2 A6 P2 P6 A1 A5 P1 P5 A0 A4 P0 P4 A7 A6 A5 A4 A3 A2 A1 A0 Fig. 5.5.4 Example of LCD panel II-52 P7 P6 EPSON P5 P4 P3 P2 P1 P0 S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) Figure display routine The segment data memory area C0H-EFH is write-only, so the display data stored in the buffers "YDSB1"-"YDSB8" (for arithmetic operations) is written to the segment memory. Two words of the buffer display data correspond to one figure of the display. The low address data corresponds to the value of the A register of DSCG, and the high address data corresponds to the value of the B register. YDSB1 YDSSG ; ; DSSG: ; DSSGLP: EQU EQU 0H 0C0H ; Segment data buffer first figure start address ; Segment memory first figure start address LD X,YDSSG LD Y,YDSB1 ; Store the segment memory first figure start ; address to X register ; Store the segment data buffer first figure start ; address to Y register LDPY LDPY CALL CP JP A,MY B,MY DSCG XH,0EH C,DSSGLP ; Display: Set the display character ; Execute "DSCG" ; ; Continue up to the eighth figure ; RET S1C62N33 TECHNICAL SOFTWARE ; Return to parent routine EPSON II-53 CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) Apostrophe and period display routine YDSBA YDSBP YDSSGA YDSSGP ; ; DSSGA: As in the Figure display routine, the display data stored in the buffers "YDSBA"-"YDSBP" is written to the segment data memory. EQU EQU EQU EQU 0H 2H 0E0H 0E2H LD LD X,YDSSGA ; Store the segment data memory apostrophe start address in X register Y,YDSBA ; Store the segment data buffer apostrophe start address in Y register ; DSSGAL: LDPX INC CP JP ; RET ; Segment data buffer apostrophe start address ; Segment data buffer period start address ; Segment data memory apostrophe start address ; Segment data memory period start address MX,MY Y XL,4H C,DSSGAL ; Display: Transfer the data, and increment X register ; Increment the Y register ; Repeat up to the eighth figure ; ; Return to parent routine (3) Zero-suppression of buffer data Specifications With the settings of (1) and (2), zero-suppression can be effected if the display data and buffer data is manipulated by this subroutine "DSSP". Program DSSP: ; DSSPRT: II-54 CP JP INC LD MY,0H NZ,DSSPRT Y MY,1H RET ; If low address data is "0" ; ; then make high address data "1" ; ; Return to parent routine EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) LCD driver memory map Table 5.5 I/O data memory map (LCD driver) Address *7 D3 CSDC Register D2 D1 ETI2 ETI8 R/W D0 Name ETI32 CSDC SR *1 Comment 1 0 0 Static Dynamic ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) LCD drive switch 78H *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Example of switching LCD drive *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary The sequence for specifying LCD static drive is as follows: Write "1" to the register at address "78H.D3". Write the same value to all registers corresponding to the segment memory COM0-COM3. The following is an example of switching LCD drive when the segment memory is allocated to C0H-EFH. S1C62N33 TECHNICAL SOFTWARE EPSON II-55 CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) (1) Static all lit for step adjustment This subroutine "SGHI" switches to static drive and light all segments. Specifications Program XIO2SH YDSSG ; ; SGHI: EQU EQU 0FH 0C0H ; The 2nd I/O memory, start high address ; Segment memory first start address LD OR X,78H MX,1000B ; Write "1" to CSDC (static drive) ; X,YDSSG MX,1111B XH,XIO2SH C,SGHILP ; All segments lit: Address to segment memory start ; Make segment high output ; Continue until no more area ; ; LD SGHILP: LDPX CP JP ; RET ; Return to parent routine Perform step adjustment by setting the segment data after all LCDs are lit. Note (2) Return to dynamic drive after no segments lit Specifications Program XIO2SH YDSSG ; ; SGLO: SGLOLP: This subroutine puts all the segments out, and then switches to dynamic drive. EQU EQU 0FH 0C0H ; The 2nd I/O memory, start high address ; Segment memory first start address LD LDPX CP JP X,YDSSG MX,0000B XH,XIO2SH C,SGLOLP ; No segment lit: Address to segment memory start Make segment low output ; ; Continue until no more area ; LD OR RET X,78H MX,1000B ; Write "0" to CSDC (dynamic drive) ; ; Return to parent routine ; II-56 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) Programming notes (1) When 40H-6FH is selected for the segment data memory, the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the segment data memory by executing initial processing. (2) When C0H-EFH is selected for the segment data memory, that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). (3) Data output from segment pins selected as DC output will be the data corresponding to the COM0 pins. (4) When performing step adjustment with the static drive, set the segment data so that all LCD segments are lit. S1C62N33 TECHNICAL SOFTWARE EPSON II-57 CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) 5.6 Clock Timer The S1C62N33 Series has a clock timer built-in. The clock timer can generate timer interrupts at 32 Hz, 8 Hz and 2 Hz. Ordinarily, this clock timer is used for all types of timing functions such as clocks. Clock timer memory map Table 5.6.1 I/O data memory map (clock timer) Address *7 D3 Register D2 D1 TM3 TM2 TM1 Name TM0 TM3 0 Timer data (clock timer 2 Hz) TM2 0 Timer data (clock timer 4 Hz) TM1 0 Timer data (clock timer 8 Hz) TM0 0 Timer data (clock timer 16 Hz) R SR *1 Comment D0 1 0 70H TMRST SWRUN SWRST IOC0 TMRST Reset Reset - W R/W W R/W SWRUN 0 RUN STOP SWRST Reset Reset - IOC0 0 Output Input Clock timer reset *5 Stopwatch counter RUN/STOP 7EH *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Stopwatch counter reset *5 I/O control register 0 (P00-P03) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary TMRST: This bit resets the clock timer. Clock timer reset When "1" is written: Clock timer reset (7EH.D3) When "0" is written: No operation Read-out: Always "0" The clock timer restarts immediately on being reset. II-58 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) Example of using clock timer (1) Initializing clock timer Specifications This program resets the clock timer. Program Notes LD OR X,7EH MX,1000B ; Reset the clock timer ; 1. When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". 2. The watchdog timer may be counted up at the clock timer reset. 3. Resetting the clock timer does not affect the stopwatch counter. (2) Reading the clock timer Specifications This program reads the clock timer data into A register. A register Fig. 5.6.1 Correspondence between clock timer and A register Program S1C62N33 TECHNICAL SOFTWARE LD LD D3 D2 D1 D0 TM3 TM2 TM1 TM0 X,70H A,MX EPSON ; Load the clock timer data into A register ; II-59 CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) (3) Detecting the edge of the clock timer Specifications This subroutine, "TMEDG", detects the edge of the timer data, and executes the 4 Hz processing routine "TM4" if the 2 Hz edge is detected. Program XTMDT2 YTMDTB ; ; TMEDG: EQU EQU 0100B xH ; Timer data 2 Hz ; Address of timer data buffer LD LD XOR FAN JP CALL X,70H Y,TMDTBF MY,MX MY,XTMDT2 Z,TMEDGRT TM4 ; Detect change (edge) in timer data ; ; ; If 2 Hz edge ; ; then execute 4 Hz processing "TM4" ; TMEDGRT: RET ; Return to parent routine The processing routine for frequencies not set in the clock timer interrupt can be executed by repeatedly calling this subroutine at high frequency. n sec (n+1) sec Time "1" TM2 "0" 125 ms Fig. 5.6.2 Timing chart II-60 Timeing for executing "TM4" EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) (4) Alarm bell using clock timer and BZ output Specifications When called every 8 Hz, this subroutine generates the alarm bell sound by switching the BZ output ON and OFF, as shown in the timing chart. n sec (n+1) sec Time "1" TISF "0" "1" 2 Hz "0" "1" 4 Hz "0" 8 Hz interrupt Fig. 5.6.3 Alarm bell timing chart ON BZ output OFF Program XTISF XBESYNF YFTM ; ; BE: EQU EQU EQU 0001B 0010B H ; 0.5 sec flag (TISF) ; Bell sound synchro flag ; Address of timing flag set LD FAN JP Y,YFTM MY,XTISF NZ,BZOF ; TISF = "0" or "1"? ; ; TISF = "1": Execute "BZOF", return to parent routine LD LD AND CP JP X,70H A,MX A,1100B A,0000B NZ,BE1 ; TISF = "0": Is the timer data of 2 Hz and 4 Hz ; ; ; all "0"? ; OR JP MY,XBESYNF BZ ; Both 2 Hz and 4 Hz are "0": Reset BESYNF Execute "BZ", return to parent routine ; FAN JP CP JP MY,XBESYNF Z,BZOF A,1000B NZ,BZOF ; 2 Hz and 4 Hz not both "0": When BESYNF = "0" ; or 4 Hz = "1" ; execute "BZOF", return to parent routine ; AND JP MY,XBESYNF XOR 0FH ; BZ ; ; ; ; BE1: ; S1C62N33 TECHNICAL SOFTWARE EPSON In other cases: Reset BESYNF Execute "BZ", return to parent routine II-61 CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) Timer interrupt memory map Table 5.6.2 I/O data memory map (timer interrupt) Address *7 D3 CSDC Register D2 D1 ETI2 ETI8 D0 Name ETI32 CSDC R/W SR *1 Comment 1 0 0 Static Dynamic ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) - *2 TI2 0 Yes No Interrupt factor flag (clock timer 2 Hz) *4 TI8 0 Yes No Interrupt factor flag (clock timer 8 Hz) *4 TI32 0 Yes No Interrupt factor flag (clock timer 32 Hz) *4 LCD drive switch 78H - TI2 TI8 R TI32 Unused *5 79H *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary TI32, TI8, TI2: These flags indicate the status of the clock timer interrupt. Interrupt factor flags When "1" is read out: Interrupt has occurred (79H.D0-D2) When "0" is read out: Interrupt has not occurred Writing: Invalid These flags can be reset through being read out by the software. Note Even if these flag interrupts are masked, the flags are set to "1" at the falling edge of the corresponding signal. II-62 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) Clock timer timing chart Address 70H Clock timer timing chart Register Frequency D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz 32 Hz interrupt request Fig. 5.6.4 Timing chart of the clock timer 8 Hz interrupt request 2 Hz interrupt request Interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz). At this time, the corresponding interrupt factor flag (TI32, TI8, TI2) is set to "1". Example of using timer interrupt (1) Initializing clock timer and setting interrupt mask register (2 Hz) This program resets the clock timer after enabling the timer 2 Hz interrupt only. Specifications Program DI LD LD LD OR LD FAN EI Notes X,78H MX,0100B X,7EH MX,1000B X,79H MX,0111B ; Disable interrupts ; Enable timer 2 Hz interrupt, and mask all others ; ; Reset clock timer ; ; Reset the timer interrupt factor flags ; ; Enable interrupt 1. Write to the interrupt mask registers (ETI) only in the DI status. 2. The generated timer interrupt factor flag is also reset through the clock timer being reset. S1C62N33 TECHNICAL SOFTWARE EPSON II-63 CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) (2) Operating interrupt mask register by separate bits This program enables the timer 8 Hz interrupt only, and then masks the timer 32 Hz interrupt. Specifications DI LD OR AND EI Program X,78H MX,0010B MX,1110B ; Disable interrupt ; Enable timer 8 Hz interrupt ; ; Mask timer 32 Hz interrupt ; Enable interrupt Write to the interrupt mask registers (ETI) only in the DI status. Note (3) Processing after timer interrupt generated This program stores the register when an interrupt is generated, and when the interrupt processing is completed it recovers the register data and returns to the main routine. Specifications The order of priority for the interrupts is set as shown in the table below, interrupt nesting is disabled, and processing proceeds in descending order of priority. The interrupt processing routine is called with CALL instruction and processed. Table 5.6.3 Order of priority of interrupts in program example Order of Priority Interrupt Factor 1 2 3 Clock timer 32 Hz Clock timer 8 Hz Clock timer 2 Hz Program ORG 104H ; Interrupt vector address of timer interrupt JP INTI ; Go to "INTI" if timer interrupt is generated EQU H ; Buffer address of timer interrupt factor flags ; ; ; YTIB ; ; II-64 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) INTI: PUSH PUSH PUSH PUSH PUSH PUSH PUSH XH XL YH YL A B F ; Store value of X register in stack ; ; Store value of Y register in stack ; ; Store value of A register in stack ; Store value of B register in stack ; Store value of F register in stack LD LD LD LD AND X,79H Y,YTIB MY,MX X,78H MY,MX ; (Reset) the timer interrupt factor flags ; and store in buffer ; ; Mask the timer interrupt factor flags ; by the value of the timer interrupt mask register FAN JP CALL MY,0001B ; If the TM32Hz interrupt factor flag is set, Z,INTI8 ; and enabled TI32 ; then "TI32" is executed ; ; ; INTI8: LD FAN JP CALL ; INTI2: LD FAN JP CALL ; INRT: Y,YTIB MY,0010B Z,INTI2 TI8 ; If the TM8Hz interrupt factor flag is set, ; and enabled ; ; then "TI8" is executed Y,YTIB MY,0100B Z,INRT TI2 ; If the TM2Hz interrupt factor flag is set, ; and enabled ; ; then "TI2" is executed For details on "INRT", see the interrupt routine in "4.5 Example of Interrupt Vector Processing". Notes 1. Read the interrupt factor flags (TI) only in the DI status. 2. Regardless of the setting of the interrupt mask register (ETI), the interrupt factor flag (TI) is set to "1" at the falling edge of the corresponding signal. Hence, the presence of an interrupt factor is judged by the result of ANDing the factor flag stored in the buffer and the interrupt mask register. S1C62N33 TECHNICAL SOFTWARE EPSON II-65 CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) (4) Clock using timer 2 Hz interrupt Specifications This program is for a clock that uses the timer 2 Hz interrupt. It judges when 1 second elapses after the 2 Hz interrupt and counts the clock's seconds. Table 5.6.4 Clock data Address 0H 1H 2H 3H Data Second count data (single digit seconds column, BCD) Second count data (ten's seconds column, BCD) Minute count data (single digit minutes column, BCD) Minute count data (ten's digit minutes column, BCD) Program XTISF YFTM YCKS ; ; TI2: EQU EQU EQU 0001B H 0H ; 0.5 sec flag (TISF) ; Address of timing flag set ; Start address of second counter data (BCD) LD FAN JP X,YFTM MX,XBTSF NZ,TI21 ; TISF = "0" or "1"? ; ; OR RET AND LD CALZ RET JP MX,XTISF ; TISF = "0": Set TISF ; Return to "INTI" ; TISF = "1": Reset TISF ; Increment the second counter data by 1 ; ; No carry: Return to "INTI" ; Carry: Execute clock processing for ; at least a minute "CK", ; and return to "INTI" ; TI21: II-66 MX,XTISF XOR 0FH X,YCKS CT60 CK EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) Reference Page 0 routine "CT60" ; CT60: PAGE 0 ; CALZ CP JP LDPX RETS CTUP MX,6H NZ,RTP0 MX,0H ; Count 1 up the BCD counter ; Where is the tens' position? ; Not "6": Go to RTP0 Zero clear ; "6": ; Return to parent routine and skip Page 0 routine "CTUP" PAGE ; CTUP: RTP0: S1C62N33 TECHNICAL SOFTWARE SDF ADD INC ADC RDF RET 0 MX,1H X MX,0H EPSON ; ; Preparation: Set D flag ; Increment data by 1 with BCD ; Set tens' place address ; Carry processing to tens' place ; After process: Reset D flag ; Return to parent routine II-67 CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) Programming notes (1) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Consequently, perform flag read-out (reset the flag) when necessary at reset. (2) The watchdog timer may be counted up at clock timer reset. (3) Resetting the clock timer has no effect on the stopwatch counter, and vice versa. (4) Writing to the interrupt mask register (ETI) can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause an error. (5) Read out the interrupt flag (TI) only during the DI status (interrupt flag = "0"). Read-out during EI status will cause an error. (6) Regardless of the setting of the interrupt mask register (ETI), the interrupt factor flag (TI) is set to "1" at the falling edge of the corresponding signal. II-68 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) 5.7 Input Ports (K00-K03, K10) The S1C62N33 Series has general-purpose input ports consisting of a total of five bits. Four bits are reserved for pins K00-K03 and one bit is for K10. All five bits of these input ports have interrupt functions. Input port memory map Table 5.7.1 I/O data memory map (input ports) Address *7 D3 Register D2 D1 D0 Name K03 K02 K00 K03 K01 SR *1 0 *2 High Low K02 *2 High Low K01 *2 High Low K00 *2 High Low DFK03 0 Falling Rising DFK02 0 Falling Rising DFK01 0 Falling Rising DFK00 0 Falling Rising EIK03 0 Enable Mask EIK02 0 Enable Mask EIK01 0 Enable Mask EIK00 0 Enable Mask K10 SCTRG SIOF - 0 Trigger Run - Stop Serial interface clock trigger SIOF R EIK10 0 Enable Mask Interrupt mask register (K10) DFK10 0 Falling Rising Differential register (K10) K10 *2 High Low Input port (K10) IK1 0 Yes No Interrupt factor flag (K10) *4 IK0 0 Yes No Interrupt factor flag (K00-K03) *4 SWIT1 0 Yes No Interrupt factor flag (stopwatch 1 Hz) *4 SWIT0 0 Yes No Interrupt factor flag (stopwatch 10 Hz) *4 R 73H DFK03 DFK02 DFK01 DFK00 R/W 74H EIK03 EIK02 EIK01 EIK00 R/W 75H SCTRG SIOF 77H EIK10 W R IK1 DFK10 R/W IK0 SWIT1 R Comment 1 SWIT0 Input port (K00-K03) Differential register (K00-K03) Interrupt mask register (K00-K03) 7AH *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read S1C62N33 TECHNICAL SOFTWARE EPSON *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary II-69 CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) DFK00-DFK03, DFK10: Interrupt conditions can Differential registers When read-out is "1": (74H, 77H.D1) When read-out is "0": Read-out: be set with these registers. Falling edge Rising edge Available In the K00-K03 pin group, the interrupt is enabled inside K00-K03, but the interrupt factor flag IK0 is set to "1" when the values of the input port data and the differential register changes from matching to non-matching. Note Even though the values of the input port data and the differential register change from non-matching to matching, the interrupt factor flag IK0 will not be set to "1". When the interrupt is enabled for K10, the interrupt factor flag IK1 is set to "1" at the falling edge when the differential register is "1" and at the rising edge when "0". Furthermore, since the SCTRG/SIOF registers are at this address, care needs to be taken when using operational commands (AND, OR, ADD, SUB, etc.). IK0, IK1: These flags indicate the occurrence of input interrupt. Interrupt factor flags When "1" is read out: Interrupt has occurred (7AH.D2 and D3) When "0" is read out: Interrupt has not occurred Writing: Invalid These flags are reset when the software reads them. Note When "noise rejector circuit enable" is selected with the mask option, a maximum delay of 1 ms occurs from the time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. II-70 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) Example of using input ports (1) Reading to input ports Specifications This program reads the input port (K00-K03) data to RAM, YINB. Table 5.7.2 Correspondence of input ports Data Bits Address (K00-K03) and store memory H D3 D2 D1 D0 K03 K02 K01 K00 Then it reads the input port (K10) data to the A register. A register Fig. 5.7.1 Correspondence of input port D3 D2 D1 D0 0 EIK10 DFK10 K10 (K10) and A register Program YINB ; ; EQU H ; Buffer address of K00-K03 input data LD LD LD X,73H Y,YINB MY,MX ; Store K00-K03 data in RAM, YINB ; ; LD LD AND X,77H A,MX A,0001B ; Load K10 data to A register (D0) ; ; Reset all bits except D0 to "0" ; Note S1C62N33 TECHNICAL SOFTWARE When input ports are changed from high to low by pulldown resistor, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. EPSON II-71 CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) (2) Input ports determination per bit Specifications This is an example of whether each terminal is high or low, using computational command on the input port (K00-K03) registers. ON/OFF switching of BZ output, or BZ frequency is controlled according to the result of the determination. Program YDTB ; ; KYTS: ; KYTS2: ; KYTSOF: ; KYTSLP: II-72 EQU H ; Data buffer address LD CP JP CALL X,73H MX,0001B NZ,KYTS2 BZ4 ; If only K00 is high input ; ; ; then sound BZ at 4 kHz LD LD LD XOR JP CALL Y,YDTB A,MY X,73H A,MX Z,KYTSOF BZ2 ; If the value of RAM, YDTB ; ; does not match the value of K00-K03 ; ; ; then sound BZ at 2 kHz LD FAN JP CALL X,73H MX,0001B NZ,KYTSLP BZOF ; If K00 is low input ; ; ; then stop the buzzer LD FAN JP JP X,77H MX,0001B Z,KYTSLP KYTS ; Loop: K10 pin is low or high? ; Low input: Loop ; ; High input: Returns to KYTS EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) (3) Setting differential register and interrupt mask register This program sets the mask registers and differential registers of K00-K03 and K10 as shown in the table below. Specifications Table 5.7.3 Setting of interrupt generation conditions Port K10 K03 K02 K01 K00 Mask Register 1 0 1 1 1 Generation of Interrupt Enabled Disabled Enabled Enabled Enabled Differential 0 1 1 0 1 Generation Conditions Rising edge Don't care Interrupt Generated K1 interrupt Change from Change from Change from High input Low input High input status status status K0 interrupt Program DI ; Disable interrupts ; LD LDPX LD X,74H MX,1101B MX,0111B ; Set the differential registers of K00-K03 ; to "1101", Set the interrupt mask registers of ; K00-K03 to "0111" LD LD X,77H MX,0100B ; Enable interrupt at the rising edge of K10 ; ; ; EI Note S1C62N33 TECHNICAL SOFTWARE ; Enable interrupt Write to the interrupt mask registers (EIK) only in the DI status (interrupt flag = "0"). EPSON II-73 CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) (4) Processing after interrupt generated Specifications This program stores the register data when an interrupt is generated, recovers the register data when the interrupt processing completes, and returns to the main routine. The order of priority for the interrupts is set as shown in the table below, interrupt nesting is disabled, and processing proceeds in descending order of priority. The interrupt processing routine is called with CALL instruction and processed. Table 5.7.4 Order of Priority Order of interrupt priority in program example 1 2 Interrupt Factor Input ports K00-K03 Input port K10 Program ORG 102H ;Interrupt vector address of K0 and K1 interrupts JP INIK ;If the K0 and K1 interrupts are generated, go to "INIK" EQU H ;Buffer address of input interrupt factor flags PUSH PUSH PUSH PUSH PUSH PUSH PUSH XH XL YH YL A B F ;Store the value of X register in stack ; ;Store the value of Y register in stack ; ;Store the value of A register in stack ;Store the value of B register in stack ;Store the value of the flag group in stack LD LD LD X,7AH Y,YIKB MY,MX ;(Reset) the input interrupt factor flags ;and store in buffer ; ; ; ; YIKB ; ; INIK: ; ; II-74 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) FAN JP CALL ; INIK1: LD FAN JP CALL ; INRT: MY,0100B Z,INIK1 IK0 ; If the K0 interrupt factor flag is set ; ; then execute "IK0" Y,YIKB MY,1000B Z,INRT IK1 ; If the K1 interrupt factor flag is set ; ; then execute "IK1" ; See details of "INRT" in the section on "Interrupt routine" in "4.5 Example of Processing Interrupt Vector". Note Read the interrupt factor flags (IK) only in the DI status. (5) Evaluating input pins (K00-K03) Specifications This routine decides which of K00-K03 are high input pins when an interrupt is generated by high input from the input ports (K00-K03). It then executes the corresponding subroutine "K0n". If an interrupt has come from more than one pin, this is treated as "multiple key entry", and subroutine "IK0MLT" is executed. Moreover, in case interrupt is inadvertently generated, the error display process "DSER" will be executed. S1C62N33 TECHNICAL SOFTWARE EPSON II-75 CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) Program ; ; YINB ; ; IK0: DI LD LDPX LD EI X,74H MX,0000B MX,1111B ; Disable interrupts ; Set differential registers of K00-K03 ; to "0000" ; Enable K00-K03 interrupt ; Enable interrupts EQU H ; Read data buffer address LD LD LD LD X,73H Y,YINB MY,MX A,0H ; Store K00-K03 data in RAM, YK0B ; ; ; Preparation: CP JP JP MY,0001B Z,K00 C,DSER CP JP CP JP CP JP MY,0010B Z,K01 MY,0100B Z,K02 MY,1000B Z,K03 ; If only K00 is high input ; then execute K00 input processing "K00", and return to "INIK" ; If not high input pin ; then execute the error display processing "DSER", ; and return to "INIK" ; If only K01 is high input ; then execute K01 input processing "K01", and return to "INIK" ; If only K02 is high input ; then execute K02 input processing "K02", and return to "INIK" ; If only K03 is high input ; then execute K03 input processing "K03", and return to "INIK" JP IK0MLT ; Multiple key entry: Execute multiple key entry processing "IK0MLT", and ; ; return to "INIK" This routine assumes that processing routines "K00"-"K03", "IK0MLT" and "DSER" have been prepared separately. II-76 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) (6) Key matrix (K00-K03 x R00-R03) processing This is the interrupt routine "IK0" which specifies the high input key from the key matrix shown in Figure 5.7.2 and converts it to the key code. Note, however, that the duplicate input process "K0MLT" will be executed when multiple keys are simultaneously pressed, and the no-entry process "K0NOENT" will be executed when interrupt is inadvertently generated. Specifications K02 K03 R03 R02 Fig. 5.7.2 Key matrix (K00-K03 x R00-R03) R01 K01 K00 No.F No.E No.D No.C No.B No.A No.9 No.8 No.7 No.6 No.5 No.4 No.3 No.2 No.1 No.0 Address Data 0 H Input key code (No. 0-F) R00 At first, the key matrix is scanned and then the status of the 16 keys is read into the buffer memory. Next, these 16 data are converted to high input key numbers. Program Table 5.7.5 Contents of RAM and input data buffer DI LD LDPX LD LD LD EI Address 0H 1H 2H 3H X,74H MX,0000B MX,1111B X,7BH MX,1111B Data Bits D3 D2 D1 D0 No.3 No.7 No.B No.F No.2 No.6 No.A No.E No.1 No.5 No.9 No.D No.0 No.4 No.8 No.C ; Disable interrupts ; Set the differential registers DFK00-DFK03 ; to "0000" ; Enable K00-K03 interrupt ; Make R00-R03 high output ; ; Enable interrupts ; ; S1C62N33 TECHNICAL SOFTWARE EPSON II-77 CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) YK0B0: ; ; IK0: EQU 0H ; Input data buffer start address LD LD LD LD LD X,75H MX,0000B X,7BH MX,0001B Y,YK0B0 ; Mask K00-K03 interrupt ; ; Preparation: Make only R00 high output ; Store YK0B0 in Y register ; A,1H A,0FH NZ,IK0SCDLLP X,73H MY,MX X,7BH MX,MX NZ,IK0SCLP ; Scanning loop: Delay: Preparation Delay loop ; ; Store K00-K03 data in the buffer ; Address next buffer ; Shift high output to the left ; ; Continue until all are low ; K0 X,75H MX,1111B X,7BH MX,1111B ; Execute key processing routine "K0" ; Enable K00-K03 interrupt again ; ; Make R00-R03 high output again ; ; Return to "INIK" A,0H Y,YK0B0 MY,0H K0RDCT A,1H Y YL,4H NZ,K0RDLP ; Preparation: Clear A register Store YK0B0 in Y register ; ; Loop: If contents of input data buffer are not "0", ; then add 1 to A register ; and address next buffer ; ; Continue until four times ; A,0H Z,K0N0ENT ; If not high input execute non-input processing "K0NOENT" ; and return to "IK0" ; A,2H NC,K0MLT ; If multiple key entry execute multiple key entry processing "K0MLT" ; and return to "IK0" ; ; IK0SCLP: LD IK0SCDLLP: ADD JP LD LDPY LD ADD JP ; CALL LD LD LD LD RET ; ; K0: LD LD K0RDLP: CP JP ADD K0RDCT: INC CP JP ; CP JP ; CP JP II-78 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) ; ; K0ECLP: ; K0ECLP3: K0ECLP2: K0ECLP1: K0ECLP0: K0ECLP4: LD LD LD A,0H B,0H Y,YK0B0 ; Preparation: Clear A register Clear B register ; Store YK0B0 in Y register ; CP JP JP CP JP CP JP CP JP JP MY,0001B Z,K0ECLP0 C,K0ECLP4 MY,0010B Z,K0ECLP1 MY,0100B Z,KPECLP2 MY,1000B Z,K0ECLP3 K0MLT ; Coding loop: Judge high input pin K00 high input: Go to K0ECLP0 ; Not high input: Go to K0ECLP4 ; K01 high input: ; Go to K0ECLP1 ; K02 high input: ; Go to K0ECLP2 ; K03 high input: ; Go to K0ECLP3 ; Multiple key entry: Execute multiple key entry ; processing "K0MLT", and return to "IK0" ; ADD ADD ADD ADD A,1H A,1H A,1H A,B LD ADD INC CP JP M ,A B,4H Y YL,4H NZ,K0ECLP K03 high input: A 3 ; K02 high input: A 2 ; K01 high input: A 1 ; K00 high input: Add the value of B register ; to A register ; Store result in memory register M ; ; Increase the value of B register by four ; Address next buffer ; Continue until four times ; ; RET ; Return to "IK0" This routine assumes that processing routines "K0NOENT" and "K0MLT" have been prepared separately. Notes 1. When the key scan is executed, the input status changes and the condition is ready for an interrupt factor flag to be set. Hence, the K00-K03 interrupt is masked in advance. 2. When input ports are changed from high to low by pulldown resistance, the fall of the waveform is delayed. Hence, when fetching key scan input, set an appropriate wait time. S1C62N33 TECHNICAL SOFTWARE EPSON II-79 CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) Programming notes (1) When input ports are changed from high to low by pulldown resistor, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time of about 1 ms. (2) Writing to the interrupt mask registers (EIK) can be done only in the DI status (interrupt flag = "0"). Writing during EI status can cause an error. (3) When "noise rejector circuit enable" is selected with the mask option, a maximum delay of 1 ms occurs from the time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. (4) Input interrupt programing related precautions Port K input Active status Active status Differential register Falling edge interrupt Rising edge interrupt Mask register Fig. 5.7.3 Input interrupt timing Factor flag set Not set Factor flag set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flags are set at and , being the interrupt due to the falling edge and the interrupt due to the rising edge. When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status, the factor flag for input interrupt may be set. II-80 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) Therefore, when using the input interrupt, the active status of the input terminal implies input terminal = low status, when the falling edge interrupt is effected and input terminal = high status, when the rising edge interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of shown in Figure 5.7.3. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the timing of shown in Figure 5.7.3. In this case, when the mask registers cleared, then set, you should set the mask register, when the input terminal is in the low status. In addition, when the mask register = "1" and the content of the differential register is rewritten in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite the content of the differential register in the mask register = "0" status. (5) Read out the interrupt factor flag (IK) only in the DI status (interrupt flag = "0"). Read-out during EI status can cause an error. (6) Even when the values of the input data and differential register changes from non-matching to matching, the interrupt factor flag is not set to "1". (7) Since the SCTRG/SIOF registers are at 77H, care needs to be taken when using operational commands (AND, OR, ADD, SUB, etc.). S1C62N33 TECHNICAL SOFTWARE EPSON II-81 CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports) 5.8 I/O Ports The S1C62N33 Series reserves eight bits for general-purpose I/O ports. The I/O ports are the allocated into two lots of four bits, P00-P03 and P10-P13, which can be set to either input mode or output mode. I/O port memory map Table 5.8.1 I/O data memory map (I/O ports) Address *7 D3 Register D2 D1 D0 Name P03 P02 P00 P03 P01 R/W SR *1 1 0 *2 High Low P02 *2 High Low P01 *2 High Low P00 *2 High Low 7DH Comment I/O port (P00-P03) Output latch reset at time of initial reset TMRST SWRUN SWRST IOC0 TMRST Reset Reset - W R/W W R/W SWRUN 0 RUN STOP SWRST Reset Reset - IOC0 0 Output Input P13 *2 High Low P12 *2 High Low P11 *2 High Low P10 *2 High Low - *2 CLKCHG 0 OSC3 OSC1 CPU clock switch OSCC 0 ON OFF OSC3 oscillator ON/OFF IOC1 0 Output Input I/O control register 1 (P10-P13) Clock timer reset *5 Stopwatch counter RUN/STOP 7EH P13 P12 P11 P10 R/W FDH - R CLKCHG OSCC R/W IOC1 Stopwatch counter reset *5 I/O control register 0 (P00-P03) I/O port (P10-P13) Output latch reset at time of initial reset Unused *5 FEH *1 *2 *3 *4 II-82 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports) P00-P03, P10-P13: I/O port data can be read and output data can be set I/O port data through these ports. (7DH, FDH) * When writing data When "1" is written: When "0" is written: High level Low level Port data can be written also in input mode. * When reading data out When "1" is read out: When "0" is read out: High level Low level The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage level being input to the port terminal can be read out; in output mode the output voltage level can be read. Further, the built-in pull-down resistance goes ON during read-out, so that the I/O port terminal is pulled down. Example of program for I/O ports (1) Reading to I/O ports (P00-P03, P10-P13), when OSC1 running Specifications When the CPU clock is OSC1, this routine sets I/O ports (P00-P03) to input mode, and reads the input data to A register. A register Fig. 5.8.1 Correspondence of I/O ports D3 D2 D1 D0 P03 P02 P01 P00 (input) and A register S1C62N33 TECHNICAL SOFTWARE EPSON II-83 CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports) Next it sets P10-P13 to input mode, and reads the input data to RAM, YINB. Finally it sets P00-P03 to output mode, and reads the status of pins P00-P03 into RAM, YDTB. Table 5.8.2 Data Bits Address Correspondence of I/O ports and RAM store data H H D3 D2 D1 D0 P13 P03 P12 P02 P11 P01 P10 P00 Program YINB YDTB ; ; EQU EQU H H ;Data buffer address to read ;Data buffer address LD AND LD LD X,7EH MX,1110B X,7DH A,MX ;Set ports P00-P03 to input mode ; ;Load the input to P00-P03 into A register ; LD AND LD LD LD X,0FEH MX,1110B X,0FDH Y,YINB MY,MX ;Set ports P10-P13 to input mode ; ;Store the input to P10-P13 into RAM, YINB ; ; LD OR LD LD LD X,7EH MX,0001B X,7DH Y,YDTB MY,MX ;Set ports P00-P03 to output mode ; ;Store the pin data of P00-P03 to RAM, YDTB ; ; ; ; Note II-84 When the I/O port is set to output mode and a low-impedance load is connected to the port pins, the value of data written to the register and data read out may differ. EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports) (2) Reading to I/O ports (P00-P03) when OSC3 running Specifications When the CPU clock is OSC3, this routine sets I/O ports (P00-P03) to input mode, and reads the input data to A register. Program LD AND LD LD PINLP: LD ADD JP X,7EH MX,1110B X,7DH B,9H A,MX B,0FH NZ,PINLP ; Set ports P00-P03 to input mode ; ; Read: Preparation ; ; Loop: Load to A register ; ; Repeat 10 times This program example assumes that the pull-down resistor uses the built-in pull-down resistor only, and performs the read operation ten times. Note (3) Writing to I/O ports (P00-P03, P10-P13) Specifications This routine outputs the value of A register to I/O ports (P00-P03), then outputs the value of RAM, YDTB to P10- P13. RAM, YDTB D3 D2 D1 D0 Fig. 5.8.2 Correspondence between I/O ports (output) and A register and RAM S1C62N33 TECHNICAL SOFTWARE EPSON A register D3 D2 D1 D0 P13 register P13 P12 register P12 P11 register P11 P10 register P10 P03 register P03 P02 register P02 P01 register P01 P00 register P00 II-85 CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports) Program YDTB ; EQU H ; Data buffer address LD OR LD LD X,7EH MX,0001B X,7DH MX,A ; Set the ports P00-P03 to output mode ; ; Output the value of A register to P00-P03 ; LD OR LD LD LD X,0FEH MX,0001B X,7DH Y,YDTB MX,MY ; Set the ports P10-P13 to output mode ; ; Output the value of RAM, YDTB to P10-P13 ; ; ; Programming notes (1) When the I/O port is being read out and the pull-down is executed only with the built-in pull-down resistor of the I/O ports, the read-out must be repeated about ten times when the CPU is operating with the OSC3 oscillation circuit. (2) When the I/O port is set to the output mode and the data register has been read, the pin data instead of the register data can be read out. Because of this, if a lowimpedance load is connected and read-out performed, the value of the register and the read-out result may differ. II-86 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) 5.9 Stopwatch Counter The S1C62N33 Series incorporates a 1/100 sec and 1/10 sec stopwatch counter. The stopwatch counter data can be read out by the software. Further, the stopwatch counter can generate 10 Hz (approximated 10 Hz) and 1 Hz interrupts. The stopwatch counter can be used as a separate timer from the clock timer. In particular, digital watch stopwatch functions can be realized easily with software. Stopwatch counter memory map Table 5.9.1 I/O data memory map (stopwatch counter) Address *7 D3 SWL3 Register D2 D1 SWL2 SWL1 Name SWL0 SWL3 0 MSB SWL2 0 Stopwatch counter 1/100 sec (BCD) SWL1 0 SWL0 0 LSB SWH3 0 MSB SWH2 0 Stopwatch counter 1/10 sec (BCD) SWH1 0 SWH0 0 R SR *1 1 0 71H SWH3 SWH2 SWH1 Comment D0 SWH0 R 72H LSB TMRST SWRUN SWRST IOC0 TMRST Reset Reset - W R/W W R/W SWRUN 0 RUN STOP SWRST Reset Reset - IOC0 0 Output Input Clock timer reset *5 Stopwatch counter RUN/STOP 7EH *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read S1C62N33 TECHNICAL SOFTWARE EPSON Stopwatch counter reset *5 I/O control register 0 (P00-P03) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary II-87 CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) SWRST: This bit resets the stopwatch counter. Stopwatch counter reset When "1" is written: Stopwatch counter reset (7EH.D1) When "0" is written: No operation Read-out: Always "0" Example of program for stopwatch counter (1) Resetting, starting and stopping the stopwatch counter Specifications Controlling procedure for the initial start, stop, start, and reset of the stopwatch counter is sequentially indicated. Program LD OR X,7EH MX,0110B ; Initial start the stopwatch counter ; LD OR X,7EH MX,0010B ; Reset the stopwatch counter ; LD AND X,7EH MX,1011B ; Stop the stopwatch counter ; LD OR X,7EH MX,0100B ; Restart the stopwatch counter ; ; ; ; Notes 1. Resetting the stopwatch counter does not affect the clock timer. 2. When the stopwatch counter is reset in RUN status, operation restarts immediately. Also, in STOP status the reset data is maintained. 3. In STOP status, the counter data is maintained until reset or next RUN status occurs. Also, when STOP status changes to RUN status, the data that was maintained can be used for resuming the count. II-88 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) (2) Reading to the stopwatch counter Specifications This program reads the stopwatch counter's 1/100 sec data to A register and the 1/10 sec data to B register. Fig. 5.9.1 Correspondence between stopwatch counter and general-purpose register A register D3 D2 D1 B register D0 SWL3 SWL2 SWL1 SWL0 D3 D2 D1 D0 SWH3 SWH2 SWH1 SWH0 Program LD LD AND X,71H Y,7EH MY,1011B ; Preparation: Store SWL address in X register ; Stop the stopwatch counter ; LDPX LD A,MX B,MX ; Load SWL data into A register ; Load SWH data into B register OR MY,0100B ; Restart the stopwatch counter ; ; Note S1C62N33 TECHNICAL SOFTWARE To prevent erroneous reading during carry from the stopwatch counter's low order column (SWL) to the high order column (SWH), the stopwatch counter is stopped during read. The duration of the stop status must be within 976 s (256 Hz 1/4 cycle). EPSON II-89 CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) Stopwatch interrupt memory map Table 5.9.2 I/O data memory map (stopwatch interrupt) Address *7 D3 HVLD R/W 76H IK1 Register D2 D1 SVDDT SVDON R W IK0 Name SR *1 Comment 1 0 Heavy load Normal Heavy load protection mode register SVD evaluation data (at read-out) SVD ON/OFF (at writing) Interrupt mask register (stopwatch 1 Hz) Interrupt mask register (stopwatch 10 Hz) EISWIT1 EISWIT0 HVLD 0 R/W SVDDT SVDON 0 0 Low voltage ON Normal OFF EISWIT1 0 Enable Mask EISWIT0 0 Enable Mask IK1 0 Yes No Interrupt factor flag (K10) *4 IK0 0 Yes No Interrupt factor flag (K00-K03) *4 SWIT1 0 Yes No Interrupt factor flag (stopwatch 1 Hz) *4 SWIT0 0 Yes No Interrupt factor flag (stopwatch 10 Hz) *4 SWIT1 R D0 SWIT0 7AH *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary SWIT0, SWIT1: These flags indicate the status of the stopwatch counter Interrupt factor flags interrupt. (7AH.D0 and D1) When "1" is read out: Interrupt has occurred When "0" is read out: Interrupt has not occurred Writing: Invalid These flags are reset when read out by the software. Note Regardless of the interrupt mask register setting, these flags are set to "1" by overflow of the corresponding counter. II-90 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) Stopwatch counter timing chart Address Stopwatch counter (SWL) timing chart Register D0 71H (1/100 sec BCD) D1 D2 D3 10 Hz interrupt request Address Register Stopwatch counter (SWH) timing chart D0 72H (1/10 sec BCD) Fig. 5.9.2 Timing chart for stopwatch counter D1 D2 D3 1 Hz interrupt request Interrupts are generated by the overflow of their respective counters ("9" changing to "0"). At this time the corresponding interrupt factor flags (SWIT0, SWIT1) are set to "1". S1C62N33 TECHNICAL SOFTWARE EPSON II-91 CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) Example of program for stopwatch interrupt (1) Combining interrupt factor flag and stopwatch counter Specifications Table 5.9.3 Correspondence between stopwatch counter and store data Table 5.9.4 Timer data by "SWTM" Program Table 5.9.5 Data of memory register This program uses the generation of the stopwatch 1 Hz interrupt factor flag to execute timer display from the 1/100 second to the 10 minute columns. 0H 1H ; SWLP: II-92 D3 D2 D1 D0 SWL3 SWH3 SWL2 SWH2 SWL1 SWH1 SWL0 SWH0 Address 2H 3H 4H 5H Data Single digit seconds column (BCD) Ten's digit seconds column (BCD) Single digit minutes column (BCD) Ten's digit minutes column (BCD) Stores SWIT in the memory register address M and creates data greater than a second digit. Through this, simultaneous display of 1/100 second and 1/10 second stopwatch data, and second/minute data will be possible. Address 0 H YSITB YSWLB ; ; Data Bits Address Data Bits D3 D2 D1 D0 IK1 IK0 SWIT1 SWIT0 EQU EQU 0 H 0H ; SWT interrupt factor flag buffer address ; Stopwatch counter low order data buffer address DI LD OR ; Disable interrupts X,7EH ; Initial start stopwatch counter MX,0010B ; LD LD X,7AH Y,7EH ; Preparation: Store interrupt factor flag address in the X register ; Stop the stopwatch counter EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) AND LD LD LD LDPX LD OR LD LDPX LD MY,1011B A,MX M ,A X,71H A,MX B,MX MY,0100B X,YSWLB MX,A MX,B ; ; Store stopwatch interrupt factor flags ; in the memory register M ; Load SWL data to A register ; Load SWH data to B register ; ; Restart the stopwatch counter ; Store the value of the A register in RAM, YSWLB ; Store the value of the B register in RAM, YSWLB+1 ; LD FAN JP CALL X,YSITB MX,0010B Z,SWDS SWTM ; If the ST1Hz interrupt factor flag is set ; ; ; then execute stopwatch timer "SWTM" CALL JP DSSW SWLP ; Executes the stopwatch display routine "DSSW" ; Back to SWLP ; ; SWDS: 1. Regardless of the setting of the mask register (EISWIT), the interrupt factor flag (SWIT) is set to "1" by overflow of the counter. Therefore, "interrupt generation" is not used. Nevertheless, the factor flag reset is executed, so the DI status must be in effect. Notes 2. The stopwatch counter is stopped when being read to, so as to prevent an error occurring when the counter is performing carry from the low order column (SWL) to the high order column (SWH). Stopwatch timer "SWTM" Reference SWTM: LD CALZ RET CALZ RET RET X,YSWL+2 ; Increment the seconds by 1 CT60 ; ; No carry up to minutes column: Return to parent routine CT60 ; Carry to higher column: Increment the minutes by 1 ; No carry up to hours column: Returns to parent routine ; Carry to higher column: No carry up to hours column, ; return to parent routine * For details about "CT60", see page 63, "Example of using timer interrupt". S1C62N33 TECHNICAL SOFTWARE EPSON II-93 CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) (2) Setting stopwatch interrupts Specifications Program In the interrupt disabled status, this program enables stopwatch 1 Hz interrupt only, and then enables interrupts. DI LD LD EI X,76H MX,0010B ; ; ; ; Disable interrupts Enable stopwatch 1 Hz interrupt and mask 10 Hz interrupt Enable interrupts 1. Write to the interrupt mask registers (EISWIT) only in the DI status. Notes 2. This program example avoids using arithmetic instructions to write to the interrupt mask flag (EISWIT), and assumes that SVDON is fixed at "0". (3) Processing after interrupt is generated Specifications Table 5.9.6 Order of priority in program example II-94 This routine stores the register data when an interrupt occurs, recovers the register data when the interrupt processing completes, and returns to the main routine. The order of priority for setting the interrupts is shown in the table below. Nesting of interrupts cannot be done. Processing proceeds in descending order of priority. Further, the interrupt processing routine is called with CALL instruction and processed. Order of Priority Interrupt Factor 1 2 Stopwatch 10 Hz Stopwatch 1 Hz EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) Program ORG 108H ; Vector address of stopwatch interrupts JP INST ; If SWT interrupts occur, go to "INST" EQU H ; Buffer address of stopwatch interrupt factor flags PUSH PUSH PUSH PUSH PUSH PUSH PUSH XH XL YH YL A B F ; Store value of X register in stack ; ; Store value of Y register in stack ; ; Store value of A register in stack ; Store value of B register in stack ; Store value of flag group in stack LD LD LD LD AND X,7AH Y,YSITB MY,MX X,76H MY,MX ; (Reset and) store ; stopwatch interrupt factor flags ; in the buffer ; Mask the stopwatch interrupt factor flags ; by value of stopwatch interrupt mask register FAN JP CALL MY,0001B Z,INSIT1 SIT0 ; If the ST10Hz interrupt factor flag is set ; and enabled ; then execute "SIT0" MY,0010B Z,INRT SIT1 ; If the ST1Hz interrupt factor flag is set ; and enabled ; then execute "SIT1" ; ; ; YSITB ; ; INST: ; ; ; INSIT1: FAN JP CALL ; INRT: For details of "INRT", see "4.5 Example of Interrupt Vector Processing". Notes S1C62N33 TECHNICAL SOFTWARE 1. Read the interrupt factor flags (SWIT) only in the DI status. 2. Regardless of the setting of the mask register (EISWIT), the interrupt factor flag (SWIT) is set to "1" when the corresponding counter overflows. Therefore, the presence of each interrupt factor is judged according to the result of ANDing the factor flag stored in the buffer with the mask register. EPSON II-95 CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) Programming notes (1) Correct read-out is impossible when there is a carry from the low order bit (SWL) to the high order bit (SWH). Hence, when reading out the counter data in the RUN status, the counter must first be stopped, and then the RUN status returned again. Also, the duration of the above STOP status must be within 976 s (256 Hz 1/4 cycle). (2) Resetting the clock timer has no effect on the stopwatch counter, and vice versa. (3) Writing to the interrupt mask registers (EISWIT) can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause an error. Also, when using arithmetic instructions (AND, OR, ADD, SUB, etc.), pay attention to the control of SVD. (4) Read-out of the interrupt factor flag (SWIT) must be done only in the DI status (interrupt flag = "0"). Read-out during EI status will cause an error. (5) Regardless of the setting of the mask register (EISWIT), the interrupt factor flag (SWIT) is set to "1" when the corresponding counter overflows. II-96 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Event Counter) 5.10 Event Counter The S1C62N33 Series houses an event counter that counts the clock signals input from outside. The event counter is configured of an eight-bit binary counter (up counter). The counter data can be read out by software. Event counter memory map Table 5.10 I/O data memory map (event counter) Address *7 D3 EV03 Register D2 D1 EV02 EV01 D0 Name EV00 EV03 0 EV02 0 EV01 0 EV00 0 EV07 0 EV06 0 EV05 0 EV04 0 R SR *1 1 Event counter low order (EV00-EV03) F8H EV07 EV06 EV05 EV04 R Event counter high order (EV04-EV07) F9H - EVRUN - EVRST - *2 R R/W R W EVRUN 0 - *2 EVRST Reset Comment 0 Unused *5 RUN STOP Event counter RUN/STOP FCH *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read S1C62N33 TECHNICAL SOFTWARE EPSON Unused *5 Reset - Event counter reset *5 *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary II-97 CHAPTER 5: PERIPHERAL CIRCUITS (Event Counter) EVRST: This it the register for resetting the event counter. Event counter reset When "1" is written: Event counter reset (FCH.D0) When "0" is written: No operation Read-out: Always "0" Example of program for event counter (1) Resetting, starting, and stopping the event counter Specifications Controlling procedure for the initial start, stop, start, and reset of the event counter is sequentially indicated. Program LD LD X,0FCH MX,0101B ; Initial start event counter ; LD LD X,0FCH MX,0000B ; Stop event counter ; LD LD X,0FCH MX,0100B ; Start event counter ; LD LD X,0FCH MX,0001B ; Reset event counter ; ; ; ; II-98 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Event Counter) (2) Reading event counter Specifications This program reads the four high order bits of the event counter to B register, and the four low order bits to A register. Fig. 5.10 Correspondence between event counter and generalpurpose register A register B register D3 D2 D1 D0 D3 D2 D1 D0 EV03 EV02 EV01 EV00 EV07 EV06 EV05 EV04 Program LD LD LD LD CP JP LD LD X,0F8H Y,0F9H B,MY A,MX MY,B Z,EV A,MX B,MY ; First reading: Preparation Load EV04-EV07 data to B register ; ; Load EV00-EV03 data to A register ; ; If there is a carry to EV04-EV07 ; ; Redo read: EV00-EV03 data EV04-EV07 data ; ; EV : . . . Note To prevent erroneous reading when there is a carry from the event counter's low order data (EV00-EV03) to the high order data (EV04-EV07), the counter data is read out multiple times and compared. Programming note To prevent erroneous reading of the event counter data, read out the counter data multiple times for comparison, and use the matching data for the result. S1C62N33 TECHNICAL SOFTWARE EPSON II-99 CHAPTER 5: PERIPHERAL CIRCUITS (Analog Comparator) 5.11 Analog Comparator The S1C62N33 Series incorporates an MOS input analog comparator. This analog comparator, which has two differential input terminals (inverted input terminal AMPM, noninverted input terminal AMPP), can be used for general purposes. To keep current consumption low, the analog comparator circuit can be switched ON and OFF by the software. Analog comparator memory map Table 5.11 I/O data memory map (analog comparator) Address *7 D3 - Register D2 D1 - R AMPDT SR *1 Comment D0 Name AMPON - *2 Unused *5 R/W - *2 Unused *5 AMPDT 1 +>- ->+ Analog comparator data AMPON 0 ON OFF Analog comparator ON/OFF 1 0 F7H *1 *2 *3 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary AMPDT: Reads out the output from the analog comparator. Analog comparator data When "1" is read out: AMPP (+) > AMPM (-) (F7H.D1) When "0" is read out: AMPP (+) < AMPM (-) Example of program Note To keep the current consumption low, set the analog comparator to OFF when it is not needed. for analog comparator II-100 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Analog Comparator) (1) Setting the analog comparator ON and OFF, and reading data (when OSC1 is running) Specifications With OSC1 as the CPU clock, this program sets the AMP circuit to ON, allows a delay, reads the result into A register, and sets the circuit to OFF. Program LD LD LD AMDLLP: ADD JP LD LD Note The delay is made to allow the output to stabilize. X,0F7H MX,0001B A,0FH A,0FH NZ,AMDLLP A,MX MX,1110B ; AMP circuit ON ; ; Delay: Preparation Delay loop ; ; ; Load the result to A register ; AMP circuit OFF (2) Setting the analog comparator ON and OFF, and reading data (when OSC3 is running) Specifications With OSC3 as the CPU clock, this program sets the AMP circuit to ON, allows a delay, reads the result into A register, and sets the circuit to OFF. Program LD LD LD AMDLLP: ADD JP LD AND Note The delay is made to allow the output to stabilize. Programming notes X,0F7H MX,0001B Y,54H Y,0FH NZ,AMDLLP A,MX MX,1110B ; AMP circuit ON ; ; Delay: Preparation ; Delay loop ; ; Load the result to A register ; AMP circuit OFF (1) To keep the current consumption low, set the analog comparator to OFF when it is not needed. (2) After AMPON is set to "1", allow a wait of at least 3 ms for the analog comparator's operation to stabilize before reading out the analog comparator's output data AMPDT. S1C62N33 TECHNICAL SOFTWARE EPSON II-101 CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface) 5.12 Serial Interface (SIN, SOUT, SCLK, SIOF) Serial interface memory map Table 5.12.1 I/O data memory map (serial interface) Address *7 D3 Register D2 D1 SD3 SD2 SD1 Name SR *1 SD0 SD3 x *3 SD2 x *3 SD1 x *3 SD0 x *3 SD7 x *3 SD6 x *3 SD5 x *3 SD4 x *3 SCS1 1 *6 *6 SCS0 1 *6 *6 SE2 0 Rising Falling Clock edge selection register EISIO 0 Enable Mask Interrupt mask register (serial interface) - *2 Unused *5 - *2 Unused *5 - *2 Unused *5 ISIO 0 Yes No K10 SCTRG SIOF - 0 Trigger RUN - STOP Serial interface clock trigger SIOF R EIK10 0 Enable Mask Interrupt mask register (K10) DFK10 0 Falling Rising Input comparison register (K10) K10 *2 High Low R/W F0H SD7 SD6 SD5 SD4 R/W 1 0 Serial interface data regsiter Low order (SD0-SD3) Serial interface data regsiter High order (SD4-SD7) F1H SCS1 SCS0 SE2 Comment D0 EISIO R/W Clock mode selection register (SCS0, SCS1) F2H - - - ISIO R F3H SCTRG SIOF 77H *1 *2 *3 *4 II-102 W R EIK10 DFK10 R/W Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read EPSON Interrupt factor flag (serial interface) *4 Input port (K10) *5 Always "0" when being read *6 Refer to main manual *7 Page switching in I/O memory is not necessary S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface) SD0-SD3, SD4-SD7: These registers are used for writing and reading serial data. Serial interface data * When writing data registers When "1" is written: High level (F0H, F1H) When "0" is written: Low level These registers write serial data to be output from the SOUT pin. The serially converted data is output from the SOUT pin as high (VDD) when the bit is set to "1" and as low (VSS) when the bit is set to "0". * When reading data When "1" is read out: High level When "0" is read out: Low level Input serial data is read out from the SIN pin. These registers are loaded with data that has been parallel converted so that the high (VDD) level bit input from the SIN pin is "1", and the low (VSS) bit is "0". Perform data reading only while serial interface is halted (i.e., the synchronous clock is neither being input or output). Data is undefined in this register at initial reset. SCS1, SCS0: The synchronous clock (SCLK) of the serial interface can be Clock mode selection selected with these registers. register (F2H.D3 and D2) SCS1 SCS0 Mode Synchronous Clock Table 5.12.2 0 0 Synchronous clock selection 0 1 1 1 0 1 Master mode Slave mode CLK CLK/2 CLK/4 External clock CLK: system clock The synchronous clock (SCLK) can be selected from among the four types listed above, namely from three types of internal clock and one external clock. At initial reset, the external clock is selected. S1C62N33 TECHNICAL SOFTWARE EPSON II-103 CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface) SE2: Timing for reading in the serial data input from the SIN pin Clock edge selection can be selected with these registers. register When "1" is written: SCLK rising edge (F2H.D1) When "0" is written: SCLK falling edge Read-out: Valid These registers enable selection of whether to perform reading to the serial input data register (SD0-SD7) at the SCLK signal's rising edge (when "1" is written) or falling edge (when "0" is written). Pay attention if the synchronous clock goes into reverse phase (SCLKSCLK) through the mask option. SCLK rising = SCLK falling, SCLK falling = SCLK rising When the internal clock is selected as the synchronous clock (SCLK), a hazard occurs in the synchronous clock (SCLK) when data is written to register SE2. The timing for reading in the input data can be selected, but the output timing for the output data is fixed to the SCLK rising edge. At initial reset, SCLK falling (SE2 = "0") is selected. EISIO: The interrupt mask from Interrupt mask register this register. (F2H.D0) When "1" is written: When "0" is written: Read-out: the serial interface can be set with Enabled Masked Valid At initial reset, the mask (EISIO = "0") is selected. II-104 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface) ISIO: This flag indicates the status of the interrupt from the serial Interrupt factor flag interface. (F3H.D0) When "1" is read out: Interrupt has occurred When "0" is read out: Interrupt has not occurred Writing: Invalid By reading out this interrupt factor flag, the software can judge whether an interrupt from the serial interface has occurred. The interrupt factor flag is reset when it has been read out. Note, however, that even if the interrupt is masked, this flag will be set to "1" after the 8 bits data input/output. The flag can be read out only when in the DI status (interrupt flag = "0"). At initial reset, this flag is set to "0". SCTRG: This is the trigger for starting input or output of the synClock trigger chronous clock (SCLK). (77H.D3) When "1" is written: Trigger input When "0" is written: No operation Read-out: Always "0" When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK) input/output is started. As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Whenever the serial interface is in the RUN status, apply this trigger input once only. Refrain from performing trigger input multiple times, as this leads to malfunctioning. S1C62N33 TECHNICAL SOFTWARE EPSON II-105 CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface) Further, if the synchronous clock (SCLK) is the external clock, start the external clock input after the trigger input. SCTRG resides in the same bit at the same address as SIOF, and one or the other is selected by write or read operation. When writing a "1" to SCTRG use the OR command, and when writing a "0" use the AND command. No other commands should be used for this purpose. SIOF: Indicates the running status of the serial interface. Special output port data When "1" is read out: RUN status (77H.D3) When "0" is read out: STOP status Writing: Invalid The RUN status is indicated from the end of writing "1" to SCTRG through to the end of serial data input/output. Example of program for serial interface (1) Fetching data used by the internal clock Specifications This program outputs to the outside a clock having the same frequency as the CPU system clock, and takes serial data into the general registers (A, B). Figure 5.12.1 shows an example of data being taken in when the mask option has been used to select SCLK = positive logic, permutation = MSB first. SCLK SIN Fig. 5.12.1 Example of fetching serial interface data II-106 (SE2=0) B register D3 1 D2 0 EPSON D1 1 A register D0 0 D3 0 D2 1 D1 0 D0 1 S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface) Program ZK10 ZR1 ZSDL ZSDH ZSC XSCTRG XSIOF XSCS ; EQU EQU EQU EQU EQU EQU EQU EQU 077H 077H 0F0H 0F1H 0F2H 1000B 1000B 1100B LD AND X,ZSC ;Select SCS address by X register MX,XSCS XOR 0FH ;Set internal clock mode ; ( CLK/1 ) LD LD X,ZSDH A,MX ;Select SD47 address by X register ;Initialize circuit LD OR X,ZK10 MX,XSCTRG ;Select SCTRG address by X register ;Shot SCTRG LD FAN JP X,ZR1 MX,XSIOF NZ,WAIT ;Select SIOF address by X register ;Check SIO status ;If SIO running then loop LD LDPX LD X,ZSDL A,MX B,MX ;Select SD03 address by X register ;Read SD0-SD3 data to A register ;Read SD4-SD7 data to B register ; ; ; WAIT ; S1C62N33 TECHNICAL SOFTWARE EPSON II-107 CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface) (2) Output of data used by the external clock This program synchronizes SCLK with the external clock it is assigned to, and sends the contents of the general registers (A, B) to the outside. Figure 5.12.2 shows an output example when the mask option has been used to select SCLK = positive logic, permutation = MSB first. Specifications B register D3 1 D2 0 D1 1 A register D0 0 D3 0 D2 1 D1 0 D0 1 SIOF Fig. 5.12.2 Example of output of serial SCLK interface data SOUT Program ZK10 ZSDL ZSC XSCTRG XSCS ; EQU EQU EQU EQU EQU 077H 0F0H 0F2H 1000B 1100B LD OR X,ZSC MX,XSCS ;Select SCS address by X register ;Set external clock mode LD LDPX LD X,ZSDL MX,A MX,B ;Select SD03 address by X register ;Write A register to SD0-SD3 ;Write B register to SD4-SD7 LD OR X,ZK10 MX,XSCTRG ;Select SCTRG address by X register ;Shot SCTRG ; ; II-108 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface) Programming notes (1) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fosc1 fosc3) while the serial interface is operating. (2) Perform data writing/reading to data registers SD0-SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). (3) As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. (4) If the bit data of SE2 changes while SCLK is in the master mode, a hazard will be output to the SCLK pin. If this poses a problem for the system, be sure to set the SCLK to the external clock mode if the bit data of SE2 is to be changed. (5) Reading the interrupt factor flag (ISIO) can be done only in the DI status (interrupt flag = "0"). Reading during EI status (interrupt flag = "1") will cause malfunction. (6) Writing the interrupt mask register (EISIO) can be done only in the DI status (interrupt flag = "0"). Writing during EI status (interrupt flag = "1") will cause malfunction. (7) SCTRG resides in the same bit at the same address as SIOF, and one or the other is selected by write or read operation. When writing a "1" to SCTRG use the OR command, and when writing a "0" use the AND command. No other commands should be used for this purpose. S1C62N33 TECHNICAL SOFTWARE EPSON II-109 CHAPTER 6: INITIAL RESET CHAPTER 6 INITIAL RESET Initial reset is required to initialize the circuits in the S1C62N33 Series. 6.1 Internal Status at Initial Reset At initial reset, the CPU can be initialized in the following ways. Table 6.1.1 Initial setting values (1) CPU Core Signal Number of Bits Setting Value Name Program counter step Program counter page PCS PCP 8 4 00H 1H New page pointer Stack pointer NPP SP 4 8 1H Undefined Index register IX Index register IY IX IY 9 9 Undefined Undefined Register pointer General-purpose register A RP A 4 4 Undefined Undefined General-purpose register B Interrupt flag B I 4 1 Undefined 0 Decimal flag Zero flag D Z 1 1 Undefined Undefined Carry flag C 1 Undefined Further, data memory is initialized as below. Table 6.1.2 Peripheral Circuits Initial setting values (2) Name RAM Segment data Other peripheral circuit Number of Bits Setting Value 256 x 4 Undefined 40 x 4 - Undefined *1 *1 See "3.4 I/O Memory Map". Note Undefined setting values must be initialized by the program. II-110 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 6: INITIAL RESET 6.2 Example of Initialize Program After initial reset, and the CPU and data memory are reset as shown on the previous page, this program starts from address 100H (reset vector). Then the initialize program's label (INIT) is defined in the reset vector, and the program executes the initialize operation. Reset vector ORG 100H ; Reset vector address JP INIT ; Start program ; Specifications Table 6.2 Result of initializing internal circuits This program defines the bottom address of Stack pointer, clears RAM (including segment data) and resets Flag group, in that order. Internal Circuit Setting Value General-purpose register A Stack pointer SP Interrupt flag IF Decimal flag DF Zero flag ZF Carry flag CF RAM data (000H-06FH) (080H-09FH) (100H-16FH) Segment data (0C0H-0EFH) 0H 0A0H 0 0 0 0 0H 0H 0H 0H * The values for the B, X and Y registers are undefined. S1C62N33 TECHNICAL SOFTWARE EPSON II-111 CHAPTER 6: INITIAL RESET Program INIT: LD LD LD LD LD LD A,0 XP,A A,0AH SPH,A A,0H SPL,A ; ; Page 0 selected ; Set Stack pointer bottom as 0A0H ; ; ; X,00H MX,0H XH,7H C,CLRLP1 ; Clear RAM area 000H-06FH ; Clear MX, and increment X register ; Continue until X register become 70H ; X,80H MX,0H XH,0FH C,CLRLP2 ; Clear RAM area 080H-0EFH ; Clear MX, and increment X register ; Continue until X register becomes F0H ; A,1 XP,A X,00H MX,0H XH,7H C,CLRLP3 ; ; Page 1 selected ; Clear RAM area 100H-16FH ; Clear MX, and increment X register ; Continue until X register becomes 70H ; F,0000B ; Reset Flag group ; LD CLRLP1: LDPX CP JP ; LD CLRLP2: LDPX CP JP ; LD LD LD CLRLP3: LDPX CP JP ; RST Note II-112 This program is the basic initialize program for the S1C62N33 Series. When this program is executed, the internal circuits are initialized as shown in Table 6.2. When using the program example, be sure to add any setting items necessary for your applications. EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 7: SUMMARY OF NOTES CHAPTER 7 SUMMARY OF NOTES - Program Memory (1) To use a branch instruction such as "JP" to branch outside the page of that instruction, the page to branch to must first be set with the "PSET" instruction; then the branch instruction can be executed. Be sure to execute the branch instruction as the step immediately following "PSET". (2) Immediately after the "PSET" instruction mentioned in above item (1), it will automatically be DI state until execution of the branch instruction is completed. (3) When moving from the last step of one page to the top step of the next page, there is no need to execute branch instructions such as "PSET" and "JP". (4) With just the one instruction "CALZ", subroutines on page 0 can be called from any page without using "PSET". Programming can be done efficiently if universal subroutines are located on page 0. (5) If the "PSET" instruction is executed immediately before "CALZ", "CALZ" will have priority and data set with "PSET" will be ignored. (6) The program memory can be used as a data table through the table look-up instruction. - Data Memory (1) Part of the data memory is used as stack area for subroutine calls and register storage, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words of the stack area. (3) When addresses 40H-6FH have been allocated as segment memory by option selection, 48 words of RAM can be used as segment area. (4) Memory is not mounted in unused area within the memory map and in memory area not indicated in this manual. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. S1C62N33 TECHNICAL SOFTWARE EPSON II-113 CHAPTER 7: SUMMARY OF NOTES - Interrupt and HALT (1) Write to the interrupt mask registers only in the DI status (interrupt flag = "0"). Writing in the EI status can cause an error. (2) Even when the interrupt mask registers (ETI, EISWIT) are set to "0", the interrupt factor flags (TI, SWIT) of the clock timer and stopwatch counter can be set when the timing conditions are established. (3) When an interrupt is generated, three words of RAM are used; also, it takes 12 cycles of the CPU system clock until the value of the interrupt vector is set in the program counter. (4) When an interrupt occurs, the DI status (interrupt flag = "0") comes into effect automatically. (5) Read the interrupt factor flags only in the DI status (interrupt flag = "0"). Reading out in the EI status can cause an error. - Watchdog Timer When the watchdog timer is used for the reset function, the software must reset the watch dog timer within 3 seconds. In this case, timer data (WD0-WD2) cannot be used for timer applications. - OSC3 (1) It takes at least 5 ms from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 ms have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (2) When switching the clock from OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. (3) To lessen current consumption, keep OSC3 oscillation OFF except when the CPU must be run at high speed. Also, with S1C62N33/62L33, keep OSCC fixed to "0". II-114 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 7: SUMMARY OF NOTES - SVD Circuit and Heavy Load Protection Functions (1) It takes 100 s from the time the SVD circuit goes ON until a stable result is obtained. For this reason, keep the following software notes in mind: When the CPU system clock is fosc1 1. When detection is done at HVLD After writing "1" on HVLD, read the SVDDT after 1 instruction has passed. 2. When detection is done at SVDON After writing "1" on SVDON, write "0" after at least 100 s has lapsed (possible with the next instruction) and then read the SVDDT. When the CPU system clock is fosc3 (in case of S1C62A33 only) 1. When detection is done at HVLD After writing "1" on HVLD, read the SVDDT after 0.6 sec has passed. (HVLD holds "1" for at least 0.6 sec) 2. When detection is done at SVDON Before writing "1" on SVDON, write "1" on HVLD first; after at least 100 s has lapsed after writing "1" on SVDON, write "0" on SVDON and then read the SVDDT. (2) To reduce current consumption, set the SVD operation to OFF unless otherwise necessary. (3) SVDON resides in the same bit at the same address as SVDDT, and one or the other is selected by write or read operation. When writing a "1" to SVDON use the OR command, and when writing a "0" use the AND command. No other commands should be used for this purpose. (4) Select one of the following software processing to return to the normal mode after a heavy load has been driven in the heavy load protection mode (S1C62L33). After heavy load drive is completed, return to the normal mode after at least one second has elapsed. After heavy load drive is completed, switch SVD ON and OFF (at least 100 s is necessary for the ON status) and then return to the normal mode. S1C62N33 TECHNICAL SOFTWARE EPSON II-115 CHAPTER 7: SUMMARY OF NOTES (5) To reduce current consumption, be careful not to set the heavy load protection mode with the software unless otherwise necessary. - Output Ports When BZ has been selected by the output application for pin R13, the mask option decides whether output is controlled by register R13, or by register R10 simultaneously with BZ. In particular, when BZ output is under R10 control, register R13 can be used as a 1-bit general register for read/write. Data in this register has no affect on BZ output (output of pin R13). - LCD Driver (1) When 40H-6FH is selected for the segment data memory, the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the segment data memory by executing initial processing. (2) When C0H-EFH is selected for the segment data memory, that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). (3) Data output from segment pins selected as DC output will be the data corresponding to the COM0 pins. (4) When performing step adjustment with the static drive, set the segment data so that all LCD segments are lit. - Clock Timer (1) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Consequently, perform flag read-out (reset the flag) when necessary at reset. (2) The watchdog timer may be counted up at clock timer reset. (3) Resetting the clock timer has no effect on the stopwatch counter, and vice versa. (4) Writing to the interrupt mask register (ETI) can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause an error. II-116 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 7: SUMMARY OF NOTES (5) Read out the interrupt flag (TI) only during the DI status (interrupt flag = "0"). Read-out during EI status will cause an error. (6) Regardless of the setting of the interrupt mask register (ETI), the interrupt factor flag (TI) is set to "1" at the falling edge of the corresponding signal. - Input Ports (1) When input ports are changed from high to low by pulldown resistor, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time of about 1 ms. (2) Writing to the interrupt mask registers (EIK) can be done only in the DI status (interrupt flag = "0"). Writing during EI status can cause an error. (3) When "noise rejector circuit enable" is selected with the mask option, a maximum delay of 1 ms occurs from the time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. (4) Input interrupt programing related precautions Port K input Active status Active status Differential register Falling edge interrupt Rising edge interrupt Mask register Fig. 7.1 Input interrupt timing S1C62N33 TECHNICAL SOFTWARE Factor flag set Not set Factor flag set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flags are set at and , being the interrupt due to the falling edge and the interrupt due to the rising edge. EPSON II-117 CHAPTER 7: SUMMARY OF NOTES When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status, the factor flag for input interrupt may be set. Therefore, when using the input interrupt, the active status of the input terminal implies input terminal = low status, when the falling edge interrupt is effected and input terminal = high status, when the rising edge interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of shown in Figure 7.1. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the timing of shown in Figure 7.1. In this case, when the mask registers cleared, then set, you should set the mask register, when the input terminal is in the low status. In addition, when the mask register = "1" and the content of the differential register is rewritten in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite the content of the differential register in the mask register = "0" status. (5) Read out the interrupt factor flag (IK) only in the DI status (interrupt flag = "0"). Read-out during EI status can cause an error. (6) Even when the values of the input data and differential register changes from non-matching to matching, the interrupt factor flag is not set to "1". II-118 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 7: SUMMARY OF NOTES - I/O Ports (1) When the I/O port is being read out and the pull-down is executed only with the built-in pull-down resistor of the I/O ports, the read-out must be repeated about ten times when the CPU is operating with the OSC3 oscillation circuit. (2) When the I/O port is set to the output mode and the data register has been read, the pin data instead of the register data can be read out. Because of this, if a low-impedance load is connected and read-out performed, the value of the register and the read-out result may differ. - Stopwatch Counter (1) Correct read-out is impossible when there is a carry from the low order bit (SWL) to the high order bit (SWH). Hence, when reading out the counter data in the RUN status, the counter must first be stopped, and then the RUN status returned again. Also, the duration of the above STOP status must be within 976 s (256 Hz 1/4 cycle). (2) Resetting the clock timer has no effect on the stopwatch counter, and vice versa. (3) Writing to the interrupt mask registers (EISWIT) can be done only in the DI status (interrupt flag = "0"). Writing during EI status will cause an error. Also, when using arithmetic instructions (AND, OR, ADD, SUB, etc.), pay attention to the control of SVD. (4) Read out of the interrupt factor flag (SWIT) must be done only in the DI status (interrupt flag = "0"). Read-out during EI status will cause an error. (5) Regardless of the setting of the mask register (EISWIT), the interrupt factor flag (SWIT) is set to "1" when the corresponding counter overflows. - Event Counter S1C62N33 TECHNICAL SOFTWARE To prevent erroneous reading of the event counter data, read out the counter data multiple times for comparison, and use the matching data for the result. EPSON II-119 CHAPTER 7: SUMMARY OF NOTES - Analog Comparator (1) To keep the current consumption low, set the analog comparator to OFF when it is not needed. (2) After AMPON is set to "1", allow a wait of at least 5 ms for the analog comparator's operation to stabilize before reading out the analog comparator's output data AMPDT. - Serial Interface (1) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fosc1 fosc3) while the serial interface is operating. (2) Perform data writing/reading to data registers SD0-SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). (3) As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. (4) If the bit data of SE2 changes while SCLK is in the master mode, a hazard will be output to the SCLK pin. If this poses a problem for the system, be sure to set the SCLK to the external clock mode if the bit data of SE2 is to be changed. (5) Reading the interrupt factor flag (ISIO) can be done only in the DI status (interrupt flag = "0"). Reading during EI status (interrupt flag = "1") will cause malfunction. (6) Writing the interrupt mask register (EISIO) can be done only in the DI status (interrupt flag = "0"). Writing during EI status (interrupt flag = "1") will cause malfunction. (7) SCTRG resides in the same bit at the same address as SIOF, and one or the other is selected by write or read operation. When writing a "1" to SCTRG use the OR command, and when writing a "0" use the AND command. No other commands should be used for this purpose. II-120 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 8: CPU CHAPTER 8 CPU The S1C62N33 Series employs the four-bit core CPU S1C6200 for the CPU, so that register configuration, instructions and so forth are virtually identical to those in other family processors using the S1C6200. Refer to "S1C6200/6200A Core CPU Manual" for details about the S1C6200. 8.1 S1C62N33 Restrictions Note the following points with regard to the S1C62N33 Series: (1) The SLEEP operation is not assumed, so that SLP instruction cannot be used. (2) Because the ROM capacity is 3,072 words, bank bits are unnecessary and PCB and NBP are not used. (3) Since RAM is set for up to 1 page, only the subordinate 1 bit of the page section of the index register which specifies address is effective. (The 3 superordinate bits are ignored.) 8.2 Instruction Set The S1C62N33 Series has some 108 types of instructions including arithmetical instructions. All instructions consist of one word (= 12 bits). The following pages contain tables of the instruction set of the 4-bit Core CPU, S1C6200. S1C62N33 TECHNICAL SOFTWARE EPSON II-121 CHAPTER 8: CPU Table 8.2(a) Instruction set (1) Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation p 1 1 1 0 0 1 0 p4 p3 p2 p1 p0 5 NBP p4, NPP p3~p0 s 0 0 0 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 C, s 0 0 1 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if C=1 NC, s 0 0 1 1 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if C=0 Z, s 0 1 1 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if Z=1 NZ, s 0 1 1 1 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if Z=0 JPBA 1 1 1 1 1 1 1 0 1 0 0 0 5 PCB NBP, PCP NPP, PCSH B, PCSL A CALL s 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0 7 M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1 CALZ s 0 1 0 1 s7 s6 s5 s4 s3 s2 s1 s0 7 RET 1 1 1 1 1 1 0 1 1 1 1 1 7 RETS 1 1 1 1 1 1 0 1 1 1 1 0 12 RETD l 0 0 0 1 l7 l6 l5 l4 l3 l2 l1 l0 12 System NOP5 1 1 1 1 1 1 1 1 1 0 1 1 5 No operation (5 clock cycles) control NOP7 1 1 1 1 1 1 1 1 1 1 1 1 7 No operation (7 clock cycles) instructions HALT 1 1 1 1 1 1 1 1 1 0 0 0 5 Halt (stop clock) X 1 1 1 0 1 1 1 0 0 0 0 0 5 X X+1 operation Y 1 1 1 0 1 1 1 1 0 0 0 0 5 Y Y+1 instructions LD X, x 1 0 1 1 x7 x6 x5 x4 x3 x2 x1 x0 5 XH x7~x4, XL x3~x0 Y, y 1 0 0 0 y7 y6 y5 y4 y3 y2 y1 y0 5 YH y7~y4, YL y3~y0 XP, r 1 1 1 0 1 0 0 0 0 0 r1 r0 5 XP r XH, r 1 1 1 0 1 0 0 0 0 1 r1 r0 5 XH r XL, r 1 1 1 0 1 0 0 0 1 0 r1 r0 5 XL r YP, r 1 1 1 0 1 0 0 1 0 0 r1 r0 5 YP r YH, r 1 1 1 0 1 0 0 1 0 1 r1 r0 5 YH r YL, r 1 1 1 0 1 0 0 1 1 0 r1 r0 5 YL r r, XP 1 1 1 0 1 0 1 0 0 0 r1 r0 5 r XP r, XH 1 1 1 0 1 0 1 0 0 1 r1 r0 5 r XH r, XL 1 1 1 0 1 0 1 0 1 0 r1 r0 5 r XL r, YP 1 1 1 0 1 0 1 1 0 0 r1 r0 5 r YP r, YH 1 1 1 0 1 0 1 1 0 1 r1 r0 5 r YH r, YL 1 1 1 0 1 0 1 1 1 0 r1 r0 5 r YL XH, i 1 0 1 0 0 0 0 0 i3 i2 i1 i0 7 XH XH+i3~i0+C XL, i 1 0 1 0 0 0 0 1 i3 i2 i1 i0 7 XL XL+i3~i0+C YH, i 1 0 1 0 0 0 1 0 i3 i2 i1 i0 7 YH YH+i3~i0+C YL, i 1 0 1 0 0 0 1 1 i3 i2 i1 i0 7 YL YL+i3~i0+C Branch PSET instructions JP SP SP-3, PCP NPP, PCS s7~s0 M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1 SP SP-3, PCP 0, PCS s7~s0 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) SP SP+3 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) SP SP+3, PC PC+1 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) SP SP+3, M(X) l 3~ l 0, M(X+1) l 7~ l 4, X X+2 Index INC ADC II-122 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 8: CPU Table 8.2(b) Instruction set (2) Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation XH, i 1 0 1 0 0 1 0 0 i3 i2 i1 i0 7 XH-i3~i0 operation XL, i 1 0 1 0 0 1 0 1 i3 i2 i1 i0 7 XL-i3~i0 instructions YH, i 1 0 1 0 0 1 1 0 i3 i2 i1 i0 7 YH-i3~i0 YL, i 1 0 1 0 0 1 1 1 i3 i2 i1 i0 7 YL-i3~i0 r, i 1 1 1 0 0 0 r1 r0 i3 i2 i1 i0 5 r i3~i0 transfer r, q 1 1 1 0 1 1 0 0 r1 r0 q1 q0 5 r q instructions A, Mn 1 1 1 1 1 0 1 0 n3 n2 n1 n0 5 A M(n3~n0) B, Mn 1 1 1 1 1 0 1 1 n3 n2 n1 n0 5 B M(n3~n0) Mn, A 1 1 1 1 1 0 0 0 n3 n2 n1 n0 5 M(n3~n0) A Mn, B 1 1 1 1 1 0 0 1 n3 n2 n1 n0 5 M(n3~n0) B LDPX MX, i 1 1 1 0 0 1 1 0 i3 i2 i1 i0 5 M(X) i3~i0, X X+1 1 1 1 0 1 1 1 0 r1 r0 q1 q0 5 r q, X X+1 LDPY MY, i 1 1 1 0 0 1 1 1 i3 i2 i1 i0 5 M(Y) i3~i0, Y Y+1 1 1 1 0 1 1 1 1 r1 r0 q1 q0 5 r q, Y Y+1 1 0 0 1 l7 l6 l5 l4 l3 l2 l1 l0 5 M(X) l 3~ l 0, M(X+1) l 7~ l 4, X X+2 Index Data CP LD r, q r, q LBPX MX, l Flag SET F, i 1 1 1 1 0 1 0 0 i3 i2 i1 i0 7 F F i3~i0 operation RST F, i 1 1 1 1 0 1 0 1 i3 i2 i1 i0 7 F F i3~i0 7 C 1 instructions SCF 1 1 1 1 0 1 0 0 0 0 0 1 RCF 1 1 1 1 0 1 0 1 1 1 1 0 7 C 0 SZF 1 1 1 1 0 1 0 0 0 0 1 0 7 Z 1 RZF 1 1 1 1 0 1 0 1 1 1 0 1 7 Z 0 SDF 1 1 1 1 0 1 0 0 0 1 0 0 7 D 1 (Decimal Adjuster ON) RDF 1 1 1 1 0 1 0 1 1 0 1 1 7 D 0 (Decimal Adjuster OFF) EI 1 1 1 1 0 1 0 0 1 0 0 0 7 I 1 (Enables Interrupt) DI 1 1 1 1 0 1 0 1 0 1 1 1 7 I 0 (Disables Interrupt) Stack INC SP 1 1 1 1 1 1 0 1 1 0 1 1 5 SP SP+1 operation DEC SP 1 1 1 1 1 1 0 0 1 0 1 1 5 SP SP-1 1 1 1 1 1 1 0 0 0 0 r1 r0 5 SP SP-1, M(SP) r XP 1 1 1 1 1 1 0 0 0 1 0 0 5 SP SP-1, M(SP) XP XH 1 1 1 1 1 1 0 0 0 1 0 1 5 SP SP-1, M(SP) XH XL 1 1 1 1 1 1 0 0 0 1 1 0 5 SP SP-1, M(SP) XL YP 1 1 1 1 1 1 0 0 0 1 1 1 5 SP SP-1, M(SP) YP YH 1 1 1 1 1 1 0 0 1 0 0 0 5 SP SP-1, M(SP) YH YL 1 1 1 1 1 1 0 0 1 0 0 1 5 SP SP-1, M(SP) YL F 1 1 1 1 1 1 0 0 1 0 1 0 5 SP SP-1, M(SP) F r 1 1 1 1 1 1 0 1 0 0 r1 r0 5 r M(SP), SP SP+1 XP 1 1 1 1 1 1 0 1 0 1 0 0 5 XP M(SP), SP SP+1 XH 1 1 1 1 1 1 0 1 0 1 0 1 5 XH M(SP), SP SP+1 XL 1 1 1 1 1 1 0 1 0 1 1 0 5 XL M(SP), SP SP+1 YP 1 1 1 1 1 1 0 1 0 1 1 1 5 YP M(SP), SP SP+1 instructions PUSH r POP S1C62N33 TECHNICAL SOFTWARE EPSON II-123 CHAPTER 8: CPU Table 8.2(c) Instruction set (3) Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation YH 1 1 1 1 1 1 0 1 1 0 0 0 5 YH M(SP), SP SP+1 operation YL 1 1 1 1 1 1 0 1 1 0 0 1 5 YL M(SP), SP SP+1 instructions F 1 1 1 1 1 1 0 1 1 0 1 0 5 F M(SP), SP SP+1 SPH, r 1 1 1 1 1 1 1 0 0 0 r1 r0 5 SPH r SPL, r 1 1 1 1 1 1 1 1 0 0 r1 r0 5 SPL r r, SPH 1 1 1 1 1 1 1 0 0 1 r1 r0 5 r SPH r, SPL 1 1 1 1 1 1 1 1 0 1 r1 r0 5 r SPL Stack POP LD Arithmetic r, i 1 1 0 0 0 0 r1 r0 i3 i2 i1 i0 7 r r+i3~i0 r, q 1 0 1 0 1 0 0 0 r1 r0 q1 q0 7 r r+q r, i 1 1 0 0 0 1 r1 r0 i3 i2 i1 i0 7 r r+i3~i0+C r, q 1 0 1 0 1 0 0 1 r1 r0 q1 q0 7 r r+q+C SUB r, q 1 0 1 0 1 0 1 0 r1 r0 q1 q0 7 r r-q SBC r, i 1 1 0 1 0 1 r1 r0 i3 i2 i1 i0 7 r r-i3~i0-C r, q 1 0 1 0 1 0 1 1 r1 r0 q1 q0 7 r r-q-C r, i 1 1 0 0 1 0 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 0 0 r1 r0 q1 q0 7 r r q r, i 1 1 0 0 1 1 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 0 1 r1 r0 q1 q0 7 r r q r, i 1 1 0 1 0 0 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 1 0 r1 r0 q1 q0 7 r r q r, i 1 1 0 1 1 1 r1 r0 i3 i2 i1 i0 7 r-i3~i0 r, q 1 1 1 1 0 0 0 0 r1 r0 q1 q0 7 r-q r, i 1 1 0 1 1 0 r1 r0 i3 i2 i1 i0 7 r i3~i0 r, q 1 1 1 1 0 0 0 1 r1 r0 q1 q0 7 r q RLC r 1 0 1 0 1 1 1 1 r1 r0 r1 r0 7 d3 d2, d2 d1, d1 d0, d0 C, C d3 RRC r 1 1 1 0 1 0 0 0 1 1 r1 r0 5 d3 C, d2 d3, d1 d2, d0 d1, C d0 INC Mn 1 1 1 1 0 1 1 0 n3 n2 n1 n0 7 M(n3~n0) M(n3~n0)+1 DEC Mn 1 1 1 1 0 1 1 1 n3 n2 n1 n0 7 M(n3~n0) M(n3~n0)-1 ACPX MX, r 1 1 1 1 0 0 1 0 1 0 r1 r0 7 M(X) M(X)+r+C, X X+1 ACPY MY, r 1 1 1 1 0 0 1 0 1 1 r1 r0 7 M(Y) M(Y)+r+C, Y Y+1 SCPX MX, r 1 1 1 1 0 0 1 1 1 0 r1 r0 7 M(X) M(X)-r-C, X X+1 SCPY MY, r 1 1 1 1 0 0 1 1 1 1 r1 r0 7 M(Y) M(Y)-r-C, Y Y+1 7 r r ADD instructions ADC AND OR XOR CP FAN NOT II-124 r 1 1 0 1 0 0 r1 r0 1 1 1 1 EPSON S1C62N33 TECHNICAL SOFTWARE CHAPTER 8: CPU Abbreviations used in the explanations have the following meanings. Symbols associated with A .............. A register registers and memory B .............. B register X .............. XHL register (low order eight bits of index register IX) Y .............. YHL register (low order eight bits of index register IY) XH ........... XH register (high order four bits of XHL register) XL ............ XL register (low order four bits of XHL register) YH ............ YH register (high order four bits of YHL register) YL ............ YL register (low order four bits of YHL register) XP ............ XP register (high order four bits of index register IX) YP ............ YP register (high order four bits of index register IY) SP ............ Stack pointer SP SPH .......... High-order four bits of stack pointer SP SPL .......... Low-order four bits of stack pointer SP MX, M(X) .. Data memory whose address is specified with index register IX MY, M(Y) ... Data memory whose address is specified with index register IY Mn, M(n) .. Data memory address 000H-00FH (address specified with immediate data n of 00H-0FH) M(SP) ....... Data memory whose address is specified with stack pointer SP r, q ........... Two-bit register code r, q is two-bit immediate data; according to the contents of these bits, they indicate registers A, B, and MX and MY (data memory whose addresses are specified with index registers IX and IY) r S1C62N33 TECHNICAL SOFTWARE q r1 r0 q1 q0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 EPSON Registers specified A B MX MY II-125 CHAPTER 8: CPU Symbols associated with NBP ..... program counter NPP ..... PCB ..... PCP ..... PCS ..... PCSH .. PCSL ... New bank pointer New page pointer Program counter bank Program counter page Program counter step Four high order bits of PCS Four low order bits of PCS Symbols associated with F ......... Flag register (I, D, Z, C) flags C ......... Carry flag Z ......... Zero flag D ......... Decimal flag I .......... Interrupt flag ............. Flag reset ............. Flag set .......... Flag set or reset Associated with p ......... immediate data s .......... l .......... i .......... Five-bit immediate data or label 00H-1FH Eight-bit immediate data or label 00H-0FFH Eight-bit immediate data 00H-0FFH Four-bit immediate data 00H-0FH Associated with + ......... Add arithmetic and other - .......... Subtract operations ............. Logical AND ............. Logical OR ............ Exclusive-OR ......... Add-subtract instruction for decimal operation when the D flag is set II-126 EPSON S1C62N33 TECHNICAL SOFTWARE APPENDIX APPENDIX * Table of cross assembler pseudo-instructions Item No. 1 2 3 4 5 Pseudo-instruction EQU (Equation) ORG (Origin) SET (Set) DW (Define word) PAGE (Page) Meaning To allocate data to label To define location counter To allocate data to label (data can be changed) To define ROM data Example of Use ABC EQU 9 BCD EQU ABC+1 ORG 100H ORG 256 ABC SET 0001H ABC SET 0002H ABC DW 'AB' BCD DW 0FFBH PAGE 1H PAGE 11 To define boundary of page 6 SECTION (Section) To define boundary of section SECTION 7 END (End) To terminate assembly END 8 MACRO (Macro) To define macro CHECK 1 9 LOCAL (Local) To make local specification of label during macro definition MACRO LOOP CP JP DATA 10 ENDM (End Macro) S1C62N33 TECHNICAL SOFTWARE CHECK LOCAL LOOP MX,DATA NZ,LOOP To end macro definition ENDM EPSON II-127 APPENDIX * Table of ICE commands Item No. Function 1 2 3 Assemble Disassemble Dump 4 Fill 5 Set Run Mode 6 Trace 7 Break Command Format #A,a #L,a1,a2 #DP,a1,a2 #DD,a1,a2 #FP,a1,a2,d #FD,a1,a2,d #G,a #TIM #OTF #T,a,n #U,a,n #BA,a #BAR,a #BD #BDR #BR #BRR #BM #BMR 8 Move #BRES #BC #BE #BSYN #BT #BRKSEL,REM #MP,a1,a2,a3 #MD,a1,a2,a3 9 Data Set 10 Change CPU Internal Registers II-128 #SP,a #SD,a #DR #SR #I #DXY #SXY Outline of Operation Assemble command mnemonic code and store at address "a" Contents of addresses a1 to a2 are disassembled and displayed Contents of program area a1 to a2 are displayed Content of data area a1 to a2 are displayed Data d is set in addresses a1 to a2 (program area) Data d is set in addresses a1 to a2 (data area) Program is executed from the "a" address Execution time and step counter selection On-the-fly display selection Executes program while displaying results of step instruction from "a" address Displays only the final step of #T,a,n Sets Break at program address "a" Breakpoint is canceled Break condition is set for data RAM Breakpoint is canceled Break condition is set for Evaluation Board CPU internal registers Breakpoint is canceled Combined break conditions set for program data RAM address and registers Cancel combined break conditions for program data ROM address and registers All break conditions canceled Break condition displayed Enter break enable mode Enter break disable mode Set break stop/trace modes Set BA condition clear/remain modes Contents of program area addresses a1 to a2 are moved to addresses a3 and after Contents of data area addresses a1 to a2 are moved to addresses a3 and after Data from program area address "a" are written to memory Data from data area address "a" are written to memory Display Evaluation Board CPU internal registers Set Evaluation Board CPU internal registers Reset Evaluation Board CPU Display X, Y, MX and MY Set data for X and Y display and MX, MY EPSON S1C62N33 TECHNICAL SOFTWARE APPENDIX Item No. 11 Function History Command Format #HSW,a #HSR,a #RF,file #RFD,file #VF,file #VFD,file #WF,file #WFD,file #CL,file #CS,file #CVD #CVR #RP #VP #ROM #Q #HELP Display ICE instruction #CHK Report results of ICE self diagnostic test #HA,a1,a2 #HAR,a1,a2 #HAD #HS,a 12 File 13 Coverage 14 ROM Access 15 Terminate ICE Command Display Self Diagnosis 16 17 Outline of Operation Display history data for pointer 1 and pointer 2 Display upstream history data Display 21 line history data Display history pointer Set history pointer Sets up the history information acquisition before (S), before/after (C) and after (E) Sets up the history information acquisition from program area a1 to a2 Sets up the prohibition of the history information acquisition from program area a1 to a2 Indicates history acquisition program area Retrieves and indicates the history information which executed a program address "a" Retrieves and indicates the history information which wrote or read the data area address "a" Move program file to memory Move data file to memory Compare program file and contents of memory Compare data file and contents of memory Save contents of memory to program file Save contents of memory to data file Load ICE set condition from file Save ICE set condition to file Indicates coverage information Clears coverage information Move contents of ROM to program memory Compare contents of ROM with contents of program memory Set ROM type Terminate ICE and return to operating system control #H,p1,p2 #HB #HG #HP #HPS,a #HC,S/C/E means press the RETURN key. S1C62N33 TECHNICAL SOFTWARE EPSON II-129 International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 28F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 Fax: +1-310-955-5400 SHANGHAI BRANCH 4F, Bldg., 27, No. 69, Gui Jing Road Caohejing, Shanghai, CHINA Phone: 21-6485-5552 Fax: 21-6485-0775 - SALES OFFICES West 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. Phone: +1-815-455-7630 Fax: +1-815-455-7633 Northeast 301 Edgewater Place, Suite 120 Wakefield, MA 01880, U.S.A. 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FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. S1C62N33 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue January, 1992 Printed March, 2001 in Japan M B