S1C62N33 - Epson Company - Datasheet.Directory

MF633-04

Technical Manual

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C62N33 Technical Hardware/S1C62N33 Technical Software

S1C62N33

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko

Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or

circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such

as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there

is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright

infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic

products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from

the Ministry of International Trade and Industry or other approval from another government agency.

PREFACE

This manual is individualy described about the hardware and the software

of the S1C62N33.

I. S1C62N33 Technical Hardware

This part explains the function of the S1C62N33, the circuit configu-

rations, and details the controlling method.

II. S1C62N33 Technical Software

This part explains the programming method of the S1C62N33.

Hardware

Software

The information of the product number change

Configuration of product number

Devices

Comparison table between new and previous number

S1C60 Family processors

Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,

2001 please use the new product number. For further information, please contact Epson sales

representative.

S1 C60N01 F0A01 Packing specification

Specification

Package (D: die form; F: QFP)

Model number

Model name (C: microcomputer, digital products)

Product classification (S1: semiconductor)

Development tools

S5U1 C60R08 D1 1Packing specification

Version (1: Version 1 ∗2)

Tool type (D1: Development Tool ∗1)

Corresponding model number (60R08: for S1C60R08)

Tool classification (C: microcomputer use)

Product classification

(S5U1: development tool for semiconductor products)

∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)

∗2: Actual versions are not written in the manuals.

Previous No.

E0C6001

E0C6002

E0C6003

E0C6004

E0C6005

E0C6006

E0C6007

E0C6008

E0C6009

E0C6011

E0C6013

E0C6014

E0C60R08

New No.

S1C60N01

S1C60N02

S1C60N03

S1C60N04

S1C60N05

S1C60N06

S1C60N07

S1C60N08

S1C60N09

S1C60N11

S1C60N13

S1C60140

S1C60R08

S1C62 Family processors

Previous No.

E0C621A

E0C6215

E0C621C

E0C6S27

E0C6S37

E0C623A

E0C623E

E0C6S32

E0C6233

E0C6235

E0C623B

E0C6244

E0C624A

E0C6S46

New No.

S1C621A0

S1C62150

S1C621C0

S1C6S2N7

S1C6S3N7

S1C6N3A0

S1C6N3E0

S1C6S3N2

S1C62N33

S1C62N35

S1C6N3B0

S1C62440

S1C624A0

S1C6S460

Previous No.

E0C6247

E0C6248

E0C6S48

E0C624C

E0C6251

E0C6256

E0C6292

E0C6262

E0C6266

E0C6274

E0C6281

E0C6282

E0C62M2

E0C62T3

New No.

S1C62470

S1C62480

S1C6S480

S1C624C0

S1C62N51

S1C62560

S1C62920

S1C62N62

S1C62660

S1C62740

S1C62N81

S1C62N82

S1C62M20

S1C62T30

Comparison table between new and previous number of development tools

Development tools for the S1C60/62 Family

Previous No.

ASM62

DEV6001

DEV6002

DEV6003

DEV6004

DEV6005

DEV6006

DEV6007

DEV6008

DEV6009

DEV6011

DEV60R08

DEV621A

DEV621C

DEV623B

DEV6244

DEV624A

DEV624C

DEV6248

DEV6247

New No.

S5U1C62000A

S5U1C60N01D

S5U1C60N02D

S5U1C60N03D

S5U1C60N04D

S5U1C60N05D

S5U1C60N06D

S5U1C60N07D

S5U1C60N08D

S5U1C60N09D

S5U1C60N11D

S5U1C60R08D

S5U1C621A0D

S5U1C621C0D

S5U1C623B0D

S5U1C62440D

S5U1C624A0D

S5U1C624C0D

S5U1C62480D

S5U1C62470D

Previous No.

DEV6262

DEV6266

DEV6274

DEV6292

DEV62M2

DEV6233

DEV6235

DEV6251

DEV6256

DEV6281

DEV6282

DEV6S27

DEV6S32

DEV6S37

EVA6008

EVA6011

EVA621AR

EVA621C

EVA6237

EVA623A

New No.

S5U1C62620D

S5U1C62660D

S5U1C62740D

S5U1C62920D

S5U1C62M20D

S5U1C62N33D

S5U1C62N35D

S5U1C62N51D

S5U1C62560D

S5U1C62N81D

S5U1C62N82D

S5U1C6S2N7D

S5U1C6S3N2D

S5U1C6S3N7D

S5U1C60N08E

S5U1C60N11E

S5U1C621A0E2

S5U1C621C0E

S5U1C62N37E

S5U1C623A0E

Previous No.

EVA623B

EVA623E

EVA6247

EVA6248

EVA6251R

EVA6256

EVA6262

EVA6266

EVA6274

EVA6281

EVA6282

EVA62M1

EVA62T3

EVA6S27

EVA6S32R

ICE62R

KIT6003

KIT6004

KIT6007

New No.

S5U1C623B0E

S5U1C623E0E

S5U1C62470E

S5U1C62480E

S5U1C62N51E1

S5U1C62N56E

S5U1C62620E

S5U1C62660E

S5U1C62740E

S5U1C62N81E

S5U1C62N82E

S5U1C62M10E

S5U1C62T30E

S5U1C6S2N7E

S5U1C6S3N2E2

S5U1C62000H

S5U1C60N03K

S5U1C60N04K

S5U1C60N07K

Hardware

S1C62N33

Technical Hardware

Hardware

S1C62N33 TECHNICAL HARDWARE EPSON I-i

CONTENTS

CHAPTER 1 OVERVIEW........................................................................ I-1

1.1 Configuration .................................................................... I-1

1.2 Features ........................................................................... I-2

1.3 Block Diagram .................................................................. I-3

1.4 Pin Layout Diagram.......................................................... I-4

1.5 Pin Description ................................................................. I-5

CHAPTER 2 POWER SUPPLY AND INITIAL RESET ................................. I-6

2.1 Power Supply ................................................................... I-6

2.2 Initial Reset....................................................................... I-7

Oscillation detection circuit ....................................... I-8

Reset terminal (RESET) ............................................. I-8

Simultaneous high input to input ports (K00–K03) .... I-8

Watchdog timer......................................................... I-9

Internal register at initial setting .............................. I-10

2.3 Test Terminal (TEST)...................................................... I-10

CHAPTER 3 CPU, ROM, RAM ............................................................. I-11

3.1 CPU................................................................................. I-11

3.2 ROM ................................................................................ I-11

3.3 RAM ................................................................................ I-12

I-ii EPSON S1C62N33 TECHNICAL HARDWARE

CONTENTS

CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ....................... I-13

4.1 Memory Map ................................................................... I-13

4.2 Resetting Watchdog Timer.............................................. I-19

Configuration of watchdog timer............................... I-19

Mask option ............................................................. I-19

Control of watchdog timer ........................................ I-20

Programming note.................................................... I-20

4.3 Oscillation Circuit............................................................. I-21

OSC1 oscillation circuit............................................ I-21

OSC3 oscillation circuit............................................ I-21

Configuration of oscillation circuit............................ I-23

Control of oscillation circuit ..................................... I-24

Programming notes .................................................. I-25

4.4 Input Ports (K00–K03, K10) ............................................ I-26

Configuration of input ports ..................................... I-26

Differential registers and interrupt function.............. I-27

Mask option ............................................................. I-29

Control of input ports............................................... I-30

Programming notes .................................................. I-32

4.5 Output Ports (R00–R03, R10–R13) ................................ I-34

Configuration of output ports ................................... I-34

Mask option ............................................................. I-35

Control of output ports............................................. I-38

Programming note.................................................... I-40

4.6 I/O Ports (P00–P03, P10–P13) ....................................... I-41

Configuration of I/O ports........................................ I-41

I/O control register and I/O mode............................ I-42

Mask option ............................................................. I-42

Control of I/O ports.................................................. I-43

Programming notes .................................................. I-45

Hardware

S1C62N33 TECHNICAL HARDWARE EPSON I-iii

CONTENTS

4.7 LCD Driver (COM0–COM3, SEG0–SEG39) ................... I-46

Configuration of LCD driver...................................... I-46

Switching between dynamic and static drive............. I-49

Mask option (segment allocation).............................. I-50

Control of LCD driver ............................................... I-52

Programming notes .................................................. I-53

4.8 Clock Timer ..................................................................... I-54

Configuration of clock timer ..................................... I-54

Interrupt function .................................................... I-55

Control of clock timer ............................................... I-56

Programming notes .................................................. I-58

4.9 Stopwatch Counter.......................................................... I-59

Configuration of stopwatch counter.......................... I-59

Count-up pattern ..................................................... I-60

Interrupt function .................................................... I-61

Control of stopwatch counter ................................... I-62

Programming notes .................................................. I-65

4.10 Event Counter ................................................................. I-66

Configuration of event counter ................................. I-66

Operation of event counter ....................................... I-65

Mask option ............................................................. I-67

Control of event counter ........................................... I-67

Programming note.................................................... I-68

4.11 Analog Comparator ......................................................... I-69

Configuration of analog comparator.......................... I-69

Operation of analog comparator ............................... I-69

Control of analog comparator ................................... I-70

Programming notes .................................................. I-70

I-iv EPSON S1C62N33 TECHNICAL HARDWARE

CONTENTS

4.12 Supply Voltage Detection (SVD) Circuit

and Heavy Load Protection Function .............................. I-71

Configuration of SVD circuit..................................... I-71

Heavy load protection function (S1C62L33) .............. I-72

Detection timing of SVD circuit ................................ I-73

Control of SVD circuit .............................................. I-75

Programing notes ..................................................... I-77

4.13 Serial Interface (SIN, SOUT, SCLK, SIOF) ..................... I-78

Configuration of serial interface................................ I-78

Master mode and slave mode of serial interface ........ I-79

Data input/output and interrupt function................ I-81

Mask option ............................................................. I-85

Control of serial interface ......................................... I-86

Programing notes ..................................................... I-90

4.14 Interrupt and HALT.......................................................... I-91

Interrupt factors....................................................... I-93

Specific masks and factor flags for interrupt............. I-94

Interrupt vectors ...................................................... I-95

Control of interrupt and HALT.................................. I-96

Programming notes .................................................. I-99

CHAPTER 5 SUMMARY OF NOTES..................................................... I-100

5.1 Notes for Low Current Consumption .............................. I-100

5.2 Summary of Notes by Function ...................................... I-101

CHAPTER 6 DIAGRAM OF BASIC

EXTERNAL CONNECTIONS ............................................ I-108

Hardware

S1C62N33 TECHNICAL HARDWARE EPSON I-v

CONTENTS

CHAPTER 7 ELECTRICAL CHARACTERISTICS .................................... I-111

7.1 Absolute Maximum Rating ............................................. I-111

7.2 Recommended Operating Conditions ............................ I-112

7.3 DC Characteristics ......................................................... I-113

7.4 Analog Circuit Characteristics

and Consumed Current .................................................. I-115

7.5 Oscillation Characteristics .............................................. I-121

CHAPTER 8 PACKAGE ...................................................................... I-125

8.1 Plastic Package.............................................................. I-125

8.2 Ceramic Package for Test Samples............................... I-126

CHAPTER 9 PAD LAYOUT .................................................................. I-127

9.1 Diagram of Pad Layout................................................... I-127

9.2 Pad Coordinates............................................................. I-128

S1C62N33 TECHNICAL HARDWARE EPSON I-1

CHAPTER 1: OVERVIEW

CHAPTER 1

1.1

Model S1C62N33 S1C62L33 S1C62A33

Supply Voltage 3.0 V 1.5 V 3.0 V

Oscillation OSC1 only OSC1 only OSC1 and OSC3

Circuits (Single Clock) (Single Clock) (Twin Clock)

OVERVIEW

The S1C62N33 Series is a single-chip microcomputer made

up of the 4-bit core CPU S1C6200, ROM (3,072 words, 12

bits to a word), RAM (256 words, 4 bits to a word) LCD

driver circuit, analog comparator, event counter, serial

interface, watchdog timer, and two types of time base coun-

ter. Because of its low-voltage operation and low power

consumption, this series is ideal for a wide range of applica-

tions, and is especially suitable for battery-driven systems.

Configuration

The S1C62N33 Series is configured as follows, depending on

supply voltage and oscillation circuits.

I-2 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 1: OVERVIEW

OSC1 oscillation circuit Crystal oscillation circuit 32,768 Hz (Typ.)

OSC3 oscillation circuit No setting CR or ceramic oscillation

circuit (selected by mask

option) 500 kHz (Typ.)

Instruction sets 108 types

Instruction execution time 153 µs, 214 µs, 366 µs (CLK = 32,768 Hz)

(differs depending oninstruction) 10 µs, 14 µs, 24 µs

(CLK: CPU operation frequency) (CLK = 500 kHz)

ROM capacity 3,072 words, 12 bits per word

RAM capacity 256 words, 4 bits per word

Input ports 5 bits (pull-down resistor can be added through mask option)

Output ports 8 bits (BZ, BZ, FOUT outputs are available through mask option)

Input/output ports 8 bits (pull-down resistor is added during input data read-out)

Serial interface 1 port (serial 8 bits, clock synchronized)

LCD driver Either 40 segments x 4 or 3 common (selected through mask option)

V-3V 1/4 or 1/3 duty (regulated voltage circut and booster voltage circuit built-in)

Time base counter Two types (timer and stopwatch)

Watchdog timer Built-in (can be disabled through mask option)

Event counter One 8-bit inputs

Analog comparator Inverted input x 1, noninverted input x 1

Supply voltage detection circuit (SVD) 2.4 V 1.2 V 2.4 V

External interrupt Input port interrupt; dual system

Internal interrupt Time base counter interrupt; dual system

Serial interface interrupt; single system

Supply voltage 3.0 V (1.8–3.5 V) 1.5 V (0.9–1.7 V) 3.0 V (2.2–3.5 V)

Consumed CLK = 32,768 Hz

current (when halted)

CLK = 32,768 Hz

(Typ. value) (when executed)

CLK = 500 kHz

(when executed)

Form when shipped 100-pin QFP (plastic) or chip

S1C62N33 S1C62L33 S1C62A33

1.2 Features

1.5 µA 1.0 µA 2.0 µA

6.0 µA 3.0 µA 8.0 µA

– – 135 µA

S1C62N33 TECHNICAL HARDWARE EPSON I-3

CHAPTER 1: OVERVIEW

Block Diagram1.3

COM0~3

K00~03, K10

P00~03, P10~13

R00~03, R10~13

AMPP

AMPM

OSC4

OSC3

OSC2

OSC1

RESET

SEG0~39 TEST

VL1~3

CA~CC

VS1

VSS

Power

Controller

LCD Driver

RAM

256 words x 4 bits

ROM

3,072 words x 12 bits OSC System Reset

Control

Event

Counter

Interrupt

Generator

Input Port

I/O Port

Output Port

Comparator

Timer

Stop Watch

Core CPU S1C6200

SVD

Serial Interface SIN

SOUT

SCLK

SIOF

Fig. 1.3

Block diagram

I-4 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 1: OVERVIEW

1.4

N.C.=No Connection

N.C.

TEST

N.C.

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

Pin No. Pin Name

SEG38

SEG39

N.C.

AMPP

N.C.

AMPM

K10

K03

K02

K01

K00

P03

P02

P01

P00

P13

P12

P11

P10

R03

R02

N.C.

R01

R00

R12

Pin No. Pin Name

N.C.

R11

R10

R13

RESET

OSC4

OSC3

OSC2

OSC1

COM3

COM2

COM1

COM0

Pin No. Pin Name

100

SIOF

SCLK

N.C.

SOUT

SIN

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

Pin No. Pin Name

QFP5-100pin

Fig. 1.4

Pin layout diagram

5180

301

100

Index

Pin Layout Diagram

S1C62N33 TECHNICAL HARDWARE EPSON I-5

CHAPTER 1: OVERVIEW

1.5 Pin Description

Table 1.5 Pin description

*1 62N33/62L33 : Not connected

62A33 : CR or ceramic oscillation input terminal

(Switchable through mask option.)

*2 62N33/62L33 : Not connected

62A33 : CR or ceramic oscillation output terminal

(Switchable through mask option.)

CA–CC

OSC1

OSC2

OSC3

OSC4

K00–10

P00–13

R00–03

R10

R13

R11

R12

AMPP

AMPM

SEG0–39

COM0–3

SIN

SOUT

SCLK

SIOF

RESET

TEST

69–71

32–36

37–44

45, 46, 48, 49

6–27, 83–100

72–75

Pin Name

Power source positive terminal

Power source negative terminal

Constant voltage output terminal for oscillation

Function

Crystal oscillator input terminal

Crystal oscillator output terminal

Input terminal

Input/output terminal

Output terminal

Output terminal (Can output BZ through mask option.)

Output terminal

Output terminal (Can output FOUT through mask option.)

Analog comparator noninverted input terminal

Analog comparator inverted input terminal

LCD segment output terminal

(DC output available through mask option.)

LCD common output terminal

Constant voltage output terminal for LCD (approx. -1.05 V)

Booster output terminal for LCD (V 2)

Booster output terminal for LCD (V 3)

Booster condenser connector terminal

Pin Number

Serial interface input terminal

Serial interface output terminal

Serial interface clock input/output terminal

Serial interface output terminal

Initial setting input terminal

Test input terminal

Input/output

(I)

–

I/O

I-6 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

POWER SUPPLY AND

INITIAL RESET

Power Supply

With a single external power supply (*1) supplied to VDD

through VSS, the S1C62N33 Series generates the necessary

internal voltage with the regulated voltage circuit (<VS1> for

oscillators, <VL1> for LCDs) and the voltage booster circuit

(<VL2, VL3> for LCDs).

Figure 2.1 shows the configuration of power supply.

*1 Supply voltage: 62N33/62A33 .. 3 V, 62L33 .. 1.5 V

- External loads cannot be driven by the regulated voltage and

voltage booster circuit's output voltage.

- See "7 ELECTRICAL CHARACTERISTICS" for voltage values.

CHAPTER 2

Note

2.1

External

power

supply

Internal

circuit

Oscillation

circuit

LCD driver

circuit

LCD system

voltage

booster circuit

LCD system regulated

voltage circuit

Oscillation system

regulated voltage

circuit

OSC1–4

COM0–3

SEG0–39

S1 S1

Fig. 2.1

Configuration of

power supply

S1C62N33 TECHNICAL HARDWARE EPSON I-7

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Initial Reset

To initialize the S1C62N33 Series circuits, initial reset must

be executed. There are four ways of doing this.

(1)Initial reset by the oscillation detection circuit

(2)External initial reset by the RESET terminal

(3)External initial reset by simultaneous high input to

terminals K00–K03

(4)Initial reset by watchdog timer

Figure 2.2 shows the configuration of the initial reset circuit.

2.2

Vss

RESET

K03

K02

K01

K00

OSC2

OSC1

Oscillation

circuit

Vss

Noise

rejector

Initial

reset

Time

authorize

circuit

Oscillation

detection

circuit

Watchdog

timer

Fig. 2.2

Configuration of

initial reset circuit

I-8 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

The oscillation detection circuit outputs the initial reset

signal at power-on until the crystal oscillation circuit (OSC1)

begins oscillating, or when this crystal oscillation circuit

(OSC1) halts oscillating for some reason.

Initial reset can be executed externally by setting the reset

terminal to the high level. This high level must be main-

tained for at least 5 ms (when oscillating frequency is fosc1

= 32 kHz), because the initial reset circuit contains a noise

rejector circuit. When the reset terminal goes low the CPU

begins to operate.

When oscillation is stopped, reset input from the reset terminal

triggered by the noise reject circuit cannot be received. When

oscillation is stopped, initialization of internal circuits is triggered by

the oscillation detection circuit.

Another way of executing initial reset externally is to input a

high signal simultaneously to the input ports (K00–K03)

selected with the mask option. The specified input port

terminals must be kept high for at least 5 ms (when oscillat-

ing frequency is fosc1 = 32 kHz), because the initial reset

circuit contains a noise rejector circuit. Table 2.2.1 shows

the combinations of input ports (K00–K03) that can be

selected with the mask option.

Oscillation detection

circuit

Reset terminal

(RESET)

Note

Simultaneous high

input to input ports

(K00–K03)

Table 2.2.1

Input port combinations ANot used

BK00*K01

CK00*K01*K02

DK00*K01*K02*K03

S1C62N33 TECHNICAL HARDWARE EPSON I-9

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

When, for instance, mask option D (K00*K01*K02*K03) is

selected, initial reset is executed when the signals input to

the four ports K00–K03 are all high at the same time. Fur-

thermore, initial reset is also applied when key input, which

includes the combination of input ports selected, is per-

formed.

Further, when the input time of the simultaneous HIGH

input is tested and found to be the same or more than the

defined time (1–3 sec), the time test circuit that performs

initial reset can be selected with the mask option.

If you use this function, make sure that the specified ports

do not go high at the same time during ordinary operation.

When oscillation is stopped, the reset triggered by the noise reject

circuit which would normally take place when the input ports are

simultaneously switched to HIGH cannot be received.

If the CPU runs away for some reason, the watchdog timer

will detect this situation and output an initial reset signal.

See "4.2 Resetting Watchdog Timer" for details.

Watchdog timer

Note

I-10 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Internal register at

initial setting

CPU Core

Name Signal Number of Bits Setting Value

Program counter step PCS 8 00H

Program counter page PCP 4 1H

New page pointer NPP 4 1H

Stack pointer SP 8 Undefined

Index register IX IX 9 Undefined

Index register IY IY 9 Undefined

General-purpose register A A 4 Undefined

General-purpose register B B 4 Undefined

Interrupt flag I 1 0

Decimal flag D 1 Undefined

Zero flag Z 1 Undefined

Carry flag C 1 Undefined

Peripheral Circuits

Name Number of Bits Setting Value

RAM 256 × 4 Undefined

Segment data 40 × 4 Undefined

Other peripheral circuit –*1

Table 2.2.2

Initial values

2.3

Initial reset initializes the CPU as shown in the table below.

*1 See "4.1 Memory Map"

Test Terminal (TEST)

This terminal is used when the IC load is being detected.

During ordinary operation be certain to connect this termi-

nal to VSS.

S1C62N33 TECHNICAL HARDWARE EPSON I-11

CHAPTER 3: CPU, ROM, RAM

CPU, ROM, RAM

CPU

The S1C62N33 Series employs the core CPU S1C6200 for

the CPU, so that register configuration, instructions and so

forth are virtually identical to those in other family proces-

sors using the S1C6200.

Refer to "S1C6200/6200A Core CPU Manual" for details

about the S1C6200.

Note the following points with regard to the S1C62N33

Series:

(1)The SLEEP operation is not assumed, so the SLP instruc-

tion cannot be used.

(2)Because the ROM capacity is 3,072 words, bank bits are

unnecessary and PCB and NBP are not used.

(3)Since RAM is set for up to 1 page, only the subordinate 1

bit of the page section of the index register which speci-

fies address is effective. (The 3 superordinate bits are

ignored.)

CHAPTER 3

3.1

ROM

The built-in ROM, a mask ROM for loading the program, has

a capacity of 3,072 steps, 12 bits each. The program area is

12 pages (0–11), each of 256 steps (00H–FFH). After initial

reset, the program beginning address is page 1, step 00H.

The interrupt vector is allocated to page 1, steps 01H–0FH.

3.2

I-12 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 3: CPU, ROM, RAM

Fig. 3.2

ROM configuration

RAM

The RAM, a data memory storing a variety of data, has a

capacity of 256 words, each of four bits. When program-

ming, keep the following points in mind.

(1)Part of the data memory can be used as stack area when

saving subroutine calls and registers, so be careful not to

overlap the data area and stack area.

(2)Subroutine calls and interrupts take up three words of

the stack area.

(3)The data memory 000H–00FH is for the register pointers

(RP), and is the addressable memory register area.

(4)The data memory is split into three areas, 000H–06FH,

080H–09FH and 100H–16FH, so take care when allocat-

ing the data. (See "4.1 Memory Map" for details.)

3.3

00H step

0FH step

10H step

FFH step

12 bits

Program start address

Interrupt vector area

0 page

1 page

01H step

2 page

3 page

4 page

5 page

6 page

7 page

8 page

9 page

10 page

11 page

S1C62N33 TECHNICAL HARDWARE EPSON I-13

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

CHAPTER 4

4.1

PERIPHERAL CIRCUITS AND OPERA-

TION

Peripheral circuits (timer, I/O, and so on) of the S1C62N33

Series are memory mapped, and interfaced with the CPU.

Thus, all the peripheral circuits can be controlled by using

the memory operation command to access the I/O data

memory in the memory map.

The following sections describe how the peripheral circuits

operation.

Memory Map

Data memory of the S1C62N33 Series has an address space

of 360 words, of which 48 words are allocated to display

memory and 64 words to I/O data memory.

Figures 4.1.1 and 4.1.2 present the overall memory maps of

the S1C62N33 Series, and Tables 4.1(a)–(c) the peripheral

circuits' (I/O space) memory maps.

The I/O data memory in all units of the S1C62N33 Series is

configured in the same manner at 070H–07FH, 170H–17FH

and 0F0H–0FFH, 1F0H–1FFH. This makes it possible to

access I/O data memory without switching data memory

pages.

I-14 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Address

Page High

Low 0123456789ABCDEF

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF0

RAM (112 words x 4 bits)

R/W

1I/O data memory Tables 4.1(a), (b)

RAM (32 words x 4 bits)

R/W

I/O data memory Tables 4.1(a), (b)

RAM (112 words x 4 bits)

R/W

Unused area

I/O data memory Table 4.1(c)

Unused area

I/O data memory Table 4.1(c)

Fig. 4.1.1

Memory map

S1C62N33 TECHNICAL HARDWARE EPSON I-15

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

(1)The I/O data memory registers of 070H–07FH, 170H–17FH and

0F0H–0FFH, 1F0H–1FFH are each linked. For instance, by

switching the I/O data memory at 074H, data memory at 174H

can by switched simultaneously.

See Tables 4.1(a)–(c) for details of I/O data memory.

(2)The mask option can be used to select whether to assign the

overall area of segment data memory to 040H–06FH or 0C0H–

0EFH.

When 040H–06FH is selected, read/write is enabled.

When 0C0H–0EFH is selected, write only is enabled.

If 040H–06FH is assigned, RAM is used as the segment area

(48 words).

(3)Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this

reason, normal operation cannot be assured for programs that

have been prepared with access to these areas.

Note

Fig. 4.1.2

Memory map

(segment area)

Address

Page High

Low 0123456789ABCDEF

4 or C

5 or D

6 or E

Segment data memory (40 words x 4 bits)

40H–6FH = R/W

C0H–EFH = W

I-16 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Table 4.1(a) I/O memory map (70H–77H)

Address Comment

D3 D2 D1 D0 Name Init 1 0

70H

TM0

TM3

TM2

TM1

TM0

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

TM1TM2TM3

71H

SWL0

SWL3

SWL2

SWL1

SWL0

SWL1SWL2SWL3

72H

SWH0

SWH3

SWH2

SWH1

SWH0

SWH1SWH2SWH3 0

K00

K03

K02

K01

K00

High

Low

K01K02K03

73H

74H

DFK00

R/W

DFK03

DFK02

DFK01

DFK00

Falling

Rising

DFK01DFK02DFK03

75H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

EIK01EIK02EIK03

76H

HVLD

SVDDT

SVDON

EISWIT1

EISWIT0

Heavy load protection mode register

SVD evaluation data (at read-out)

SVD ON/OFF (at writing)

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

Enable

Normal

Off

Mask

SVDDT

SVDON

Stopwatch counter

1/100 sec (BCD)

MSB

LSB

Stopwatch counter

1/10 sec (BCD)

MSB

LSB

Input port

(K00–K03)

Differential register

(K00–K03)

Interrupt mask register

(K00–K03)

EISWIT0

EISWIT1HVLD

R/W R

WR/W

77H

SCTRG

SIOF

EIK10

DFK10

K10

–

Serial interface clock trigger

SIOF

Interrupt mask register (K10)

Differential register (K10)

Input port (K10)

Trigger

Run

Enable

Falling

High

–

Stop

Mask

Rising

Low

SCTRG

SIOF K10

DFK10

EIK10

R/W

Heavy load

Low voltage

S1C62N33 TECHNICAL HARDWARE EPSON I-17

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1(b) I/O memory map (78H–7FH)

Address Comment

D3 D2 D1 D0 Name Init 1 0

78H

ETI32

R/W

CSDC

ETI2

ETI8

ETI32

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

Static

Enable

Dynamic

Mask

ETI8ETI2CSDC

79H

TI32 –

TI2

TI8

TI32

Unused *5

Interrupt factor flag (clock timer 2 Hz) *4

Interrupt factor flag (clock timer 8 Hz) *4

Interrupt factor flag (clock timer 32 Hz) *4

Yes

TI8TI2–

7AH

SWIT0 IK1

IK0

SWIT1

SWIT0

Interrupt factor flag (K10) *4

Interrupt factor flag (K00–K03) *4

Interrupt factor flag (stopwatch 1 Hz) *4

Interrupt factor flag (stopwatch 10 Hz) *4

Yes

SWIT1IK0IK1

7BH

R00 R03

R02

R01

R00

High

Low

R01R02R03

R/W

7CH

R10

R/W

R13

R12

R11

R10

High

Low

R11R12R13

7DH

P00 P03

P02

P01

P00

High

Low

P01P02P03

7EH

IOC0

R/W

TMRST

SWRUN

SWRST

IOC0

Reset

Clock timer reset *5

Stopwatch counter RUN/STOP

Stopwatch counter reset *5

I/O control register 0 (P00–P03)

Reset

Run

Reset

Output

–

Stop

–

Input

SWRST

SWRUN

R/W

TMRST

7FH

WD0 WDRST

WD2

WD1

WD0

Reset

Watchdog timer reset *5

Timer data (watchdog timer 1/4 Hz)

Timer data (watchdog timer 1/2 Hz)

Timer data (watchdog timer 1 Hz)

Reset –

WD1

WD2WDRST

Output port

(R00–R03)

Output port (R13, BZ) *6

Output port (R12, FOUT) *6

Output port (R11)

Output port (R10, BZ) *6

R/W

I/O port (P00–P03)

Output latch reset at time of initial reset

I-18 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1(c) I/O memory map (F0H–F3H, F6H–F9H, FCH–FEH)

AMPON

R/W

Falling

Mask

Address Comment

D3 D2 D1 D0 Name Init 1 0

F0H

SD0

R/W

SD3

SD2

SD1

SD0

Serial interface data register

Low order (SD0–SD3)

SD1SD2SD3

F1H

SD4

R/W

SD7

SD6

SD5

SD4

SD5SD6SD7

F2H

EISIO

R/W

SCS1

SCS0

SE2

EISIO

Clock edge selection register

Interrupt mask register (serial interface)

SE2SCS0SCS1 1

ISIO

–

ISIO 0

Unused *5

Interrupt factor flag (serial interface) *4

Yes No

–––

F3H

F6H

–BZFQ

–

Buzzer frequency selection register

Unused *5

2 kHz 4 kHz

–

BZFQ

R/W

F7H

–

AMPDT

AMPON 1

Unused *5

Analog comparator data

Analog comparator ON/OFF

On Off

AMPDT–

–

F8H

EV00

EV03

EV02

EV01

EV00

EV01EV02EV03

F9H

EV04 EV07

EV06

EV05

EV04

EV05EV06EV07

FCH

EVRST

–

EVRUN

–

EVRST

Unused *5

Event counter RUN/STOP

Unused *5

Event counter reset *5

–

EVRUN

R/W

–

FEH

IOC1 –

CLKCHG

OSCC

IOC1

OSCC

R/W

CLKCHG–

FDH

P10 P13

P12

P11

P10

High

Low

P11P12P13

R/W

Rising

Enable

Serial interface data register

High order (SD4–SD7)

Clock edge selection register

(SCS0, SCS1)

Event counter

Low order (EV00–EV03)

Event counter

High order (EV04–EV07)

+ > - - > +

Run

Reset

Stop

–

OSC3

Output

OSC1

Off

Input

Reset

I/O port (P10–P13)

Output latch reset at time of initial reset

Unused *5

CPU clock switch

OSC3 oscillator ON/OFF

I/O control register 1 (P10–P13)

S1C62N33 TECHNICAL HARDWARE EPSON I-19

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)

4.2

Configuration of

watchdog timer

Mask option

Fig. 4.2

Watchdog timer

block diagram

Resetting Watchdog Timer

The S1C62N33 Series incorporates a watchdog timer as the

source oscillator for OSC1 (clock timer 2 Hz signal). The

watchdog timer must be reset cyclically by the software. If

reset is not executed in at least 3 or 4 seconds, the initial

reset signal is output automatically for the CPU.

Figure 4.2 is the block diagram of the watchdog timer.

The watchdog timer, configured of a three-bit binary counter

(WD0–WD2), generates the initial reset signal internally by

overflow of the MSB.

Watchdog timer reset processing in the program's main

routine enables detection of program overrun, such as when

the main routine's watchdog timer processing is bypassed.

Ordinarily this routine is incorporated where periodic

processing takes place, just as for the timer interrupt rou-

tine.

The watchdog timer operates in the halt mode. If the halt

status continues for 3 or 4 seconds, the initial reset signal

restarts operation.

You can select whether or not to use the watchdog timer

with the mask option. When "Not use" is chosen, there is no

need to reset the watchdog timer.

Clock timer

TM0–TM3

2 Hz Watchdog timer

WD0–WD2 Initial reset signal

OSC1 demultiplier

(256 Hz)

Watchdog timer reset signal

I-20 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)

Table 4.2 Control bits of watchdog timer

Control of

watchdog timer

WDRST:

Watchdog timer reset

(7FH·D3)

This is the bit for resetting the watchdog timer.

When "1" is written: Watchdog timer is reset

When "0" is written: No operation

Read-out: Always "0"

When "1" is written to WDRST, the watchdog timer is reset,

and the operation restarts immediately after this. When "0"

is written to WDRST, no operation results.

This bit is dedicated for writing, and is always "0" for read-

out.

When the watchdog timer is being used, the software must

reset it within 3-second cycles, and timer data (WD0–WD2)

cannot be used for timer applications.

Address Comment

D3 D2 D1 D0 Name SR *1 10

7FH

WDRST WD2 WD1 WD0

WDRST

WD2

WD1

WD0

Reset

Watchdog timer reset *5

Timer data (watchdog timer 1/4 Hz)

Timer data (watchdog timer 1/2 Hz)

Timer data (watchdog timer 1 Hz)

–

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Table 4.2 lists the watchdog timer's control bits and their

addresses.

Programming note

S1C62N33 TECHNICAL HARDWARE EPSON I-21

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

Oscillation Circuit

The S1C62N33 Series has a built-in crystal oscillation

circuit. As an external element, the OSC1 oscillation circuit

generates the operating clock for the CPU and peripheral

circuitry by connecting the crystal oscillator (Typ. 32.768

kHz) and trimmer capacitor (5–25 pF).

Figure 4.3.1 is the block diagram of the OSC1 oscillation

circuit.

As Figure 4.3.1 indicates, the crystal oscillation circuit can

be configured simply by connecting the crystal oscillator

(X'tal) between terminals OSC1 and OSC2 to the trimmer

capacitor (CGX) between terminals OSC1 and VDD.

In the S1C62N33 Series, the S1C62A33 has twin clock

specification. The mask option enables selection of either

the CR or ceramic oscillation circuit (OSC3 oscillation

circuit) as the CPU's subclock. Because the oscillation

circuit itself is built-in, it provides the resistance as an

external element when CR oscillation is selected, but when

ceramic oscillation is selected both the ceramic oscillator

and two capacitors (gate and drain capacitance) are

required.

Figure 4.3.2 is the block diagram of the OSC3 oscillation

circuit.

4.3

OSC1 oscillation

circuit

OSC3 oscillation

circuit

Fig. 4.3.1

OSC1 oscillation circuit

X'tal

OSC2

OSC1

To CPU and

peripheral circuits

S1C62N33 Series

I-22 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

As indicated in Figure 4.3.2, the CR oscillation circuit can be

configured simply by connecting the resistor (RCR) between

terminals OSC3 and OSC4 when CR oscillation is selected.

When 82 kΩ is used for RCR, the oscillation frequency is

about 430 kHz. When ceramic oscillation is selected, the

ceramic oscillation circuit can be configured by connecting

the ceramic oscillator (Typ. 500 kHz) between terminals

OSC3 and OSC4 to the two capacitors (CGC and CDC) located

between terminals OSC3 and OSC4 and VDD. For both CGC

and CDC, connect capacitors that are about 100 pF. To lower

current consumption of the OSC3 oscillation circuit, oscilla-

tion can be stopped through the software.

For the S1C62N33 and 62L33 (single clock specification), do

not connect anything to terminals OSC3 and OSC4.

To CPU (SIO)

Oscillation circuit

control signal

CCR

OSC3

OSC4

Ceramic

OSC4

OSC3

To CPU (SIO)

Oscillation circuit

control signal

S1C62A33

Fig. 4.3.2

OSC3 oscillation circuit

S1C62N33 TECHNICAL HARDWARE EPSON I-23

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

Configuration of

oscillation circuit

The S1C62N33 and 62L33 have one oscillation circuit

(OSC1), and the S1C62A33 has two oscillation circuits

(OSC1 and OSC3). OSC1 is a crystal oscillation circuit that

supplies the operating clock the CPU and peripheral cir-

cuits. OSC3 is either a CR or ceramic oscillation circuit.

When processing with the S1C62A33 requires high-speed

operation, the CPU operating clock can be switched from

OSC1 to OSC3.

Figure 4.3.3 is the block diagram of this oscillation system.

Fig. 4.3.3

Oscillation system

For S1C62A33, selection of either OSC1 or OSC3 for the

CPU's operating clock can be made through the software.

Oscillation circuit control signal

CPU clock selection signal

To CPU (SIO)

To peripheral circuit

Clock

switch

OSC1

oscillation

circuit

OSC3

oscillation

circuit

I-24 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

Table 4.3 lists the control bits and their addresses for the

oscillation circuit.

Table 4.3 Control bits of oscillation circuit and prescaler

Control of oscillation

circuit

Controls oscillation ON/OFF for the OSC3 oscillation circuit.

(S1C62A33 only.)

When "1" is written: The OSC3 oscillation ON

When "0" is written: The OSC3 oscillation OFF

Read-out: Valid

When it is necessary to operate the CPU of the S1C62A33 at

high speed, set OSCC to "1". At other times, set it to "0" to

lessen the current consumption.

For the S1C62N33 and 62L33, keep OSCC set to "0".

At initial reset, OSCC is set to "0".

OSCC:

OSC3 oscillation control

(FEH·D1)

Address

*7 Comment

D3 D2 D1 D0 Name SR *1 10

FEH

OSCC IOC1

–

CLKCHG

OSCC

IOC1

OSC3

Output

OSC1

OFF

Input

Unused *5

CPU clock switch

OSC3 oscillator ON/OFF

I/O control register 1 (P10–P13)

R/W

CLKCHG

–

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

S1C62N33 TECHNICAL HARDWARE EPSON I-25

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

The CPU's operation clock is selected with this register.

(S1C62A33 only.)

When "1" is written: OSC3 clock is selected

When "0" is written: OSC1 clock is selected

Read-out: Valid

When the S1C62N33's CPU clock is to be OSC3, set

CLKCHG to "1"; for OSC1, set CLKCHG to "0". This register

cannot be controlled for the S1C62N33 and 62L33, so that

OSC1 is selected no matter what the set value.

At initial reset, CLKCHG is set to "0".

(1)It takes at least 5 ms from the time the OSC3 oscillation

circuit goes ON until the oscillation stabilizes. Conse-

quently, when switching the CPU operation clock from

OSC1 to OSC3, do this after a minimum of 5 ms have

elapsed since the OSC3 oscillation went ON.

Further, the oscillation stabilization time varies depend-

ing on the external oscillator characteristics and condi-

tions of use, so allow ample margin when setting the wait

time.

(2)When switching the clock form OSC3 to OSC1, use a

separate instruction for switching the OSC3 oscillation

OFF. An error in the CPU operation can result if this

processing is performed at the same time by the one

instruction.

CLKCHG:

The CPU's clock switch

(FEH·D2)

Programming notes

I-26 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Input Ports (K00–K03, K10)

The S1C62N33 Series has five bits general-purpose input

ports. Each of the input port terminals (K00–K03, K10)

provides internal pull-down resistor. Pull-down resistor can

be selected for each bit with the mask option.

Figure 4.4.1 shows the configuration of input port.

Configuration of

input ports

4.4

Selection of "pull-down resistance enabled" with the mask

option suits input from the push switch, key matrix, and so

forth. When "pull-down resistance disabled" is selected, the

port can be used for slide switch input and interfacing with

other LSIs.

Further, the input port terminal K10 is used as the input

terminals for the event counter. (See "4.10 Event Counter"

for details.)

Fig. 4.4.1

Configuration of

input port

Vss

Mask option

Address

VDD

Interrupt

request

Data bus

S1C62N33 TECHNICAL HARDWARE EPSON I-27

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

All five bits of the input ports (K00–K03, K10) provide the

interrupt function. The conditions for issuing an interrupt

can be set by the software. Further, whether to mask the

interrupt function can be selected individually for all five

bits by the software.

Figure 4.4.2 shows the configuration of K00–K03 and K10.

Differential registers

and interrupt func-

tion

Note

Fig. 4.4.2

Input interrupt circuit

configuration

(K00–K03, K10)

Data bus

Interrupt mask

Differential

Mask option

(K00–K03, K10)

Noise

rejector

One for each terminal series

Interrupt factor

flag (IK) Interrupt

request

Address

The input interrupt timing for K00–K03 and K10 depends on

the value set for the differential registers (DFK00–DFK03

and DFK10). Interrupt can be selected to occur at the rising

or falling edge of the input.

The interrupt mask registers (EIK00–EIK03, EIK10) enables

the interrupt mask to be selected individually for K00–K03

and K10. However, whereas the interrupt function is ena-

bled inside K00–K03, the interrupt occurs when the con-

tents change from matching those of the differential register

to non-matching contents. Interrupt for K10 can be gener-

ated by setting the same conditions individually.

When the interrupt is generated, the interrupt factor flag

(IK0 and IK1) is set to "1".

Figure 4.4.3 shows an example of an interrupt for K00–K03.

Writing to the interrupt mask registers (EIK00–EIK03, EIK10) can

be done only in the DI status (interrupt flag = "0").

I-28 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Interrupt mask register Differential register

EIK03 EIK02 EIK01 EIK00 DFK03 DFK02 DFK01 DFK00

1110 1 0 1 0

With the above setting, the interrupt for K00–K03 occurs in

the following conditions.

Input port

(1) K03 K02 K01 K00

1 0 1 0 (Initial value)

(2) K03 K02 K01 K00

1011

(3) K03 K02 K01 K00

0011 → Interrupt generated

(4) K03 K02 K01 K00

0111

↓

K00 is masked, so the three bits

of K01–K03 cease matching

those of the differential register

DFK01–DFK03, and an inter-

rupt occurs.

↓

K00 is masked by the interrupt mask register (EIK00), so

that an interrupt does not occur at (2). At (3), K03 changes

to "0"; the data of the terminal that is interrupt enabled no

longer matches the data of the differential register, so that

interrupt occurs. As already explained, the condition for the

interrupt to occur is the change in the port data and con-

tents of the differential register from matching to

nonmatching. Hence, in (4), when the nonmatching status

changes to another nonmatching status, an interrupt does

not occur. Further, terminals that have been masked for

interrupt do not affect the conditions for interrupt genera-

tion.

Fig. 4.4.3

Example of interrupt of

K00–K03

S1C62N33 TECHNICAL HARDWARE EPSON I-29

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

The contents that can be selected with the input port mask

option are as follows:

(1)Internal pull-down resistor can be selected for each of the

five bits of the input ports (K00–K03, K10).

When you have selected "pull-down resistor disabled",

take care that the floating status does not occur for the

input. Select "pull-down resistor enabled" for input ports

that are not being used.

(2)The input interrupt circuit contains a noise rejector for

preventing interrupt occurring through noise. The mask

option enables selection of whether to use the noise

rejector for each separate terminal series.

When "Use" is selected, a maximum delay of 1 ms occurs

from the time interrupt condition is established until the

interrupt factor flag (IK) is set to "1".

Mask option

I-30 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Table 4.4 list the input ports control bits and their ad-

dresses.

Table 4.4 Input port control bits

Control of input ports

Address Comment

D3 D2 D1 D0 Name SR *1 10

73H

74H

K03 K02 K01 K00

DFK03 DFK02 DFK01 DFK00

R/W

K03

K02

K01

K00

High

Low

DFK03

DFK02

DFK01

DFK00

Falling

Rising

Input port

(K00–K03)

Differential register

(K00–K03)

75H

77H

EIK03 EIK02 EIK01 EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

Enable

Falling

High

Interrupt mask register

(K00–K03)

7AH

IK1 IK0 SWIT1 SWIT0

IK1

IK0

SWIT1

SWIT0

Yes

Interrupt factor flag (K10) *4

Interrupt factor flag (K00–K03) *4

Interrupt factor flag (stopwatch 1 Hz) *4

Interrupt factor flag (stopwatch 10 Hz) *4

EIK10 DFK10 K10

EIK10

DFK10

K10

Mask

Rising

Low

Interrupt mask register (K10)

Differential register (K10)

Input port (K10)

SCTRG

SIOF

SCTRG

SIOF –

Trigger

Run Serial interface clock trigger

SIOF

–

Stop

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

S1C62N33 TECHNICAL HARDWARE EPSON I-31

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

K00–K03, K10:

Input port data

(73H, 77H·D0)

Input data of the input port terminals can be read out with

these registers.

When "1" is read out: High level

When "0" is read out: Low level

Writing: Invalid

The read-out is "1" when the terminal voltage of the five bits

of the input ports (K00–K03, K10) goes high (VDD), and "0"

when the voltage goes low (VSS).

These bits are dedicated for read-out, so writing cannot be

done.

Interrupt conditions can be set with these registers.

When read out is "1": Falling edge

When read out is "0": Rising edge

Read-out: Valid

The interrupt conditions can be set for the rising or falling

edge of input for each of the five bits (K00–K03 and K10),

through the differential registers (DFK00–DFK03 and

DFK10).

At initial reset, these registers are set to "0".

Masking the interrupt of the input port terminals can be

selected with these registers.

When "1" is written: Enable

When "0" is written: Mask

Read-out: Valid

With these registers, masking of the input port bits can be

selected for each of the five bits.

Writing to the interrupt mask registers can be done only in

the DI status (interrupt flag = "0").

At initial reset, these registers are all set to "0".

These flags indicate the occurrence of input interrupt.

When "1" is read out: Interrupt has occurred

When "0" is read out: Interrupt has not occurred

Writing: Invalid

The interrupt factor flags IK0 and IK1 are associated with

K00–K03 and K10, respectively.

DFK00–DFK03, DFK10:

Differential registers

(74H, 77H·D1)

EIK00–EIK03, EIK10:

Interrupt mask registers

(75H, 77H·D2)

IK0, IK1:

Interrupt factor flags

(7AH·D2 and D3)

I-32 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

From the status of these flags, the software can decide

whether an input interrupt has occurred.

These flags are reset when the software reads them. Read-

out can be done only in the DI status (interrupt flag = "0").

At initial reset, these flags are set to "0".

(1)When input ports are changed from high to low by pull-

down resistance, the fall of the waveform is delayed on

account of the time constant of the pull-down resistance

and input gate capacitance. Hence, when fetching input

ports, set an appropriate wait time.

Particular care needs to be taken of the key scan during

key matrix configuration. Aim for a wait time of about 1

ms.

(2)When "noise rejector circuit enable" is selected with the

mask option, a maximum delay of 1 ms occurs from time

the interrupt conditions are established until the inter-

rupt factor flag (IK) is set to "1" (until the interrupt is

actually generated).

Hence, pay attention to the timing when reading out

(resetting) the interrupt factor flag.

For example, when performing a key scan with the key

matrix, the key scan changes the input status to set the

interrupt factor flag, so it has to be read out to reset it.

However, if the interrupt factor flag is read out immedi-

ately after key scanning, the delay will cause the flag to

be set after read-out, so that it will not be reset.

(3)Input interrupt programing related precautions

Programming notes

When the content of the mask register is rewritten, while the port K

input is in the active status. The input interrupt factor flags are set at

➀ and ➁, ➀ being the interrupt due to the falling edge and ➁ the

interrupt due to the rising edge.

Fig. 4.4.4

Input interrupt timing

Port K input

Factor flag set Not set ➁Factor flag set

Differential register

Mask register

Active status Active status

Rising edge interrupt

➀

Falling edge interrupt

S1C62N33 TECHNICAL HARDWARE EPSON I-33

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

When using an input interrupt, if you rewrite the content

of the mask register, when the value of the input terminal

which becomes the interrupt input is in the active status,

the factor flag for input interrupt may be set. Therefore,

when using the input interrupt, the active status of the

input terminal implies

input terminal = low status, when the falling edge

interrupt is effected and

input terminal = high status, when the rising edge

interrupt is effected.

When an interrupt is triggered at the falling edge of an

input terminal, a factor flag is set with the timing of ➀

shown in Figure 4.4.4. However, when clearing the con-

tent of the mask register with the input terminal kept in

the low status and then setting it, the factor flag of the

input interrupt is again set at the timing that has been

set. Consequently, when the input terminal is in the

active status (low status), do not rewrite the mask regis-

ter (clearing, then setting the mask register), so that a

factor flag will only set at the falling edge in this case.

When clearing, then setting the mask register, set the

mask register, when the input terminal is not in the

active status (high status).

When an interrupt is triggered at the rising edge of the

input terminal, a factor flag will be set at the timing of ➁

shown in Figure 4.4.4. In this case, when the mask

registers cleared, then set, you should set the mask

In addition, when the mask register = "1" and the content

of the differential register is rewritten in the input termi-

nal active status, an input interrupt factor flag may be

set. Thus, you should rewrite the content of the differen-

tial register in the mask register = "0" status.

(4)Read-out the interrupt factor flag (IK) only in the DI

status (interrupt flag = "0"). Read-out during EI status

will cause malfunction.

(5)Writing to the interrupt mask registers (EIK) can be done

only in the DI status (interrupt flag = "0").

Writing during EI status will cause malfunction.

I-34 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Output Ports (R00–R03, R10–R13)

The S1C62N33 Series has general output ports (4 bits x 2).

Output specifications of the output ports can be selected

individually with the mask option. Two kinds of output

specifications are available: complementary output and Pch

open drain output.

Further, the mask option enables the output ports R10,

R12, and R13 to be used as special output ports.

Figure 4.5.1 shows the configuration of the output ports.

Configuration of

output ports

4.5

Fig. 4.5.1

Configuration of output ports

Data bus

Address

Mask option

S1C62N33 TECHNICAL HARDWARE EPSON I-35

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Pin Name When Special Output Selected

R10 BZ

R13 BZ (Only when R10 = BZ output is selected)

R12 FOUT

The mask option enables the following output port selection.

(1)Output specifications of output ports

Output specifications for the output ports (R00–R03,

R10–R13) enable selection of either complementary

output or Pch open drain output for each of the eight

bits.

However, even when Pch open drain output is selected,

voltage exceeding source voltage must not be applied to

the output port.

(2)Special output

In addition to the regular DC output, special output can

be selected for the output ports R10, R12, and R13 as

shown in Table 4.5.1. Figure 4.5.2 shows the structure of

the output ports R10–R13.

Mask option

Table 4.5.1

Special output

I-36 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Address

(7CH)

(R10)

FOUT

Data bus

R12

R11

R13

R10

Mask option

(Without SW)

(R13)

(R11)

(R12)

Fig. 4.5.2

Structure of output port

R10–R13

S1C62N33 TECHNICAL HARDWARE EPSON I-37

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

BZ and BZ are the buzzer signal output for driving the

piezoelectric buzzer. The buzzer signal frequency of 2 kHz or

4 kHz can be selected by software.

When the BZ and BZ output signals are turned ON or OFF, a

hazard can result.

When DC output is set for the output port R10, the output port R13

cannot be set for BZ output.

Figure 4.5.3 shows the output waveform for BZ and BZ.

Fig. 4.5.3

Output waveform of

BZ and BZ

Clock Frequency (Hz)

fosc1 = 32,768

fosc1 / 1 32,768

fosc1 / 2 16,384

fosc1 / 4 8,192

fosc1 / 8 4,096

fosc1 / 16 2,048

fosc1 / 32 1,024

fosc1 / 64 512

fosc1 /128 256

When the output port R12 is set for FOUT output, it outputs

the clock of fosc1 or the demultiplied fosc1. The clock fre-

quency is selectable with the mask options, from the fre-

quencies listed in Table 4.5.2.

A hazard may occur when the FOUT signal is turned ON or OFF.

Setting Value

BZ, BZ

(R10, R13)

Note

FOUT

(R12)

Table 4.5.2

FOUT clock frequency

Note

BZ output

(R10 terminal)

"H"

"L"

"H"

"L"

BZ output

(R13 terminal)

I-38 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Table 4.5.3 lists the output ports' control bits and their

addresses.

Table 4.5.3 Control bits of output ports

Control of output

ports

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Address Comment

D3 D2 D1 D0 Name SR

7BH

7CH

R03 R01 R00

R12 R11 R10

R/W

R03

R02

R01

R00

High

Low

R13

R12

R11

R10

High

Low

Output port (R00–R03)

Output port (R13, BZ) *6

Output port (R12, FOUT) *6

Output port (R11)

Output port (R10, BZ) *6

R02

R/W

R13

F6H

BZFQ BZFQ

–

0 2 kHz 4 kHz

Buzzer frequency selection register

Unused *5

RR/W

–––

S1C62N33 TECHNICAL HARDWARE EPSON I-39

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

R00–R03, R10–R13

(when DC output):

Output port data

(7BH, 7CH)

R10, R13 (when BZ and

BZ output is selected):

Special output port data

(7CH·D0 and D3)

Sets the output data for the output ports.

When "1" is written: High output

When "0" is written: Low output

Read-out: Valid

The output port terminals output the data written in the

corresponding registers (R00–R03, R10–R13) without chang-

ing it. When "1" is written in the register, the output port

terminal goes high (VDD), and when "0" is written, the output

port terminal goes low (VSS).

At initial reset, all registers are set to "0".

These bits control the output of the buzzer signals (BZ, BZ).

When "1" is written: Buzzer signal is output

When "0" is written: Low level (DC) is output

Read-out: Valid

BZ is output from terminal R13. With the mask option,

selection can be made perform this output control by R13,

or to perform output control simultaneously with BZ by

R10.

•When R13 controls BZ output

BZ output and BZ output can be controlled independently.

BZ output is controlled by writing data to R10, and BZ

output is controlled by writing data to R13.

•When R10 controls BZ output

BZ output and BZ output can be controlled simultane-

ously by writing data to R10 only. For this case, R13 can

be used as a one-bit general register having both read and

write functions, and data of this register exerts no affect

on BZ output (output from the R13 pin).

At initial reset, registers R10 and R13 are set to "0".

I-40 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

BZFQ:

Buzzer frequency

selection register

(F6H·D3)

R12

(when FOUT is selected):

Special output port data

(7CH·D2)

Programming note

Selects the frequency of the buzzer signal.

When "1" is written: 2 kHz

When "0" is written: 4 kHz

Read-out: Valid

When "1" is written to register BZFQ, the frequency of the

buzzer signal is set in 2 kHz, and in 4 kHz when "0" is

written.

At initial reset, BZFQ is set to "0" (4 kHz).

Controls the FOUT (clock) output.

When "1" is written: Clock output

When "0" is written: Low level (DC) output

Read-out: Valid

FOUT output can be controlled by writing data to R12.

At initial reset, this register is set to "0".

When BZ, BZ and FOUT are selected with the mask option,

a hazard may be observed in the output waveform when the

data of the output register changes.

S1C62N33 TECHNICAL HARDWARE EPSON I-41

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

I/O Ports (P00–P03, P10–P13)

The S1C62N33 Series has general-purpose I/O ports (4 bits

x 2). Figure 4.6 shows the configuration of the I/O ports.

The four bits of each of the I/O ports P00–P03 and P10–P13

can be set to either input mode or output mode. Modes can

be set by writing data to the I/O control register.

4.6

Configuration of

I/O ports

Fig. 4.6

Configuration of I/O ports

Address

Input

control

I/O control

Data bus

Address

I-42 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

Input or output mode can be set for the four bits of I/O port

P00–P03 and I/O port P10–P13 by writing data into the

corresponding I/O control register IOC0 and IOC1.

To set the input mode, "0" is written to the I/O control

high impedance status and works as an input port. How-

ever, the input line is pulled down when input data is read.

The output mode is set when "1" is written to the I/O control

output port, it outputs a high signal (VDD) when the port

output data is "1", and a low signal (VSS) when the port

output data is "0".

At initial reset, the I/O control registers are set to "0", and

the I/O port enters the input mode.

The output specification during output mode (IOC = "1") of

these I/O ports can be set with the mask option for either

complementary output or Pch open drain output. This

setting can be performed for each bit of each port.

However, when Pch open drain output has been selected,

voltage in excess of the power voltage must not be applied to

the port.

Mask option

I/O control register

and I/O mode

S1C62N33 TECHNICAL HARDWARE EPSON I-43

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

Table 4.6 lists the I/O ports' control bits and their ad-

dresses.

Table 4.6 I/O port control bits

Control of I/O ports

Address Comment

D3 D2 D1 D0 Name SR *1 10

7DH

7EH

P03 P02 P01 P00

SWRUN SWRST IOC0

R/W

P03

P02

P01

P00

High

Low

TMRST

SWRUN

SWRST

IOC0

Reset

Clock timer reset *5

Stopwatch counter RUN/STOP

Stopwatch counter reset *5

I/O control register 0 (P00–P03)

TMRST

W R/W W R/W

I/O port (P00–P03)

Output latch reset at time of initial reset

Reset

RUN

Reset

Output

–

STOP

–

Input

FDH

FEH

P13

OSCC IOC1

P13

P12

P11

P10

High

Low

–

CLKCHG

OSCC

IOC1

OSC3

Output

OSC1

OFF

Input

Unused *5

CPU clock switch

OSC3 oscillator ON/OFF

I/O control register 1 (P10–P13)

R/W

I/O port (P10–P13)

Output latch reset at time of initial reset

P12 P11 P10

CLKCHG

–

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

I-44 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

I/O port data can be read and output data can be set

through these ports.

•When writing data

When "1" is written: High level

When "0" is written: Low level

When an I/O port is set to the output mode, the written data

is output unchanged from the I/O port terminal. When "1" is

written as the port data, the port terminal goes high (VDD),

and when "0" is written, the level goes low (VSS).

Port data can be written also in the input mode.

•When reading data out

When "1" is read out: High level

When "0" is read out: Low level

The terminal voltage level of the I/O port is read out. When

the I/O port is in the input mode the voltage level being

input to the port terminal can be read out; in the output

mode the output voltage level can be read. When the termi-

nal voltage is high (VDD) the port data that can be read is "1",

and when the terminal voltage is low (VSS) the data is "0".

Further, the built-in pull-down resistance goes ON during

read-out, so that the I/O port terminal is pulled down.

Internal pull down resistors are only ON during readout and

gate floating by means of an input control signal cannot

occur even at times other than readout.

- When the I/O port is set to the output mode and a low-impedance

load is connected to the port terminal, the data written to the

- When the I/O port is set to the input mode and a low-level voltage

(VSS) is input, erroneous input results if the time constant of the

capacitive load of the input line and the built-in pull-down resis-

tance load is greater than the read-out time.

P00–P03, P10–P13:

I/O port data

(7DH, FDH)

Note

S1C62N33 TECHNICAL HARDWARE EPSON I-45

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

When the input data is being read out, the time that the input line

is pulled down is equivalent to 1.5 cycles of the CPU system

clock. However, the electric potential of the terminals must be

settled within 0.5 cycles. If this condition cannot be fulfilled, some

measure must be devised such as arranging pull-down resis-

tance externally, or performing multiple read-outs.

The input and output modes of the I/O ports can be set

with these registers.

When "1" is written: Output mode

When "0" is written: Input mode

Read-out: Valid

The input and output modes of the I/O ports are set in units

of four bits. IOC0 sets the mode for P00–P03, and IOC1 sets

the mode for P10–P13.

Writing "1" to the I/O control register makes the correspond-

ing I/O port enter the output mode, and writing "0" induces

the input mode.

At initial reset, these two registers are set to "0", so the I/O

ports are in the input mode.

(1)When the I/O port is being read out, the built-in pull-

down resistance of the I/O port goes ON. Consequently, if

data is read out while the CPU is running in the OSC3

oscillation circuit, data must be read out continuously for

about 500 µs.

(2)When the I/O port is set to the output mode and the data

impedance load is connected and read-out performed, the

value of the register and the read-out result may differ.

IOC0, IOC1:

I/O control registers

(7EH·D0, FEH·D0)

Programming notes

I-46 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD Driver (COM0–COM3, SEG0–SEG39)

The S1C62N33 Series has four common terminals and 40

segment terminals, so that it can drive an LCD with a maxi-

mum of 160 (40 x 4) segments.

The power for driving the LCD is generated by the CPU

internal circuit so that there is no need to apply power

especially from outside.

The driving method is 1/4 duty (or 1/3 duty with the mask

option) dynamic drive depending on the four types of poten-

tial, VDD, VL1, VL2 and VL3. The frame frequency is fosc1/

1,024 Hz for 1/4 duty, and fosc1/768 Hz for 1/3 duty.

Figure 4.7.1 shows the drive waveform for 1/4 duty, and

Figure 4.7.2 shows the drive waveform for 1/3 duty.

Fosc1 indicates the oscillation frequency of the OSC1 oscillation

circuit.

4.7

Configuration of LCD

driver

Note

S1C62N33 TECHNICAL HARDWARE EPSON I-47

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Fig. 4.7.1

Drive waveform for 1/4 duty

LCD lighting status

COM0

COM1

COM2

COM3

Not lit

Lit

-V

COM0

COM1

COM2

COM3

SEG

0–39

Frame frequency

SEG0–39

-V

I-48 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Frame frequency

SEG

0–39

COM3

COM2

COM1

COM0

-V

Not lit

Lit

SEG0–39

LCD lighting status

COM0

COM1

COM2

-V

Fig. 4.7.2

Drive waveform for 1/3 duty

S1C62N33 TECHNICAL HARDWARE EPSON I-49

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

The S1C62N33 Series provides software setting of the LCD

static drive. This function enables easy adjustment (cadence

adjustment) of the oscillation frequency of the OSC1 oscilla-

tion circuit (crystal oscillation circuit).

The procedure for executing static drive of the LCD is as

follows:

➀Write "1" to register CSDC at address 78H·D3.

➁Write the same value to all registers corresponding to

COM0–COM3 of the segment memory.

- Even when 1/3 duty is selected, COM3 is valid for static drive.

However, the output frequency is the same as for the frame

frequency.

- For cadence adjustment, set the segment data so that all the

LCDs light.

Figure 4.7.3 shows the drive waveform for static drive.

Switching between

dynamic and static

drive

Note

Fig. 4.7.3

LCD static drive waveform

SEG

0–39

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–39

–V

Not lit Lit

–V

I-50 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(1)Segment allocation

As shown in Figure 4.1.2, segment data of the S1C62N33

Series is decided depending on display data written to the

segment data memory (write-only) at address 40H–6FH or

C0H–EFH.

➀The mask option enables the segment data memory to

be allocated entirely to either 40H–6FH or C0H–EFH.

➁The address and bits of the segment data memory can

be made to correspond to the segment pins (SEG0–

SEG39) in any form through the mask option. This

makes design easy by increasing the degree of freedom

with which the liquid crystal panel can be designed.

Figure 4.7.4 shows an example of the relationship be-

tween the LCD segments (on the panel) and the segment

data memory (when 40H–6FH is selected) for the case of

1/3 duty.

Mask option

(segment allocation)

Data

D3 D2 D1 D0

6AH d c b a

6BH p g f e

6CH d' c' b' a'

6DH p' g' f'e'

Common 0 Common 1 Common 2

SEG10 6A, D0 6B, D1 6B, D0

(a) (f) (e)

SEG11 6A, D1 6B, D2 6A, D3

(b) (g) (d)

SEG12 6D, D1 6A, D2 6B, D3

(f' ) (c) (p)

Pin address allocation

Example of LCD panel

↑

Address

→

Segment data memory allocation

Fig. 4.7.4

Segment allocation

aa'

ff'

ee'

dd' p'

SEG10 SEG11 SEG12

Common 0

Common 1

Common 2

S1C62N33 TECHNICAL HARDWARE EPSON I-51

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Table 4.7.1 Differences depending on selected duty

Duty Pins Used in Common Maximum Number of Segments Frame Frequency (when fosc1 = 32 kHz)

1/4 COM0–COM3 160 (40 x 4) fosc1/1,024 (32 Hz)

1/3 COM0–COM2 120 (40 x 3) fosc1/768 (42.7 Hz)

(2)Drive duty

With the mask option, either 1/4 or 1/3 duty can be

selected for the LCD drive duty.

Table 4.7.1 shows the differences in the number of seg-

ments depending on the selected duty.

(3)Output specification

➀The segment pins (SEG0–SEG39) are selected with the

mask option in pairs for either segment signal output

or DC output (VDD and VSS binary output).

When DC output is selected, the data corresponding to

COM0 of each segment pin is output.

➁When DC output is selected, either complementary

output or Pch open drain output can be selected for

each pin with the mask option.

The pin pairs are the combination of SEG2*n and SEG2*n + 1

(where n is an integer from 0 to 18).

Note

I-52 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Table 4.7.2 Control bits of LCD driver

Control of LCD driver

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Address Comment

D3 D2 D1 D0 Name SR *1 10

78H

CSDC ETI2 ETI8 ETI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

Fig. 4.7.5

Segment data memory map

Address

Page High

Low 0123456789ABCDEF

4 or C

5 or D

6 or E

Segment data memory (40 words x 4 bits)

40H–6FH = R/W

C0H–EFH = W

Table 4.7.2 shows the LCD driver's control bits and their

addresses. Figure 4.7.5 shows the segment data memory

map.

S1C62N33 TECHNICAL HARDWARE EPSON I-53

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

CSDC:

LCD drive switch

(78H·D3)

Segment data memory

(40H–6FH or C0H–EFH)

Programming notes

The LCD drive format can be selected with this switch.

When "1" is written: Static drive

When "0" is written: Dynamic drive

Read-out: Valid

At initial reset, dynamic drive (CSDC = "0") is selected.

The LCD segments are lit or turned off depending on this

data.

When "1" is written: Lit

When "0" is written: Not lit

Read-out: Valid for 40H–6FH

Undefined C0H–EFH

By writing data into the segment data memory allocated to

the LCD segment (on the panel), the segment can be lit or

put out.

At initial reset, the contents of the segment data memory are

undefined.

(1)When 40H–6FH is selected for the segment data memory,

the memory data and the display will not match until the

area is initialized (through, for instance, memory clear

processing by the CPU). Initialize the segment data mem-

ory by executing initial processing.

(2)When C0H–EFH is selected for the segment data memory,

that area becomes write-only. Consequently, data cannot

be rewritten by arithmetic operations (such as AND, OR,

ADD, SUB).

I-54 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Clock Timer

The S1C62N33 Series has a built-in clock timer as the

source oscillator for OSC1 (crystal oscillator). The clock

timer is configured of a seven-bit binary counter that serves

as the input clock, a 256 kHz signal output by the prescaler.

Data of the four high-order bits (16 Hz–2 Hz) can be read out

by the software.

Figure 4.8.1 is the block diagram for the clock timer.

4.8

Configuration of

clock timer

Ordinarily, this clock timer is used for all types of timing

functions such as clocks.

Fig. 4.8.1

Block diagram of clock timer

128 Hz–32 Hz

Data bus

32 Hz, 8 Hz, 2 Hz

256 Hz

Clock timer reset signal

OSC1

oscillation

circuit

Interrupt request

Interrupt

control

16 Hz–2 Hz

S1C62N33 TECHNICAL HARDWARE EPSON I-55

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

The clock timer can cause interrupts at the falling edge of 32

Hz, 8 Hz and 2 Hz signals. Software can set whether to mask

any of these frequencies.

Figure 4.8.2 is the timing chart of the clock timer.

Interrupt function

Fig. 4.8.2

Timing chart of

clock timer

As shown in Figure 4.8.2, interrupt is generated at the

falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz). At this

time, the corresponding interrupt factor flag (TI32, TI8, TI2)

is set to "1". Selection of whether to mask the separate

interrupts can be made with the interrupt mask registers

(ETI32, ETI8, ETI2). However, regardless of the interrupt

mask register setting, the interrupt factor flag is set to "1" at

the falling edge of the corresponding signal.

Note Perform writing to the interrupt mask registers (ETI32, ETI8, ETI2)

and readout from the interrupt factor flags (TI32, TI8, TI2) only in

the DI status (interrupt flag = "0").

Clock timer timing chart

FrequencyRegisterAddress

70H

D0 16 Hz

8 Hz

4 Hz

2 Hz

32 Hz interrupt request

8 Hz interrupt request

2 Hz interrupt request

I-56 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Control of clock

timer

Table 4.8 Control bits of clock timer

Table 4.8 shows the clock timer control bits and their ad-

dresses.

78H

79H

CSDC ETI2 ETI8 ETI32

TI2 TI8 TI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

–

TI2

TI8

TI32

Yes

Unused *5

Interrupt factor flag (clock timer 2 Hz) *4

Interrupt factor flag (clock timer 8 Hz) *4

Interrupt factor flag (clock timer 32 Hz) *4

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

–

Address Comment

D3 D2 D1 D0 Name SR

70H

TM3 TM2 TM1 TM0

TM3

TM2

TM1

TM0

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

7EH

SWRUN SWRST IOC0 TMRST

SWRUN

SWRST

IOC0

Reset

Clock timer reset *5

Stopwatch counter RUN/STOP

Stopwatch counter reset *5

I/O control register 0 (P00–P03)

TMRST

W R/W W R/W

Reset

RUN

Reset

Output

–

STOP

–

Input

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

S1C62N33 TECHNICAL HARDWARE EPSON I-57

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

The 16 Hz–2 Hz timer data of the clock timer can be read

out with this register. These four bits are read-out only, and

writing operations are invalid.

At initial reset, the timer data is initialized to "0H".

These registers are used to select whether to mask the clock

timer interrupt.

When "1" is written: Enabled

When "0" is written: Masked

Read-out: Valid

The interrupt mask registers (ETI32, ETI8, ETI2) are used to

select whether to mask the interrupt to the separate fre-

quencies (32 Hz, 8 Hz, 2 Hz).

Writing to the interrupt mask registers can be done only in

the DI status (interrupt flag = "0").

At initial reset, these registers are all set to "0".

These flags indicate the status of the clock timer interrupt.

When "1" is read out: Interrupt has occurred

When "0" is read out: Interrupt has not occurred

Writing: Invalid

The interrupt factor flags (TI32, TI8, TI2) correspond to the

clock timer interrupts of the respective frequencies (32 Hz, 8

Hz, 2 Hz). The software can judge from these flags whether

there is a clock timer interrupt. However, even if the inter-

rupt is masked, the flags are set to "1" at the falling edge of

the signal.

These flags can be reset through being read out by the

software. Also, the flags can be read out only in the DI

status (interrupt flag = "0").

At initial reset, these flags are set to "0".

TM0–TM3:

Timer data

(70H)

ETI32, ETI8, ETI2:

Interrupt mask registers

(78H·D0–D2)

TI32, TI8, TI2:

Interrupt factor flags

(79H·D0–D2)

I-58 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

This bit resets the clock timer.

When "1" is written: Clock timer reset

When "0" is written: No operation

Read-out: Always "0"

The clock timer is reset by writing "1" to TMRST. The clock

timer starts immediately after this. No operation results

when "0" is written to TMRST.

This bit is write-only, and so is always "0" at read-out.

(1)When the clock timer has been reset, the interrupt factor

flag (TI) may sometimes be set to "1". Consequently,

perform flag read-out (reset the flag) as necessary at

reset.

(2)The input clock of the watchdog timer is the 2 Hz signal

of the clock timer, so that the watchdog timer may be

counted up at timer reset.

(3)Read-out the interrupt factor flag (TI) only during the DI

status (interrupt flag = "0"). Read-out during EI status

will cause malfunction.

(4)Writing to the interrupt mask register (ETI) can be done

only in the DI status (interrupt flag = "0").

Writing during EI status will cause malfunction.

TMRST:

Clock timer reset

(7EH·D3)

Programming notes

S1C62N33 TECHNICAL HARDWARE EPSON I-59

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

Stopwatch Counter

The S1C62N33 Series incorporates a 1/100 sec and 1/10

sec stopwatch counter. The stopwatch counter is configured

of a two-stage, four-bit BCD counter serving as the input

clock of an approximately 100 Hz signal (signal obtained by

approximately demultiplying the 256 Hz signal output by

the prescaler). Data can be read out four bits at a time by

the software.

Figure 4.9.1 is the block diagram of the stopwatch counter.

The stopwatch counter can be used as a separate timer from

the clock timer. In particular, digital watch stopwatch func-

tions can be realized easily with software.

4.9

Configuration of

stopwatch counter

Fig. 4.9.1

Block diagram of

stopwatch counter

SWL counter

Data bus

10 Hz, 1 Hz

256 Hz

Stopwatch counter reset signal

OSC1

oscillation

circuit

Interrupt request

Interrupt

control

10 Hz

SWH counter

Stopwatch counter RUN/STOP signal

I-60 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

The stopwatch counter is configured of four-bit BCD count-

ers SWL and SWH.

The counter SWL, at the stage preceding the stopwatch

counter, has an approximated 100 Hz signal for the input

clock. It counts up every 1/100 sec, and generates an

approximated 10 Hz signal. The counter SWH has an ap-

proximated 10 Hz signal generated by the counter SWL for

the input clock. It count-up every 1/10 sec, and generated 1

Hz signal.

Figure 4.9.2 shows the count-up pattern of the stopwatch

counter.

SWL generates an approximated 10 Hz signal from the basic

256 Hz signal. The count-up intervals are 2/256 sec and 3/

256 sec, so that finally two patterns are generated: 25/256

sec and 26/256 sec intervals. Consequently, these patterns

do not amount to an accurate 1/100 sec.

SWH counts the approximated 10 Hz signals generated by

the 25/256 sec and 26/256 sec intervals in the ratio of 4:6,

to generate a 1 Hz signal. The count-up intervals are 25/

256 sec and 26/256 sec, which do not amount to an

accurate 1/10 sec.

Count-up pattern

Fig. 4.9.2

Count-up pattern of

stopwatch counter

256 26

256

256 25

256

256 2

256 3

256 2

256

256 3

256

256 2

256

256 2

256

256 3

256

256 2

256

256 25

256

x 6 + x 4 = 1 (S)

0 1 2 3 4 5 6 7 8 9 0

1 Hz

signal

generation

Approximate

10 Hz

signal

generation

Approximate

10 Hz

signal

generation

SWH count value

Count time (S)

(S)

SWL count value

Count time (S)

SWL count value

Count time (S)

SWH count up pattern

SWL count up pattern 1

SWL count up pattern 2

S1C62N33 TECHNICAL HARDWARE EPSON I-61

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

The 10 Hz (approximate 10 Hz) and 1 Hz interrupts can be

generated through the overflow of stopwatch counters SWL

and SWH respectively. Also, software can set whether to

separately mask the frequencies described earlier.

Figure 4.9.3 is the timing chart for the stopwatch counter.

Interrupt function

Fig. 4.9.3

Timing chart for

stopwatch counter

As shown in Figure 4.9.3, the interrupts are generated by

the overflow of their respective counters ("9" changing to

"0"). Also, at this time the corresponding interrupt factor

flags (SWIT0, SWIT1) are set to "1".

The respective interrupts can be masked separately through

the interrupt mask registers (EISWIT0, EISWIT1). However,

regardless of the setting of the interrupt mask registers, the

interrupt factor flags are set to "1" by the overflow of their

corresponding counters.

Perform writing to the interrupt mask registers (EISWIT0, EISWIT1)

and readout from the interrupt factor flags (SWIT0, SWIT1) only in

the DI status (interrupt flag = "0").

Note

Address

Stopwatch counter (SWL) timing chart

Stopwatch counter (SWH) timing chart

10 Hz interrupt request

1 Hz interrupt request

72H

(1/10 sec BCD)

71H

(1/100 sec BCD)

I-62 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

Table 4.9.1 list the stopwatch counter control bits and their

addresses.

Table 4.9.1 Stopwatch counter control bits

Control of stopwatch

counter

Address Comment

D3 D2 D1 D0 Name SR *1 10

71H

72H

SWL3 SWL2 SWL1 SWL0

SWH3 SWH2 SWH1 SWH0

SWL3

SWL2

SWL1

SWL0

MSB

Stopwatch counter

1/100 sec (BCD)

LSB

SWH3

SWH2

SWH1

SWH0

MSB

Stopwatch counter

1/10 sec (BCD)

LSB

76H

HVLD SVDDT

SVDON

EISWIT1 EISWIT0

R/W

HVLD

EISWIT1

EISWIT0

Enable

Mask

SVD evaluation data (at read-out)

SVD ON/OFF (at writing)

Interrupt mask register

(stopwatch 1 Hz)

Interrupt mask register

(stopwatch 10 Hz)

R/W SVDDT

SVDON 0

Heavy

load Normal

ON Normal

OFF

Heavy load protection mode register

7AH

IK1 IK0 SWIT1 SWIT0

IK1

IK0

SWIT1

SWIT0

Yes

7EH

SWRUN SWRST IOC0 TMRST

SWRUN

SWRST

IOC0

Reset

Clock timer reset *5

Stopwatch counter RUN/STOP

Stopwatch counter reset *5

I/O control register 0 (P00–P03)

TMRST

W R/W W R/W

Reset

RUN

Reset

Output

–

STOP

–

Input

Interrupt factor flag (K10) *4

Interrupt factor flag (K00–K03) *4

Interrupt factor flag (stopwatch 1 Hz) *4

Interrupt factor flag (stopwatch 10 Hz) *4

Low voltage

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

S1C62N33 TECHNICAL HARDWARE EPSON I-63

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

SWL0–SWL3:

Stopwatch counter

1/100 sec (71H)

Data (BCD) of the 1/100 sec column of the stopwatch coun-

ter can be read out. These four bits are read-only, and

cannot be used for writing operations.

At initial reset, the counter data is set to "0H".

Data (BCD) of the 1/10 sec column of the stopwatch counter

can be read out. These four bits are read-only, and cannot

be used for writing operations.

At initial reset, the counter data is set to "0H".

These registers are used to select whether to mask the

stopwatch counter interrupt.

When "1" is written: Enabled

When "0" is written: Masked

Read-out: Valid

The interrupt mask registers (EISWIT0, EISWIT1) are used

to separately select whether to mask the 10 Hz and 1 Hz

interrupts.

Writing to the interrupt mask registers can be done only in

the DI status (interrupt flag = "0").

At initial reset, these registers are both set to "0".

These flags indicate the status of the stopwatch counter

interrupt.

When "1" is read out: Interrupt has occurred

When "0" is read out: Interrupt has not occurred

Writing: Invalid

The interrupt factor flags (SWIT0, SWIT1) correspond to the

10 Hz and 1 Hz interrupts respectively. With these flags, the

software can judge whether a stopwatch counter interrupt

has occurred. However, regardless of the interrupt mask

overflow.

These flags are reset when read out by the software. Also,

read-out is only possible in the DI status (interrupt flag =

"0").

At initial reset, these flags are set to "0".

SWIT0, SWIT1:

Interrupt factor flag

(7AH·D0 and D1)

EISWIT0, EISWIT1:

Interrupt mask register

(76H·D0 and D1)

SWH0–SWH3:

Stopwatch counter

1/10 sec (72H)

I-64 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

This bit resets the stopwatch counter.

When "1" is written: Stopwatch counter reset

When "0" is written: No operation

Read-out: Always "0"

The stopwatch counter is reset when "1" is written to

SWRST. When the stopwatch counter is reset in the RUN

status, operation restarts immediately. Also, in the STOP

status the reset data is maintained.

This bit is write-only, and is always "0" at read-out.

This bit controls RUN/STOP of the stopwatch counter.

When "1" is written: RUN

When "0" is written: STOP

Read-out: Valid

The stopwatch counter enters the RUN status when "1" is

written to SWRUN, and the STOP status when "0" is written.

In the STOP status, the counter data is maintained until the

next RUN status or resets counter. Also, when the STOP

status changes to the RUN status, the data that was main-

tained can be used for resuming the count.

When the counter data is read out in the RUN status, cor-

rect read-out may be impossible because of the carry from

the low-order bit (SWL) to the high-order bit (SWH). This

occurs when read-out has extended over the SWL and SWH

bits when the carry occurs. To prevent this, perform read

out after entering the STOP status, and then return to the

RUN status. Also, the duration of the STOP status must be

within 976 µs (256 Hz 1/4 cycle).

At initial reset, this register is set to "0".

SWRST:

Stopwatch counter reset

(7EH·D1)

SWRUN:

Stopwatch counter

RUN/STOP

(7EH·D2)

S1C62N33 TECHNICAL HARDWARE EPSON I-65

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

Programming notes (1)If counter data is read out in the RUN status, the counter

must be made into the STOP status, and after data is

read out the RUN status can be restored. If data is read

out when a carry occurs, the data cannot be read cor-

rectly.

Also, the processing above must be performed within the

STOP interval of 976 µs (256 Hz 1/4 cycle).

(2)Read-out of the interrupt factor flag (SWIT) must be done

only in the DI status (interrupt flag = "0").

Read-out during EI status will cause malfunction.

(3)Writing to the interrupt mask registers (EISWIT) can be

done only in the DI status (interrupt flag = "0").

Writing during EI status will cause malfunction.

I-66 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

Event Counter

The S1C62N33 Series has an event counter that counts the

clock signals input from outside.

The event counter is configured of eight-bit binary counters

(UP counters). The clock pulses are input through pins K02

and K03 of the input port.

Figure 4.10.1 shows the configuration of the event counter.

4.10

Configuration of

event counter

The clock signal input from terminal K10 is input to the

event counter via the noise rejector.

The event counter increments when the clock signal is

input, and the incremented data can be read out through

the software.

RUN and STOP of the event counter are performed by mak-

ing the clock of the noise rejector ON and OFF. This is

controlled by writing data to the EVRUN register.

Figure 4.10.2 is the timing chart for the event counter.

Operation of event

counter

Input port

Noise rejector

circuit

K10

Event counter

[EV00–EV07]

Interrupt request

Data bus

Event counter RUN/STOP

Event counter reset

Fig. 4.10.1

Configuration of

event counter

Input of K10 terminal

EVRUN

Input of event counter

Defined time

ON2

OFF

Noise

STP

STOP

OFF

STP

ON2

≥ 1.5 T

≥ 1.0 T

< 0.5 T

≥ 0.5 T

≥ 1.5 T

+ T

STP

(Execution time)

T = 1/f

Through the mask option, f

selects fosc 1/16 or fosc 1/128

for the clock frequency of the

noise rejector

CH CH

RUN

Fig. 4.10.2

Timing chart of

event counter

S1C62N33 TECHNICAL HARDWARE EPSON I-67

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

The clock frequency of the noise rejector can be selected as

fosc1/16 or fosc1/128.

Table 4.10.1 lists the defined time depending on the fre-

quency selected.

Mask option

Selection fosc1/16 fosc1/128

TON 0.74 5.86

TOFF 0.49 3.91

TN 0.24 1.95

TSTP 0.25 1.96

fosc1 = 32,768 Hz (Unit: ms)

TN : Max value

Others : Min value

Table 4.10.1

Defined time depending

on frequency selected

Table 4.10.2 shows the event counter control bits and their

addresses.

Control of event

counter

Table 4.10.2 Event counter control bits

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Address Comment

D3 D2 D1 D0 Name SR

F8H

F9H

EV03 EV02 EV01 EV00

EV06 EV05 EV04

EV03

EV02

EV01

EV00

EV07

EV06

EV05

EV04

EV07

Event counter

low order (EV00–EV03)

Event counter

high order (EV04–EV07)

FCH

EVRUN EVRST

–

EVRUN

–

EVRST

Reset

RUN

Reset

Unused *5

Event counter RUN/STOP

Unused *5

Event counter reset *5

R/W W

STOP

–

––

I-68 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

EV00–EV03:

Event counter Low-order

(F8H)

EV04–EV07:

Event counter High-order

(F9H)

The four low-order data bits of event counter are read out.

These four bits are read-only, and cannot be used for writ-

ing.

At initial reset, event counter is set to "00H".

The four high-order data bits of event counter are read out.

These four bits are read-only, and cannot be used for writ-

ing.

At initial reset, event counter is set to "00H".

This is the register for resetting event counter.

When "1" is written: Event counter reset

When "0" is written: No operation

Read-out: Always "0"

When "1" is written, event counter is reset and the data

becomes "00H". When "0" is written, no operation is exe-

cuted.

This is a write-only bit, and is always "0" at read-out.

This register controls the event counter RUN/STOP status.

When "1" is written: RUN

When "0" is written: STOP

Read-out: Valid

When "1" is written, the event counter enters the RUN

status and starts receiving the clock signal input.

When "0" is written, the event counter enters the STOP

status and the clock signal input is ignored. (However, input

to the input port is valid.)

At initial reset, this register is set to "0".

To prevent erroneous reading of the event counter data, read

out the counter data several times, compare it, and use the

matching data as the result.

EVRST:

Event counter reset

(FCH·D0)

EVRUN:

Event counter RUN/STOP

(FCH·D2)

Programming note

S1C62N33 TECHNICAL HARDWARE EPSON I-69

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator)

Analog Comparator

The S1C62N33 Series incorporates an MOS input analog

comparator. This analog comparator, which has two differ-

ential input terminals (inverted input terminal AMPM,

noninverted input terminal AMPP), can be used for general

purposes.

Figure 4.11 shows the configuration of the analog compara-

tor.

The analog comparator is ON when the AMPON register is

"1", and compares the input levels of the AMPP and AMPM

terminals. The result of the comparison is read from the

AMPDT register. It is "1" when AMPP (+) > AMPM (-) and "0"

when AMPP (+) < AMPM (-).

After the analog comparator goes ON it takes a maximum of

3 ms until the output stabilizes.

4.11

Configuration of

analog comparator

Operation of analog

comparator

Fig. 4.11

Configuration of

analog comparator

Address

AMPON Power source

control

Input control

Data bus

AMPP

AMPM

–

AMPDT

I-70 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator)

Table 4.11 lists the analog comparator control bits and their

addresses.

Control of analog

comparator

Table 4.11 Analog comparator control bits

Address Comment

D3 D2 D1 D0 Name SR *1 10

F7H

AMPDT AMPON

–

AMPDT

AMPON

0 ON OFF

Unused *5

Analog comparator data

Analog comparator ON/OFF

R/W

––

+ > - - > +

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Switches the analog comparator ON and OFF.

When "1" is written: The analog comparator goes ON

When "0" is written: The analog comparator goes OFF

Read-out: Valid

The analog comparator goes ON when "1" is written to

AMPON, and OFF when "0" is written.

At initial reset, AMPON is set to "0".

Reads out the output from the analog comparator.

When "1" is read out: AMPP (+) > AMPM (-)

When "0" is read out: AMPP (+) < AMPM (-)

Writing: Invalid

AMPDT is "0" when the input level of the inverted input

terminal (AMPM) is greater than the input level of the

noninverted input terminal (AMPP); and "1" when smaller.

At initial reset, AMPDT is set to "1".

(1)To reduce current consumption, set the analog compara-

tor to OFF when it is not necessary.

(2)After setting AMPON to "1", wait at least 3 ms for the

operation of the analog comparator to stabilize before

reading the output data of the analog cpmparator from

AMPDT.

AMPON:

Analog comparator

ON/OFF (F7H·D0)

AMPDT:

Analog comparator data

(F7H·D1)

Programming notes

S1C62N33 TECHNICAL HARDWARE EPSON I-71

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

Supply Voltage Detection (SVD) Circuit

and Heavy Load Protection Function

The S1C62N33 Series has a built-in supply voltage detection

(SVD) circuit, so that the software can find when the source

voltage lowers. The configuration of the SVD circuit is shown

in Figure 4.12.

Turning the SVD operation ON/OFF is controlled through

the software (HVLD, SVDON). Moreover, when a drop in

source voltage (SVDDT = "1") is detected, SVD operation is

periodically performed by the hardware until the source

voltage is recovered (SVDDT = "0").

Because the power current consumption of the IC becomes

big when the SVD operation is turned ON, set the SVD

operation to OFF unless otherwise necessary.

See "7 ELECTRICAL CHARACTERISTICS" for the evaluation

voltage accuracy.

4.12

Configuration of

SVD circuit

Fig. 4.12

Configuration of SVD circuit

SVD circuit

Detection output

Address 76H

SVDON

SVDDT

HVLD

Data bus

SVD

sampling

control

I-72 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

Heavy load protec-

tion function

(S1C62L33)

Note that the heavy load protection function on the

S1C62L33 is different from the S1C62N33.

(1)In case of S1C62L33

The S1C62L33 has the heavy load protection function for

when the battery load becomes heavy and the source

voltage drops, such as when an external buzzer sounds

or an external lamp lights. The state where the heavy

load protection function is in effect is called the heavy

load protection mode. In this mode, operation with a

lower voltage than normal is possible.

The normal mode changes to the heavy load protection

mode in the following two cases:

➀When the software changes the mode to the heavy load

protection mode (HVLD = "1")

➁When supply voltage drop (SVDDT = "1") in the SVD

circuit is detected, the mode will automatically shift to

the heavy load protection mode until the supply volt-

age is recovered (SVDDT = "0")

In the heavy load protection mode, the internally regu-

lated voltage is generated by the liquid crystal driver

source output VL2 so as to operate the internal circuit.

Consequently, more current is consumed in the heavy

load protection mode than in the normal mode. Unless it

is necessary, be careful not to set the heavy load protec-

tion mode with the software. Also, when the SVD is to be

turned on during operation in the heavy load protection

mode, limit the ON time to 10 ms per second of operation

time.

(2)In case of S1C62N33/62A33

The S1C62N33/62A33 has the heavy load protection

function for when the battery load becomes heavy and

the source voltage changes, such as when an external

buzzer sounds or an external lamp lights. The state

where the heavy load protection function is in effect is

called the heavy load protection mode. Compared with

the normal operation mode, this mode can reduce the

output voltage variation of the constant voltage/booster

voltage circuit of the LCD system.

The normal mode changes to the heavy load protection

mode in the following case:

S1C62N33 TECHNICAL HARDWARE EPSON I-73

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

➀When the software changes the mode to the heavy load

protection mode (HVLD = "1")

The heavy load protection mode switches the constant

voltage circuit of the LCD system to the high-stability

mode from the low current consumption mode. Conse-

quently, more current is consumed in the heavy load

protection mode than in the normal mode. Unless it is

necessary, be careful not to set the heavy load protection

mode with the software.

This section explains the timing for when the SVD circuit

writes the result of the source voltage detection to the

SVDDT latch.

Turning the SVD operation ON/OFF is controlled through

the software (HVLD, SVDON). Moreover, when a drop in

source voltage (SVDON = "1") is detected, SVD operation is

periodically performed by the hardware until the source

voltage is recovered (SVDON = "0").

The result of the source voltage detection is written to the

SVDDT latch by the SVD circuit, and this data can be read

out by the software to find the status of the source voltage.

There are three methods, explained below, for executing the

detection operation of the SVD circuit.

(1)Sampling with HVLD set to "1"

When HVLD is set to "1" and SVD sampling executed, the

detection results can be written to the SVDDT latch in

the following two timings.

➀Immediately after the time for one instruction cycle

has ended immediately after HVLD = "1"

➁Immediately after sampling in the 2 Hz cycle output by

the clock timer while HVLD = "1"

Consequently, the SVDDT latch data is loaded immedi-

ately after HVLD has been set to "1", and at the same

time the new detection result is written in 2 Hz cycles.

To obtain a stable SVD detection result, the SVD circuit

must be set to ON with at least 100 µs. Consequently,

when the CPU system clock is fosc3 in S1C62A33, the

detection result at the timing in ➀ above may be invalid

or incorrect. (When performing SVD detection using the

timing in ➀, be sure that the CPU system clock is fosc1.)

Detection timing of

SVD circuit

I-74 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

(2)Sampling with SVDON set to "1"

When SVDON is set to "1", SVD detection is executed. As

soon as SVDON is reset to "0" the detection result is

loaded to the SVDDT latch. To obtain a stable SVD detec-

tion result, the SVD circuit must be set to ON with at

least 100 µs. Hence, to obtain the SVD detection result,

follow the programming sequence below.

0. Set HVLD to "1"(only when the CPU system clock is

fosc3 in S1C62A33)

1. Set SVDON to "1"

2. Maintain at 100 µs minimum

3. Set SVDON to "0"

4. Read out SVDDT

5. Set HVLD to "0"(only when the CPU system clock is

fosc3 in S1C62A33)

However, when a crystal oscillation clock (fosc1) is se-

lected for the CPU system clock in S1C62N33, S1C62L33,

and S1C62A33, the instruction cycles are long enough,

so that there is no need for concern about maintaining

100 µs for the SVDON = "1" with the software.

(3)Sampling by hardware when SVDDT latch is set to "1"

When SVDDT latch is set to "1", the detection results can

be written to the SVDDT latch in the following two tim-

ings (same as that sampling with HVLD set to "1").

➀Immediately after the time for one instruction cycle

has ended immediately after SVDDT = "1"

➁Immediately after sampling in the 2 Hz cycle output by

the clock timer while SVDDT = "1"

Consequently, the SVDDT latch data is loaded immedi-

ately after SVDDT latch has been set to "1", and at the

same time the new detection result is written in 2 Hz

cycles.

To obtain a stable SVD detection result, the SVD circuit

must be set to ON with at least 100 µs.

When the CPU system clock is fosc3 in S1C62A33, the

detection result at the timing in ➀ above may be invalid

or incorrect.

S1C62N33 TECHNICAL HARDWARE EPSON I-75

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

Control of SVD cir-

cuit

Table 4.12 shows the SVD circuit's control bits and their

addresses.

Table 4.12 Control bits of SVD circuit

When "1" is written: Heavy load protection mode is set

When "0" is written: Heavy load protection mode

is released

Read-out: Valid

When HVLD is set to "1", the IC operating status enters the

heavy load protection mode and at the same time the supply

voltage detection of the SVD circuit is controlled (ON/OFF).

When HVLD is set to "1", sampling control is executed for

the SVD circuit ON time. There are two types of sampling

time, as follows:

(1)The time of one instruction cycle immediately after HVLD

= "1"

(2)Sampling at cycles of 2 Hz output by the clock timer

while HVLD = "1"

The SVD circuit must be made ON with at least 100 µs for

the SVD circuit to respond. Hence, when the CPU system

clock is fosc3 in S1C62A33, the detection result at the

timing in (1) above may be invalid or incorrect. (When per-

forming SVD detection using the timing in (1), be sure that

the CPU system clock is fosc1.)

HVLD:

Heavy load protection

mode (76H·D3)

Address Comment

D3 D2 D1 D0 Name SR

76H

HVLD SVDDT

SVDON

EISWIT1 EISWIT0

R/W

HVLD

EISWIT1

EISWIT0

Enable

Mask

SVD evaluation data (at read-out)

SVD ON/OFF (at writing)

Interrupt mask register

(stopwatch 1 Hz)

Interrupt mask register

(stopwatch 10 Hz)

R/W SVDDT

SVDON 0

Heavy

load Normal

Low voltage Normal

OFF

Heavy load protection mode register

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

I-76 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

When SVD sampling is done with HVLD set to "1", the

results are written to the SVDDT latch in the timing as

follows:

(1)As soon as the time has elapsed for one instruction cycle

immediately following HVLD = "1"

(2)Immediately on completion of sampling at cycles of 2 Hz

output by the clock timer while HVLD = "1"

Consequently, the SVDDT latch data is written immediately

after HVLD is set to "1", and at the same time the new

detection result is written in 2 Hz cycles.

When "0" is written: SVD detection OFF

When "1" is written: SVD detection ON

When "0" is read out: Source voltage (VDD–VSS)

is higher than SVD set value

When "1" is read out: Source voltage (VDD–VSS)

is lower than SVD set value

Note that the function of this bit when written is different to

when read out.

When this bit is written to, ON/OFF of the SVD detection

operation is controlled; when this bit is read out, the result of

the SVD detection (contents of SVDDT latch) is obtained.

Appreciable current is consumed during operation of SVD

detection, so keep SVD detection OFF except when necessary.

When SVDON is set to "1", SVD detection is executed. As

soon as SVDON is reset to "0" the detection result is loaded

to the SVDDT latch. To obtain a stable SVD detection result,

the SVD circuit must be set to ON with at least 100 µs.

Hence, to obtain the SVD detection result, follow the pro-

gramming sequence below.

0. Set HVLD to "1"(only when the CPU system clock is

fosc3 in S1C62A33)

1. Set SVDON to "1"

2. Maintain at 100 µs minimum

3. Set SVDON to "0"

4. Read out SVDDT

5. Set HVLD to "0"(only when the CPU system clock is

fosc3 in S1C62A33)

However, when a crystal oscillation clock (fosc1) is selected

for the CPU system clock in S1C62N33, S1C62L33, and

S1C62A33, the instruction cycles are long enough, so that

there is no need for concern about maintaining 100 µs for

the SVDON = "1" with the software.

SVDON/SVDDT:

SVD detection/SVD data

(76H·D2)

S1C62N33 TECHNICAL HARDWARE EPSON I-77

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

(1)It takes 100 µs from the time the SVD circuit goes ON

until a stable result is obtained. For this reason, keep the

following software notes in mind:

➀When the CPU system clock is fosc1

1. When detection is done at HVLD

After writing "1" on HVLD, read the SVDDT after 1

instruction has passed.

2. When detection is done at SVDON

After writing "1" on SVDON, write "0" after at least

100 µs has lapsed (possible with the next instruc-

tion) and then read the SVDDT.

➁When the CPU system clock is fosc3 (in case of

S1C62A33 only)

1. When detection is done at HVLD

After writing "1" on HVLD, read the SVDDT after 0.6

sec has passed. (HVLD holds "1" for at least 0.6 sec)

2. When detection is done at SVDON

Before writing "1" on SVDON, write "1" on HVLD

first; after at least 100 µs has lapsed after writing

"1" on SVDON, write "0" on SVDON and then read

the SVDDT.

(2)

SVDON resides in the same bit at the same address as

SVDDT, and one or the other is selected by write or read

operation. When writing a "1" to SVDON use the OR

command, and when writing a "0" use the AND command.

No other commands should be used for this purpose.

(3)Select one of the following software processing to return

to the normal mode after a heavy load has been driven in

the heavy load protection mode (S1C62L33).

➀ After heavy load drive is completed, return to the

normal mode after at least one second has elapsed.

➁After heavy load drive is completed, switch SVD ON

and OFF (at least 100 µs is necessary for the ON

status) and then return to the normal mode.

The S1C62N33/62A33 returns to the normal mode after

driving a heavy load without special software processing.

(4)When the SVD is to be turned on during operation in the

heavy load protection mode, limit the ON time to 10 ms

per second of operation time.

Programming notes

I-78 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Serial Interface (SIN, SOUT, SCLK, SIOF)4.13

Configuration of

serial interface

The S1C62N33 has a synchronous clock type 8 bits serial

interface built-in.

The configuration of the serial interface is shown in Figure

4.13.1.

The CPU, via the 8 bits shift register, can read the serial

input data from the SIN terminal. Moreover, via the same 8

bits shift register, it can convert parallel data to serial data

and output it to the SOUT terminal.

The synchronous clock for serial data input/output may be

set by selecting by software any one of 3 types of master

mode (internal clock mode: when the S1C62N33 is to be the

master for serial input/output) and a type of slave mode

(external clock mode: when the S1C62N33 is to be the slave

for serial input/output).

Also, when the serial interface is used at slave mode, SIOF

signal which indicates whether or not the serial interface is

available to transmit or receive output to output port SIOF.

SD0–SD7

SIN

SCLK

SCS0 SCS1 SEN

Output

latch

EISIO

Serial interface

interrupt control circuit ISIO

SOUT

SIOF

SCTRG

Serial interface

activating circuit

System clock

Serial clock

generator

Shift register (8 bits)

Serial clock

selector Serial clock

counter

Fig. 4.13.1

Configuration of

serial interface

S1C62N33 TECHNICAL HARDWARE EPSON I-79

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Master mode and

slave mode of

serial interface

The serial interface of the S1C62N33 has two types of opera-

tion mode: master mode and slave mode.

In the master mode, it uses an internal clock as synchro-

nous clock of the built-in shift register, generates this

internal clock at the SCLK terminal and controls the exter-

nal (slave side) serial device.

In the slave mode, the synchronous clock output from the

external (master side) serial device is input from the SCLK

terminal and uses it as the synchronous clock to the built-

in shift register.

The master mode and slave mode are selected by writing

data to registers SCS1 and SCS0 (address F2H·D2, D3).

When the master mode is selected, a synchronous clock

may be selected from among 3 types as shown in Table

4.13.1.

SCS1

SCS0

Mode

Master mode

Slave mode

Synchronous Clock

CLK

CLK/2

CLK/4

External clock

CLK: system clock

At initial reset, the slave mode (external clock mode) is

selected.

Moreover, the synchronous clock, along with the input

/output of the 8 bits serial data, is controlled as follows:

• At master mode, after output of 8 clocks from the SCLK

terminal, clock output is automatically suspended and

SCLK terminal is fixed at low level.

• At slave mode, after input of 8 clocks to the SCLK termi-

nal, subsequent clock inputs are masked.

When using the serial interface in the master mode, CPU system

clock is used as the synchronous clock. Accordingly, when the

serial interface is operating, system clock switching (fosc1

↔

fosc3)

should not be performed.

Table 4.13.1

Synchronous clock selection

Note

I-80 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

A sample basic serial input/output portion connection is

shown in Figure 4.13.2.

Fig. 4.13.2

Sample basic connection of

serial input/output section

a. Master mode

b. Slave mode

S1C62N33

SCLK

SOUT

SIN

Input terminal

External serial

device

CLK

SOUT

SIN

READY

S1C62N33

SCLK

SOUT

SIN

SIOF

External serial

device

CLK

SOUT

SIN

Input terminal

S1C62N33 TECHNICAL HARDWARE EPSON I-81

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Data input/output

and interrupt func-

tion

The serial interface of S1C62N33 can input/output data via

the internal 8 bits shift register. The shift register operates

by synchronizing with either the synchronous clock output

from SCLK terminal (master mode), or the synchronous

clock input to SCLK (slave mode).

The serial interface generates interrupt on completion of the

8 bits serial data input/output. Detection of serial data

input/output is done by the counting of the synchronous

clock (SCLK); the clock completes input/output operation

when 8 counts (equivalent to 8 cycles) have been made and

then generates interrupt.

The serial data input/output procedure data is explained

below:

(1)Serial data output procedure and interrupt

The S1C62N33 serial interface is capable of outputting

parallel data as serial data, in units of 8 bits.

By setting the parallel data to 4 bits registers SD0–SD3

(address F0H) and SD4–SD7 (address F1H) individually

and writing "1" to SCTRG bit (address 77H·D3), it syn-

chronizes with the synchronous clock and serial data is

output at the SOUT terminal. The synchronous clock

used here is as follows: in the master mode, internal

clock which is output to the SCLK terminal while in the

slave mode, external clock which is input from the SCLK

terminal. The serial output of the SOUT termina changes

with the rising edge of the clock that is input or output

from the SCLK terminal.

The serial data to the built-in shift register is shifted with

the rising edge of the SCLK signal when SE2 bit (address

F2H·D1) is "1" and is shifted with the falling edge of the

SCLK signal when SE2 bit (address F2H·D1) is "0".

When the output of the 8 bits data from SD0 to SD7 is

completed, the interrupt factor flag ISIO (address

F3H·D0) is set to "1" and interrupt is generated. Moreo-

ver, the interrupt can be masked by the interrupt mask

I-82 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

(2)Serial data input procedure and interrupt

The S1C62N33 serial interface is capable of inputting

serial data as parallel data, in units of 8 bits.

The serial data is input from the SIN terminal, synchro-

nizes with the synchronous clock, and is sequentially

read in the 8 bits shift register. As in the above item (1),

the synchronous clock used here is as follows: in the

master mode, internal clock which is output to the SCLK

terminal while in the slave mode, external clock which is

input from the SCLK terminal.

The serial data to the built-in shift register is read with

the rising edge of the SCLK signal when SE2 bit is "1"

and is read with the falling edge of the SCLK signal when

SE2 bit is "0". Moreover, the shift register is sequentially

shifted as the data is fetched.

When the input of the 8 bits data from SD0 to SD7 is

completed, the interrupt factor flag ISIO is set to "1" and

interrupt is generated. Moreover, the interrupt can be

masked by the interrupt mask register EISIO. Note,

however, that regardless of the setting of the interrupt

mask register, the interrupt factor flag is set to "1" after

input of the 8 bits data.

The data input in the shift register can be read from data

registers SD0–SD7 by software.

S1C62N33 TECHNICAL HARDWARE EPSON I-83

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

(3) Serial data input/output permutation

S1C62N33 allows the input/output permutation of serial

data to be selected by mask option as to either LSB first

or MSB first. The block diagram showing input/output

permutation in case of LSB first and MSB first is provided

in Figure 4.13.3.

(4)SIOF signal

When the S1C62N33 serial interface is used in the slave

mode (external clock mode), SIOF is used to indicate

whether the internal serial interface is available to trans-

mit or receive data for the master side (external) serial

device.

SIOF signal becomes "1" (high) when the S1C62N33 serial

interface becomes available to transmit or receive data;

normally, it is at "0" (low).

SIOF signal changes from "0" to "1" immediately after "1"

is written to SCTRG and returns from "1" to "0" when

eight synchronous clock has been counted.

Fig. 4.13.3

Serial data input/output

permutation

SIN

Address F1H

Address F0H Address F1H

Address F0H

Output

latch

SOUT

SD3 SD2 SD1 SD0

SD4 SD5 SD6 SD7

SD7 SD6 SD5 SD4

SD0 SD1 SD2 SD3

Output

latch

(In case of LSB first)

(In case of MSB first)

I-84 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

(5)Timing chart

The S1C62N33 serial interface timing chart is shown in

Figure 4.13.4.

b. Timing chart, SE2 = "0"

a. Timing chart, SE2 = "1"

Fig. 4.13.4

Serial interface timing chart

SCTRG

SCLK

SIN

8-BIT SHIFT REGISTER

SOUT

ISIO

SIOF

SCTRG

SCLK

SIN

8-BIT SHIFT REGISTER

SOUT

ISIO

SIOF

S1C62N33 TECHNICAL HARDWARE EPSON I-85

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Mask option The serial interface may be selected for the following by

mask option.

(1)Whether or not the SIN terminal will use built-in pull

down resistor may be selected.

If the use of no pull down resistor is selected, take care

that floating state does not occur at the SIN terminal.

When the SIN terminal is not used, the use of pull down

resistor should be selected.

(2)Either complementary output or P channel (Pch) open

drain as output specification for the SOUT terminal may

be selected.

However, even if Pch open drain has been selected, appli-

cation of voltage exceeding power source voltage to the

SOUT terminal will be prohibited.

(3)Whether or not the SCLK terminal will use pull down

resistor which is turned ON during input mode (external

clock) may be selected.

If the use of no pull down resistor is selected, take care

that floating state does not occur at the SCLK terminal

during input mode.

Normally, the use of pull down resistor should be se-

lected.

(4)As output specification during output mode, either com-

plementary output or P channel (Pch) open drain output

may be selected for the SCLK terminal.

(5)Positive or negative logic can be selected for the signal

logic of the SCLK pin (SCLK or SCLK).

However, keep in mind that only pull-down resistance

can be set for the input mode (pull-up resistance is not

built-in).

(6)LSB first or MSB first as input/output permutation of

serial data may be selected.

I-86 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Control of serial

interface

Table 4.13.2 lists the serial interface control bits and their

addresses.

Table 4.13.2 Control registers of serial interface

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Address Comment

D3 D2 D1 D0 Name SR

F0H

F1H

F2H

F3H

77H

EIK10 DFK10 K10

R/W EIK10

DFK10

K10

Interrupt mask register (K10)

Input comparison register (K10)

Input port (K10)

SCTRG

SIOF

SD3 SD2 SD1 SD0

SD7 SD6 SD5 SD4

SCS1 SCS0 SE2 EISIO

–– –ISIO

R/W

SD3

SD2

SD1

SD0

Serial interface data regsiter

Low order (SD0–SD3)

SD7

SD6

SD5

SD4

Serial interface data regsiter

High order (SD4–SD7)

SCS1

SCS0

SE2

EISIO

–

ISIO 0 Yes No

Clock mode selection register

(SCS0, SCS1)

Clock edge selection register

Interrupt mask register (serial interface)

Unused *5

Interrupt factor flag (serial interface) *4

SCTRG

SIOF –

0Trigger

RUN

Serial interface clock trigger

SIOF

–

STOP

Rising

Enable

Falling

Mask

Enable

Falling

High

Mask

Rising

Low

S1C62N33 TECHNICAL HARDWARE EPSON I-87

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

SD0–SD3, SD4–SD7:

Serial interface data

registers

(F0H, F1H)

These registers are used for writing and reading serial data.

• During writing operation

When "1" is written: High level

When "0" is written: Low level

Writes serial data will be output to SOUT terminal. From the

SOUT terminal, the data converted to serial data as high

(VDD) level bit for bits set at "1" and as low (VSS) level bit for

bits set at "0".

• During reading operation

When "1" is read out: High level

When "0" is read out: Low level

The serial data input from the SIN terminal can be read by

this register.

The data converted to parallel data, as high (V

) level bit "1"

and as low (V

) level bit "0" input from SIN terminal. Per-

form data reading only while the serial interface is halted

(i.e., the synchronous clock is neither being input or output).

At initial reset, these registers will be undefined.

Selects the synchronous clock for the serial interface

(SCLK).

SCS1, SCS0:

Clock mode selection

(F2H·D3, D2)

Table 4.13.3

Synchronous clock selection

SCS1

SCS0

Mode

Master mode

Slave mode

Synchronous Clock

CLK

CLK/2

CLK/4

External clock

CLK: system clock

Synchronous clock (SCLK) is selected from among the above

4 types: 3 types of internal clock and external clock.

At initial reset, external clock is selected.

I-88 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Selects the timing for reading in the serial data input.

When "1" is written: Rising edge of SCLK

When "0" is written: Falling edge of SCLK

Read-out: Valid

Selects whether the fetching for the serial input data to

registers (SD0–SD7) at the rising edge (at "1" writing) or

falling edge (at "0" writing) of the SCLK signal.

Pay attention if the synchtonous clock goes into reverse

phase (SCLK → SCLK) through the mask option.

SCLK rising = SCLK falling, SCLK falling = SCLK rising

When the internal clock is selected as the synchronous

clock (SCLK), a hazard occurs in the synchronous clock

(SCLK) when data is written to register SE2.

The input data fetching timing may be selected but output

timing for output data is fixed at SCLK rising edge.

At initial reset, falling edge of SCLK (SE2 = "0") is selected.

This is the interrupt mask register of the serial interface.

When "1" is written: Enabled

When "0" is written: Masked

Read-out: Valid

At initial reset, this register is set to "0" (mask).

This is the interrupt factor flag of the serial interface.

When "1" is read out: Interrupt has occurred

When "0" is read out: Interrupt has not occurred

Writing: Invalid

From the status of this flag, the software can decide whether

the serial interface interrupt.

The interrupt factor flag is reset when it has been read out.

Note, however, that even if the interrupt is masked, this flag

will be set to "1" after the 8 bits data input/output.

Be sure that the interrupt factor flag reading is done with

the interrupt in the DI status (interrupt flag = "0").

At initial reset, this flag is set to "0".

SE2:

Clock edge selection

(F2H·D1)

EISIO:

Interrupt mask register

(F2H·D0)

ISIO:

Interrupt factor flag

(F3H·D0)

S1C62N33 TECHNICAL HARDWARE EPSON I-89

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

SCTRG:

Clock trigger

(77H·D3)

SIOF:

Serial interface running

status

(77H·D3)

This is a trigger to start input/output of synchronous clock.

When "1" is written: Trigger

When "0" is written: No operation

Read-out: SIOF

When this trigger is supplied to the serial interface activat-

ing circuit, the synchronous clock (SCLK) input/output is

started.

As a trigger condition, it is required that data writing or

reading on data registers SD0–SD7 be performed prior to

writing "1" to SCTRG. (The internal circuit of the serial

interface is initiated through data writing/reading on data

registers SD0–SD7.)

Supply trigger only once every time the serial interface is

placed in the RUN state. Refrain from perfoming trigger

input multiple times, as leads to malfunctioning.

Moreover, when the synchronous clock SCLK is external

clock, start to input the external clock after the trigger.

SCTRG resides in the same bit at the same address as SIOF,

and one or the other is selected by write or read operation.

When writing a "1" to SCTRG use the OR command, and

when writing a "0" use the AND command. No other com-

mands should be used for this purpose.

Indicates the running status of the serial interface.

When "1" is read out: RUN status

When "0" is read out: STOP status

Writing: SCTRG

The RUN status is indicated from immediatery after "1" is

written to SCTRG bit through to the end of serial data in-

put/output.

I-90 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Programming notes (1)If the bit data of SE2 changes while SCLK is in the mas-

ter mode, a hazard will be output to the SCLK pin. If this

poses a problem for the system, be sure to set the SCLK

to the external clock if the bit data of SE2 is to be

changed.

(2)Be sure that read-out of the interrupt factor flag (ISIO) is

done only when the serial port is in the STOP status

(SIOF = "0") and the DI status (interrupt flag = "0"). If

read-out is performed while the serial data is in the RUN

status (during input or output), the data input or output

will be suspended and the initial status resumed. Read-

out during the EI status (interrupt flag = "1") causes

malfunctioning.

(3) When using the serial interface in the master mode, the

synchronous clock uses the CPU system clock. Accord-

ingly, do not change the system clock (fosc1 ↔ fosc3)

while the serial interface is operating.

(4) Perform data writing/reading to data registers SD0–SD7

only while the serial interface is halted (i.e., the synchro-

nous clock is neither being input or output).

(5) As a trigger condition, it is required that data writing or

reading on data registers SD0–SD7 be performed prior to

writing "1" to SCTRG. (The internal circuit of the serial

interface is initiated through data writing/reading on

data registers SD0–SD7.) Supply trigger only once every

time the serial interface is placed in the RUN state. More-

over, when the synchronous clock SCLK is external clock,

start to input the external clock after the trigger.

(6) Writing to the interrupt mask registers can be done only

in the DI status (interrupt flag = "0").

Writing during EI status will cause malfunction.

(7) SCTRG resides in the same bit at the same address as

SIOF, and one or the other is selected by write or read

operation. When writing a "1" to SCTRG use the OR

command, and when writing a "0" use the AND com-

mand. No other commands should be used for this pur-

pose.

S1C62N33 TECHNICAL HARDWARE EPSON I-91

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Interrupt and HALT

The S1C62N33 Series provides the following interrupt set-

tings, each of which is maskable.

External interrupt: Input interrupt (two)

Internal interrupt: Timer interrupt (three)

Stopwatch interrupt (two)

Serial interface interrupt (one)

To authorize interrupt, the interrupt flag must be set to "1"

(EI) and the necessary related interrupt mask registers must

be set to "1" (enable).

When an interrupt occurs the interrupt flag is automatically

reset to "0" (DI), and interrupts after that are inhibited.

When a HALT instruction is input the CPU operating clock

stops, and the CPU enters the HALT status.

The CPU is reactivated from the HALT status when an inter-

rupt request occurs.

If reactivation is not caused by an interrupt request, initial

reset by the watchdog timer causes reactivates the CPU

(when the watchdog timer is enabled).

Figure 4.14 shows the configuration of the interrupt circuit.

4.14

I-92 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Interrupt factor flag

Interrupt mask register

Differential register

Interrupt flag

INT

(interrupt request)

Program counter

(four low-order bits)

(MSB)

(LSB)

Interrupt vector

SWIT1

EISWIT1

SWIT0

EISWIT0

TI2

ETI2

TI8

ETI8

TI32

ETI32

K00

K01

K02

K03

K10

DFK00

DFK01

EIK00

EIK01

DFK02

EIK02

DFK03

EIK03

DFK10

EIK10

IK0

IK1

ISIO

EISIO

Fig. 4.14

Configuration of

interrupt circuit

S1C62N33 TECHNICAL HARDWARE EPSON I-93

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Table 4.14.1 shows the factors for generating interrupt

requests.

The interrupt flags are set to "1" depending on the corre-

sponding interrupt factors.

The CPU operation is interrupted when any of the conditions

below set an interrupt factor flag to "1".

• The corresponding mask register is "1" (enabled)

• The interrupt flag is "1" (EI)

The interrupt factor flag is a read-only register, but can be

reset to "0" when the register data is read out.

At initial reset, the interrupt factor flags are reset to "0".

Read the interrupt factor flags only in the DI status (interrupt flag =

"0").

A malfunction could result from read-out during the EI status

(interrupt flag = "1").

Interrupt factors

Note

Table 4.14.1

Interrupt factors

Interrupt Factor

Clock timer 2 Hz falling edge

Clock timer 8 Hz falling edge

Clock timer 32 Hz falling edge

Interrupt Factor Flag

TI2

TI8

TI32

SWIT1

SWIT0

IK0

IK1

ISIO

(79H D2)

(79H D1)

(79H D0)

(7AH D1)

(7AH D0)

(7AH D2)

(7AH D3)

(F3H D0)

Stopwatch counter

1 Hz falling edge

Stopwatch counter

10 Hz falling edge

Input data (K00–K03)

Rising or falling edge

Input data (K10)

Rising or falling edge

Serial interface

Data (8 bits) input/output has completed

I-94 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Specific masks and

factor flags for inter-

rupt

Note

Table 4.14.2

Interrupt mask registers and

interrupt factor flags

The interrupt factor flags can be masked by the correspond-

ing interrupt mask registers.

The interrupt mask registers are read/write registers. They

are enabled (interrupt authorized) when "1" is written to

them, and masked (interrupt inhibited) when "0" is written

to them.

At initial reset, the interrupt mask register is set to "0".

Table 4.14.2 shows the correspondence between interrupt

mask registers and interrupt factor flags.

Writing to the interrupt mask registers can be done only in the DI

status (interrupt flag = "0").

A malfunction could result from writing during the EI status.

* There is an interrupt mask register for each pin

of the input ports.

Interrupt Mask Register

ETI2

ETI8

ETI32

EISWIT1

EISWIT0

EISIO

EIK03

EIK02

EIK01

EIK00

EIK10

Interrupt Factor Flag

(78H D2)

(78H D1)

(78H D0)

(76H D1)

(76H D0)

(F2H D0)

(75H D3)

(75H D2)

(75H D1)

(75H D0)

(77H D2)

TI2

TI8

TI32

SWIT1

SWIT0

ISIO

IK1

(79H D2)

(79H D1)

(79H D0)

(7AH D1)

(7AH D0)

(F3H D0)

(7AH D3)

IK0 (7AH D2)

S1C62N33 TECHNICAL HARDWARE EPSON I-95

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

When an interrupt request is input to the CPU, the CPU

begins interrupt processing. After the program being exe-

cuted is terminated, the interrupt processing is executed in

the following order.

➀The address data (value of program counter) of the pro-

gram to be executed next is saved in the stack area

(RAM).

➁The interrupt request causes the value of the interrupt

vector (page 1, 01H–0FH) to be set in the program coun-

ter.

➂The program at the specified address is executed (execu-

tion of interrupt processing routine by software).

Table 4.14.3 shows the correspondence of interrupt requests

and interrupt vectors.

The processing in

➀

and

➁

above take 12 cycles of the CPU

system clock.

Interrupt vectors

Note

Table 4.14.3

Interrupt request and

interrupt vectors

Interrupt Request

Stopwatch interrupt

Timer interrupt

Input (K00–K03, K10) interrupt

Serial interface interrupt

Enabled

Masked

Enabled

Masked

Enabled

Masked

Enabled

Masked

PCS3

PCS2

PCS1

PCS0

PC Value

The four low-order bits of the program counter are indirectly

addressed through the interrupt request.

I-96 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Tables 4.14.4(a) and (b) show the interrupt control bits and

their addresses.

Table 4.14.4(a) Interrupt control bits (1)

Control of interrupt

and HALT

Address Comment

D3 D2 D1 D0 Name SR *1 10

74H

DFK03 DFK02 DFK01 DFK00

R/W

DFK03

DFK02

DFK01

DFK00

Falling

Rising

Differential register

(K00–K03)

75H

76H

EIK03 EIK02 EIK01 EIK00

HVLD SVDDT

SVDON

EISWIT1 EISWIT0

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

HVLD

EISWIT1

EISWIT0

Enable

Mask

SVD evaluation data (at read-out)

SVD ON/OFF (at writing)

Interrupt mask register

(stopwatch 1 Hz)

Interrupt mask register

(stopwatch 10 Hz)

Interrupt mask register

(K00–K03)

R/W SVDDT

SVDON 0

Heavy

load Normal

Normal

OFF

Heavy load protection mode register

77H

DFK10 K10

EIK10

DFK10

K10

Enable

Falling

High

Mask

Rising

Low

Interrupt mask register (K10)

Differential register (K10)

Input port (K10)

R/W

EIK10

SCTRG

SIOF –

Serial interface clock trigger

SIOF

Trigger

Run

–

Stop

SCTRG

SIOF

Low voltage

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

S1C62N33 TECHNICAL HARDWARE EPSON I-97

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Table 4.14.4(b) Interrupt control bits (2)

Address Comment

D3 D2 D1 D0 Name SR *1 10

78H

79H

CSDC ETI2 ETI8 ETI32

TI2 TI8 TI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

–

TI2

TI8

TI32

Yes

Unused *5

Interrupt factor flag (clock timer 2 Hz) *4

Interrupt factor flag (clock timer 8 Hz) *4

Interrupt factor flag (clock timer 32 Hz) *4

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

7AH

IK1 IK0 SWIT1 SWIT0

IK1

IK0

SWIT1

SWIT0

Yes

–

F3H

–– –ISIO

–

ISIO 0 Yes No

F2H

SCS1 SCS0 SE2 EISIO

R/W

SCS1

SCS0

SE2

EISIO

Rising

Enable

Falling

Mask

Unused *5

Interrupt factor flag (serial interface) *4

Interrupt factor flag (K10) *4

Interrupt factor flag (K00–K03) *4

Interrupt factor flag (stopwatch 1 Hz) *4

Interrupt factor flag (stopwatch 10 Hz) *4

Clock edge selection register

(SCS0, SCS1)

Clock edge selection register

Interrupt mask register (serial interface)

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

I-98 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

–ETI32, ETI8, ETI2: Interrupt mask registers (78H·D0–D2)

–TI32, TI8, TI2: Interrupt factor flags (79H·D0–D2)

See "Control of clock timer".

–EISWIT0, EISWIT1: Interrupt mask registers (76H·D0, D1)

–SWIT0, SWIT1: Interrupt factor flags (7AH·D0, D1)

See "Control of stopwatch counter".

–EISIO: Interrupt mask register (F2H·D0)

–ISIO: Interrupt factor flag (F3H·D0)

See "Control of serial interface".

–DFK00–DFK03: Differential registers (74H)

–EIK00–EIK03: Interrupt mask registers (75H)

–IK0: Interrupt factor flag (7AH·D2)

See "Control of input ports".

–DFK10: Differential register (77H·D1)

–EIK10: Interrupt mask register (77H·D2)

–IK1: Interrupt factor flag (7AH·D3)

See "Control of input ports".

S1C62N33 TECHNICAL HARDWARE EPSON I-99

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Programming notes (1)When the interrupt mask register (EIK) is set to "0", the

interrupt factor flag (IK) of the input port cannot be set

even though the pin status of the input port has changed.

(2)The interrupt factor flags of the clock timer and stop-

watch counter (TI, SWIT) are set when the timing condi-

tion is established, even if the interrupt mask registers

(ETI, EISWIT) are set to "0".

(3)Read out the interrupt factor flags only in the DI status

(interrupt flag = "0"). If read-out is performed in the EI

status a malfunction will result.

(4)Writing to the interrupt mask registers can be done only

in the DI status (interrupt flag = "0").

Writing during EI status will cause malfunction.

I-100 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 5: SUMMARY OF NOTES

SUMMARY OF NOTES

Notes for Low Current Consumption

The S1C62N33 Series contains control registers for each of

the circuits so that current consumption can be lowered.

These control registers lower the current consumption

through programs that operate the circuits at the minimum

levels.

The following text explains the circuits that can control

operation and their control registers. Refer to these when

putting programs together.

Table 5.1 Circuits and control registers

CHAPTER 5

5.1

Below are the circuit statuses at initial reset.

CPU: Operating status

CPU operating frequency: Low speed side (CLKCHG = "0"),

OSC3 oscillation circuit stop

status (OSCC = "0")

Heavy load protection mode: Normal operating mode

(HVLD = "0")

SVD circuit:

OFF status (HVLD = "0", SVDON = "0")

Analog comparator: OFF status (AMPON = "0")

Also, be careful about panel selection because the current

consumption can differ by the order of several µA on ac-

count of the LCD panel characteristics.

Circuits (and Items)

CPU

CPU operation frequency

(SMC62A33)

Heavy load protection mode

SVD circuit

Analog comparator

Control Registers

HALT instruction

CLKCHG, OSCC

HVLD

HVLD, SVDON

AMPON

Order of Consumed Current

See electrical characteristics (Chapter 7)

Several tens µA

S1C62N33 TECHNICAL HARDWARE EPSON I-101

CHAPTER 5: SUMMARY OF NOTES

Summary of Notes by Function

Here, the cautionary notes are summed up by function

category. Keep these notes well in mind when programming.

Memory is not mounted in unused area within the memory

map and in memory area not indicated in this manual. For

this reason, normal operation cannot be assured for pro-

grams that have been prepared with access to these areas.

When oscillation is stopped, reset input from the reset

terminal triggered by the noise reject circuit cannot be

received. When oscillation is stopped, initialization of inter-

nal circuits is triggered by the oscillation detection circuit.

When the watchdog timer is being used, the software must

reset it within 3-second cycles, and timer data (WD0–WD2)

cannot be used for timer applications.

(1)It takes at least 5 ms from the time the OSC3 oscillation

circuit starts operating until the oscillation stabilizes.

Consequently, when switching the CPU operation clock

from OSC1 to OSC3, do this after a minimum of 5 ms

have elapsed since the OSC3 oscillation went ON. Fur-

ther, the oscillation stabilization time varies depending on

the external oscillator characteristics and conditions of

use, so allow ample margin when setting the wait time.

(2)When switching the clock from OSC3 to OSC1, use a

separate instruction for switching the OSC3 oscillation

OFF. An error in the CPU operation can result if this

processing is performed at the same time by the one

instruction.

(1)When input ports are changed from high to low by pull-

down resistance, the fall of the waveform is delayed on

account of the time constant of the pull-down resistance

and input gate capacitance. Hence, when fetching input

ports, set an appropriate wait time. Particular care needs

to be taken of the key scan during key matrix configura-

tion. Aim for a wait time of about 1 ms.

5.2

Input port

Oscillation circuit

and prescaler

Watchdog timer

Reset terminal

Memory

I-102 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 5: SUMMARY OF NOTES

(2)When "noise rejector circuit enable" is selected with the

mask option, a maximum delay of 1 ms occurs from the

time the interrupt conditions are established until the

interrupt factor flag (IK) is set to "1" (until the interrupt is

actually generated). Hence, pay attention to the timing

when reading out (resetting) the interrupt factor flag. For

example, immediately after performing a key scan with

the key matrix, the flag will not be reset because the

delay in the interrupt factor flag read-out means the flag

is set after read-out. (The key scan changes the input

status and the interrupt factor flag is set, necessitating

read-out to reset the flag.)

(3)Input interrupt programing related precautions

When the content of the mask register is rewritten, while the port K

input is in the active status. The input interrupt factor flags are set

at ➀ and ➁, ➀ being the interrupt due to the falling edge and ➁ the

interrupt due to the rising edge.

Port K input

Factor flag set Not set ➁Factor flag set

Differential register

Mask register

Active status Active status

Rising edge interrupt

➀

Falling edge interrupt

When using an input interrupt, if you rewrite the content

of the mask register, when the value of the input terminal

which becomes the interrupt input is in the active status,

the factor flag for input interrupt may be set. Therefore,

when using the input interrupt, the active status of the

input terminal implies

input terminal = low status, when the falling edge

interrupt is effected and

input terminal = high status, when the rising edge

interrupt is effected.

When an interrupt is triggered at the falling edge of an

input terminal, a factor flag is set with the timing of ➀

shown in Figure 5.2.1. However, when clearing the con-

tent of the mask register with the input terminal kept in

the low status and then setting it, the factor flag of the

input interrupt is again set at the timing that has been

set.

Fig. 5.2.1

Input interrupt timing

S1C62N33 TECHNICAL HARDWARE EPSON I-103

CHAPTER 5: SUMMARY OF NOTES

Consequently, when the input terminal is in the active

status (low status), do not rewrite the mask register

(clearing, then setting the mask register), so that a factor

flag will only set at the falling edge in this case. When

clearing, then setting the mask register, set the mask

status (high status).

When an interrupt is triggered at the rising edge of the

input terminal, a factor flag will be set at the timing of ➁

shown in Figure 5.2.1. In this case, when the mask

registers cleared, then set, you should set the mask

In addition, when the mask register = "1" and the content

of the differential register is rewritten in the input termi-

nal active status, an input interrupt factor flag may be

set. Thus, you should rewrite the content of the differen-

tial register in the mask register = "0" status.

(4)Read-out the interrupt factor flag (IK) only in the DI

status (interrupt flag = "0"). Read-out during EI status

will cause malfunction.

(5)Writing to the interrupt mask registers (EIK) can be done

only in the DI status (interrupt flag = "0"). Writing during

EI status will cause malfunction.

(6)When oscillation is stopped, the reset triggered by the

noise reject circuit which would normally take place

when the input ports are simultaneously switched to

HIGH cannot be received.

When BZ, BZ and FOUT are selected with the mask option,

a hazard may be observed in the output waveform when the

data of the output register changes.

(1)When the I/O port is being read out, the in-built pull-

down resistance of the I/O port goes ON. Consequently, if

data is read out while the CPU is running in the OSC3

oscillation circuit, data must be read out continuously for

about 500 µs.

Output port

I/O port

I-104 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 5: SUMMARY OF NOTES

(2)When the I/O port is set to the output mode and the data

impedance load is connected and read-out performed, the

value of the register and the read-out result may differ.

(1)When 40H–6FH is selected for the segment data memory,

the memory data and the display will not match until the

area is initialized (through, for instance, memory clear

processing by the CPU). Initialize the segment data mem-

ory by executing initial processing.

(2)When C0H–EFH is selected for the segment data memory,

that area becomes write-only. Consequently, data cannot

be rewritten by arithmetic operations (such as AND, OR,

ADD, SUB).

(1)When the clock timer has been reset, the interrupt factor

flag (TI) may sometimes be set to "1". Consequently,

perform flag read-out (reset the flag) as necessary at

reset.

(2)The input clock of the watchdog timer is the 2 Hz signal

of the clock timer, so that the watchdog timer may be

counted up at timer reset.

(3)Read-out the interrupt factor flag (TI) only during the DI

status (interrupt flag = "0"). Read-out during EI status

will cause malfunction.

(4)Writing to the interrupt mask registers (ETI) can be done

only in the DI status (interrupt flag = "0"). Writing during

EI status will cause malfunction.

(1)If counter data is read out in the RUN status, the counter

must be made into the STOP status, and after data is

read out the RUN status can be restored. If data is read

out when a carry occurs, the data cannot be read cor-

rectly.

Also, the processing above must be performed within the

STOP interval of 976 µs (256 Hz 1/4 cycle).

(2)Read-out of the interrupt factor flag (SWIT) must be done

only in the DI status (interrupt flag = "0"). Read-out

during EI status will cause malfunction.

LCD driver

Clock timer

Stopwatch counter

S1C62N33 TECHNICAL HARDWARE EPSON I-105

CHAPTER 5: SUMMARY OF NOTES

(3)Writing to the interrupt mask registers (EISWIT) can be

done only in the DI status (interrupt flag = "0"). Writing

during EI status will cause malfunction.

To prevent erroneous reading of the event counter data, read

out the counter data several times, compare it, and use the

matching data as the result.

(1)To reduce current consumption, set the analog compara-

tor to OFF when it is not necessary.

(2)After setting AMPON to "1", wait at least 3 ms for the

operation of the analog comparator to stabilize before

reading the output data of the analog cpmparator from

AMPDT.

(1)It takes 100 µs from the time the SVD circuit goes ON

until a stable result is obtained. For this reason, keep the

following software notes in mind:

➀When the CPU system clock is fosc1

1. When detection is done at HVLD

After writing "1" on HVLD, read the SVDDT after 1

instruction has passed.

2. When detection is done at SVDON

After writing "1" on SVDON, write "0" after at least

100 µs has lapsed (possible with the next instruc-

tion) and then read the SVDDT.

➁When the CPU system clock is fosc3 (in case of

S1C62A33 only)

1. When detection is done at HVLD

After writing "1" on HVLD, read the SVDDT after 0.6

sec has passed. (HVLD holds "1" for at least 0.6 sec)

2. When detection is done at SVDON

Before writing "1" on SVDON, write "1" on HVLD

first; after at least 100 µs has lapsed after writing

"1" on SVDON, write "0" on SVDON and then read

the SVDDT.

Event counter

Analog comparator

Supply voltage detection

(SVD) circuit and heavy

load protection function

I-106 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 5: SUMMARY OF NOTES

(2)SVDON resides in the same bit at the same address as

SVDDT, and one or the other is selected by write or read

operation. This means that arithmetic operations (AND,

OR, ADD, SUB and so forth) cannot be used for SVDON

control.

(3)Select one of the following software processing to return

to the normal mode after a heavy load has been driven in

the heavy load protection mode.

➀ After heavy load drive is completed, return to the

normal mode after at least one second has elapsed.

➁After heavy load drive is completed, switch SVD ON

and OFF (at least 100 µs is necessary for the ON

status) and then return to the normal mode.

(4)When the SVD is to be turned on during operation in the

heavy load protection mode, limit the ON time to 10 ms

per second of operation time.

(1)If the bit data of SE2 changes while SCLK is in the mas-

ter mode, a hazard will be output to the SCLK pin. If this

poses a problem for the system, be sure to set the SCLK

to the external clock if the bit data of SE2 is to be

changed.

(2)Be sure that read-out of the interrupt factor flag (ISIO) is

done only when the serial port is in the STOP status

(SIOF = "0") and the DI status (interrupt flag = "0"). If

read-out is performed while the serial data is in the RUN

status (during input or output), the data input or output

will be suspended and the initial status resumed. Read-

out during the EI status (interrupt flag = "1") causes

malfunctioning.

(3) When using the serial interface in the master mode, the

synchronous clock uses the CPU system clock. Accord-

ingly, do not change the system clock (fosc1 ↔ fosc3)

while the serial interface is operating.

(4) Perform data writing/reading to data registers SD0–SD7

only while the serial interface is halted (i.e., the synchro-

nous clock is neither being input or output).

Serial interface

S1C62N33 TECHNICAL HARDWARE EPSON I-107

CHAPTER 5: SUMMARY OF NOTES

(5) As a trigger condition, it is required that data writing or

reading on data registers SD0–SD7 be performed prior to

writing "1" to SCTRG. (The internal circuit of the serial

interface is initiated through data writing/reading on

data registers SD0–SD7.) Supply trigger only once every

time the serial interface is placed in the RUN state. More-

over, when the synchronous clock SCLK is external clock,

start to input the external clock after the trigger.

(6) Writing to the interrupt mask registers can be done only

in the DI status (interrupt flag = "0").

Writing during EI status will cause malfunction.

(7) SCTRG resides in the same bit at the same address as

SIOF, and one or the other is selected by write or read

operation. When writing a "1" to SCTRG use the OR

command, and when writing a "0" use the AND com-

mand. No other commands should be used for this pur-

pose.

(1)When the interrupt mask register (EIK) is set to "0", the

interrupt factor flag (IK) of the input port cannot be set

even though the pin status of the input port has changed.

(2)The interrupt factor flags of the clock timer and stop-

watch counter (TI, SWIT) are set when the timing condi-

tion is established, even if the interrupt mask registers

(ETI, EISWIT) are set to "0".

(3)Read-out the interrupt factor flags only in the DI status

(interrupt flag = "0"). If read-out is performed in the EI

status a malfunction will result.

(4)Writing to the interrupt mask registers can be done only

in the DI status (interrupt flag = "0").

Writing during EI status will cause malfunction.

Interrupt and HALT

I-108 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS

DIAGRAM OF BASIC EXTERNAL

CONNECTIONS

CHAPTER 6

S1C62N33 and S1C62L33

X'tal Crystal oscillator 32,768 Hz, CI (MAX) = 35 kΩ

CGX Trimmer capacitor 5–25pF

C1 0.1 µF

C2 0.1 µF

C3 0.1 µF

C4 0.1 µF

C5 0.1 µF

C6 0.1 µF

CP 3.3 µF

Note The above table is simply an example, and is not guaranteed to work.

• CC

• CB

• CA

• V

• OSC1

• OSC2

• V

• OSC3

• OSC4

• RESET

• TEST

• V

• R10(BZ)

• R13(BZ)

• R11

• R12(FOUT)

S1C

62N33/62L33

• SEG0

↓

• SEG39

• COM0

↓

• COM3

LCD

panel

LAMP

Piezo

N.C

X'tal

1.5V

(S1C62L33)

3.0V

(S1C62N33)

N.C

• K00

↓

• K03

• K10

• P00

↓

• P03

• P10

↓

• P13

• SOUT

• SCLK

• SIN

• SIOF

• R00

↓

• R03

I/O

O I I/O O

• AMPP

• AMPM

S1C62N33 TECHNICAL HARDWARE EPSON I-109

CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS

S1C62A33

Note

X'tal Crystal oscillator 32,768 Hz, CI (MAX)=35 kΩ

CGX Trimmer capacitor 5–25 pF

CR Ceramic oscillator 500 kHz

CGC Gate capacitance 100 pF

CDC Drain capacitance 100 pF

RCR Resistance for CR oscillation 82 kΩ

C1 0.1 µF

C2 0.1 µF

C3 0.1 µF

C4 0.1 µF

C5 0.1 µF

C6 0.1 µF

CP 3.3 µF

The above table is simply an example, and is not guaranteed to work.

•

K00

↓

•

K03

•

K10

•

P00

↓

•

P03

•

P10

↓

•

P13

•

AMPP

•

AMPM

•

R00

↓

•

R03

•

OSC1

•

OSC2

•

OSC4

•

RESET

•

TEST

•

R10(BZ)

•

R13(BZ)

•

R11

•

R12(FOUT)

S1C62A33

•

SEG0

↓

•

SEG39

•

COM0

↓

•

COM3

LCD

panel

I/O

LAMP

Piezo

X'tal

3.0V

CR *1 *2

*1 Ceramic oscillation

*2 CR oscillation

•

OSC3

GC CR

•

SOUT

•

SCLK

•

SIN

•

SIOF

O I I/O O

I-110 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS

RA1 Protection resistance 100 Ω

RA2 Protection resistance 100 Ω

When the piezoelectric buzzer is driven directly

Piezo

RA1 RA2

S1C62N33 Series

R10

(BZ) R13

(BZ)

S1C62N33 TECHNICAL HARDWARE EPSON I-111

CHAPTER 7: ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Rating

S1C62N33 and S1C62A33

(VDD = 0 V)

Item Code Rated Value Unit

Supply voltage VSS -5.0 to 0.5 V

Input voltage (1) VIVSS-0.3 to 0.5 V

Input voltage (2) VIOSC VS1-0.3 to 0.5 V

Permissible total output current ΣIVSS 10 mA

Operating temperature Topr -20 to 70 °C

Storage temperature Tstg -65 to 150 °C

Soldered temperature, time Tsol 260°C, 10 sec (lead section) –

Permitted loss PD250 mW

S1C62L33

(VDD = 0 V)

Item Code Rated Value Unit

Supply voltage VSS -2.0 to 0.5 V

Input voltage (1) VIVSS-0.3 to 0.5 V

Input voltage (2) VIOSC VS1-0.3 to 0.5 V

Permissible total output current ΣIVSS 10 mA

Operating temperature Topr -20 to 70 °C

Storage temperature Tstg -65 to 150 °C

Soldered temperature, time Tsol 260°C, 10 sec (lead section) –

Permitted loss PD250 mW

*1 For 100-pin plastic package

*2 The permissible total output current is the sum total of the current (average

current) that simultaneously flows from the output pins (or is drawn in).

CHAPTER 7

I-112 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 7: ELECTRICAL CHARACTERISTICS

S1C62N33

(Ta = -20–70°C)

Item Code Condition Min. Typ. Max. Unit

Supply voltage VSS VDD = 0V -3.5 -3.0 -1.8 V

Oscillation frequency fosc1 – 32,768 – Hz

S1C62L33

(Ta = -20–70°C)

Item Code Condition Min. Typ. Max. Unit

Supply voltage VSS VDD = 0V -1.7 -1.5 -1.1 V

-1.7 -1.5 -0.9 V

-1.7 -1.5 -1.2 V

Oscillation frequency fosc1 – 32,768 – Hz

S1C62A33

(Ta = -20–70°C)

Item Code Condition Min. Typ. Max. Unit

Supply voltage VSS VDD = 0V -3.5 -3.0 -2.2 V

Oscillation frequency (1) fosc1 – 32,768 – Hz

Oscillation frequency (2) fosc3 duty 50±5% 50 500 600 kHz

*1 When switching to heavy load protection mode. (See Section 4.12 for details.)

Note, however, that the ON time for SVD in the heavy load protection must be limited

to 10 ms per second of operation time.

*2 The possibility of LCD panel display differs depending on the characteristics of the

LCD panel.

7.2 Recommended Operating Conditions

VDD = 0V

software

controllable

VDD = 0V When

use the analog

comparator

*1*2

S1C62N33 TECHNICAL HARDWARE EPSON I-113

CHAPTER 7: ELECTRICAL CHARACTERISTICS

7.3 DC Characteristics

S1C62N33 and S1C62A33

(VDD=0V, VSS=-3V, fosc1=32,768Hz, Ta=25°C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1µF)

Item Code Condition Min. Typ. Max. Unit

High-level VIH1 0.2· 0 V

input voltage (1) VSS

High-level VIH2 0.1· 0 V

input voltage (2) RESET, TEST VSS

Low-level VIL1 K00–03·10 VSS 0.8· V

input voltage (1) P00–03·10–13 VSS

Low-level VIL2 VSS 0.9· V

input voltage (2) RESET, TEST VSS

High-level IIH1 VIH = 0V K00–03·10 0 0.5 µA

input current (1) SIN, SCLK

P00–03·10–13

AMPP, AMPM

High-level IIH2 VIH = 0V K00–03·10 4 16 µA

input current (2)

High-level IIH3 VIH = 0V P00–03·10–13 25 100 µA

input current (3) RESET, TEST

Low-level IIL VIL = VSS K00–03·10, SIN -0.5 0 µA

input current P00–03·10–13, SCLK

AMPP, AMPM

RESET, TEST

High-level IOH1 VOH1 = 0.1·VSS R10 -1.8 mA

output current (1) R11

R13

High-level IOH2 VOH2 = 0.1·VSS -0.9 mA

output current (2)

Low-level IOL1 VOL1 = 0.9·VSS R10 6.0 mA

output current (1) R11

R13

Low-level IOL2 VOL2 = 0.9·VSS 3.0 mA

output current (2)

Common IOH3 VOH3 = -0.05V COM0–3 -3 µA

output current IOL3 VOL3 = VL3+0.05V 3µA

Segment output current IOH4 VOH4 = -0.05V SEG0–39 -3 µA

(at LCD output) IOL4 VOL4 = VL3+0.05V 3µA

Segment output current IOH5 VOH5 = 0.1·VSS SEG0–39 -200 µA

(at DC output) IOL5 VOL5 = 0.9·VSS 200 µA

K00–03·10

SIN, SCLK

P00–03·10–13

R00–03·12

SOUT, SIOF

P00–03·10–13, SCLK

R00–03·12

SOUT, SIOF

P00–03·10–13, SCLK

Has pull-down

resistance

Has pull-down

resistance

No pull-down

resistance

I-114 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 7: ELECTRICAL CHARACTERISTICS

Item Code Condition Min. Typ. Max. Unit

High-level VIH1 0.2· 0 V

input voltage (1) VSS

High-level VIH2 0.1· 0 V

input voltage (2) RESET, TEST VSS

Low-level VIL1 K00–03·10 VSS 0.8· V

input voltage (1) P00–03·10–13 VSS

Low-level VIL2 VSS 0.9· V

input voltage (2) RESET, TEST VSS

High-level IIH1 VIH = 0V K00–03·10 0 0.5 µA

input current (1) SIN, SCLK

P00–03·10–13

AMPP, AMPM

High-level IIH2 VIH = 0V K00–03·10 2 10 µA

input current (2)

High-level IIH3 VIH = 0V P00–03·10–13 12 60 µA

input current (3) RESET, TEST

Low-level IIL VIL = VSS K00–03·10, SIN -0.5 0 µA

input current P00–03·10–13, SCLK

AMPP, AMPM

RESET, TEST

High-level IOH1 VOH1 = 0.1·VSS R10 -300 µA

output current (1) R11

R13

High-level IOH2 VOH2 = 0.1·VSS -150 µA

output current (2)

Low-level IOL1 VOL1 = 0.9·VSS R10 1,400 µA

output current (1) R11

R13

Low-level IOL2 VOL2 = 0.9·VSS 700 µA

output current (2)

Common IOH3 VOH3 = -0.05V COM0–3 -3 µA

output current IOL3 VOL3 = VL3+0.05V 3µA

Segment output current IOH4 VOH4 = -0.05V SEG0–39 -3 µA

(at LCD output) IOL4 VOL4 = VL3+0.05V 3µA

Segment output current IOH5 VOH5 = 0.1·VSS SEG0–39 -100 µA

(at DC output) IOL5 VOL5 = 0.9·VSS 100 µA

S1C62L33

=0V, V

=-1.5V, fosc1=32,768Hz, Ta=25°C, V

, V

are internal voltage, C1=C2=C3=C4=C5=C6=0.1µF)

R00–03·12

SOUT, SIOF

P00–03·10–13, SCLK

R00–03·12

SOUT, SIOF

P00–03·10–13, SCLK

K00–03·10

SIN, SCLK

P00–03·10–13

No pull-down

resistance

Has pull-down

resistance

Has pull-down

resistance

S1C62N33 TECHNICAL HARDWARE EPSON I-115

CHAPTER 7: ELECTRICAL CHARACTERISTICS

7.4 Analog Circuit Characteristics and Consumed Current

S1C62N33 (Always in operating mode)

(VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal

voltage, C1=C2=C3=C4=C5=C6=0.1µF)

Item Code Condition Min. Typ. Max. Unit

Internal voltage VL1 Connects a 1MΩ load resistance -1.15 -1.05 -0.95 V

between VDD and VL1

(No panel load)

VL2 Connects a 1MΩ load resistance 2·VL1 2·VL1 V

between VDD and VL2

(No panel load)

-0.1 × 0.9

VL3 Connects a 1MΩ load resistance 3·VL1 3·VL1 V

between VDD and VL3

(No panel load)

-0.1 × 0.9

SVD voltage VSVD -2.55 -2.40 -2.25 V

SVD circuit response time TSVD 100 µs

Analog comparator VIP Noninverted input (AMPP) VSS+0.3 VDD-0.9 V

input voltage VIM Inverted input (AMPM)

Analog comparator VOF 10 mV

offset voltage

Analog comparator TAMP VIP = -1.5V 3ms

response time VIM = VIP±15mV

Consumed current IOP During HALT No panel load 1.5 4.0 µA

During operation 6.0 10.0 µA

*1 The SVD circuit and analog comparator are in the OFF status.

I-116 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 7: ELECTRICAL CHARACTERISTICS

S1C62N33 (Heavy load protection mode)

(VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal

voltage, C1=C2=C3=C4=C5=C6=0.1µF)

Item Code Condition Min. Typ. Max. Unit

Internal voltage VL1 Connects a 1MΩ load resistance -1.15 -1.05 -0.95 V

between VDD and VL1

(No panel load)

VL2 Connects a 1MΩ load resistance 2·VL1 2·VL1 V

between VDD and VL2

(No panel load)

-0.1 × 0.9

VL3 Connects a 1MΩ load resistance 3·VL1 3·VL1 V

between VDD and VL3

(No panel load)

-0.1 × 0.9

SVD voltage VSVD -2.55 -2.40 -2.25 V

SVD circuit response time TSVD 100 µs

Analog comparator VIP Noninverted input (AMPP) VSS+0.3 VDD-0.9 V

input voltage VIM Inverted input (AMPM)

Analog comparator VOF 10 mV

offset voltage

Analog comparator TAMP VIP = -1.5V 3ms

response time VIM = VIP±15mV

Consumed current IOP During HALT No panel load 11.2 34.0 µA

During operation 14.5 40.0 µA

*1 The SVD circuit is on status (HVLD = "1", SVDON = "0"). The analog comparator

is in the OFF status.

S1C62N33 TECHNICAL HARDWARE EPSON I-117

CHAPTER 7: ELECTRICAL CHARACTERISTICS

S1C62L33 (Always in operating mode)

(VDD=0V, VSS=-1.5V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal

voltage, C1=C2=C3=C4=C5=C6=0.1µF)

Item Code Condition Min. Typ. Max. Unit

Internal voltage VL1 Connects a 1MΩ load resistance -1.15 -1.05 -0.95 V

between VDD and VL1

(No panel load)

VL2 Connects a 1MΩ load resistance 2·VL1 2·VL1 V

between VDD and VL2

(No panel load)

-0.1 × 0.9

VL3 Connects a 1MΩ load resistance 3·VL1 3·VL1 V

between VDD and VL3

(No panel load)

-0.1 × 0.9

SVD voltage VSVD -1.30 -1.20 -1.10 V

SVD circuit response time TSVD 100 µs

Analog comparator VIP Noninverted input (AMPP) VSS+0.3 VDD-0.9 V

input voltage VIM Inverted input (AMPM)

Analog comparator VOF 20 mV

offset voltage

Analog comparator TAMP VIP = -1.1V 3ms

response time VIM = VIP±30mV

Consumed current IOP During HALT No panel load 1.0 3.0 µA

During operation 3.0 8.0 µA

*1 The SVD circuit and analog comparator are in the OFF status.

I-118 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 7: ELECTRICAL CHARACTERISTICS

Item Code Condition Min. Typ. Max. Unit

Internal voltage VL1 Connects a 1MΩ load resistance -1.15 -1.05 -0.95 V

between VDD and VL1

(No panel load)

VL2 Connects a 1MΩ load resistance 2·VL1 2·VL1 V

between VDD and VL2

(No panel load)

-0.1 × 0.85

VL3 Connects a 1MΩ load resistance 3·VL1 3·VL1 V

between VDD and VL3

(No panel load)

-0.1 × 0.85

SVD voltage VSVD -1.30 -1.20 -1.10 V

SVD circuit response time TSVD 100 µs

Analog comparator VIP Noninverted input (AMPP) VSS+0.3 VDD-0.9 V

input voltage VIM Inverted input (AMPM)

Analog comparator VOF 20 mV

offset voltage

Analog comparator TAMP VIP = -1.1V 3ms

response time VIM = VIP±30mV

Consumed current IOP During HALT No panel load 2.0 7.0 µA

During operation 8.0 18.0 µA

S1C62L33 (Heavy load protection mode)

(VDD=0V, VSS=-1.5V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal

voltage, C1=C2=C3=C4=C5=C6=0.1µF)

*1 The SVD circuit is on status (HVLD = "1", SVDON = "0"). The analog comparator

is in the OFF status.

S1C62N33 TECHNICAL HARDWARE EPSON I-119

CHAPTER 7: ELECTRICAL CHARACTERISTICS

S1C62A33 (Always in operating mode)

(VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal

voltage, C1=C2=C3=C4=C5=C6=0.1µF)

Item Code Condition Min. Typ. Max. Unit

Internal voltage VL1 Connects a 1MΩ load resistance -1.15 -1.05 -0.95 V

between VDD and VL1

(No panel load)

VL2 Connects a 1MΩ load resistance 2·VL1 2·VL1 V

between VDD and VL2

(No panel load)

-0.1 × 0.9

VL3 Connects a 1MΩ load resistance 3·VL1 3·VL1 V

between VDD and VL3

(No panel load)

-0.1 × 0.9

SVD voltage VSVD -2.55 -2.40 -2.25 V

SVD circuit response time TSVD 100 µs

Analog comparator VIP Noninverted input (AMPP) VSS+0.3 VDD-0.9 V

input voltage VIM Inverted input (AMPM)

Analog comparator VOF 10 mV

offset voltage

Analog comparator TAMP VIP = -1.5V 3ms

response time VIM = VIP±15mV

Consumed current IOP During HALT No panel load 2.0 5.0 µA

During operation OSCC = "0" 8.0 15.0 µA

During operation No panel load 135 300 µA

at 500 kHz

*1 The SVD circuit and analog comparator are in the OFF status.

I-120 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 7: ELECTRICAL CHARACTERISTICS

S1C62A33 (Heavy load protection mode)

(VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal

voltage, C1=C2=C3=C4=C5=C6=0.1µF)

Item Code Condition Min. Typ. Max. Unit

Internal voltage VL1 Connects a 1MΩ load resistance -1.15 -1.05 -0.95 V

between VDD and VL1

(No panel load)

VL2 Connects a 1MΩ load resistance 2·VL1 2·VL1 V

between VDD and VL2

(No panel load)

-0.1 × 0.9

VL3 Connects a 1MΩ load resistance 3·VL1 3·VL1 V

between VDD and VL3

(No panel load)

-0.1 × 0.9

SVD voltage VSVD -2.55 -2.40 -2.25 V

SVD circuit response time TSVD 100 µs

Analog comparator VIP Noninverted input (AMPP) VSS+0.3 VDD-0.9 V

input voltage VIM Inverted input (AMPM)

Analog comparator VOF 10 mV

offset voltage

Analog comparator TAMP VIP = -1.5V 3ms

response time VIM = VIP±15mV

Consumed current IOP During HALT No panel load 11.5 35.0 µA

During operation OSCC = "0" 16.0 45.0 µA

During operation No panel load 130 330 µA

at 500 kHz

*1 The SVD circuit is on status (HVLD = "1", SVDON = "0"). The analog comparator

is in the OFF status.

S1C62N33 TECHNICAL HARDWARE EPSON I-121

CHAPTER 7: ELECTRICAL CHARACTERISTICS

7.5 Oscillation Characteristics

The oscillation characteristics change depending on the conditions (components

used, board pattern, etc.). Use the following characteristics as reference values.

S1C62N33

If no special requirement

VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CG=25pF, CD=built-in,

Ta=25°C

Item Code Condition Min. Typ. Max. Unit

Oscillation start Vsta Tsta 5sec -1.8 V

voltage (VSS)

Oscillation stop Vstp Tstp 10sec -1.8 V

voltage (VSS)

Built-in capacitance CDIncluding incidental 18 pF

(drain) capacitance inside IC

Frequency/voltage f/V VSS = -1.8 to -3.5V 5 ppm

deviation

Frequency/IC f/IC-10 10 ppm

deviation

Frequency adjustment f/CGCG = 5 to 25pF 35 45 ppm

range

Harmonic oscillation Vhho -3.5 V

start voltage (VSS)

Permitted leak Rleak Between OSC1 200 MΩ

resistance and VDD, VSS

I-122 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 7: ELECTRICAL CHARACTERISTICS

Item Code Condition Min. Typ. Max. Unit

Oscillation start Vsta Tsta 5sec -1.1 V

voltage (VSS)

Oscillation stop Vstp Tstp 10sec -1.1 V

voltage (VSS) (-0.9)*1

Built-in capacitance CDIncluding incidental 18 pF

(drain) capacitance inside IC

Frequency/voltage f/V VSS = -1.1 to -1.7V 5 ppm

deviation (-0.9)*1

Frequency/IC f/IC-10 10 ppm

deviation

Frequency adjustment f/CGCG = 5 to 25pF 35 45 ppm

range

Harmonic oscillation Vhho -1.7 V

start voltage (VSS)

Permitted leak Rleak Between OSC1 200 MΩ

resistance and VDD, VSS

S1C62L33

If no special requirement

VDD=0V, VSS=-1.5V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25°C

*1 Parentheses indicate value for operation in heavy load protection mode.

Note, however, that the ON time for SVD must be limited to 10 ms per second

of operation time.

S1C62N33 TECHNICAL HARDWARE EPSON I-123

CHAPTER 7: ELECTRICAL CHARACTERISTICS

S1C62A33

OSC1, 2

If no special requirement

VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CG=25pF, CD=built-in,

Ta=25°C

Item Code Condition Min. Typ. Max. Unit

Oscillation start Vsta Tsta 5sec -2.2 V

voltage (VSS)

Oscillation stop Vstp Tstp 10sec -2.2 V

voltage (VSS)

Built-in capacitance CDIncluding incidental 18 pF

(drain) capacitance inside IC

Frequency/voltage f/V VSS = -2.2 to -3.5V 5 ppm

deviation

Frequency/IC f/IC-10 10 ppm

deviation

Frequency adjustment f/CGCG = 5 to 25pF 35 45 ppm

range

Harmonic oscillation Vhho -3.5 V

start voltage (VSS)

Permitted leak Rleak Between OSC1 200 MΩ

resistance and VDD, VSS

I-124 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 7: ELECTRICAL CHARACTERISTICS

Item Code Condition Min. Typ. Max. Unit

Oscillation frequency fosc3 -30 430 kHz 30 %

Oscillation start voltage Vsta -2.2 V

Oscillation start time Tsta VSS = -2.2 to -3.5V 3 ms

Oscillation stop voltage Vstp -2.2 V

OSC3, OSC4 (for CR oscillation circuit)

If no special requirement

VDD=0V, VSS=-3.0V, RCR=82kΩ, Ta=25°C

OSC3, OSC4 (for ceramic oscillation circuit)

If no special requirement

VDD=0V, VSS=-3.0V, ceramic oscillation: 500kHz

CGC=CDC=100pF, Ta=25°C

Item Code Condition Min. Typ. Max. Unit

Oscillation start voltage Vsta -2.2 V

Oscillation start time Tsta VSS = -2.2 to -3.5V 5 ms

Oscillation stop voltage Vstp -2.2 V

S1C62N33 TECHNICAL HARDWARE EPSON I-125

CHAPTER 8: PACKAGE

CHAPTER 8 PACKAGE

Plastic Package

QFP5-100pin (Unit: mm)

8.1

5180

301

100

14.0

± 0.1

19.6

± 0.4

20.0

± 0.1

25.6

± 0.4

0.65

± 0.1

0.30

± 0.1

0.15

± 0.05

2.7

± 0.1

2.8

1.5

± 0.3

0~12°

Index

I-126 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 8: PACKAGE

8.2 Ceramic Package for Test Samples

(Unit: mm)

Note The ceramic package is fixed in this form regardless selecting of the

plastic package form.

5180

301

100

14.0

20.9

20.0

26.8

0.65 0.30

0.4

0.8

0.76

0.95

Grass

S1C62N33 TECHNICAL HARDWARE EPSON I-127

CHAPTER 9: PAD LAYOUT

9.1

PAD LAYOUT

Diagram of Pad Layout

CHAPTER 9

Chip thickness: 400µm

Pad opening: 95µm

(0, 0)

12345678910111314151617181920 12

44 45 46 47 48 49 50 51 52 55 56 57 58 59 60 61 62 6353 54 64

4.31 mm

4.77 mm

DIE No.

I-128 EPSON S1C62N33 TECHNICAL HARDWARE

CHAPTER 9: PAD LAYOUT

9.2 Pad Coordinates

(Unit : µm)

Pad No.

Pad Name

AMPP

AMPM

K10

K03

K02

K01

K00

P03

P02

P01

P00

P13

P12

P11

P10

R03

R02

R01

R00

R12

R11

R10

R13

RESET

OSC4

OSC3

OSC2

OSC1

Pad Name

COM3

COM2

COM1

COM0

SIOF

SCLK

SOUT

SIN

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

1,990

1,765

1,560

1,400

1,240

1,080

920

630

470

310

150

-50

-210

-370

-530

-738

-898

-1,058

-1,218

-1,426

-1,990

-1,589

-1,428

-1,202

-1,042

-882

-722

-562

-402

-242

-82

238

398

558

718

878

1,038

2,220

1,780

1,620

1,460

1,291

1,036

876

716

556

396

236

-84

-244

-404

-564

-724

-884

-1,070

-1,230

-1,390

-1,590

-1,750

-2,010

-2,220

Pad No.

Pad Name

SEG15

SEG16

SEG17

TEST

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

1,198

1,358

1,518

1,990

-2,220

-2,005

-1,559

-1,399

-1,239

-1,079

-919

-759

-599

-439

-279

-119

201

361

521

681

841

1,001

1,161

1,377

1,537

1,697

1,857

Chip size X : 4.31 (mm)

Y : 4.77 (mm)

Software

S1C62N33

II.

Technical Software

Software

S1C62N33 TECHNICAL SOFTWARE EPSON II-i

CONTENTS

CHAPTER 1 BLOCK DIAGRAM .......................................................... II-1

CHAPTER 2 PROGRAM MEMORY ..................................................... II-2

2.1 Program Memory Map.................................................... II-2

2.2 Programming Notes ....................................................... II-3

CHAPTER 3 DATA MEMORY.............................................................. II-4

3.1 Data Memory Map.......................................................... II-4

3.2 RAM Map ....................................................................... II-6

3.3 Programming Notes ....................................................... II-6

3.4 I/O Memory Map............................................................. II-7

CHAPTER 4 INTERRUPT AND HALT.................................................... II-10

4.1 Control of Interrupt and HALT ....................................... II-10

4.2 Generation of Interrupt .................................................. II-13

4.3 Example of Main Routine: Entering HALT

and waiting for reactivation by interrupt......................... II-14

4.4 Interrupt Vector Map...................................................... II-15

4.5 Example of Interrupt Vector Processing........................ II-16

4.6 Programming Notes ...................................................... II-19

CHAPTER 5 PERIPHERAL CIRCUITS................................................... II-20

5.1 Watchdog Timer ............................................................ II-20

Watchdog timer memory map................................. II-20

Example of reset processing for watchdog timer ..... II-21

Programming note.................................................. II-22

II-ii EPSON S1C62N33 TECHNICAL SOFTWARE

CONTENTS

5.2 OSC3............................................................................. II-23

OSC3 memory map ................................................ II-23

Example of using OSC3.......................................... II-24

Programming notes ................................................ II-25

5.3 Supply Voltage Detection (SVD) Circuit

and Heavy Load Protection Function ............................ II-26

SVD circuit memory map ....................................... II-26

Example of finding supply voltage using SVD circuit II-26

Example of using heavy load protection function .... II-31

Programming notes ................................................ II-36

5.4 Output Ports (R00–R03, R10–R13) .............................. II-38

Output port memory map....................................... II-38

Example of using output ports ............................... II-40

Programming note.................................................. II-46

5.5 LCD Driver..................................................................... II-47

Segment data memory map .................................... II-47

Example of control program

for LCD segment output ......................................... II-48

LCD driver memory map ........................................ II-55

Example of switching LCD drive ............................. II-55

Programming notes ................................................ II-57

5.6 Clock Timer ................................................................... II-58

Clock timer memory map ....................................... II-58

Example of using clock timer ................................. II-59

Timer interrupt memory map ................................. II-62

Clock timer timing chart ........................................ II-63

Example of using timer interrupt............................ II-63

Programming notes ................................................ II-68

5.7 Input Ports (K00–K03, K10) .......................................... II-69

Input port memory map ......................................... II-69

Example of using input ports ................................. II-71

Programming notes ................................................ II-80

5.8 I/O Ports ........................................................................ II-82

I/O port memory map ............................................ II-82

Example of program for I/O ports........................... II-83

Programming notes ................................................ II-86

Software

S1C62N33 TECHNICAL SOFTWARE EPSON II-iii

CONTENTS

5.9 Stopwatch Counter........................................................ II-87

Stopwatch counter memory map ............................ II-87

Example of program for stopwatch counter ............ II-88

Stopwatch interrupt memory map .......................... II-90

Stopwatch counter timing chart ............................. II-91

Example of program for stopwatch interrupt .......... II-92

Programming notes ................................................ II-96

5.10 Event Counter ............................................................... II-97

Event counter memory map ................................... II-97

Example of program for event counter .................... II-98

Programming note.................................................. II-99

5.11 Analog Comparator ...................................................... II-100

Analog comparator memory map ........................... II-100

Example of program for analog comparator ........... II-100

Programming notes ............................................... II-101

5.12 Serial Interface (SIN, SOUT, SCLK, SIOF) .................. II-102

Serial interface memory map................................. II-102

Example of program for serial interface ................. II-106

Programming notes ............................................... II-109

CHAPTER 6 INITIAL RESET ................................................................ II-110

6.1 Internal Status at Initial Reset ...................................... II-110

6.2 Example of Initialize Program....................................... II-111

CHAPTER 7 SUMMARY OF NOTES................................................... II-113

CHAPTER 8 CPU............................................................................... II-121

8.1 S1C62N33 Restrictions ................................................ II-121

8.2 Instruction Set .............................................................. II-121

APPENDIX • Table of cross assembler pseudo-instructions .................. II-127

• Table of ICE commands ................................................... II-128

S1C62N33 TECHNICAL SOFTWARE EPSON II-1

CHAPTER 1: BLOCK DIAGRAM

BLOCK DIAGRAMCHAPTER 1

COM0~3

K00~03, K10

P00~03, P10~13

R00~03, R10~13

AMPP

AMPM

OSC4

OSC3

OSC2

OSC1

RESET

SEG0~39 TEST

L1~3

CA~CC

Power

Controller

LCD Driver

RAM

256 words x 4 bits

ROM

3,072 words x 12 bits OSC System Reset

Control

Event

Counter

Interrupt

Generator

Input Port

I/O Port

Output Port

Comparator

Timer

Stop Watch

Core CPU S1C6200

SVD

Serial Interface SIN

SOUT

SCLK

SIOF

Fig. 1

Block diagram

II-2 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 2: PROGRAM MEMORY

PROGRAM MEMORY

The S1C62N33 Series has a mask ROM of 3,072 steps × 12

bits, for storing programs. Address space for program

memory is configured of one bank of 12 pages × 256 steps.

Program Memory Map

CHAPTER 2

2.1

After initial reset, the program start address is page 1, step

00H; interrupt vectors can be allocated to page 1, steps

01H–0FH.

Fig. 2.1

Program memory map

00H step

0FH step

10H step

FFH step

12 bits

Program start address

Interrupt vector area

0 page

1 page

01H step

2 page

3 page

4 page

5 page

6 page

7 page

8 page

9 page

10 page

11 page

S1C62N33 TECHNICAL SOFTWARE EPSON II-3

CHAPTER 2: PROGRAM MEMORY

Programming Notes

(1)To use a branch instruction such as "JP" to branch

outside the page of that instruction, the page to branch

to must first be set with the "PSET" instruction; then the

branch instruction can be executed. Be sure to execute

the branch instruction as the step immediately following

"PSET".

(2)Immediately after the "PSET" instruction mentioned in

above item (1), it will automatically be DI state until

execution of the branch instruction is completed.

(3)When moving from the last step of one page to the top

step of the next page, there is no need to execute branch

instructions such as "PSET" and "JP".

(4)With just the one instruction "CALZ", subroutines on

page 0 can be called from any page without using "PSET".

Programming can be done efficiently if universal subrou-

tines are located on page 0.

(5)If the "PSET" instruction is executed immediately before

"CALZ", "CALZ" will have priority and data set with

"PSET" will be ignored.

(6)The program memory can be used as a data table

through the table look-up instruction.

For details of the instructions, refer to "S1C6200/6200A

Core CPU Manual".

2.2

II-4 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 3: DATA MEMORY

DATA MEMORY

The S1C62N33 Series has a general-purpose RAM (256 words

× 4 bits ), I/O memory for controlling the internal peripheral

circuits (64 words × 4 bits), and the optionally selectable

segment memory (48 words × 4 bits). All these are allocated

to the data memory addresses on page 0 and page 1.

Data Memory Map

Data memory of the S1C62N33 Series has an address space

of 360 words, of which 48 words are allocated to display

memory and 64 words to I/O data memory.

Figure 3.1 present the overall memory maps of the

S1C62N33 Series, and Tables 3.4 (a)–(c) the peripheral

circuits' (I/O space) memory maps.

The I/O data memory in all units of the S1C62N33 Series is

configured in the same manner at 070H–07FH, 170H–17FH

and 0F0H–0FFH, 1F0H–1FFH. This makes it possible to

access I/O data memory without switching data memory

pages.

CHAPTER 3

3.1

S1C62N33 TECHNICAL SOFTWARE EPSON II-5

CHAPTER 3: DATA MEMORY

Address

Page High

Low 0123456789ABCDEF

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF0

RAM (112 words x 4 bits)

R/W

1I/O data memory Tables 3.4(a), (b)

RAM (32 words x 4 bits)

R/W

I/O data memory Tables 3.4(a), (b)

RAM (112 words x 4 bits)

R/W

Unused area

I/O data memory Table 3.4(c)

Unused area

I/O data memory Table 3.4(c)

Fig. 3.1

Data memory map

(1)The I/O data memory registers of 070H–07FH, 170H–17FH and

0F0H–0FFH, 1F0H–1FFH are each linked. For instance, by

switching the I/O data memory at 074H, data memory at 174H

can by switched simultaneously.

See Tables 3.4(a)–(c) for details of I/O data memory.

(2)The mask option can be used to select whether to assign the

overall area of segment data memory to 040H–06FH or 0C0H–

0EFH.

When 040H–06FH is selected, read/write is enabled.

When 0C0H–0EFH is selected, write only is enabled.

If 040H–06FH is assigned, RAM is used as the segment area

(48 words).

(3)Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this

reason, normal operation cannot be assured for programs that

have been prepared with access to these areas.

Note

II-6 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 3: DATA MEMORY

RAM Map3.2

Fig. 3.2

RAM map

Addresses 000H–00FH are the memory register area that

can be addressed with the register pointer (RP).

Addresses 040H–06FH can be allocated to segment memory by

option selection. With this selection, 48 words of RAM can be

used as segment area.

Programming Notes

(1)Part of the data memory is used as stack area for subrou-

tine calls and register storage, so be careful not to overlap

the data area and stack area.

(2)Subroutine calls and interrupts take up three words of

the stack area.

(3)When addresses 040H–06FH have been allocated as

segment memory by option selection, 48 words of RAM

can be used as segment area.

3.3

Note

Address

Page High

Low 0123456789ABCDEF

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF0

S1C62N33 TECHNICAL SOFTWARE EPSON II-7

CHAPTER 3: DATA MEMORY

Table 3.4(a) I/O data memory map (70H–77H)

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

3.4 I/O Memory Map

Address Comment

D3 D2 D1 D0 Name Init 1 0

70H

TM0

TM3

TM2

TM1

TM0

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

TM1TM2TM3

71H

SWL0

SWL3

SWL2

SWL1

SWL0

SWL1SWL2SWL3

72H

SWH0

SWH3

SWH2

SWH1

SWH0

SWH1SWH2SWH3 0

K00

K03

K02

K01

K00

High

Low

K01K02K03

73H

74H

DFK00

R/W

DFK03

DFK02

DFK01

DFK00

Falling

Rising

DFK01DFK02DFK03

75H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

EIK01EIK02EIK03

76H

HVLD

SVDDT

SVDON

EISWIT1

EISWIT0

Heavy load protection mode register

SVD evaluation data (at read-out)

SVD ON/OFF (at writing)

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

Enable

Normal

Off

Mask

SVDDT

SVDON

Stopwatch counter

1/100 sec (BCD)

MSB

LSB

Stopwatch counter

1/10 sec (BCD)

MSB

LSB

Input port

(K00–K03)

Differential register

(K00–K03)

Interrupt mask register

(K00–K03)

EISWIT0

EISWIT1HVLD

R/W R

WR/W

77H

SCTRG

SIOF

EIK10

DFK10

K10

–

Serial interface clock trigger

SIOF

Interrupt mask register (K10)

Differential register (K10)

Input port (K10)

Trigger

Run

Enable

Falling

High

–

Stop

Mask

Rising

Low

SCTRG

SIOF K10

DFK10

EIK10

R/W

Heavy load

Low voltage

II-8 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 3: DATA MEMORY

Table 3.4(b) I/O data memory map (78H–7FH)

Address Comment

D3 D2 D1 D0 Name Init 1 0

78H

ETI32

R/W

CSDC

ETI2

ETI8

ETI32

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

Static

Enable

Dynamic

Mask

ETI8ETI2CSDC

79H

TI32 –

TI2

TI8

TI32

Unused *5

Interrupt factor flag (clock timer 2 Hz) *4

Interrupt factor flag (clock timer 8 Hz) *4

Interrupt factor flag (clock timer 32 Hz) *4

Yes

TI8TI2–

7AH

SWIT0 IK1

IK0

SWIT1

SWIT0

Interrupt factor flag (K10) *4

Interrupt factor flag (K00–K03) *4

Interrupt factor flag (stopwatch 1 Hz) *4

Interrupt factor flag (stopwatch 10 Hz) *4

Yes

SWIT1IK0IK1

7BH

R00 R03

R02

R01

R00

High

Low

R01R02R03

R/W

7CH

R10

R/W

R13

R12

R11

R10

High

Low

R11R12R13

7DH

P00 P03

P02

P01

P00

High

Low

P01P02P03

7EH

IOC0

R/W

TMRST

SWRUN

SWRST

IOC0

Reset

Clock timer reset *5

Stopwatch counter RUN/STOP

Stopwatch counter reset *5

I/O control register 0 (P00–P03)

Reset

Run

Reset

Output

–

Stop

–

Input

SWRST

SWRUN

R/W

TMRST

7FH

WD0 WDRST

WD2

WD1

WD0

Reset

Watchdog timer reset *5

Timer data (watchdog timer 1/4 Hz)

Timer data (watchdog timer 1/2 Hz)

Timer data (watchdog timer 1 Hz)

Reset –

WD1

WD2WDRST

Output port

(R00–R03)

Output port (R13, BZ) *6

Output port (R12, FOUT) *6

Output port (R11)

Output port (R10, BZ) *6

R/W

I/O port (P00–P03)

Output latch reset at time of initial reset

S1C62N33 TECHNICAL SOFTWARE EPSON II-9

CHAPTER 3: DATA MEMORY

Table 3.4(c) I/O data memory map (F0H–F3H, F6H–F9H, FCH–FEH)

AMPON

R/W

Falling

Mask

Address Comment

D3 D2 D1 D0 Name Init 1 0

F0H

SD0

R/W

SD3

SD2

SD1

SD0

Serial interface data register

Low order (SD0–SD3)

SD1SD2SD3

F1H

SD4

R/W

SD7

SD6

SD5

SD4

SD5SD6SD7

F2H

EISIO

R/W

SCS1

SCS0

SE2

EISIO

Clock edge selection register

Interrupt mask register (serial interface)

SE2SCS0SCS1 1

ISIO

–

ISIO 0

Unused *5

Interrupt factor flag (serial interface) *4

Yes No

–––

F3H

F6H

–BZFQ

–

Buzzer frequency selection register

Unused *5

2 kHz 4 kHz

–

BZFQ

R/W

F7H

–

AMPDT

AMPON 1

Unused *5

Analog comparator data

Analog comparator ON/OFF

On Off

AMPDT–

–

F8H

EV00

EV03

EV02

EV01

EV00

EV01EV02EV03

F9H

EV04 EV07

EV06

EV05

EV04

EV05EV06EV07

FCH

EVRST

–

EVRUN

–

EVRST

Unused *5

Event counter RUN/STOP

Unused *5

Event counter reset *5

–

EVRUN

R/W

–

FEH

IOC1 –

CLKCHG

OSCC

IOC1

OSCC

R/W

CLKCHG–

FDH

P10 P13

P12

P11

P10

High

Low

P11P12P13

R/W

Rising

Enable

Serial interface data register

High order (SD4–SD7)

Clock edge selection register

(SCS0, SCS1)

Event counter

Low order (EV00–EV03)

Event counter

High order (EV04–EV07)

+ > - - > +

Run

Reset

Stop

–

OSC3

Output

OSC1

Off

Input

Reset

I/O port (P10–P13)

Output latch reset at time of initial reset

Unused *5

CPU clock switch

OSC3 oscillator ON/OFF

I/O control register 1 (P10–P13)

II-10 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 4: INTERRUPT AND HALT

INTERRUPT AND HALT

The S1C62N33 Series provides the following interrupt set-

tings, each of which is maskable.

External interrupts: Input interrupts (two)

Internal interrupts: Timer interrupt (three)

Stopwatch interrupt (two)

Serial interface interrupt (one)

When a HALT instruction is input the CPU operating clock

stops, and the CPU enters the HALT status.

The CPU is reactivated from the HALT status when an

interrupt request occurs.

CHAPTER 4

S1C62N33 TECHNICAL SOFTWARE EPSON II-11

CHAPTER 4: INTERRUPT AND HALT

Control of Interrupt and HALT

4.1

Table 4.1(a) I/O data memory map (interrupt 1)

Address Comment

D3 D2 D1 D0 Name SR

74H

DFK03 DFK02 DFK01 DFK00

R/W

DFK03

DFK02

DFK01

DFK00

Falling

Rising

Differential register

(K00–K03)

75H

76H

EIK03 EIK02 EIK01 EIK00

HVLD SVDDT

SVDON

EISWIT1 EISWIT0

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

HVLD

EISWIT1

EISWIT0

Enable

Mask

SVD evaluation data (at read-out)

SVD ON/OFF (at writing)

Interrupt mask register

(stopwatch 1 Hz)

Interrupt mask register

(stopwatch 10 Hz)

Interrupt mask register

(K00–K03)

R/W SVDDT

SVDON 0

Heavy

load Normal

Normal

OFF

Heavy load protection mode register

77H

DFK10 K10

EIK10

DFK10

K10

Enable

Falling

High

Mask

Rising

Low

Interrupt mask register (K10)

Differential register (K10)

Input port (K10)

R/W

EIK10

SCTRG

SIOF –

Serial interface clock trigger

SIOF

Trigger

Run

–

Stop

SCTRG

SIOF

Low voltage

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

II-12 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 4: INTERRUPT AND HALT

Table 4.1(b) I/O data memory map (interrupt 2)

Address Comment

D3 D2 D1 D0 Name SR *1 10

78H

79H

CSDC ETI2 ETI8 ETI32

TI2 TI8 TI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

–

TI2

TI8

TI32

Yes

Unused *5

Interrupt factor flag (clock timer 2 Hz) *4

Interrupt factor flag (clock timer 8 Hz) *4

Interrupt factor flag (clock timer 32 Hz) *4

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

7AH

IK1 IK0 SWIT1 SWIT0

IK1

IK0

SWIT1

SWIT0

Yes

–

F3H

–– –ISIO

–

ISIO 0 Yes No

F2H

SCS1 SCS0 SE2 EISIO

R/W

SCS1

SCS0

SE2

EISIO

Rising

Enable

Falling

Mask

Unused *5

Interrupt factor flag (serial interface) *4

Interrupt factor flag (K10) *4

Interrupt factor flag (K00–K03) *4

Interrupt factor flag (stopwatch 1 Hz) *4

Interrupt factor flag (stopwatch 10 Hz) *4

Clock edge selection register

(SCS0, SCS1)

Clock edge selection register

Interrupt mask register (serial interface)

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

S1C62N33 TECHNICAL SOFTWARE EPSON II-13

CHAPTER 4: INTERRUPT AND HALT

Generation of Interrupt4.2

Interrupt Factor

Clock timer 2 Hz falling edge

Clock timer 8 Hz falling edge

Clock timer 32 Hz falling edge

Stopwatch counter

1 Hz falling edge

Stopwatch counter

10 Hz falling edge

Serial interface

Data (8 bits) input/output has completed

Input data (K00–K03)

Change from match to mismatch

of differential register data

and port register data

Input data (K10)

Rising or falling edge

T2Hz

T8Hz

T32Hz

SWT1Hz

SWT10Hz

SIO

Interrupt

Factor Flag

Interrupt Mask

ETI2

ETI8

ETI32

EISWIT1

EISWIT0

EISIO

EIK03

EIK02

EIK01

EIK00

EIK10

(78H•D2)

(78H•D1)

(78H•D0)

(76H•D1)

(76H•D0)

(F2H•D0)

(75H•D3)

(75H•D2)

(75H•D1)

(75H•D0)

(77H•D2)

TI2

TI8

TI32

SWIT1

SWIT0

ISIO

IK0

IK1

(79H•D2)

(79H•D1)

(79H•D0)

(7AH•D1)

(7AH•D0)

(F3H•D0)

(7AH•D2)

(7AH•D3)

Table 4.2

Interrupt factors

The CPU operation is interrupted when any of the conditions

below sets an interrupt factor flag to "1".

• The corresponding interrupt mask register is "1" (enabled)

• The interrupt flag is "1" (EI)

The interrupt flag is set to "1" depending on the correspond-

ing interrupt factor.

The interrupt factor flag is a read-only register, and is reset

to "0" when the register data is read out.

Write to the interrupt mask registers only in the DI status (inter-

rupt flag = "0").

An error could result from writing during the EI status.

Even when the interrupt mask registers (ETI, EISWIT) are set to

"0", the interrupt factor flags (TI, SWIT) of the clock timer and

stopwatch counter can be set when the timing conditions are

established.

Read the interrupt factor flags only in the DI status (interrupt flag

= "0").

An error could result from reading out during the EI status.

Note

II-14 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 4: INTERRUPT AND HALT

Example of Main Routine: Entering HALT

and waiting for reactivation by interrupt

This main routine enables K00–K03 input interrupt and 2

Hz timer interrupt, after which it enters the HALT status to

wait for reactivation by interrupts.

At every loop, the EI instruction enables an interrupt after

execution of the display routine "DS" (of the watch or what-

ever the application happens to be).

LD X,75H ; Enable K00–K03 input interrupt

LD MX,1111B ;

LD X,78H ; Enable 2 Hz timer interrupt

LD MX,0100B ;

;

MAINLP: CALL DS ; Execute display processing "DS"

EI ; Enable interrupts

HALT ; Enter HALT

JP MAINLP ; Interrupts' return address: Back to "MAINLP"

This routine assumes that "DS" has been prepared sepa-

rately.

1. This program example is one to follow the initialize

program. Even without executing the DI instruction,

writing to interrupt mask registers is done in the DI

status.

2. When an interrupt is generated, the DI status (interrupt

flag = "0") comes into effect automatically, so the EI

instruction is necessary for each loop.

4.3

Specifications

Program

Notes

S1C62N33 TECHNICAL SOFTWARE EPSON II-15

CHAPTER 4: INTERRUPT AND HALT

Interrupt Vector Map4.4

Table 4.4

Interrupt vector map

Addresses (start addresses of interrupt processing routines)

to jump to are written into the addresses available for inter-

rupt vector allocation.

Step

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

Interrupt VectorPage

Initial reset

Generation of Serial interface interrupt (ISIO)

Generation of input port interrupt (INTK0 or INTK1)

Generation of ISIO and (INTK0 or INTK1)

Generation of timer interrupt (TINT)

Generation of ISIO and TINT

Generation of (INTK0 or INTK1) and TINT

Generation of ISIO, (INTK0 or INTK1) and TINT

Generation of stopwatch interrupt (SWINTT)

Generation of ISIO and SWINTT

Generation of (INTK0 or INTK1) and SWINTT

Generation of ISIO, (INTK0 or INTK1) and SWINTT

Generation of TINT and SWINTT

Generation of ISIO, TINT and SWINTT

Generation of (INTK0 or INTK1), TINT and SWINTT

Generation of all interrupts

II-16 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 4: INTERRUPT AND HALT

ORG 101H ; Vector leading address

;JP IN ; Generation of Serial interface interrupt (ISIO)

JP IN ; Generation of input port interrupt (INTK0 or INTK1)

JP IN ; Generation of ISIO and (INTK0 or INTK1)

JP IN ; Generation of timer interrupt (TINT)

JP IN ; Generation of ISIO and TINT

JP IN ; Generation of (INTK0 or INTK1) and TINT

JP IN ; Generation of ISIO, (INTK0 or INTK1) and TINT

JP IN ; Generation of stopwatch interrupt (SWINTT)

JP IN ; Generation of ISIO and SWINTT

JP IN ; Generation of (INTK0 or INTK1) and SWINTT

JP IN ; Generation of ISIO, (INTK0 or INTK1) and SWINTT

JP IN ; Generation of TINT and SWINTT

JP IN ; Generation of ISIO, TINT and SWINTT

JP IN ; Generation of (INTK0 or INTK1), TINT and SWINTT

JP IN ; Generation of all interrupts

Example of Interrupt Vector Processing

When interrupts having different vectors occur simultane-

ously, they are processed in the specified order of priority.

Because of this, it is convenient to process all interrupts

with the one interrupt routine "IN".

4.5

Interrupt vectors

Specifications

Interrupt routine Table 4.5 lists the order of priority for processing interrupts.

Values of registers X, Y, A, B and F are retained in stack.

Priority Interrupt Factor

1 Stopwatch 10 Hz

2 Stopwatch 1 Hz

3 Serial interface

4K00–K03 input ports

5 K10 input port

6 Clock timer 32 Hz

7 Clock timer 8 Hz

8 Clock timer 2 Hz

Table 4.5

Order of interrupt priority in

program example

S1C62N33 TECHNICAL SOFTWARE EPSON II-17

CHAPTER 4: INTERRUPT AND HALT

YIKSTB EQU ●▲●▲H;

;

YTIB EQU ●■●■H;

;

IN: PUSH XH ;

PUSH XL ;

PUSH XP ;

PUSH YH ;

PUSH YL ;

PUSH YP ;

PUSH A ;

PUSH B ;

PUSH F ;

;LD X,7AH ;

LD Y,YIKSTB ;

LD MY,MX ;

LD X,76H ;

LD A,MX ;

OR A,1100B ;

AND MY,A ;

;FAN MY,0001B ;

JP Z,INSIT1 ;

CALL STI0 ;

;

INSIT1: LD Y,YIKSTB ;

FAN MY,0010B ;

JP Z,INSIO ;

CALL SIT1 ;

;

INSIO: LD Y,0F3H ;

LD A,MX ;

FAN A,0001B ;

JP Z,INK0 ;

CALL ISIO ;

;

INK0: LD Y,YIKSTB ;

FAN MY,0100B ;

JP Z,INK1 ;

CALL IK0 ;

Buffer address for factor flags of input interrupts

and stopwatch interrupts

Buffer address for timer interrupt factor flags

Store the value of X register to stack

Store the value of Y register to stack

Store the value of A register to stack

Store the value of B register to stack

Store the value of F register to stack

Reset and store

input interrupt and stopwatch interrupt factor flags

in the buffer

Mask the stopwatch interrupt factor flags

by the value of the stopwatch interrupt mask register

If the ST10Hz interrupt factor flag is set

and enabled

then execute ST10Hz interrupt processing "SIT0"

If the ST1Hz interrupt factor flag is set

and enabled

then execute ST1Hz interrupt processing "SIT1"

Reset and store

serial interface interrupt factor flag in the A register

If the serial interface interrupt factor flag is set

then execute serial interface interrupt processing "ISIO"

If the K0 interrupt factor flag is set

then execute K0 interrupt processing "IK0"

II-18 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 4: INTERRUPT AND HALT

;

INK1: LD Y,YIKSTB ;

FAN MY,1000B ;

JP Z,INTI ;

CALL IK1 ;

;

INTI: LD X,79H ;

LD Y,YETI ;

LD MY,MX ;

LD X,78H ;

AND MY,MX ;

;FAN MY,0001B ;

JP Z,INTI8 ;

CALL TI32 ;

;

INTI8: LD Y,YTIB ;

FAN MY,0010B ;

JP Z,INTI2 ;

CALL TI8 ;

;

INTI2: LD Y,YTIB ;

FAN MY,0100B ;

JP Z,INRT ;

CALL TI2 ;

;

INRT: POP F ;

POP B ;

POP A ;

POP YP ;

POP YL ;

POP YH ;

POP XP ;

POP XL ;

POP XH ;

RET ;

If the K1 interrupt factor flag is set

then execute K1 interrupt processing "IK1"

Reset and store

the timer interrupt factor flags

in the buffer

Mask the timer interrupt factor flag

by the value of the timer interrupt mask register

If the T32Hz interrupt factor flag is set

and enabled

then execute T32Hz interrupt processing "TI32"

If the T8Hz interrupt factor flag is set

and enabled

then execute T8Hz interrupt processing "TI8"

If the TI2Hz interrupt factor flag is set

and enabled

then execute T2Hz interrupt processing "TI2"

Return the value of F register from stack

Return the value of B register from stack

Return the value of A register from stack

Return the value of Y register from stack

Return the value of X register from stack

Return to parent routine

Addresses of buffers IKSTB and TIB can be set anywhere in

RAM.

This routine assumes that processing routines "SIT0",

"SIT1", "ISIO", "IK0", "IK1", "TI32", "TI8" and "TI2" have been

prepared separately for each of the interrupts.

S1C62N33 TECHNICAL SOFTWARE EPSON II-19

CHAPTER 4: INTERRUPT AND HALT

4.6 Programming Notes

(1)Write to the interrupt mask registers only in the DI status

(interrupt flag = "0"). Writing in the EI status can cause

an error.

(2)Even when the interrupt mask registers (ETI, EISWIT) are

set to "0", the interrupt factor flags (TI, SWIT) of the clock

timer and stopwatch counter can be set when the timing

conditions are established.

(3)When an interrupt is generated, three words of RAM are

used; also, it takes 12 cycles of the CPU system clock

until the value of the interrupt vector is set in the pro-

gram counter.

(4)When an interrupt occurs, the DI status (interrupt flag =

"0") comes into effect automatically.

(5)Read the interrupt factor flags only in the DI status

(interrupt flag = "0"). Reading out in the EI status can

cause an error.

II-20 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Watchdog Timer)

PERIPHERAL CIRCUITS

Peripheral circuits of the S1C62N33 Series, such as the timer

and I/O, are interfaced with the CPU by memory mapped I/O

format. This means that all peripheral circuits can be

controlled by accessing the memory map's I/O memory or

segment memory with memory operation instructions.

This chapter details how to control the peripheral circuits.

Watchdog Timer

The S1C62N33 Series incorporates a watchdog timer.

If the watchdog timer reset is not executed by the software

in at least 3–4 seconds, the initial reset signal is output

automatically for the CPU.

You can select whether or not to use the watchdog timer

with the mask option. When "Not use" is chosen, there is no

need to reset the watchdog timer.

CHAPTER 5

5.1

Watchdog timer

memory map

Table 5.1 I/O data memory map (watchdog timer)

Address Comment

D3 D2 D1 D0 Name SR *1 10

7FH

WDRST WD2 WD1 WD0

WDRST

WD2

WD1

WD0

Reset

Watchdog timer reset *5

Timer data (watchdog timer 1/4 Hz)

Timer data (watchdog timer 1/2 Hz)

Timer data (watchdog timer 1 Hz)

–

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

S1C62N33 TECHNICAL SOFTWARE EPSON II-21

CHAPTER 5: PERIPHERAL CIRCUITS (WATCHDOG TIMER)

This is the bit for resetting the watchdog timer.

When "1" is written: Watchdog timer is reset.

When "0" is written: No operation

Read-out: Always "0"

When the watchdog timer is used for the reset function, the

software must reset the watchdog timer within 3 seconds.

Operation restarts immediately after the watchdog timer is

reset.

Ordinarily, this routine is incorporated where periodic

processing takes place, such as in the timer interrupt rou-

tine, to detect program overrun, for instance when the

watchdog timer processing is bypassed.

In this case, timer data (WD0–WD2) cannot be used for timer

applications.

The watchdog timer operates in the halt mode. If the halt

status continues for 3–4 seconds, the initial reset signal

restarts operation.

When the timing flag ("0.5 sec flag") is set in the T2Hz inter-

rupt processing routine "TI2", the watchdog timer will be

reset every second.

When the routine "basic timer 'CK'" for the timer is executed

every second on the second, the watchdog timer will be reset

every second on the half-second.

WDRST:

Watchdog timer reset

(7FH.D3)

Note

Specifications

Example of reset

processing for

watchdog timer

Fig. 5.1

Timing chart

n sec n.5 sec (n+1) sec (n+1).5 sec

"CK" is executed "CK" is executed

Watchdog timer

is reset Watchdog timer

is reset

Time

II-22 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Watchdog Timer)

Program

XTISF EQU 0001B ;

YFTM EQU ◆◆◆◆H;

;

TI2: LD X,YFTM ;

FAN MX,XTISF ;

JP NZ,TI21 ;

;OR MX,XTISF ;

LD X,7FH ;

LD MX,0001B ;

RET ;

TI21: AND MX,XTISF XOR 0FH ;

CALL CK ;

;RET ;

0.5 sec flag (TISF)

Address for timing flag set

TISF = "0" or "1"?

TISF = "0": Set the TIS flag

Reset the watchdog timer

Returns to parent routine

TISF = "1": Reset the TIS flag

Execute the basic timer "CK"

Returns to parent routine

The address for the timing flag set FTM can be set anywhere

in RAM.

Further, this routine assumes that a timer subroutine has

been prepared separately to make 1 second the unit for the

routine "basic timer 'CK'".

(See page 63, "Example of using timer interrupt" for how to

make "basic timer 'CK'".)

When the watchdog timer is used for the reset function, the

software must reset the watchdog timer within 3 seconds.

In this case, timer data (WD0–WD2) cannot be used for

timer applications.

Programming note

S1C62N33 TECHNICAL SOFTWARE EPSON II-23

CHAPTER 5: PERIPHERAL CIRCUITS (OSC3)

OSC3

S1C62A33 has two built-in oscillation circuits (OSC1 and

OSC3).

When processing of S1C63A33 requires high-speed opera-

tions, the CPU's operating clock should be switched from

OSC1 to OSC3.

5.2

OSC3 memory map

Table 5.2 I/O data memory map (OSC3)

Address

*7 Comment

D3 D2 D1 D0 Name SR *1 10

FEH

OSCC IOC1

–

CLKCHG

OSCC

IOC1

OSC3

Output

OSC1

OFF

Input

Unused *5

CPU clock switch *6

OSC3 oscillator ON/OFF

I/O control register 1 (P10–P13)

R/W

CLKCHG

–

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

The CPU's operation clock is selected with this register

(S1C62N33 only).

When "1" is written: OSC3 is selected

When "0" is written: OSC1 is selected

Read-out: Available

This register cannot be controlled for S1C62N33/62L33, so

that OSC1 is selected regardless of the set value.

CLKCHG:

The CPU's clock switch

(FEH.D2)

II-24 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (OSC3)

To lessen current consumption, keep OSC3 oscillation OFF except

when the CPU must be run at high speed. Also, with S1C62N33/

62L33, keep OSCC fixed to "0".

This subroutine first sets OSC3 to ON, and then, after about

5 ms, switches the CPU clock to OSC3.

(1) Switching from OSC1 to OSC3

OS3: LD X,0FEH ;

OR MX,0010B

;LD A,0EH ;

OS3DLLP: ADD A,0FH ;

JP NZ,OS3DLLP ;

;OR MX,0100B ;

RET ;

Set OSC3 to ON

Delay of 5.28 ms: preparation

Loop for delay

Switche the CPU clock to OSC3

Return to parent routine

A 5.28 ms delay is specified before switching to OSC3, to

allow time for the oscillation circuit to stabilize.

Example of using

OSC3

Note

Specifications

Program

Note

S1C62N33 TECHNICAL SOFTWARE EPSON II-25

CHAPTER 5: PERIPHERAL CIRCUITS (OSC3)

(2) Switching from OSC3 to OSC1

This subroutine switches the CPU clock to OSC1, and then

sets OSC3 to OFF.

OS1: LD X,0FEH ;

AND MX,1011B ;

;AND MX,1101B ;

RET ;

Switche the CPU clock to OSC1

Set OSC3 to OFF

Return to parent routine

To prevent an error, first switch OSC1, and then set OSC3

to OFF in the next step.

(1)It takes at least 5 ms from the time the OSC3 oscillation

circuit goes ON until the oscillation stabilizes. Conse-

quently, when switching the CPU operation clock from

OSC1 to OSC3, do this after a minimum of 5 ms have

elapsed since the OSC3 oscillation went ON.

Further, the oscillation stabilization time varies depend-

ing on the external oscillator characteristics and condi-

tions of use, so allow ample margin when setting the wait

time.

(2)When switching the clock from OSC3 to OSC1, use a

separate instruction for switching the OSC3 oscillation

OFF.

(3)To lessen current consumption, keep OSC3 oscillation

OFF except when the CPU must be run at high speed.

Also, with S1C62N33/62L33, keep OSCC fixed to "0".

Program

Note

Specifications

Programming notes

II-26 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Supply Voltage Detection (SVD) Circuit and

Heavy Load Protection Function

The S1C62N33 Series has a built-in supply voltage detection

(SVD) circuit, so that the software can find when the source

voltage lowers.

S1C62L33 has a heavy load protection function for when the

battery load becomes heavy and the source voltage drops.

*1 Initial value following initial reset *5 Always

5.3

SVD circuit memory

map

Table 5.3 I/O data memory map (SVD circuit and heavy load protection function)

Address Comment

D3 D2 D1 D0 Name SR

76H

HVLD SVDDT

SVDON

EISWIT1 EISWIT0

R/W

HVLD

EISWIT1

EISWIT0

Enable

Mask

SVD evaluation data (at read-out)

SVD ON/OFF (at writing)

Interrupt mask register

(stopwatch 1 Hz)

Interrupt mask register

(stopwatch 10 Hz)

R/W SVDDT

SVDON 0

Heavy

load Normal

Low voltage Normal

OFF

Heavy load protection mode register

"0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

To obtain the SVD detection result, follow the programming

sequence below.

0. Set HVLD to "1" (only when the CPU system clock is

fosc3 in S1C62A33)

1. Set SVDON to "1"

2. Maintain at 100 µs minimum

3. Set SVDON to "0"

4. Read out SVDDT

5. Set HVLD to "0" (only when the CPU system clock is

fosc3 in S1C62A33)

Example of finding

supply voltage using

SVD circuit

S1C62N33 TECHNICAL SOFTWARE EPSON II-27

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

When HVLD is set to "1" or low voltage is detected by the

SVD, the HVLD circuit is turned ON. At the same time the

SVD circuit is switched ON and OFF.

At this time, sampling control is executed for the SVD cir-

cuit ON time. There are two types of sampling time, as

follows:

➀The time of one instruction cycle immediately after the

HVLD circuit is turned ON.

➁Sampling at cycles of 2 Hz output by the clock timer

while HVLD circuit ON time.

When the CPU system clock is fosc3 in S1C62A33, the

detection result at the timing in ➀ above may be invalid or

incorrect. When performing SVD detection using the timing

in ➀, be sure that the CPU system clock is fosc1.

Appreciable current is consumed during operation of SVD detec-

tion, so keep SVD detection OFF except when necessary.

Note

(1) For OSC1 using SVDON

Specifications When the CPU clock is OSC1, the timing flag ("0.5 sec flag")

is set in the T2Hz interrupt processing routine "TI2", so that

the supply voltage is detected every second.

Every second on the second the timer routine "basic timer

'CK'" is executed, to turn SVD ON or OFF every second on

the half second.

If the detection result indicates that the voltage is low, the

separately prepared low voltage display routine "DSSVD" is

executed.

n sec n.5 sec (n+1) sec (n+1).5 sec

"CK" is executed "CK" is executed

Supply voltage

is detected

Time

Supply voltage

is detected

Fig. 5.3.1

Timing chart

II-28 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

The address for the timing flag set FTM can be set anywhere

in RAM.

This routine assumes that a timer subroutine has been

prepared separately to make 1 second the unit for the rou-

tine "basic timer 'CK'".

(See page 63, "Example of using timer interrupt" for how to

make "basic timer 'CK'".)

XTISF EQU 0001B ;

YFTM EQU ◆◆◆◆H;

;

TI2: LD X,YFTM ;

FAN MX,XTISF ;

JP NZ,TI21 ;

;OR MX,XTISF ;

LD X,76H ;

OR MX,0100B ;

AND MX,1011B ;

FAN MX,0100B ;

JP Z,TI2RT ;

CALL DSSVD ;

;

TI2RT: RET ;

TI21: AND MX,XTISF XOR 0FH ;

CALL CK ;

;RET ;

Program

0.5 sec flag (TISF)

Address for timing flag set

TISF = "0" or "1"?

TISF = "0": Set the TIS flag

Detect: SVD ON

SVD OFF

If result is "1" (low voltage)

then execute display routine "DSSVD"

Return to parent routine

TISF = "1": Reset the TIS flag

Execute the basic timer "CK"

Return to parent routine

Timing chart of SVD operation

Fig. 5.3.2

Timing chart of

SVD operation

0.5 sec

SVD circuit

HVLD circuit

SVDDT register

SVDON register

Source voltage

1 sec

Criteria voltage

(1.2 V)

S1C62N33 TECHNICAL SOFTWARE EPSON II-29

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

(2) For OSC3 using HVLD

When the CPU clock is OSC3, the supply voltage is detected

every second, just as for (1). However, the method of detec-

tion is through the ON and OFF status of HVLD.

When the CPU clock is OSC3, detection must be performed

after switching the CPU clock to OSC1.

XTISF EQU 0001B ;

YFTM EQU ◆◆◆◆H;

;

TI2: LD X,YFTM ;

FAN MX,XTISF ;

JP NZ,TI21 ;

;OR MX,XTISF ;

LD X,76H ;

LD Y,0FEH ;

AND MY,1011B ;

OR MX,1000B ;

AND MX,0011B ;

OR MY,0100B ;

FAN MX,0100B ;

JP Z,TI2RT ;

CALL DSSVD ;

;

TI2RT: RET ;

TI21: AND MX,XTISF XOR 0FH ;

CALL CK ;

;RET ;

SVDON is fixed to "0" when the HVLD is turnd OFF, because

SVDON risides in the same bits at the same address as

SVDDT, and one or the other is selected by write or read

operation.

Specifications

Program

Note

0.5 sec flag (TISF)

Address for timing flag set

TISF = "0" or "1"?

TISF = "0": Set the TIS flag

Detect: Preparation

Switch the CPU's operating clock OSC1

HVLD ON

HVLD OFF

Return the CPU's operating clock to OSC3

If the result is "1" (low voltage)

then execute display routine "DSSVD"

Return to parent routine

TISF = "1": Reset the TIS flag

Execute the basic timer "CK"

Return to parent routine

II-30 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

(3) For S1C62L33 using HVLD

S1C62L33 uses HVLD to detect supply voltage. The other

conditions are the same as for (1) and (2). However, the

CPU of S1C62L33 does not use OSC3 for the clock.

S1C62L33 has a heavy load protection function, so do not

use HVLD to detect supply voltage in the heavy load protec-

tion mode.

(See the following sections for the heavy load protection

function.)

XTISF EQU 0001B ;

YFTM EQU ◆◆◆◆H;

;

TI2: LD X,YFTM ;

FAN MX,XTISF ;

JP NZ,TI21 ;

;OR MX,XTISF ;

LD X,76H ;

FAN MX,1000B ;

JP NZ,TI2DSB ;

;OR MX,1000B ;

AND MX,0011B ;

TI2DSB: FAN MX,0100B ;

JP Z,TI2RT ;

CALL DSSVD ;

;

TI2RT: RET ;

TI21: AND MX,XTISF XOR 0FH ;

CALL CK ;

;RET ;

0.5 sec flag (TISF)

Address for timing flag set

TISF = "0" or "1"?

TISF = "0": Set the TIS flag

If HVLD is OFF

then detect: HVLD ON

HVLD OFF

If the result is "1" (low voltage)

then execute display routine "DSSVD"

Return to parent routine

TISF = "1": Reset the TIS flag

Execute the basic timer "CK"

Return to parent routine

When the HVLD is turned OFF, SVDON is fixed to "0".

Program

Note

Specifications

S1C62N33 TECHNICAL SOFTWARE EPSON II-31

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Note that the heavy load protection function on the

S1C62L33 is different from the S1C62N33.

(1)In case of S1C62L33

The S1C62L33 has the heavy load protection function for

when the battery load becomes heavy and the source

voltage drops, such as when an external buzzer sounds

or an external lamp lights. The state where the heavy

load protection function is in effect is called the heavy

load protection mode. In this mode, operation with a

lower voltage than normal is possible.

The normal mode changes to the heavy load protection

mode in the following two cases:

➀When the software changes the mode to the heavy load

protection mode (HVLD = "1")

➁When supply voltage drop (SVDDT = "1") in the SVD

circuit is detected, the mode will automatically shift to

the heavy load protection mode until the supply volt-

age is recovered (SVDDT = "0")

In the heavy load protection mode, the internally regu-

lated voltage is generated by the liquid crystal driver

source output VL2 so as to operate the internal circuit.

Consequently, more current is consumed in the heavy

load protection mode than in the normal mode. Unless it

is necessary, be careful not to set the heavy load protec-

tion mode with the software. Also, when the SVD is to be

turned on during operation in the heavy load protection

mode, limit the ON time to 10 ms per second of operation

time.

(2)In case of S1C62N33/62A33

This function can be used when the "Use" is selected by

the mask option for the heavy load protection function.

The S1C62N33/62A33 has the heavy load protection

function for when the battery load becomes heavy and

the source voltage changes, such as when an external

buzzer sounds or an external lamp lights. The state

where the heavy load protection function is in effect is

called the heavy load protection mode. Compared with

the normal operation mode, this mode can reduce the

output voltage variation of the constant voltage/booster

voltage circuit of the LCD system.

Example of using

heavy load protec-

tion function

II-32 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

The normal mode changes to the heavy load protection

mode in the following case:

➀When the software changes the mode to the heavy load

protection mode (HVLD = "1")

The heavy load protection mode switches the constant

voltage circuit of the LCD system to the high-stability

mode from the low current consumption mode. Conse-

quently, more current is consumed in the heavy load

protection mode than in the normal mode. Unless it is

necessary, be careful not to set the heavy load protection

mode with the software.

(1) Control of heavy load protection function using flag (S1C62L33)

Specifications When heavy load protection mode is set, this will be routine

"HLONBZ" which switches BZ ON, routine "BZOF" which

switches BZ OFF, and 2 Hz interrupt routine "TI2" which

controls 1-second waiting release.

This routine employs the heavy load protection mode release

flag HLOFF, which recognizes termination of heavy load

drive, and the heavy load protection mode release delay flag

HLOFDLF, which takes the timing of a 1-second wait.

Setting heavy load protection mode

XHLOF EQU 1000B ;

XHLOFDL EQU 0100B ;

XNOTHL EQU 0011B ;

YFHL EQU ◆◆◆◆H;

;

HLONBZ: LD X,76H ;

OR MX,1000B ;

LD X,YFHL ;

AND MX,XNOTHL ;

LD X,7CH ;

OR MX,0001B ;

RET ;

Heavy load protection mode release flag

Heavy load protection mode release delay flag

Address of heavy load protection function related flag set

Set heavy load protection mode

Reset flags related to heavy load protection

Switch BZ ON

Return to parent routine

This routine assumes that the addresses of the flag set

related to heavy load protection functions together with the

0.5 sec flag are allocated suitably in RAM as the addresses

of the timing flag set.

S1C62N33 TECHNICAL SOFTWARE EPSON II-33

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Release of heavy load protection mode

When the heavy load drive terminates, the heavy load

protection mode release flag is set, the heavy load protection

mode delay flag is set and reset with the 1-second timer

during the T2Hz interrupt processing routine, the heavy

load protection mode is released.

Fig. 5.3.3

Timing chart

n sec n.5 sec (n+1) sec (n+1).5 sec

Heavy load

drive terminates

(HLOF flag is set)

HLOFDL

flag is set

Time

Heavy load protection

mode is released

(Two flags are reset)

"CK" is executed "CK" is executed

XTISF EQU 0001B ;

XHLOFF EQU 1000B ;

XHLOFDL EQU 0100B ;

XNOTHL EQU 1100B ;

YFTM EQU ◆■◆■H;

YFHL EQU ◆◆◆◆H;

;

BZOF: LD X,7CH ;

AND MX,1110B ;

LD X,YFHL ;

OR MX,XHLOF ;

RET ;

;

TI2: LD X,YFTM ;

FAN MX,XTISF ;

JP NZ,TI21 ;

;

OR MX,XTISF ;

FAN MX,XHLOFDL ;

JP Z,TI2RT ;

FAN MX,XHLOFDL ;

JP NZ,TI2HLO ;

;OR MX,XHLOFDL ;

RET ;

0.5 sec flag (TISF)

High load protection mode release flag (HLOFF)

High load protection mode release delay flag (HLOFDLF)

Address of timing flag set

Address of heavy load protection flag set

Stop BZ

Set the HLOF flag

Return to parent routine

TISF = "0" or "1"?

TISF = "0": Set the TIS flag

If the HLOF flag is set

then HLOFDLF = "0" or "1"?

HLOFDLF = "0": Set the HLOFDL flag

Return to parent routine

II-34 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

TI2HLO: AND MX,XNOTHL ;

;

LD X,76H ;

AND MX,0011B ;

;

TI2RT: RET ;

TI21: AND MX,XTISF XOR 0FH ;

CALL CK ;

;RET ;

HLOFDLF = "1": Reset heavy load protection

flag set

Release heavy load protection mode

and fix SVDON to "0"

Return to parent routine

TISF = "1": Reset the TIS flag

Execute basic timer "CK"

Return to parent routine

See page 40, "Example of using output ports" for details on

BZ control.

1. When the heavy load protection mode is set, the heavy

load protection flags must be reset.

2. SVD is fixed to "0" when the heavy load protection mode

is released, because the SVDON result is not fed back to

SVDON through the AND instruction.

Notes

(2) Method without using flags (S1C62L33)

When heavy load protection mode is set, this will be routine

"HLONBZ" which switches BZ ON and routine "BZHLOF"

which stop BZ then releases the heavy load protection mode.

Note, however, that unlike item (1) above, it does not use

flags.

SVDON is used to release the heavy load protection mode

without using flags. After the heavy load drive terminates,

the SVD is set ON and OFF, and then the heavy load protec-

tion mode is released.

Specifications

Program

HLONBZ: LD X,76H ;

OR MX,1000B ;

LD X,7CH ;

OR MX,0001B ;

RET ;

;

BZHLOF: LD X,7CH ;

AND MX,1110B ;

LD X,76H ;

Set the heavy load protection mode

Switch BZ ON

Return to parent routine

Stop BZ

SVD ON

S1C62N33 TECHNICAL SOFTWARE EPSON II-35

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

OR MX,0100B ;

AND MX,1011B ;

AND MX,0011B ;

;

RET ;

OFF

Release the heavy load protection mode

and fix SVDON to "0"

Return to parent routine

SVD is fixed to "0" when the heavy load protection mode is

released, because the SVDON result is not fed back to

SVDON through the AND instruction.

Note

Timing chart of heavy load protection mode operation

(3) Control of heavy load protection (for S1C62N33/62A33)

When the heavy load protection function is selected for the

S1C62N33 or S1C62A33 by the mask option setting, the

"HLBZ10" routine sets the heavy load protection mode and

outputs the BZ signal for 10 ms, then, it releases the heavy

load protection mode.

However, the OSC1 clock (32.768 kHz) must be set for the

CPU operating clock.

Specifications

Fig. 5.3.4

Timing chart

of HVLD operation

0.5 sec

SVDDT register

SVD circuit

SVDON register

BZ output

HVLD circuit

HVLD register

Source voltage Criteria voltage

(1.2 V)

Fig. 5.3.5

Timing chart

HVLD

10 ms

II-36 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

HLBZ10: LD X,76H ;Set the heavy losd protection mode

OR MX,1000B ;

LD Y,7CH ;Switch BZ ON

OR MY,1000B ;

;CALL ST10MS ;10 ms soft timer call

;AND MY,0111B ;Switch BZ OFF

AND MX,0111B ;Release the heavy load protection mode

;

ST10MS: LD A,0H ;10 ms soft timer subroutine

RDF ;Reset the decimal flag

ST10MS1: NOP7 ;Loop for 10 ms

ADD A,0FH ;(7+7+5) clock × 16

JP NZ,ST10MS1 ;

RET ;

Program

Note The heavy load protection mode can be released immediately

after driving the heavy load (BZ output).

To reduce current consumption, release the heavy load

protection mode unless otherwise necessary.

(1)It takes 100 µs from the time the SVD circuit goes ON

until a stable result is obtained. For this reason, keep

the following software notes in mind:

➀When the CPU system clock is fosc1

1. When detection is done at HVLD

After writing "1" on HVLD, read the SVDDT after 1

instruction has passed.

2. When detection is done at SVDON

After writing "1" on SVDON, write "0" after at least

100 µs has lapsed (possible with the next instruc-

tion) and then read the SVDDT.

➁When the CPU system clock is fosc3 (in case of

S1C62A33 only)

When detection is done at HVLD

After writing "1" on HVLD, read the SVDDT after 0.6

sec has passed. (HVLD holds "1" for at least 0.6 sec)

Programming notes

S1C62N33 TECHNICAL SOFTWARE EPSON II-37

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

2. When detection is done at SVDON

Before writing "1" on SVDON, write "1" on HVLD

first; after at least 100 µs has lapsed after writing

"1" on SVDON, write "0" on SVDON and then read

the SVDDT.

(2)To reduce current consumption, set the SVD operation to

OFF unless otherwise necessary.

(3)SVDON resides in the same bit at the same address as

SVDDT, and one or the other is selected by write or read

operation. When writing a "1" to SVDON use the OR

command, and when writing a "0" use the AND com-

mand. No other commands should be used for this

purpose.

(4)Select one of the following software processing to return

to the normal mode after a heavy load has been driven in

the heavy load protection mode (S1C62L33).

➀After heavy load drive is completed, return to the

normal mode after at least one second has elapsed.

➁After heavy load drive is completed, switch SVD ON

and OFF (at least 100 µs is necessary for the ON

status) and then return to the normal mode.

The S1C62N33/62A33 returns to the normal mode after

driving a heavy load without special software processing.

(5)To reduce current consumption, be careful not to set the

heavy load protection mode with the software unless

otherwise necessary.

(6)When the SVD is to be turned on during operation in the

heavy load protection mode, limit the ON time to 10 ms

per second of operation time.

II-38 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)

Output Ports (R00–R03, R10–R13)

The S1C62N33 Series reserves eight bits (4 bits × 2) for

general output ports. The output ports R10–R13 can be

used as special output ports.

5.4

Output port memory

map

Table 5.4 I/O data memory map (output ports)

Address Comment

D3 D2 D1 D0 Name SR

7BH

7CH

R03 R01 R00

R12 R11 R10

R/W

R03

R02

R01

R00

High

Low

R13

R12

R11

R10

High

Low

Output port (R00–R03)

Output port (R13, BZ) *6

Output port (R12, FOUT) *6

Output port (R11)

Output port (R10, BZ) *6

R02

R/W

R13

F6H

BZFQ BZFQ

–

0 2 kHz 4 kHz

Buzzer frequency selection register

Unused *5

RR/W

–––

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

S1C62N33 TECHNICAL SOFTWARE EPSON II-39

CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)

R12

(when FOUT is selected):

Special output port

data

(7CH.D2)

R10, R13

(when BZ and BZ output is

selected):

Special output ports

data

(7CH.D0 and D3)

The following explanations cover the control registers when

special output has been selected for R10, R12, and R13.

These bits control the output of the buzzer signals (BZ, BZ).

When "1" is written: Buzzer signal is output

When "0" is written: Low level (DC) is output

Read-out: Available

BZ is output from pin R13. The mask option supports

selection of output control by R13, or output control by R10

simultaneously with BZ.

• When R13 controls BZ output

BZ output and BZ output can be controlled independ-

ently. BZ output is controlled by writing data to R10,

and BZ output is controlled by writing data to R13.

• When R10 controls BZ output

BZ output and BZ output can be controlled simultane-

ously by writing data to R10 only. For this case, R13 can

be used as a one-bit general register having both read

and write functions, and data of this register exerts no

affect on BZ output (output from pin R13).

Controls the FOUT (clock) output.

When "1" is written: Clock output

When "0" is written: Low level (DC) output

Read-out: Available

II-40 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)

option.

First, the immediate value "0010B" is output to the output

ports R00–R03.

The value of RAM, OUTB is output to output ports R10–R13.

Figure 5.4.1 indicates the correspondence of write data and

output ports.

(1) Writing and reading to output ports

Example of using

output ports

Specifications

R12 register

R13 register

R11 register

R10 register

R02 register

R03 register

R01 register

R00 register

R13

R12

R11

R10

R03: Becomes low output

R02: Becomes low output

R01: Becomes high output

R00: Becomes low output

100D0D1D2D3

RAM, OUTB Immediate value

Fig. 5.4.1

Correspondence

of write data and

output ports

Then, the status of the (outputting) pins of output ports

R00–R03 is read into B register, and the status of the pins of

output ports R10–R13 is read into RAM, DTB.

S1C62N33 TECHNICAL SOFTWARE EPSON II-41

CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)

YOUTB EQU ●▼●▼H;

YDTB EQU ●★●★H;

;

;LD X,7BH ;

LD MX,0010B ;

;LD X,7CH ;

LD Y,YOUTB ;

LD MY,MX

;LD X,7BH ;

LD B,MX ;

;LD X,7CH ;

LD Y,YDTB ;

LD MY,MX ;

Buffer address of data to be output to R10–R13

Buffer address of data

Output (write) the immediate value "0010B" to R00–R03

Output (write) the value of RAM, OUTB to R10–R13

Read the value of R00–R03 (being output) to B register

Read the value of R10–R13 (being output) to RAM, DTB

Addresses for RAM, OUTB and DTB are allocated appropri-

ately.

Program

II-42 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)

Specifications

No change

Set to "1"

Set to "0"

Set to "1"

R03: Becomes high output

R02: No change

R01: Becomes low output

R00: Becomes high output

R00R01R02R03

I/O memory

Fig. 5.4.2

Output result

(2) Operation of output ports by separate bits

This routine uses the read-out capability of the output port

control registers, to control output for separate bits with the

memory arithmetic instructions.

First, "1" is written to registers R00 and R03 by the OR

instruction, and then "0" is written to register R01 by the

AND instruction.

The result of the output to ports R00–R03 is shown in

Figure 5.4.2.

Make R00 and R03 outputs high

Make R01 output low

LD X,7BH ;

OR MX,1001B ;

AND MX,1101B ;

Program

S1C62N33 TECHNICAL SOFTWARE EPSON II-43

CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)

(3) Scanning for key input by ports R00–R03

The key matrix is shown in Figure 5.4.3. This is the scan-

ning subroutine, "KYSC", to specify the key that has been

made high input.

R03

R02

R01

R00

Kxx

"KYSC" first brings R00 to high output and the other ports

to low output, and then executes "KYIN" to judge whether an

entry has been made to the key connected to R00.

Regardless of the result of evaluation, the high output pin is

shifted to the left and the key connected to the next pin is

evaluated.

This processing is repeated up to R03.

KYSC: LD X,7BH ;

LD MX,0001B ;

;

KYSCLP: CALL KYIN ;

LD X,7BH ;

ADD MX,MX ;

JP NZ,KYSCLP ;

RET ;

Make R00 only high output

Scanning loop: Execute key input evaluation processing "KYIN"

Shift high output to left

Continue until R00–R03 are all low

Return to parent routine

This routine assumes that the key input evaluation process-

ing routine "KYIN" has been prepared separately.

Fig. 5.4.3

Key matrix (Kxx × R00–R03)

Program

Specifications

II-44 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)

(4) Control of BZ (when R13 is R10 control)

BZ4: LD X,0F6H ;

LD MX,0000B ;

LD X,7CH ;

OR MX,0001B ;

RET ;

BZ2: LD X,0F6H ;

LD MX,1000B ;

LD X,7CH ;

OR MX,0001B ;

RET ;

BZOF: LD X,7CH ;

AND MX,1110B ;

RET ;

Set BZ frequency to 4 kHz

Make R10 and R13 high output

Return to parent routine

Set BZ frequency to 2 kHz

Make R10 and R13 high output

Returns to parent routine

Make R10 and R13 low output

Return to parent routine

None of these routines affects registers R11–R13 (output

pins R11 and R12).

This is the subroutine to switch BZ and BZ ON and OFF

when R13 has become R10 control.

In subroutine "BZ4", BZ output is switched ON after the BZ

frequency is set to 4 kHz.

In subroutine "BZ2", BZ output is switched ON after the BZ

frequency is set to 2 kHz.

In subroutine "BZOF", BZ output is switched OFF.

Program

Note

Specifications

S1C62N33 TECHNICAL SOFTWARE EPSON II-45

CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)

(5) Control of BZ frequency (when R13 is R10 control)

This subroutine, "BZ", uses the BZ frequency control to

sound BZ at 4 kHz when the value of the second counter is

implemented in even time, and at 2 kHz for odd time.

The second counter is the seconds column BCD data in the

timer program. This routine assumes that the start address

of the seconds data (that is, the memory address of the 1-

second column BCD data) is defined in "YCKS", the symbol

indicating the address. (In the program example, " 0H".)

The value of the second counter is judged to be even time

(that is, even seconds) or odd time (that is, odd seconds)

depending on whether the D0 data in the BCD data is "0" or

"1". Branching is done depending on this evaluation, and

the BZ is sounded after "0" or "1" is written to the BZFQ

Specifications

Program

YCKS EQU 0H ;

;

BZ: LD X,0F6H ;

LD Y,YCKS ;

FAN MY,0001B ;

JP NZ,BZ0D ;

;LD MX,0000B ;

JP BZON ;

BZ0D: LD MX,1000B ;

;

BZON: LD X,7CH ;

OR MX,0001B ;

RET ;

Start address of second counter

Store the I/O memory BZFQ in the X register

Is the value of the second counter even or odd?

Even: Make BZFQ = "0"

Odd: Make BZFQ = "1"

Output BZ

Return to parent routine

II-46 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)

In this program example, the BZ frequency is changed

(according to even seconds or odd seconds) only when "BZ"

is called and executed.

For instance, if "BZ" is executed at even seconds and the BZ

frequency is set to 4 kHz, then the BZ frequency will still be

4 kHz, even if the second counter advances and becomes

odd seconds. As long as "BZ" is not executed again, the

frequency will not change to 2 kHz.

When BZ has been selected by the output application for pin

R13, the mask option decides whether output is controlled

by register R13, or by register R10 simultaneously with BZ.

In particular, when BZ output is under R10 control, register

R13 can be used as a 1-bit general register for read/write.

Data in this register has no affect on BZ output (output of

pin R13).

Note

Programming note

S1C62N33 TECHNICAL SOFTWARE EPSON II-47

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

LCD Driver

The S1C62N33 Series has four common pins and 40

segment pins, so that it can drive an LCD with up to 160 (40

× 4) segments.

The driving method is 1/4 duty (or 1/3 duty with the mask

option) dynamic drive.

Further, the S1C62N33 Series provides software setting of

the LCD static drive.

5.5

Segment data mem-

ory map

Fig. 5.5.1

Segment data memory map

Address

Page High

Low 0123456789ABCDEF

4 or C

5 or D

6 or E

Segment data memory (40 words x 4 bits)

40H–6FH = R/W

C0H–EFH = W

The LCD segments are lit or turned off depending on this

data.

When "1" is written: Lit

When "0" is written: Not lit

Read-out: Available for 40H–6FH

Undefined for C0H–EFH

At initial reset, the contents of the segment data memory are

undefined.

When 40H–6FH is selected for the segment data memory, the

memory data and the display will not match until the area is

initialized (through, for instance, memory clear processing by the

CPU). Initialize the segment data memory by executing initial

processing.

When C0H–EFH is selected for the segment data memory, that

area becomes write-only. Consequently, data cannot be rewrit-

ten by arithmetic operations (such as AND, OR, ADD, SUB).

Data output from segment pins selected as DC output will be the

data corresponding to the COM0 pins.

Segment data memory

(40H–6FH or C0H–EFH)

Note

II-48 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

This is the subroutine "DSCG", which uses the table lookup

instruction to generate characters corresponding to the

values of A and B registers, by writing to the A and B regis-

ters.

Segment data memory assignment table

Data

D3 D2 D1 D0

(n+0)H – c b a

(n+1)H h g f e

(n+2)H l k j i

(n+3)H – o n m

Pin address assignment table

Common 0 Common 1 Common 2 Common 3

SEG(0+4•n) (b) (a) (o) (p)

SEG(1+4•n) (g) (f) (e) (l)

SEG(2+4•n) (h) (i) (j) (k)

SEG(3+4•n) (d) (c) (m) (n)

Address

(1) Generation of 16-segment character

↓

↑

Common0

Common1

Common2

Common3

gfh

klj

SEG

(3+4•n) SEG

(1+4•n)

SEG

(2+4•n) SEG

(0+4•n)

Example of control

program for LCD

segment output

Specifications

Fig. 5.5.2

Example of LCD panel

S1C62N33 TECHNICAL SOFTWARE EPSON II-49

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

The mask options are selected as below for the segment

assignment to correspond with the LCD panel shown in

Figure 5.5.2.

• The drive duty is made 1/4 duty.

• Of the 40 segment pins, one consecutive group of four pins

(SEG0 + 4·n through SEG3 + 4·n, where n is 0 to 9) lights

one LCD figure (16 segments). (See the pin address as-

signment table.)

As a result, a group of four consecutive words in the seg-

ment memory address can control one LCD figure. (See the

segment data memory assignment table.)

The segment data memory area can be either 40H–6FH or

C0H–EFH. In the two assignment tables, the addresses of

one set of four words begin from the lowest value, as (n + 0),

(n + 1), (n + 2), (n + 3).

The relationship between the values of the A and B registers

and the characters generated is as follows:

• When the B register is "0", the value (hexadecimal) of the A

(hexadecimal).

• When the B register is "1" and A register is "0", this corre-

sponds to " " (single-figure space). When the table is

expanded, it corresponds to the character added to the A

Fig. 5.5.3

Diagram of characters

Value of A

Character

01234567 8

Value of A

Character

9ABCDEF Value of A

Character

B=1

B=0

II-50 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

"DSCG" converts the address of the steps for writing into

segment data memory the characters in the data table that

correspond to the values of registers A and B (which have

been set by the parent routine). Then it jumps to this ad-

dress with the JPBA instruction.

The PSET instruction is inserted immediately before the first

half of the JPBA instruction, so that the table look-up is on

the same page as the parent routine, and the data table part

is on a different page.

DSCG: ADD A,A ;

ADC B,B ;

PSET DSCGTB ;

JPBA ;

Set to jump to A and B

Jump to table and form subroutine

The data table begins at the start address of the page in

which it is placed. The segment memory can be written to

in such a way that numerals "0" to "9" and letters "A" to "F"

and " " (single-figure space) can be displayed. A character

can be generated by combining LBPX instruction and RETD

instruction.

Further, expansion from " " (single-figure space) can be done

according to the rule below for setting the values of the A

and B registers.

Data table

Table look-up

S1C62N33 TECHNICAL SOFTWARE EPSON II-51

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

ORG ×00H ;

;

DSCGTB LBPX MX,10000111B ;

RETD 01111000B ;

LBPX MX,01000001B ;

RETD 00000100B ;

LBPX MX,00010011B ;

RETD 00100010B ;

LBPX MX,00010011B ;

RETD 01100001B ;

LBPX MX,01010100B ;

RETD 00000101B ;

LBPX MX,00010110B ;

RETD 01100001B ;

LBPX MX,00010110B ;

RETD 01110001B ;

LBPX MX,00100110B ;

RETD 00010111B ;

LBPX MX,00010111B ;

RETD 01110001B ;

LBPX MX,00010111B ;

RETD 01000001B ;

LBPX MX,00110001B ;

RETD 01000010B ;

LBPX MX,01010011B ;

RETD 01100100B ;

LBPX MX,00000110B ;

RETD 00110000B ;

LBPX MX,01000011B ;

RETD 01100100B ;

LBPX MX,00010110B ;

RETD 01100001B ;

LBPX MX,00010110B ;

RETD 00010001B ;

LBPX MX,00000000B ;

;

RETD 00000000B ;

Start address of table

Generate "0" (write to segment memory)

, Return to parent routine

Generate "1" (write to segment memory)

, Return to parent routine

Generate "2" (write to segment memory)

, Return to parent routine

Generate "3" (write to segment memory)

, Return to parent routine

Generate "4" (write to segment memory)

, Return to parent routine

Generate "5" (write to segment memory)

, Return to parent routine

Generate "6" (write to segment memory)

, Return to parent routine

Generate "7" (write to segment memory)

, Return to parent routine

Generate "8" (write to segment memory)

, Return to parent routine

Generate "9" (write to segment memory)

, Return to parent routine

Generate "A" (write to segment memory)

, Return to parent routine

Generate "B" (write to segment memory)

, Return to parent routine

Generate "C" (write to segment memory)

, Return to parent routine

Generate "D" (write to segment memory)

, Return to parent routine

Generate "E" (write to segment memory)

, Return to parent routine

Generate "F" (write to segment memory)

, Return to parent routine

Generate " " (single-space figure)

(write to segment memory)

, Return to parent routine

II-52 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

Address

A7 A6 A5 A4 A3

P7 P6 P5 P4

P1 P0

Specifications

Fig. 5.5.4

Example of LCD panel

↑

This application example, in which the assignment shown in

(1) is made to the segment data memory area C0H–EFH, is

the "column display routine 'DSSG'" and the "apostrophe

and period display routine 'DSSGA'". Both assume, as in

(1), that eight columns of the LCD panel are to be used.

The SEG (0 + 4·n) pin for the LCD's first column is assigned

to segment memory C0H, and the remaining 31 pins are

assigned in order.

The pin assignment for the apostrophe and period assign-

ments are not shown in (1). They are assigned in the man-

ner shown in Figure 5.5.4.

Segment data memory assignment table

Data

D3 D2 D1 D0

E0H A3 A2 A1 A0

E1H A7 A6 A5 A4

E2H P3 P2 P1 P0

E3H P7 P6 P5 P4

(2) When segment memory is assigned to C0H–EFH

S1C62N33 TECHNICAL SOFTWARE EPSON II-53

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

The segment data memory area C0H–EFH is write-only, so

the display data stored in the buffers "YDSB1"–"YDSB8" (for

arithmetic operations) is written to the segment memory.

Two words of the buffer display data correspond to one

figure of the display. The low address data corresponds to

the value of the A register of DSCG, and the high address

data corresponds to the value of the B register.

YDSB1 EQU 0H ;

YDSSG EQU 0C0H ;

;

DSSG: LD X,YDSSG ;

;

LD Y,YDSB1 ;

;

DSSGLP: LDPY A,MY ;

LDPY B,MY ;

CALL DSCG ;

CP XH,0EH ;

JP C,DSSGLP

;RET ;

Segment data buffer first figure start address

Segment memory first figure start address

Store the segment memory first figure start

address to X register

Store the segment data buffer first figure start

address to Y register

Display: Set the display character

Execute "DSCG"

Continue up to the eighth figure

Return to parent routine

Figure

display

routine

II-54 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

As in the Figure display routine, the display data stored in

the buffers "YDSBA"–"YDSBP" is written to the segment data

memory.

YDSBA EQU ▲▲0H ;

YDSBP EQU ▲▲2H ;

YDSSGA EQU 0E0H ;

YDSSGP EQU 0E2H ;

;

DSSGA: LD X,YDSSGA ;

LD Y,YDSBA ;

;

DSSGAL: LDPX MX,MY ;

INC Y ;

CP XL,4H ;

JP C,DSSGAL ;

;RET ;

Segment data buffer apostrophe start address

Segment data buffer period start address

Segment data memory apostrophe start address

Segment data memory period start address

Store the segment data memory apostrophe start address in X register

Store the segment data buffer apostrophe start address in Y register

Display: Transfer the data, and increment X register

Increment the Y register

Repeat up to the eighth figure

Return to parent routine

(3) Zero-suppression of buffer data

With the settings of (1) and (2), zero-suppression can be

effected if the display data and buffer data is manipulated

by this subroutine "DSSP".

DSSP: CP MY,0H ;

JP NZ,DSSPRT ;

INC Y ;

LD MY,1H ;

;

DSSPRT: RET ;

If low address data is "0"

then make high address data "1"

Return to parent routine

Apostrophe and

period display

routine

Specifications

Program

S1C62N33 TECHNICAL SOFTWARE EPSON II-55

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

Table 5.5 I/O data memory map (LCD driver)

LCD driver memory

map

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

The sequence for specifying LCD static drive is as follows:

➀Write "1" to the register at address "78H.D3".

➁Write the same value to all registers corresponding to the

segment memory COM0–COM3.

The following is an example of switching LCD drive when the

segment memory is allocated to C0H–EFH.

Example of switch-

ing LCD drive

Address Comment

D3 D2 D1 D0 Name SR *1 10

78H

CSDC ETI2 ETI8 ETI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

II-56 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

XIO2SH EQU 0FH ;

YDSSG EQU 0C0H ;

;

SGHI: LD X,78H ;

OR MX,1000B ;

;LD X,YDSSG ;

SGHILP: LDPX MX,1111B ;

CP XH,XIO2SH ;

JP C,SGHILP ;

;RET ;

(1) Static all lit for step adjustment

This subroutine "SGHI" switches to static drive and light all

segments.

Perform step adjustment by setting the segment data after

all LCDs are lit.

The 2nd I/O memory, start high address

Segment memory first start address

Write "1" to CSDC (static drive)

All segments lit: Address to segment memory start

Make segment high output

Continue until no more area

Return to parent routine

Program

Note

Specifications

(2) Return to dynamic drive after no segments lit

This subroutine puts all the segments out, and then

switches to dynamic drive.

Specifications

XIO2SH EQU 0FH ;

YDSSG EQU 0C0H ;

;

SGLO: LD X,YDSSG ;

SGLOLP: LDPX MX,0000B ;

CP XH,XIO2SH ;

JP C,SGLOLP ;

;LD X,78H ;

OR MX,1000B ;

RET ;

The 2nd I/O memory, start high address

Segment memory first start address

No segment lit: Address to segment memory start

Make segment low output

Continue until no more area

Write "0" to CSDC (dynamic drive)

Return to parent routine

Program

S1C62N33 TECHNICAL SOFTWARE EPSON II-57

CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)

Programming notes (1)When 40H–6FH is selected for the segment data memory,

the memory data and the display will not match until the

area is initialized (through, for instance, memory clear

processing by the CPU).

Initialize the segment data memory by executing initial

processing.

(2)When C0H–EFH is selected for the segment data memory,

that area becomes write-only. Consequently, data cannot

be rewritten by arithmetic operations (such as AND, OR,

ADD, SUB).

(3)Data output from segment pins selected as DC output

will be the data corresponding to the COM0 pins.

(4)When performing step adjustment with the static drive,

set the segment data so that all LCD segments are lit.

II-58 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

Clock Timer

The S1C62N33 Series has a clock timer built-in. The clock

timer can generate timer interrupts at 32 Hz, 8 Hz and 2 Hz.

Ordinarily, this clock timer is used for all types of timing

functions such as clocks.

5.6

Clock timer memory

map

Table 5.6.1 I/O data memory map (clock timer)

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

This bit resets the clock timer.

When "1" is written: Clock timer reset

When "0" is written: No operation

Read-out: Always "0"

The clock timer restarts immediately on being reset.

Reset

Address Comment

D3 D2 D1 D0 Name SR *1 10

70H

TM3 TM2 TM1 TM0

TM3

TM2

TM1

TM0

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

7EH

SWRUN SWRST IOC0 TMRST

SWRUN

SWRST

IOC0

Clock timer reset *5

Stopwatch counter RUN/STOP

Stopwatch counter reset *5

I/O control register 0 (P00–P03)

TMRST

W R/W W R/W

Reset

RUN

Reset

Output

–

STOP

–

Input

TMRST:

Clock timer reset

(7EH.D3)

S1C62N33 TECHNICAL SOFTWARE EPSON II-59

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

(1) Initializing clock timer

This program resets the clock timer.

(2) Reading the clock timer

This program reads the clock timer data into A register.

A register

D3 D2 D1 D0

TM3 TM2 TM1 TM0

LD X,7EH ;

OR MX,1000B ;Reset the clock timer

1. When the clock timer has been reset, the interrupt factor

flag (TI) may sometimes be set to "1".

2. The watchdog timer may be counted up at the clock timer

reset.

3. Resetting the clock timer does not affect the stopwatch

counter.

LD X,70H ;

LD A,MX ;Load the clock timer data into A register

Example of using

clock timer

Specifications

Fig. 5.6.1

Correspondence between

clock timer and A register

Program

Notes

Program

Specifications

II-60 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

(3) Detecting the edge of the clock timer

This subroutine, "TMEDG", detects the edge of the timer

data, and executes the 4 Hz processing routine "TM4" if the

2 Hz edge is detected.

XTMDT2 EQU 0100B ;

YTMDTB EQU ●●×H;

;

TMEDG: LD X,70H ;

LD Y,TMDTBF ;

XOR MY,MX ;

FAN MY,XTMDT2 ;

JP Z,TMEDGRT ;

CALL TM4 ;

;

TMEDGRT: RET ;

Timer data 2 Hz

Address of timer data buffer

Detect change (edge) in timer data

If 2 Hz edge

then execute 4 Hz processing "TM4"

Return to parent routine

The processing routine for frequencies not set in the clock

timer interrupt can be executed by repeatedly calling this

subroutine at high frequency.

Program

Specifications

Fig. 5.6.2

Timing chart

TM2

Time

125 ms

n sec (n+1) sec

"1"

"0"

Timeing for executing "TM4"

S1C62N33 TECHNICAL SOFTWARE EPSON II-61

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

(4) Alarm bell using clock timer and BZ output

When called every 8 Hz, this subroutine generates the alarm

bell sound by switching the BZ output ON and OFF, as

shown in the timing chart.

Specifications

Time

TISF

2 Hz

4 Hz

8 Hz interrupt

BZ output

n sec (n+1) sec

"1"

"0"

"1"

"0"

"1"

"0"

OFF

Fig. 5.6.3

Alarm bell timing chart

XTISF EQU 0001B ;

XBESYNF EQU 0010B ;

YFTM EQU ◆◆◆◆H;

;

BE: LD Y,YFTM ;

FAN MY,XTISF ;

JP NZ,BZOF ;

;LD X,70H ;

LD A,MX ;

AND A,1100B ;

CP A,0000B ;

JP NZ,BE1 ;

;OR MY,XBESYNF ;

JP BZ ;

;

BE1: FAN MY,XBESYNF ;

JP Z,BZOF ;

CP A,1000B ;

JP NZ,BZOF ;

;AND MY,XBESYNF XOR 0FH ;

JP BZ ;

0.5 sec flag (TISF)

Bell sound synchro flag

Address of timing flag set

TISF = "0" or "1"?

TISF = "1": Execute "BZOF", return to parent routine

TISF = "0": Is the timer data of 2 Hz and 4 Hz

all "0"?

Both 2 Hz and 4 Hz are "0": Reset BESYNF

Execute "BZ", return to parent routine

2 Hz and 4 Hz not both "0":

When BESYNF = "0"

or 4 Hz = "1"

execute "BZOF", return to parent routine

In other cases: Reset BESYNF

Execute "BZ", return to parent routine

Program

II-62 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

Timer interrupt

memory map

Table 5.6.2 I/O data memory map (timer interrupt)

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Address Comment

D3 D2 D1 D0 Name SR *1 10

78H

79H

CSDC ETI2 ETI8 ETI32

TI2 TI8 TI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

–

TI2

TI8

TI32

Yes

Unused *5

Interrupt factor flag (clock timer 2 Hz) *4

Interrupt factor flag (clock timer 8 Hz) *4

Interrupt factor flag (clock timer 32 Hz) *4

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

–

These flags indicate the status of the clock timer interrupt.

When "1" is read out: Interrupt has occurred

When "0" is read out: Interrupt has not occurred

Writing: Invalid

These flags can be reset through being read out by the

software.

Even if these flag interrupts are masked, the flags are set to "1" at

the falling edge of the corresponding signal.

Note

TI32, TI8, TI2:

Interrupt factor flags

(79H.D0–D2)

S1C62N33 TECHNICAL SOFTWARE EPSON II-63

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

Interrupt is generated at the falling edge of the frequencies

(32 Hz, 8 Hz, 2 Hz). At this time, the corresponding inter-

rupt factor flag (TI32, TI8, TI2) is set to "1".

Clock timer timing

chart

Fig. 5.6.4

Timing chart of the

clock timer

Clock timer timing chartFrequencyRegisterAddress

70H

D0 16 Hz

8 Hz

4 Hz

2 Hz

32 Hz interrupt request

8 Hz interrupt request

2 Hz interrupt request

(1) Initializing clock timer and setting interrupt mask register (2 Hz)

This program resets the clock timer after enabling the timer

2 Hz interrupt only.

DI ;

LD X,78H ;

LD MX,0100B ;

LD X,7EH ;

OR MX,1000B ;

LD X,79H ;

FAN MX,0111B ;

EI ;

Disable interrupts

Enable timer 2 Hz interrupt, and mask all others

Reset clock timer

Reset the timer interrupt factor flags

Enable interrupt

1. Write to the interrupt mask registers (ETI) only in the DI

status.

2. The generated timer interrupt factor flag is also reset

through the clock timer being reset.

Example of using

timer interrupt

Specifications

Program

Notes

II-64 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

(2) Operating interrupt mask register by separate bits

This program enables the timer 8 Hz interrupt only, and

then masks the timer 32 Hz interrupt.

DI ;

LD X,78H ;

OR MX,0010B ;

AND MX,1110B ;

EI ;

Disable interrupt

Enable timer 8 Hz interrupt

Mask timer 32 Hz interrupt

Enable interrupt

Write to the interrupt mask registers (ETI) only in the DI

status.

(3) Processing after timer interrupt generated

This program stores the register when an interrupt is gener-

ated, and when the interrupt processing is completed it

recovers the register data and returns to the main routine.

The order of priority for the interrupts is set as shown in the

table below, interrupt nesting is disabled, and processing

proceeds in descending order of priority. The interrupt

processing routine is called with CALL instruction and

processed.

Order of Priority Interrupt Factor

1 Clock timer 32 Hz

2 Clock timer 8 Hz

3 Clock timer 2 Hz

ORG 104H ;

;JP INTI ;

;

YTIB EQU ●■●■H;

;

Interrupt vector address of timer interrupt

Go to "INTI" if timer interrupt is generated

Buffer address of timer interrupt factor flags

Program

Note

Table 5.6.3

Order of priority of interrupts

in program example

Program

Specifications

S1C62N33 TECHNICAL SOFTWARE EPSON II-65

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

INTI: PUSH XH ;

PUSH XL ;

PUSH YH ;

PUSH YL ;

PUSH A ;

PUSH B ;

PUSH F ;

;LD X,79H ;

LD Y,YTIB ;

LD MY,MX ;

LD X,78H ;

AND MY,MX ;

;FAN MY,0001B ;

JP Z,INTI8 ;

CALL TI32 ;

;

INTI8: LD Y,YTIB ;

FAN MY,0010B ;

JP Z,INTI2 ;

CALL TI8 ;

;

INTI2: LD Y,YTIB ;

FAN MY,0100B ;

JP Z,INRT ;

CALL TI2 ;

;

INRT:

Store value of X register in stack

Store value of Y register in stack

Store value of A register in stack

Store value of B register in stack

Store value of F register in stack

(Reset) the timer interrupt factor flags

and store in buffer

Mask the timer interrupt factor flags

by the value of the timer interrupt mask register

If the TM32Hz interrupt factor flag is set,

and enabled

then "TI32" is executed

If the TM8Hz interrupt factor flag is set,

and enabled

then "TI8" is executed

If the TM2Hz interrupt factor flag is set,

and enabled

then "TI2" is executed

For details on "INRT", see the interrupt routine in "4.5

Example of Interrupt Vector Processing".

1. Read the interrupt factor flags (TI) only in the DI status.

2. Regardless of the setting of the interrupt mask register

(ETI), the interrupt factor flag (TI) is set to "1" at the

falling edge of the corresponding signal. Hence, the

presence of an interrupt factor is judged by the result of

ANDing the factor flag stored in the buffer and the inter-

rupt mask register.

Notes

II-66 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

(4) Clock using timer 2 Hz interrupt

This program is for a clock that uses the timer 2 Hz inter-

rupt. It judges when 1 second elapses after the 2 Hz inter-

rupt and counts the clock's seconds.

Address Data

0H Second count data (single digit seconds column, BCD)

1H Second count data (ten's seconds column, BCD)

2H Minute count data (single digit minutes column, BCD)

3H Minute count data (ten's digit minutes column, BCD)

XTISF EQU 0001B ;

YFTM EQU ◆◆◆◆H;

YCKS EQU 0H ;

;

TI2: LD X,YFTM ;

FAN MX,XBTSF ;

JP NZ,TI21 ;

;OR MX,XTISF ;

RET ;

TI21: AND MX,XTISF XOR 0FH ;

LD X,YCKS ;

CALZ CT60 ;

RET ;

JP CK ;

;

0.5 sec flag (TISF)

Address of timing flag set

Start address of second counter data (BCD)

TISF = "0" or "1"?

TISF = "0": Set TISF

Return to "INTI"

TISF = "1": Reset TISF

Increment the second counter data by 1

No carry: Return to "INTI"

Carry: Execute clock processing for

at least a minute "CK",

and return to "INTI"

Program

Table 5.6.4

Clock data

Specifications

S1C62N33 TECHNICAL SOFTWARE EPSON II-67

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

Page 0 routine "CT60"

PAGE 0 ;

;

CT60: CALZ CTUP ;

CP MX,6H ;

JP NZ,RTP0 ;

LDPX MX,0H ;

RETS ;

Page 0 routine "CTUP"

Count 1 up the BCD counter

Where is the tens' position?

Not "6": Go to RTP0

"6": Zero clear

Return to parent routine and skip

PAGE 0 ;

;

CTUP: SDF ;

ADD MX,1H ;

INC X ;

ADC MX,0H ;

RDF ;

RTP0: RET ;

Preparation: Set D flag

Increment data by 1 with BCD

Set tens' place address

Carry processing to tens' place

After process: Reset D flag

Return to parent routine

Reference

II-68 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)

(1)When the clock timer has been reset, the interrupt factor

flag (TI) may sometimes be set to "1". Consequently,

perform flag read-out (reset the flag) when necessary at

reset.

(2)The watchdog timer may be counted up at clock timer

reset.

(3)Resetting the clock timer has no effect on the stopwatch

counter, and vice versa.

(4)Writing to the interrupt mask register (ETI) can be done

only in the DI status (interrupt flag = "0"). Writing during

EI status will cause an error.

(5)Read out the interrupt flag (TI) only during the DI status

(interrupt flag = "0"). Read-out during EI status will

cause an error.

(6)Regardless of the setting of the interrupt mask register

(ETI), the interrupt factor flag (TI) is set to "1" at the

falling edge of the corresponding signal.

Programming notes

S1C62N33 TECHNICAL SOFTWARE EPSON II-69

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

Input Ports (K00–K03, K10)

The S1C62N33 Series has general-purpose input ports

consisting of a total of five bits. Four bits are reserved for

pins K00–K03 and one bit is for K10. All five bits of these

input ports have interrupt functions.

5.7

Input port memory

map

Table 5.7.1 I/O data memory map (input ports)

Address Comment

D3 D2 D1 D0 Name SR *1 10

73H

74H

K03 K02 K01 K00

DFK03 DFK02 DFK01 DFK00

R/W

K03

K02

K01

K00

High

Low

DFK03

DFK02

DFK01

DFK00

Falling

Rising

Input port

(K00–K03)

Differential register

(K00–K03)

75H

77H

EIK03 EIK02 EIK01 EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

Enable

Falling

High

Interrupt mask register

(K00–K03)

7AH

IK1 IK0 SWIT1 SWIT0

IK1

IK0

SWIT1

SWIT0

Yes

Interrupt factor flag (K10) *4

Interrupt factor flag (K00–K03) *4

Interrupt factor flag (stopwatch 1 Hz) *4

Interrupt factor flag (stopwatch 10 Hz) *4

EIK10 DFK10 K10

EIK10

DFK10

K10

Mask

Rising

Low

Interrupt mask register (K10)

Differential register (K10)

Input port (K10)

SCTRG

SIOF

SCTRG

SIOF –

Trigger

Run Serial interface clock trigger

SIOF

–

Stop

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

II-70 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

Interrupt conditions can be set with these registers.

When read-out is "1": Falling edge

When read-out is "0": Rising edge

Read-out: Available

In the K00–K03 pin group, the interrupt is enabled inside

K00–K03, but the interrupt factor flag IK0 is set to "1" when

the values of the input port data and the differential register

changes from matching to non-matching.

Even though the values of the input port data and the differential

flag IK0 will not be set to "1".

When the interrupt is enabled for K10, the interrupt factor

flag IK1 is set to "1" at the falling edge when the differential

since the SCTRG/SIOF registers are at this address, care

needs to be taken when using operational commands (AND,

OR, ADD, SUB, etc.).

These flags indicate the occurrence of input interrupt.

When "1" is read out: Interrupt has occurred

When "0" is read out: Interrupt has not occurred

Writing: Invalid

These flags are reset when the software reads them.

When "noise rejector circuit enable" is selected with the mask

option, a maximum delay of 1 ms occurs from the time the interrupt

conditions are established until the interrupt factor flag (IK) is set to

"1" (until the interrupt is actually generated).

Hence, pay attention to the timing when reading out (resetting) the

interrupt factor flag.

Note

IK0, IK1:

Interrupt factor flags

(7AH.D2 and D3)

Note

DFK00–DFK03, DFK10:

Differential registers

(74H, 77H.D1)

S1C62N33 TECHNICAL SOFTWARE EPSON II-71

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

(1) Reading to input ports

This program reads the input port (K00–K03) data to RAM,

YINB.

Data Bits

D3 D2 D1 D0

●▲●▲H K03 K02 K01 K00

Then it reads the input port (K10) data to the A register.

A register

D3 D2 D1 D0

0 EIK10 DFK10 K10

YINB EQU ●▲●▲H;

;

;LD X,73H ;

LD Y,YINB ;

LD MY,MX ;

;LD X,77H ;

LD A,MX ;

AND A,0001B ;

When input ports are changed from high to low by pull-

down resistor, the fall of the waveform is delayed on account

of the time constant of the pull-down resistance and input

gate capacitance.

Buffer address of K00–K03 input data

Store K00–K03 data in RAM, YINB

Load K10 data to A register (D0)

Reset all bits except D0 to "0"

Example of using

input ports

Specifications

Program

Note

Table 5.7.2

Correspondence of input ports

(K00–K03) and store memory

Fig. 5.7.1

Correspondence of input port

(K10) and A register

Address

II-72 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

(2) Input ports determination per bit

This is an example of whether each terminal is high or low,

using computational command on the input port (K00–K03)

registers.

ON/OFF switching of BZ output, or BZ frequency is con-

trolled according to the result of the determination.

YDTB EQU ●★●★H;

;

KYTS: LD X,73H ;

CP MX,0001B ;

JP NZ,KYTS2 ;

CALL BZ4 ;

;

KYTS2: LD Y,YDTB ;

LD A,MY ;

LD X,73H ;

XOR A,MX ;

JP Z,KYTSOF ;

CALL BZ2 ;

;

KYTSOF: LD X,73H ;

FAN MX,0001B ;

JP NZ,KYTSLP ;

CALL BZOF ;

;

KYTSLP: LD X,77H ;

FAN MX,0001B ;

JP Z,KYTSLP ;

JP KYTS ;

Data buffer address

If only K00 is high input

then sound BZ at 4 kHz

If the value of RAM, YDTB

does not match the value of K00–K03

then sound BZ at 2 kHz

If K00 is low input

then stop the buzzer

Loop: K10 pin is low or high?

Low input: Loop

High input: Returns to KYTS

Program

Specifications

S1C62N33 TECHNICAL SOFTWARE EPSON II-73

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

Specifications This program sets the mask registers and differential regis-

ters of K00–K03 and K10 as shown in the table below.

(3) Setting differential register and interrupt mask register

Table 5.7.3

Setting of interrupt

generation conditions

Program

Note Write to the interrupt mask registers (EIK) only in the DI

status (interrupt flag = "0").

DI ;

;LD X,74H ;

LDPX MX,1101B ;

LD MX,0111B ;

;LD X,77H ;

LD MX,0100B ;

;EI ;

Disable interrupts

Set the differential registers of K00–K03

to "1101", Set the interrupt mask registers of

K00–K03 to "0111"

Enable interrupt at the rising edge of K10

Enable interrupt

K10Port K03 K02 K01 K00

10111Mask Register

Generation

of Interrupt

01101Differential

Rising

edge Don't care Change from

High input

status

Change from

Low input

status

Change from

High input

status

Generation

Conditions

interrupt K0 interrupt

Interrupt

Generated

Enabled Disabled Enabled Enabled Enabled

II-74 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

(4) Processing after interrupt generated

This program stores the register data when an interrupt is

generated, recovers the register data when the interrupt

processing completes, and returns to the main routine. The

order of priority for the interrupts is set as shown in the

table below, interrupt nesting is disabled, and processing

proceeds in descending order of priority. The interrupt

processing routine is called with CALL instruction and

processed.

Order of Priority Interrupt Factor

1 Input ports K00–K03

2 Input port K10

ORG 102H ;

;JP INIK ;

;

YIKB EQU ●▲●▲H;

;

INIK: PUSH XH ;

PUSH XL ;

PUSH YH ;

PUSH YL ;

PUSH A ;

PUSH B ;

PUSH F ;

;LD X,7AH ;

LD Y,YIKB ;

LD MY,MX ;

;

Interrupt vector address of K0 and K1 interrupts

If the K0 and K1 interrupts are generated, go to "INIK"

Buffer address of input interrupt factor flags

Store the value of X register in stack

Store the value of Y register in stack

Store the value of A register in stack

Store the value of B register in stack

Store the value of the flag group in stack

(Reset) the input interrupt factor flags

and store in buffer

Table 5.7.4

Order of interrupt priority in

program example

Program

Specifications

S1C62N33 TECHNICAL SOFTWARE EPSON II-75

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

FAN MY,0100B ;

JP Z,INIK1 ;

CALL IK0 ;

;

INIK1: LD Y,YIKB ;

FAN MY,1000B ;

JP Z,INRT ;

CALL IK1 ;

;

INRT:

If the K0 interrupt factor flag is set

then execute "IK0"

If the K1 interrupt factor flag is set

then execute "IK1"

See details of "INRT" in the section on "Interrupt routine" in

"4.5 Example of Processing Interrupt Vector".

Read the interrupt factor flags (IK) only in the DI status.

(5) Evaluating input pins (K00–K03)

This routine decides which of K00–K03 are high input pins

when an interrupt is generated by high input from the input

ports (K00–K03). It then executes the corresponding sub-

routine "K0n".

If an interrupt has come from more than one pin, this is

treated as "multiple key entry", and subroutine "IK0MLT" is

executed.

Moreover, in case interrupt is inadvertently generated, the

error display process "DSER" will be executed.

Note

Specifications

II-76 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

DI ;

LD X,74H ;

LDPX MX,0000B ;

LD MX,1111B ;

EI ;

;

YINB EQU ●●H;

;

IK0: LD X,73H ;

LD Y,YINB ;

LD MY,MX ;

LD A,0H ;

;CP MY,0001B ;

JP Z,K00 ;

JP C,DSER ;

;

CP MY,0010B ;

JP Z,K01 ;

CP MY,0100B ;

JP Z,K02 ;

CP MY,1000B ;

JP Z,K03 ;

;JP IK0MLT ;

Disable interrupts

Set differential registers of K00–K03

to "0000"

Enable K00–K03 interrupt

Enable interrupts

Read data buffer address

Store K00–K03 data in RAM, YK0B

Preparation:

If only K00 is high input

then execute K00 input processing "K00", and return to "INIK"

If not high input pin

then execute the error display processing "DSER",

and return to "INIK"

If only K01 is high input

then execute K01 input processing "K01", and return to "INIK"

If only K02 is high input

then execute K02 input processing "K02", and return to "INIK"

If only K03 is high input

then execute K03 input processing "K03", and return to "INIK"

Multiple key entry: Execute multiple key entry processing "IK0MLT", and

return to "INIK"

This routine assumes that processing routines "K00"–"K03",

"IK0MLT" and "DSER" have been prepared separately.

Program

S1C62N33 TECHNICAL SOFTWARE EPSON II-77

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

DI ;

LD X,74H ;

LDPX MX,0000B ;

LD MX,1111B ;

LD X,7BH ;

LD MX,1111B ;

EI ;

;

Disable interrupts

Set the differential registers DFK00–DFK03

to "0000"

Enable K00–K03 interrupt

Make R00–R03 high output

Enable interrupts

(6) Key matrix (K00–K03 × R00–R03) processing

This is the interrupt routine "IK0" which specifies the high

input key from the key matrix shown in Figure 5.7.2 and

converts it to the key code.

Note, however, that the duplicate input process "K0MLT" will

be executed when multiple keys are simultaneously pressed,

and the no-entry process "K0NOENT" will be executed when

interrupt is inadvertently generated.

Data Bits

D3 D2 D1 D0

●●0H No.3 No.2 No.1 No.0

●●1H No.7 No.6 No.5 No.4

●●2H No.B No.A No.9 No.8

●●3H No.F No.E No.D No.C

Address

At first, the key matrix is scanned and then the status of the

16 keys is read into the buffer memory. Next, these 16 data

are converted to high input key numbers.

R03

R02

R01

R00

K03 K02 K01 K00

No.0No.1No.2No.3

No.4No.5No.6No.7

No.8No.9No.ANo.B

No.CNo.DNo.ENo.F

Address

0 H Data

Input key code (No. 0–F)

Specifications

Table 5.7.5

Contents of RAM

and input data buffer

Program

Fig. 5.7.2

Key matrix

(K00–K03 × R00–R03)

II-78 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

YK0B0: EQU ●●0H ;

;

IK0: LD X,75H ;

LD MX,0000B ;

LD X,7BH ;

LD MX,0001B ;

LD Y,YK0B0 ;

;

IK0SCLP: LD A,1H ;

IK0SCDLLP: ADD A,0FH ;

JP NZ,IK0SCDLLP ;

LD X,73H ;

LDPY MY,MX ;

LD X,7BH ;

ADD MX,MX ;

JP NZ,IK0SCLP ;

;CALL K0 ;

LD X,75H ;

LD MX,1111B ;

LD X,7BH ;

LD MX,1111B ;

RET ;

;

K0: LD A,0H ;

LD Y,YK0B0 ;

K0RDLP: CP MY,0H ;

JP K0RDCT ;

ADD A,1H ;

K0RDCT: INC Y ;

CP YL,4H ;

JP NZ,K0RDLP ;

;CP A,0H ;

JP Z,K0N0ENT ;

;

;CP A,2H ;

JP NC,K0MLT ;

;

Input data buffer start address

Mask K00–K03 interrupt

Preparation: Make only R00 high output

Store YK0B0 in Y register

Scanning loop: Delay: Preparation

Delay loop

Store K00–K03 data in the buffer

Address next buffer

Shift high output to the left

Continue until all are low

Execute key processing routine "K0"

Enable K00–K03 interrupt again

Make R00–R03 high output again

Return to "INIK"

Preparation: Clear A register

Store YK0B0 in Y register

Loop: If contents of input data buffer

are not "0",

then add 1 to A register

and address next buffer

Continue until four times

If not high input

execute non-input processing "K0NOENT"

and return to "IK0"

If multiple key entry

execute multiple key entry processing "K0MLT"

and return to "IK0"

S1C62N33 TECHNICAL SOFTWARE EPSON II-79

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

;LD A,0H ;

LD B,0H ;

LD Y,YK0B0 ;

;

K0ECLP: CP MY,0001B ;

JP Z,K0ECLP0 ;

JP C,K0ECLP4 ;

CP MY,0010B ;

JP Z,K0ECLP1 ;

CP MY,0100B ;

JP Z,KPECLP2 ;

CP MY,1000B ;

JP Z,K0ECLP3 ;

JP K0MLT ;

;

K0ECLP3: ADD A,1H ;

K0ECLP2: ADD A,1H ;

K0ECLP1: ADD A,1H ;

K0ECLP0: ADD A,B ;

;

LD M●●,A ;

K0ECLP4: ADD B,4H ;

INC Y ;

CP YL,4H ;

JP NZ,K0ECLP ;

;RET ;

Preparation: Clear A register

Clear B register

Store YK0B0 in Y register

Coding loop: Judge high input pin

K00 high input: Go to K0ECLP0

Not high input: Go to K0ECLP4

K01 high input:

Go to K0ECLP1

K02 high input:

Go to K0ECLP2

K03 high input:

Go to K0ECLP3

Multiple key entry: Execute multiple key entry

processing "K0MLT", and return to "IK0"

K03 high input: A ← 3

K02 high input: A ← 2

K01 high input: A ← 1

K00 high input: Add the value of B register

to A register

Store result in memory register M●●

Increase the value of B register by four

Address next buffer

Continue until four times

Return to "IK0"

This routine assumes that processing routines "K0NOENT"

and "K0MLT" have been prepared separately.

1. When the key scan is executed, the input status changes

and the condition is ready for an interrupt factor flag to

be set. Hence, the K00–K03 interrupt is masked in

advance.

2. When input ports are changed from high to low by pull-

down resistance, the fall of the waveform is delayed.

Hence, when fetching key scan input, set an appropriate

wait time.

Notes

II-80 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

Programming notes

When the content of the mask register is rewritten, while the port K

input is in the active status. The input interrupt factor flags are set at

➀ and ➁, ➀ being the interrupt due to the falling edge and ➁ the

interrupt due to the rising edge.

Fig. 5.7.3

Input interrupt timing

Port K input

Factor flag set Not set

➁

Factor flag set

Differential register

Mask register

Active status Active status

Rising edge interrupt

➀

Falling edge interrupt

(1)When input ports are changed from high to low by pull-

down resistor, the fall of the waveform is delayed on

account of the time constant of the pull-down resistance

and input gate capacitance. Hence, when fetching input

ports, set an appropriate wait time.

Particular care needs to be taken of the key scan during

key matrix configuration. Aim for a wait time of about 1

ms.

(2)Writing to the interrupt mask registers (EIK) can be done

only in the DI status (interrupt flag = "0"). Writing during

EI status can cause an error.

(3)When "noise rejector circuit enable" is selected with the

mask option, a maximum delay of 1 ms occurs from the

time the interrupt conditions are established until the

interrupt factor flag (IK) is set to "1" (until the interrupt is

actually generated).

Hence, pay attention to the timing when reading out

(resetting) the interrupt factor flag.

(4)Input interrupt programing related precautions

When using an input interrupt, if you rewrite the content

of the mask register, when the value of the input terminal

which becomes the interrupt input is in the active status,

the factor flag for input interrupt may be set.

S1C62N33 TECHNICAL SOFTWARE EPSON II-81

CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)

Therefore, when using the input interrupt, the active

status of the input terminal implies

input terminal = low status, when the falling edge

interrupt is effected and

input terminal = high status, when the rising edge

interrupt is effected.

When an interrupt is triggered at the falling edge of an

input terminal, a factor flag is set with the timing of ➀

shown in Figure 5.7.3. However, when clearing the

content of the mask register with the input terminal kept

in the low status and then setting it, the factor flag of the

input interrupt is again set at the timing that has been

set. Consequently, when the input terminal is in the

active status (low status), do not rewrite the mask regis-

ter (clearing, then setting the mask register), so that a

factor flag will only set at the falling edge in this case.

When clearing, then setting the mask register, set the

mask register, when the input terminal is not in the

active status (high status).

When an interrupt is triggered at the rising edge of the

input terminal, a factor flag will be set at the timing of ➁

shown in Figure 5.7.3. In this case, when the mask

registers cleared, then set, you should set the mask

In addition, when the mask register = "1" and the content

of the differential register is rewritten in the input termi-

nal active status, an input interrupt factor flag may be

set. Thus, you should rewrite the content of the differen-

tial register in the mask register = "0" status.

(5)Read out the interrupt factor flag (IK) only in the DI

status (interrupt flag = "0"). Read-out during EI status

can cause an error.

(6)Even when the values of the input data and differential

interrupt factor flag is not set to "1".

(7)Since the SCTRG/SIOF registers are at 77H, care needs

to be taken when using operational commands (AND, OR,

ADD, SUB, etc.).

II-82 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports)

I/O Ports

The S1C62N33 Series reserves eight bits for general-purpose

I/O ports. The I/O ports are the allocated into two lots of

four bits, P00–P03 and P10–P13, which can be set to either

input mode or output mode.

Table 5.8.1 I/O data memory map (I/O ports)

5.8

I/O port memory

map

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Address Comment

D3 D2 D1 D0 Name SR

7DH

7EH

P03 P02 P01 P00

SWRUN SWRST IOC0

R/W

P03

P02

P01

P00

High

Low

TMRST

SWRUN

SWRST

IOC0

Reset

Clock timer reset *5

Stopwatch counter RUN/STOP

Stopwatch counter reset *5

I/O control register 0 (P00–P03)

TMRST

W R/W W R/W

I/O port (P00–P03)

Output latch reset at time of initial reset

Reset

RUN

Reset

Output

–

STOP

–

Input

FDH

FEH

P13

OSCC IOC1

P13

P12

P11

P10

High

Low

–

CLKCHG

OSCC

IOC1

OSC3

Output

OSC1

OFF

Input

Unused *5

CPU clock switch

OSC3 oscillator ON/OFF

I/O control register 1 (P10–P13)

R/W

I/O port (P10–P13)

Output latch reset at time of initial reset

P12 P11 P10

CLKCHG

–

S1C62N33 TECHNICAL SOFTWARE EPSON II-83

CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports)

I/O port data can be read and output data can be set

through these ports.

• When writing data

When "1" is written: High level

When "0" is written: Low level

Port data can be written also in input mode.

• When reading data out

When "1" is read out: High level

When "0" is read out: Low level

The terminal voltage level of the I/O port is read out. When

the I/O port is in the input mode the voltage level being

input to the port terminal can be read out; in output mode

the output voltage level can be read.

Further, the built-in pull-down resistance goes ON during

read-out, so that the I/O port terminal is pulled down.

P00–P03, P10–P13:

I/O port data

(7DH, FDH)

(1) Reading to I/O ports (P00–P03, P10–P13), when OSC1 running

When the CPU clock is OSC1, this routine sets I/O ports

(P00–P03) to input mode, and reads the input data to A

A register

D3 D2 D1 D0

P03 P02 P01 P00

Example of program

for I/O ports

Specifications

Fig. 5.8.1

Correspondence of I/O ports

(input) and A register

II-84 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports)

Next it sets P10–P13 to input mode, and reads the input

data to RAM, YINB.

Finally it sets P00–P03 to output mode, and reads the status

of pins P00–P03 into RAM, YDTB.

Data Bits

D3 D2 D1 D0

●●H P13 P12 P11 P10

●★●★H P03 P02 P01 P00

Address

Table 5.8.2

Correspondence of I/O ports

and RAM store data

YINB EQU ●●H;

YDTB EQU ●★●★H;

;

;LD X,7EH ;

AND MX,1110B ;

LD X,7DH ;

LD A,MX ;

;LD X,0FEH ;

AND MX,1110B ;

LD X,0FDH ;

LD Y,YINB ;

LD MY,MX ;

;LD X,7EH ;

OR MX,0001B ;

LD X,7DH ;

LD Y,YDTB ;

LD MY,MX ;

Data buffer address to read

Data buffer address

Set ports P00–P03 to input mode

Load the input to P00–P03 into A register

Set ports P10–P13 to input mode

Store the input to P10–P13 into RAM, YINB

Set ports P00–P03 to output mode

Store the pin data of P00–P03 to RAM, YDTB

Program

When the I/O port is set to output mode and a low-imped-

ance load is connected to the port pins, the value of data

written to the register and data read out may differ.

Note

S1C62N33 TECHNICAL SOFTWARE EPSON II-85

CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports)

(2) Reading to I/O ports (P00–P03) when OSC3 running

When the CPU clock is OSC3, this routine sets I/O ports

(P00–P03) to input mode, and reads the input data to A

LD X,7EH ;

AND MX,1110B ;

LD X,7DH ;

LD B,9H ;

PINLP: LD A,MX ;

ADD B,0FH ;

JP NZ,PINLP ;

Set ports P00–P03 to input mode

Read: Preparation

Loop: Load to A register

Repeat 10 times

This program example assumes that the pull-down resistor

uses the built-in pull-down resistor only, and performs the

read operation ten times.

Program

Note

Specifications

P01 register

P00 register

P02 register

P03 register

P11 register

P10 register

P12 register

P13 register

P00

P01

P02

P03

P10

P11

P12

P13

D1D2D3D0D1D2D3

RAM, YDTB A register

Fig. 5.8.2

Correspondence between I/O

ports (output) and A register

and RAM

(3) Writing to I/O ports (P00–P03, P10–P13)

This routine outputs the value of A register to I/O ports

(P00–P03), then outputs the value of RAM, YDTB to P10–

P13.

Specifications

II-86 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports)

YDTB EQU ●★●★H;

;LD X,7EH ;

OR MX,0001B ;

LD X,7DH ;

LD MX,A ;

;LD X,0FEH ;

OR MX,0001B ;

LD X,7DH ;

LD Y,YDTB ;

LD MX,MY ;

Data buffer address

Set the ports P00–P03 to output mode

Output the value of A register to P00–P03

Set the ports P10–P13 to output mode

Output the value of RAM, YDTB to P10–P13

Program

Programming notes (1)When the I/O port is being read out and the pull-down is

executed only with the built-in pull-down resistor of the

I/O ports, the read-out must be repeated about ten times

when the CPU is operating with the OSC3 oscillation

circuit.

(2)When the I/O port is set to the output mode and the data

impedance load is connected and read-out performed, the

value of the register and the read-out result may differ.

S1C62N33 TECHNICAL SOFTWARE EPSON II-87

CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)

Stopwatch Counter

The S1C62N33 Series incorporates a 1/100 sec and 1/10

sec stopwatch counter. The stopwatch counter data can be

read out by the software.

Further, the stopwatch counter can generate 10 Hz (ap-

proximated 10 Hz) and 1 Hz interrupts.

The stopwatch counter can be used as a separate timer from

the clock timer. In particular, digital watch stopwatch

functions can be realized easily with software.

5.9

Stopwatch counter

memory map

Table 5.9.1 I/O data memory map (stopwatch counter)

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Address Comment

D3 D2 D1 D0 Name SR

71H

72H

SWL3 SWL2 SWL1 SWL0

SWH3 SWH2 SWH1 SWH0

SWL3

SWL2

SWL1

SWL0

MSB

Stopwatch counter

1/100 sec (BCD)

LSB

SWH3

SWH2

SWH1

SWH0

MSB

Stopwatch counter

1/10 sec (BCD)

LSB

7EH

SWRUN SWRST IOC0 TMRST

SWRUN

SWRST

IOC0

Reset

Clock timer reset *5

Stopwatch counter RUN/STOP

Stopwatch counter reset *5

I/O control register 0 (P00–P03)

TMRST

W R/W W R/W

Reset

RUN

Reset

Output

–

STOP

–

Input

II-88 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)

This bit resets the stopwatch counter.

When "1" is written: Stopwatch counter reset

When "0" is written: No operation

Read-out: Always "0"

(1) Resetting, starting and stopping the stopwatch counter

Controlling procedure for the initial start, stop, start, and

reset of the stopwatch counter is sequentially indicated.

LD X,7EH ;

OR MX,0110B ;

;LD X,7EH ;

OR MX,0010B ;

;LD X,7EH ;

AND MX,1011B ;

;LD X,7EH ;

OR MX,0100B ;

Initial start the stopwatch counter

Reset the stopwatch counter

Stop the stopwatch counter

Restart the stopwatch counter

1. Resetting the stopwatch counter does not affect the clock

timer.

2. When the stopwatch counter is reset in RUN status,

operation restarts immediately. Also, in STOP status the

reset data is maintained.

3. In STOP status, the counter data is maintained until

reset or next RUN status occurs. Also, when STOP status

changes to RUN status, the data that was maintained can

be used for resuming the count.

Example of program

for stopwatch coun-

ter

Specifications

Program

Notes

SWRST:

Stopwatch counter reset

(7EH.D1)

S1C62N33 TECHNICAL SOFTWARE EPSON II-89

CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)

(2) Reading to the stopwatch counter

This program reads the stopwatch counter's 1/100 sec data

to A register and the 1/10 sec data to B register.

A register B register

D3 D2 D1 D0 D3 D2 D1 D0

SWL3 SWL2 SWL1 SWL0 SWH3 SWH2 SWH1 SWH0

LD X,71H ;

LD Y,7EH ;

AND MY,1011B ;

;LDPX A,MX ;

LD B,MX ;

;OR MY,0100B ;

Preparation: Store SWL address in X register

Stop the stopwatch counter

Load SWL data into A register

Load SWH data into B register

Restart the stopwatch counter

To prevent erroneous reading during carry from the

stopwatch counter's low order column (SWL) to the high

order column (SWH), the stopwatch counter is stopped

during read.

The duration of the stop status must be within 976 µs (256

Hz 1/4 cycle).

Fig. 5.9.1

Correspondence between

stopwatch counter and

general-purpose register

Program

Note

Specifications

II-90 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)

Table 5.9.2 I/O data memory map (stopwatch interrupt)

Stopwatch interrupt

memory map

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

These flags indicate the status of the stopwatch counter

interrupt.

When "1" is read out: Interrupt has occurred

When "0" is read out: Interrupt has not occurred

Writing: Invalid

These flags are reset when read out by the software.

Regardless of the interrupt mask register setting, these flags are

set to "1" by overflow of the corresponding counter.

SWIT0, SWIT1:

Interrupt factor flags

(7AH.D0 and D1)

Note

Address Comment

D3 D2 D1 D0 Name SR *1 10

76H

HVLD SVDDT

SVDON

EISWIT1 EISWIT0

R/W

HVLD

EISWIT1

EISWIT0

Enable

Mask

SVD evaluation data (at read-out)

SVD ON/OFF (at writing)

Interrupt mask register

(stopwatch 1 Hz)

Interrupt mask register

(stopwatch 10 Hz)

R/W SVDDT

SVDON 0

Heavy

load Normal

Low voltage

Normal

OFF

Heavy load protection mode register

7AH

IK1 IK0 SWIT1 SWIT0

IK1

IK0

SWIT1

SWIT0

Yes

Interrupt factor flag (K10) *4

Interrupt factor flag (K00–K03) *4

Interrupt factor flag (stopwatch 1 Hz) *4

Interrupt factor flag (stopwatch 10 Hz) *4

S1C62N33 TECHNICAL SOFTWARE EPSON II-91

CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)

Stopwatch counter

timing chart

Fig. 5.9.2

Timing chart for

stopwatch counter

Interrupts are generated by the overflow of their respective

counters ("9" changing to "0"). At this time the correspond-

ing interrupt factor flags (SWIT0, SWIT1) are set to "1".

Address

Stopwatch counter (SWL) timing chart

Stopwatch counter (SWH) timing chart

10 Hz interrupt request

1 Hz interrupt request

72H

(1/10 sec BCD)

71H

(1/100 sec BCD)

II-92 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)

Example of program

for stopwatch inter-

rupt

(1) Combining interrupt factor flag and stopwatch counter

This program uses the generation of the stopwatch 1 Hz

interrupt factor flag to execute timer display from the 1/100

second to the 10 minute columns.

Data Bits

D3 D2 D1 D0

▲▲0H SWL3 SWL2 SWL1 SWL0

▲▲1H SWH3 SWH2 SWH1 SWH0

Address Data

▲▲2H Single digit seconds column (BCD)

▲▲3H Ten's digit seconds column (BCD)

▲▲4H Single digit minutes column (BCD)

▲▲5H Ten's digit minutes column (BCD)

Stores SWIT in the memory register address M and creates

data greater than a second digit. Through this, simultane-

ous display of 1/100 second and 1/10 second stopwatch

data, and second/minute data will be possible.

Data Bits

D3 D2 D1 D0

0H IK1 IK0 SWIT1 SWIT0

Address

YSITB EQU 0 H;

YSWLB EQU ▲▲0H ;

;

;DI ;

LD X,7EH ;

OR MX,0010B ;

;

SWLP: LD X,7AH ;

LD Y,7EH ;

SWT interrupt factor flag buffer address

Stopwatch counter low order data buffer address

Disable interrupts

Initial start stopwatch counter

Preparation: Store interrupt factor flag address in the X register

Stop the stopwatch counter

Specifications

Table 5.9.3

Correspondence between

stopwatch counter and store

data

Table 5.9.4

Timer data by "SWTM"

Program

Table 5.9.5

Data of memory register

S1C62N33 TECHNICAL SOFTWARE EPSON II-93

CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)

AND MY,1011B ;

LD A,MX ;

LD M ,A ;

LD X,71H ;

LDPX A,MX ;

LD B,MX ;

OR MY,0100B ;

LD X,YSWLB ;

LDPX MX,A ;

LD MX,B ;

;LD X,YSITB ;

FAN MX,0010B ;

JP Z,SWDS ;

CALL SWTM ;

;

SWDS: CALL DSSW ;

JP SWLP ;

Store stopwatch interrupt factor flags

in the memory register M

Load SWL data to A register

Load SWH data to B register

Restart the stopwatch counter

Store the value of the A register in RAM, YSWLB

Store the value of the B register in RAM, YSWLB+1

If the ST1Hz interrupt factor flag is set

then execute stopwatch timer "SWTM"

Executes the stopwatch display routine "DSSW"

Back to SWLP

1. Regardless of the setting of the mask register (EISWIT),

the interrupt factor flag (SWIT) is set to "1" by overflow of

the counter. Therefore, "interrupt generation" is not

used.

Nevertheless, the factor flag reset is executed, so the DI

status must be in effect.

2. The stopwatch counter is stopped when being read to, so

as to prevent an error occurring when the counter is

performing carry from the low order column (SWL) to the

high order column (SWH).

Stopwatch timer "SWTM"

SWTM: LD X,YSWL+2 ;

CALZ CT60 ;

RET ;

CALZ CT60 ;

RET ;

;

Increment the seconds by 1

No carry up to minutes column: Return to parent routine

Carry to higher column: Increment the minutes by 1

No carry up to hours column: Returns to parent routine

Carry to higher column: No carry up to hours column,

return to parent routine

* For details about "CT60", see page 63, "Example of using

timer interrupt".

Notes

Reference

II-94 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)

(2) Setting stopwatch interrupts

In the interrupt disabled status, this program enables

stopwatch 1 Hz interrupt only, and then enables interrupts.

DI ;

LD X,76H ;

LD MX,0010B ;

EI ;

Disable interrupts

Enable stopwatch 1 Hz interrupt

and mask 10 Hz interrupt

Enable interrupts

1. Write to the interrupt mask registers (EISWIT) only in the

DI status.

2. This program example avoids using arithmetic instruc-

tions to write to the interrupt mask flag (EISWIT), and

assumes that SVDON is fixed at "0".

(3) Processing after interrupt is generated

This routine stores the register data when an interrupt

occurs, recovers the register data when the interrupt proc-

essing completes, and returns to the main routine. The

order of priority for setting the interrupts is shown in the

table below. Nesting of interrupts cannot be done. Process-

ing proceeds in descending order of priority. Further, the

interrupt processing routine is called with CALL instruction

and processed.

Order of Priority Interrupt Factor

1 Stopwatch 10 Hz

2 Stopwatch 1 Hz

Program

Notes

Table 5.9.6

Order of priority in program

example

Specifications

S1C62N33 TECHNICAL SOFTWARE EPSON II-95

CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)

ORG 108H ;

;JP INST ;

;

YSITB EQU ●▲●▲H;

;

INST: PUSH XH ;

PUSH XL ;

PUSH YH ;

PUSH YL ;

PUSH A ;

PUSH B ;

PUSH F ;

;LD X,7AH ;

LD Y,YSITB ;

LD MY,MX ;

LD X,76H ;

AND MY,MX ;

;FAN MY,0001B ;

JP Z,INSIT1 ;

CALL SIT0 ;

;

INSIT1: FAN MY,0010B ;

JP Z,INRT ;

CALL SIT1 ;

;

INRT:

Vector address of stopwatch interrupts

If SWT interrupts occur, go to "INST"

Buffer address of stopwatch interrupt factor flags

Store value of X register in stack

Store value of Y register in stack

Store value of A register in stack

Store value of B register in stack

Store value of flag group in stack

(Reset and) store

stopwatch interrupt factor flags

in the buffer

Mask the stopwatch interrupt factor flags

by value of stopwatch interrupt mask register

If the ST10Hz interrupt factor flag is set

and enabled

then execute "SIT0"

If the ST1Hz interrupt factor flag is set

and enabled

then execute "SIT1"

For details of "INRT", see "4.5 Example of Interrupt Vector

Processing".

1. Read the interrupt factor flags (SWIT) only in the DI

status.

2. Regardless of the setting of the mask register (EISWIT),

the interrupt factor flag (SWIT) is set to "1" when the

corresponding counter overflows. Therefore, the presence

of each interrupt factor is judged according to the result

of ANDing the factor flag stored in the buffer with the

mask register.

Program

Notes

II-96 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)

(1)Correct read-out is impossible when there is a carry from

the low order bit (SWL) to the high order bit (SWH).

Hence, when reading out the counter data in the RUN

status, the counter must first be stopped, and then the

RUN status returned again.

Also, the duration of the above STOP status must be

within 976 µs (256 Hz 1/4 cycle).

(2)Resetting the clock timer has no effect on the stopwatch

counter, and vice versa.

(3)Writing to the interrupt mask registers (EISWIT) can be

done only in the DI status (interrupt flag = "0"). Writing

during EI status will cause an error.

Also, when using arithmetic instructions (AND, OR, ADD,

SUB, etc.), pay attention to the control of SVD.

(4)Read-out of the interrupt factor flag (SWIT) must be done

only in the DI status (interrupt flag = "0"). Read-out

during EI status will cause an error.

(5)Regardless of the setting of the mask register (EISWIT),

the interrupt factor flag (SWIT) is set to "1" when the

corresponding counter overflows.

Programming notes

S1C62N33 TECHNICAL SOFTWARE EPSON II-97

CHAPTER 5: PERIPHERAL CIRCUITS (Event Counter)

Event Counter

The S1C62N33 Series houses an event counter that counts

the clock signals input from outside.

The event counter is configured of an eight-bit binary coun-

ter (up counter). The counter data can be read out by

software.

5.10

Event counter

memory map

Table 5.10 I/O data memory map (event counter)

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Address Comment

D3 D2 D1 D0 Name SR

F8H

F9H

EV03 EV02 EV01 EV00

EV06 EV05 EV04

EV03

EV02

EV01

EV00

EV07

EV06

EV05

EV04

EV07

Event counter

low order (EV00–EV03)

Event counter

high order (EV04–EV07)

FCH

EVRUN EVRST

–

EVRUN

–

EVRST

Reset

RUN

Reset

Unused *5

Event counter RUN/STOP

Unused *5

Event counter reset *5

R/W W

STOP

–

––

II-98 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Event Counter)

This it the register for resetting the event counter.

When "1" is written: Event counter reset

When "0" is written: No operation

Read-out: Always "0"

Example of program

for event counter

(1) Resetting, starting, and stopping the event counter

Controlling procedure for the initial start, stop, start, and

reset of the event counter is sequentially indicated.

LD X,0FCH ;

LD MX,0101B ;

;LD X,0FCH ;

LD MX,0000B ;

;LD X,0FCH ;

LD MX,0100B ;

;LD X,0FCH ;

LD MX,0001B ;

Initial start event counter

Stop event counter

Start event counter

Reset event counter

Specifications

Program

EVRST:

Event counter reset

(FCH.D0)

S1C62N33 TECHNICAL SOFTWARE EPSON II-99

CHAPTER 5: PERIPHERAL CIRCUITS (Event Counter)

LD X,0F8H ;

LD Y,0F9H ;

LD B,MY ;

LD A,MX ;

CP MY,B ;

JP Z,EV●●●● ;

LD A,MX ;

LD B,MY ;

;

EV●●●●:. . .

(2) Reading event counter

This program reads the four high order bits of the event

counter to B register, and the four low order bits to A regis-

ter.

A register B register

D3 D2 D1 D0 D3 D2 D1 D0

EV03 EV02 EV01 EV00 EV07 EV06 EV05 EV04

First reading: Preparation

Load EV04–EV07 data to B register

Load EV00–EV03 data to A register

If there is a carry to EV04–EV07

Redo read: EV00–EV03 data

EV04–EV07 data

To prevent erroneous reading when there is a carry from the

event counter's low order data (EV00–EV03) to the high

order data (EV04–EV07), the counter data is read out mul-

tiple times and compared.

Fig. 5.10

Correspondence between

event counter and general-

purpose register

Program

Note

Programming note

Specifications

To prevent erroneous reading of the event counter data, read

out the counter data multiple times for comparison, and use

the matching data for the result.

II-100 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Analog Comparator)

Analog Comparator

The S1C62N33 Series incorporates an MOS input analog

comparator. This analog comparator, which has two differ-

ential input terminals (inverted input terminal AMPM,

noninverted input terminal AMPP), can be used for general

purposes.

To keep current consumption low, the analog comparator

circuit can be switched ON and OFF by the software.

Table 5.11 I/O data memory map (analog comparator)

Analog comparator

memory map

5.11

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

Address Comment

D3 D2 D1 D0 Name SR *1 10

F7H

AMPDT AMPON

–

AMPDT

AMPON

0 ON OFF

Unused *5

Analog comparator data

Analog comparator ON/OFF

R/W

––

+ > - - > +

Reads out the output from the analog comparator.

When "1" is read out: AMPP (+) > AMPM (-)

When "0" is read out: AMPP (+) < AMPM (-)

AMPDT:

Analog comparator data

(F7H.D1)

Note To keep the current consumption low, set the analog com-

parator to OFF when it is not needed.

Example of program

for analog

comparator

S1C62N33 TECHNICAL SOFTWARE EPSON II-101

CHAPTER 5: PERIPHERAL CIRCUITS (Analog Comparator)

(1) Setting the analog comparator ON and OFF, and reading data

(when OSC1 is running)

With OSC1 as the CPU clock, this program sets the AMP

circuit to ON, allows a delay, reads the result into A register,

and sets the circuit to OFF.

LD X,0F7H ;

LD MX,0001B ;

LD A,0FH ;

AMDLLP: ADD A,0FH ;

JP NZ,AMDLLP ;

LD A,MX ;

LD MX,1110B ;

AMP circuit ON

Delay: Preparation

Delay loop

Load the result to A register

AMP circuit OFF

The delay is made to allow the output to stabilize.

Specifications

Program

Note

(2) Setting the analog comparator ON and OFF, and reading data

(when OSC3 is running)

With OSC3 as the CPU clock, this program sets the AMP

circuit to ON, allows a delay, reads the result into A register,

and sets the circuit to OFF.

LD X,0F7H ;

LD MX,0001B ;

LD Y,54H ;

AMDLLP: ADD Y,0FH ;

JP NZ,AMDLLP ;

LD A,MX ;

AND MX,1110B ;

AMP circuit ON

Delay: Preparation

Delay loop

Load the result to A register

AMP circuit OFF

The delay is made to allow the output to stabilize.

(1)To keep the current consumption low, set the analog

comparator to OFF when it is not needed.

(2)After AMPON is set to "1", allow a wait of at least 3 ms for

the analog comparator's operation to stabilize before

reading out the analog comparator's output data AMPDT.

Program

Note

Specifications

Programming notes

II-102 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)

5.12 Serial Interface (SIN, SOUT, SCLK, SIOF)

Serial interface

memory map

Table 5.12.1 I/O data memory map (serial interface)

Address Comment

D3 D2 D1 D0 Name SR

F0H

F1H

F2H

F3H

77H

EIK10 DFK10 K10

R/W EIK10

DFK10

K10

Interrupt mask register (K10)

Input comparison register (K10)

Input port (K10)

SCTRG

SIOF

SD3 SD2 SD1 SD0

SD7 SD6 SD5 SD4

SCS1 SCS0 SE2 EISIO

–– –ISIO

R/W

SD3

SD2

SD1

SD0

Serial interface data regsiter

Low order (SD0–SD3)

SD7

SD6

SD5

SD4

Serial interface data regsiter

High order (SD4–SD7)

SCS1

SCS0

SE2

EISIO

–

ISIO 0 Yes No

Clock mode selection register

(SCS0, SCS1)

Clock edge selection register

Interrupt mask register (serial interface)

Unused *5

Interrupt factor flag (serial interface) *4

SCTRG

SIOF –

0Trigger

RUN

Serial interface clock trigger

SIOF

–

STOP

Rising

Enable

Falling

Mask

Enable

Falling

High

Mask

Rising

Low

*1 Initial value following initial reset *5 Always "0" when being read

*2 Not set in the circuit *6 Refer to main manual

*3 Undefined *7 Page switching in I/O memory is

*4 Reset (0) immediately after being read not necessary

S1C62N33 TECHNICAL SOFTWARE EPSON II-103

CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)

SD0–SD3, SD4–SD7:

Serial interface data

registers

(F0H, F1H)

These registers are used for writing and reading serial data.

• When writing data

When "1" is written: High level

When "0" is written: Low level

These registers write serial data to be output from the

SOUT pin. The serially converted data is output from the

SOUT pin as high (VDD) when the bit is set to "1" and as

low (VSS) when the bit is set to "0".

• When reading data

When "1" is read out: High level

When "0" is read out: Low level

Input serial data is read out from the SIN pin.

These registers are loaded with data that has been paral-

lel converted so that the high (VDD) level bit input from

the SIN pin is "1", and the low (VSS) bit is "0".

Perform data reading only while serial interface is halted

(i.e., the synchronous clock is neither being input or

output).

Data is undefined in this register at initial reset.

SCS1, SCS0:

Clock mode selection

(F2H.D3 and D2)

The synchronous clock (SCLK) of the serial interface can be

selected with these registers.

The synchronous clock (SCLK) can be selected from among

the four types listed above, namely from three types of

internal clock and one external clock.

At initial reset, the external clock is selected.

Table 5.12.2

Synchronous clock selection

SCS1

SCS0

Mode

Master mode

Slave mode

Synchronous Clock

CLK

CLK/2

CLK/4

External clock

CLK: system clock

II-104 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)

SE2:

Clock edge selection

(F2H.D1)

Timing for reading in the serial data input from the SIN pin

can be selected with these registers.

When "1" is written: SCLK rising edge

When "0" is written: SCLK falling edge

Read-out: Valid

These registers enable selection of whether to perform

reading to the serial input data register (SD0–SD7) at the

SCLK signal's rising edge (when "1" is written) or falling edge

(when "0" is written).

Pay attention if the synchronous clock goes into reverse

phase (SCLK→SCLK) through the mask option.

SCLK rising = SCLK falling, SCLK falling = SCLK rising

When the internal clock is selected as the synchronous

clock (SCLK), a hazard occurs in the synchronous clock

(SCLK) when data is written to register SE2.

The timing for reading in the input data can be selected, but

the output timing for the output data is fixed to the SCLK

rising edge.

At initial reset, SCLK falling (SE2 = "0") is selected.

EISIO:

Interrupt mask register

(F2H.D0)

The interrupt mask from the serial interface can be set with

this register.

When "1" is written: Enabled

When "0" is written: Masked

Read-out: Valid

At initial reset, the mask (EISIO = "0") is selected.

S1C62N33 TECHNICAL SOFTWARE EPSON II-105

CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)

ISIO:

Interrupt factor flag

(F3H.D0)

This flag indicates the status of the interrupt from the serial

interface.

When "1" is read out: Interrupt has occurred

When "0" is read out: Interrupt has not occurred

Writing: Invalid

By reading out this interrupt factor flag, the software can

judge whether an interrupt from the serial interface has

occurred. The interrupt factor flag is reset when it has been

read out. Note, however, that even if the interrupt is

masked, this flag will be set to "1" after the 8 bits data

input/output.

The flag can be read out only when in the DI status

(interrupt flag = "0").

At initial reset, this flag is set to "0".

SCTRG:

Clock trigger

(77H.D3)

This is the trigger for starting input or output of the syn-

chronous clock (SCLK).

When "1" is written: Trigger input

When "0" is written: No operation

Read-out: Always "0"

When this trigger is supplied to the serial interface activat-

ing circuit, the synchronous clock (SCLK) input/output is

started.

As a trigger condition, it is required that data writing or

reading on data registers SD0–SD7 be performed prior to

writing "1" to SCTRG. (The internal circuit of the serial

interface is initiated through data writing/reading on data

registers SD0–SD7.)

Whenever the serial interface is in the RUN status, apply

this trigger input once only. Refrain from performing trigger

input multiple times, as this leads to malfunctioning.

II-106 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)

Further, if the synchronous clock (SCLK) is the external

clock, start the external clock input after the trigger input.

SCTRG resides in the same bit at the same address as SIOF,

and one or the other is selected by write or read operation.

When writing a "1" to SCTRG use the OR command, and

when writing a "0" use the AND command. No other com-

mands should be used for this purpose.

Indicates the running status of the serial interface.

When "1" is read out: RUN status

When "0" is read out: STOP status

Writing: Invalid

The RUN status is indicated from the end of writing "1" to

SCTRG through to the end of serial data input/output.

SIOF:

Special output port data

(77H.D3)

Example of program

for serial interface

(1) Fetching data used by the internal clock

Specifications This program outputs to the outside a clock having the

same frequency as the CPU system clock, and takes serial

data into the general registers (A, B). Figure 5.12.1 shows

an example of data being taken in when the mask option

has been used to select SCLK = positive logic, permutation =

MSB first.

Fig. 5.12.1

Example of fetching serial

interface data

SCLK

SIN

(SE2=0) B register

1D2

0D1

1D0

0D3

0D2

1D1

0D0

A register

S1C62N33 TECHNICAL SOFTWARE EPSON II-107

CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)

ZK10 EQU 077H

ZR1 EQU 077H

ZSDL EQU 0F0H

ZSDH EQU 0F1H

ZSC EQU 0F2H

XSCTRG EQU 1000B

XSIOF EQU 1000B

XSCS EQU 1100B

;LD X,ZSC ;Select SCS address by X register

AND MX,XSCS XOR 0FH ;Set internal clock mode

; ( CLK/1 )

;LD X,ZSDH ;Select SD47 address by X register

LD A,MX ;Initialize circuit

;LD X,ZK10 ;Select SCTRG address by X register

OR MX,XSCTRG ;Shot SCTRG

;LD X,ZR1 ;Select SIOF address by X register

WAIT FAN MX,XSIOF ;Check SIO status

JP NZ,WAIT ;If SIO running then loop

;LD X,ZSDL ;Select SD03 address by X register

LDPX A,MX ;Read SD0–SD3 data to A register

LD B,MX ;Read SD4–SD7 data to B register

Program

II-108 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)

(2) Output of data used by the external clock

This program synchronizes SCLK with the external clock it

is assigned to, and sends the contents of the general

registers (A, B) to the outside. Figure 5.12.2 shows an

output example when the mask option has been used to

select SCLK = positive logic, permutation = MSB first.

Specifications

Fig. 5.12.2

Example of output of serial

interface data

ZK10 EQU 077H

ZSDL EQU 0F0H

ZSC EQU 0F2H

XSCTRG EQU 1000B

XSCS EQU 1100B

;LD X,ZSC ;Select SCS address by X register

OR MX,XSCS ;Set external clock mode

;LD X,ZSDL ;Select SD03 address by X register

LDPX MX,A ;Write A register to SD0–SD3

LD MX,B ;Write B register to SD4–SD7

;LD X,ZK10 ;Select SCTRG address by X register

OR MX,XSCTRG ;Shot SCTRG

Program

SIOF

SCLK

SOUT

B register

1D2

0D1

1D0

0D3

0D2

1D1

0D0

A register

S1C62N33 TECHNICAL SOFTWARE EPSON II-109

CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)

Programming notes (1)When using the serial interface in the master mode, the

synchronous clock uses the CPU system clock. Accord-

ingly, do not change the system clock (fosc1 ↔ fosc3)

while the serial interface is operating.

(2)Perform data writing/reading to data registers SD0–SD7

only while the serial interface is halted (i.e., the synchro-

nous clock is neither being input or output).

(3)As a trigger condition, it is required that data writing or

reading on data registers SD0–SD7 be performed prior to

writing "1" to SCTRG. (The internal circuit of the serial

interface is initiated through data writing/reading on

data registers SD0–SD7.) Supply trigger only once every

time the serial interface is placed in the RUN state. More-

over, when the synchronous clock SCLK is external clock,

start to input the external clock after the trigger.

(4)If the bit data of SE2 changes while SCLK is in the master

mode, a hazard will be output to the SCLK pin. If this

poses a problem for the system, be sure to set the SCLK

to the external clock mode if the bit data of SE2 is to be

changed.

(5)Reading the interrupt factor flag (ISIO) can be done only

in the DI status (interrupt flag = "0"). Reading during EI

status (interrupt flag = "1") will cause malfunction.

(6)Writing the interrupt mask register (EISIO) can be done

only in the DI status (interrupt flag = "0"). Writing during

EI status (interrupt flag = "1") will cause malfunction.

(7)SCTRG resides in the same bit at the same address as

SIOF, and one or the other is selected by write or read

operation. When writing a "1" to SCTRG use the OR

command, and when writing a "0" use the AND com-

mand. No other commands should be used for this

purpose.

II-110 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 6: INITIAL RESET

INITIAL RESET

Initial reset is required to initialize the circuits in the

S1C62N33 Series.

Internal Status at Initial Reset

At initial reset, the CPU can be initialized in the following

ways.

CHAPTER 6

6.1

CPU Core

Name Signal Number of Bits Setting Value

Program counter step PCS 8 00H

Program counter page PCP 4 1H

New page pointer NPP 4 1H

Stack pointer SP 8 Undefined

Index register IX IX 9 Undefined

Index register IY IY 9 Undefined

General-purpose register A A 4 Undefined

General-purpose register B B 4 Undefined

Interrupt flag I 1 0

Decimal flag D 1 Undefined

Zero flag Z 1 Undefined

Carry flag C 1 Undefined

Further, data memory is initialized as below.

Peripheral Circuits

Name Number of Bits Setting Value

RAM 256 × 4 Undefined

Segment data 40 × 4 Undefined

Other peripheral circuit – *1

*1 See "3.4 I/O Memory Map".

Undefined setting values must be initialized by the program.

Table 6.1.2

Initial setting values (2)

Table 6.1.1

Initial setting values (1)

Note

S1C62N33 TECHNICAL SOFTWARE EPSON II-111

CHAPTER 6: INITIAL RESET

Example of Initialize Program

After initial reset, and the CPU and data memory are reset

as shown on the previous page, this program starts from

address 100H (reset vector).

Then the initialize program's label (INIT) is defined in the

reset vector, and the program executes the initialize opera-

tion.

ORG 100H ;

;JP INIT ;

Reset vector address

Start program

This program defines the bottom address of Stack pointer,

clears RAM (including segment data) and resets Flag group,

in that order.

Internal Circuit Setting Value

General-purpose register A 0H

Stack pointer SP 0A0H

Interrupt flag IF 0

Decimal flag DF 0

Zero flag ZF 0

Carry flag CF 0

RAM data (000H–06FH) 0H

(080H–09FH) 0H

(100H–16FH) 0H

Segment data (0C0H–0EFH) 0H

*The values for the B, X and Y registers are

undefined.

6.2

Reset vector

Specifications

Table 6.2

Result of initializing

internal circuits

II-112 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 6: INITIAL RESET

INIT: LD A,0 ;

LD XP,A ;

LD A,0AH ;

LD SPH,A ;

LD A,0H ;

LD SPL,A ;

;LD X,00H ;

CLRLP1: LDPX MX,0H ;

CP XH,7H ;

JP C,CLRLP1 ;

;LD X,80H ;

CLRLP2: LDPX MX,0H ;

CP XH,0FH ;

JP C,CLRLP2 ;

;LD A,1 ;

LD XP,A ;

LD X,00H ;

CLRLP3: LDPX MX,0H ;

CP XH,7H ;

JP C,CLRLP3 ;

;RST F,0000B ;

Page 0 selected

Set Stack pointer bottom as 0A0H

Clear RAM area 000H–06FH

Clear MX, and increment X register

Continue until X register become 70H

Clear RAM area 080H–0EFH

Clear MX, and increment X register

Continue until X register becomes F0H

Page 1 selected

Clear RAM area 100H–16FH

Clear MX, and increment X register

Continue until X register becomes 70H

Reset Flag group

Program

Note This program is the basic initialize program for the

S1C62N33 Series. When this program is executed, the

internal circuits are initialized as shown in Table 6.2. When

using the program example, be sure to add any setting items

necessary for your applications.

S1C62N33 TECHNICAL SOFTWARE EPSON II-113

CHAPTER 7: SUMMARY OF NOTES

SUMMARY OF NOTES

(1)To use a branch instruction such as "JP" to branch

outside the page of that instruction, the page to branch

to must first be set with the "PSET" instruction; then the

branch instruction can be executed. Be sure to execute

the branch instruction as the step immediately following

"PSET".

(2)Immediately after the "PSET" instruction mentioned in

above item (1), it will automatically be DI state until

execution of the branch instruction is completed.

(3)When moving from the last step of one page to the top

step of the next page, there is no need to execute branch

instructions such as "PSET" and "JP".

(4)With just the one instruction "CALZ", subroutines on

page 0 can be called from any page without using "PSET".

Programming can be done efficiently if universal subrou-

tines are located on page 0.

(5)If the "PSET" instruction is executed immediately before

"CALZ", "CALZ" will have priority and data set with

"PSET" will be ignored.

(6)The program memory can be used as a data table

through the table look-up instruction.

(1)Part of the data memory is used as stack area for subrou-

tine calls and register storage, so be careful not to overlap

the data area and stack area.

(2)Subroutine calls and interrupts take up three words of

the stack area.

(3)When addresses 40H–6FH have been allocated as seg-

ment memory by option selection, 48 words of RAM can

be used as segment area.

(4)Memory is not mounted in unused area within the mem-

ory map and in memory area not indicated in this man-

ual. For this reason, normal operation cannot be assured

for programs that have been prepared with access to

these areas.

CHAPTER 7

– Program Memory

– Data Memory

II-114 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 7: SUMMARY OF NOTES

(1)Write to the interrupt mask registers only in the DI status

(interrupt flag = "0"). Writing in the EI status can cause

an error.

(2)Even when the interrupt mask registers (ETI, EISWIT) are

set to "0", the interrupt factor flags (TI, SWIT) of the clock

timer and stopwatch counter can be set when the timing

conditions are established.

(3)When an interrupt is generated, three words of RAM are

used; also, it takes 12 cycles of the CPU system clock

until the value of the interrupt vector is set in the pro-

gram counter.

(4)When an interrupt occurs, the DI status (interrupt flag =

"0") comes into effect automatically.

(5)Read the interrupt factor flags only in the DI status

(interrupt flag = "0"). Reading out in the EI status can

cause an error.

When the watchdog timer is used for the reset function, the

software must reset the watch dog timer within 3 seconds.

In this case, timer data (WD0–WD2) cannot be used for

timer applications.

(1)It takes at least 5 ms from the time the OSC3 oscillation

circuit goes ON until the oscillation stabilizes. Conse-

quently, when switching the CPU operation clock from

OSC1 to OSC3, do this after a minimum of 5 ms have

elapsed since the OSC3 oscillation went ON.

Further, the oscillation stabilization time varies depend-

ing on the external oscillator characteristics and condi-

tions of use, so allow ample margin when setting the wait

time.

(2)When switching the clock from OSC3 to OSC1, use a

separate instruction for switching the OSC3 oscillation

OFF.

(3)To lessen current consumption, keep OSC3 oscillation

OFF except when the CPU must be run at high speed.

Also, with S1C62N33/62L33, keep OSCC fixed to "0".

– Interrupt and HALT

– OSC3

– Watchdog Timer

S1C62N33 TECHNICAL SOFTWARE EPSON II-115

CHAPTER 7: SUMMARY OF NOTES

(1)It takes 100 µs from the time the SVD circuit goes ON

until a stable result is obtained. For this reason, keep

the following software notes in mind:

➀When the CPU system clock is fosc1

1. When detection is done at HVLD

After writing "1" on HVLD, read the SVDDT after 1

instruction has passed.

2. When detection is done at SVDON

After writing "1" on SVDON, write "0" after at least

100 µs has lapsed (possible with the next instruc-

tion) and then read the SVDDT.

➁When the CPU system clock is fosc3 (in case of

S1C62A33 only)

1. When detection is done at HVLD

After writing "1" on HVLD, read the SVDDT after

0.6 sec has passed. (HVLD holds "1" for at least 0.6

sec)

2. When detection is done at SVDON

Before writing "1" on SVDON, write "1" on HVLD

first; after at least 100 µs has lapsed after writing

"1" on SVDON, write "0" on SVDON and then read

the SVDDT.

(2)To reduce current consumption, set the SVD operation to

OFF unless otherwise necessary.

(3)SVDON resides in the same bit at the same address as

SVDDT, and one or the other is selected by write or read

operation. When writing a "1" to SVDON use the OR

command, and when writing a "0" use the AND com-

mand. No other commands should be used for this pur-

pose.

(4)Select one of the following software processing to return

to the normal mode after a heavy load has been driven in

the heavy load protection mode (S1C62L33).

➀After heavy load drive is completed, return to the

normal mode after at least one second has elapsed.

➁After heavy load drive is completed, switch SVD ON

and OFF (at least 100 µs is necessary for the ON

status) and then return to the normal mode.

– SVD Circuit and Heavy

Load Protection

Functions

II-116 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 7: SUMMARY OF NOTES

(5)To reduce current consumption, be careful not to set the

heavy load protection mode with the software unless

otherwise necessary.

When BZ has been selected by the output application for pin

R13, the mask option decides whether output is controlled

by register R13, or by register R10 simultaneously with BZ.

In particular, when BZ output is under R10 control, register

R13 can be used as a 1-bit general register for read/write.

Data in this register has no affect on BZ output (output of

pin R13).

(1)When 40H–6FH is selected for the segment data memory,

the memory data and the display will not match until the

area is initialized (through, for instance, memory clear

processing by the CPU).

Initialize the segment data memory by executing initial

processing.

(2)When C0H–EFH is selected for the segment data memory,

that area becomes write-only. Consequently, data cannot

be rewritten by arithmetic operations (such as AND, OR,

ADD, SUB).

(3)Data output from segment pins selected as DC output

will be the data corresponding to the COM0 pins.

(4)When performing step adjustment with the static drive,

set the segment data so that all LCD segments are lit.

(1)When the clock timer has been reset, the interrupt factor

flag (TI) may sometimes be set to "1". Consequently,

perform flag read-out (reset the flag) when necessary at

reset.

(2)The watchdog timer may be counted up at clock timer

reset.

(3)Resetting the clock timer has no effect on the stopwatch

counter, and vice versa.

(4)Writing to the interrupt mask register (ETI) can be done

only in the DI status (interrupt flag = "0"). Writing during

EI status will cause an error.

– Output Ports

– LCD Driver

– Clock Timer

S1C62N33 TECHNICAL SOFTWARE EPSON II-117

CHAPTER 7: SUMMARY OF NOTES

(5)Read out the interrupt flag (TI) only during the DI status

(interrupt flag = "0"). Read-out during EI status will

cause an error.

(6)Regardless of the setting of the interrupt mask register

(ETI), the interrupt factor flag (TI) is set to "1" at the

falling edge of the corresponding signal.

(1)When input ports are changed from high to low by pull-

down resistor, the fall of the waveform is delayed on

account of the time constant of the pull-down resistance

and input gate capacitance. Hence, when fetching input

ports, set an appropriate wait time.

Particular care needs to be taken of the key scan during

key matrix configuration. Aim for a wait time of about 1

ms.

(2)Writing to the interrupt mask registers (EIK) can be done

only in the DI status (interrupt flag = "0"). Writing during

EI status can cause an error.

(3)When "noise rejector circuit enable" is selected with the

mask option, a maximum delay of 1 ms occurs from the

time the interrupt conditions are established until the

interrupt factor flag (IK) is set to "1" (until the interrupt is

actually generated).

Hence, pay attention to the timing when reading out

(resetting) the interrupt factor flag.

(4)Input interrupt programing related precautions

– Input Ports

When the content of the mask register is rewritten, while the port K

input is in the active status. The input interrupt factor flags are set at

➀ and ➁, ➀ being the interrupt due to the falling edge and ➁ the

interrupt due to the rising edge.

Fig. 7.1

Input interrupt timing

Port K input

Factor flag set Not set

➁

Factor flag set

Differential register

Mask register

Active status Active status

Rising edge interrupt

➀

Falling edge interrupt

II-118 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 7: SUMMARY OF NOTES

When using an input interrupt, if you rewrite the content

of the mask register, when the value of the input terminal

which becomes the interrupt input is in the active status,

the factor flag for input interrupt may be set. Therefore,

when using the input interrupt, the active status of the

input terminal implies

input terminal = low status, when the falling edge

interrupt is effected and

input terminal = high status, when the rising edge

interrupt is effected.

When an interrupt is triggered at the falling edge of an

input terminal, a factor flag is set with the timing of ➀

shown in Figure 7.1. However, when clearing the content

of the mask register with the input terminal kept in the

low status and then setting it, the factor flag of the input

interrupt is again set at the timing that has been set.

Consequently, when the input terminal is in the active

status (low status), do not rewrite the mask register

(clearing, then setting the mask register), so that a factor

flag will only set at the falling edge in this case. When

clearing, then setting the mask register, set the mask

status (high status).

When an interrupt is triggered at the rising edge of the

input terminal, a factor flag will be set at the timing of ➁

shown in Figure 7.1. In this case, when the mask regis-

ters cleared, then set, you should set the mask register,

when the input terminal is in the low status.

In addition, when the mask register = "1" and the content

of the differential register is rewritten in the input termi-

nal active status, an input interrupt factor flag may be

set. Thus, you should rewrite the content of the differen-

tial register in the mask register = "0" status.

(5)Read out the interrupt factor flag (IK) only in the DI

status (interrupt flag = "0"). Read-out during EI status

can cause an error.

(6)Even when the values of the input data and differential

interrupt factor flag is not set to "1".

S1C62N33 TECHNICAL SOFTWARE EPSON II-119

CHAPTER 7: SUMMARY OF NOTES

(1)When the I/O port is being read out and the pull-down is

executed only with the built-in pull-down resistor of the

I/O ports, the read-out must be repeated about ten times

when the CPU is operating with the OSC3 oscillation

circuit.

(2)When the I/O port is set to the output mode and the data

ter data can be read out. Because of this, if a low-imped-

ance load is connected and read-out performed, the value

of the register and the read-out result may differ.

(1)Correct read-out is impossible when there is a carry from

the low order bit (SWL) to the high order bit (SWH).

Hence, when reading out the counter data in the RUN

status, the counter must first be stopped, and then the

RUN status returned again.

Also, the duration of the above STOP status must be

within 976 µs (256 Hz 1/4 cycle).

(2)Resetting the clock timer has no effect on the stopwatch

counter, and vice versa.

(3)Writing to the interrupt mask registers (EISWIT) can be

done only in the DI status (interrupt flag = "0"). Writing

during EI status will cause an error.

Also, when using arithmetic instructions (AND, OR, ADD,

SUB, etc.), pay attention to the control of SVD.

(4)Read out of the interrupt factor flag (SWIT) must be done

only in the DI status (interrupt flag = "0"). Read-out

during EI status will cause an error.

(5)Regardless of the setting of the mask register (EISWIT),

the interrupt factor flag (SWIT) is set to "1" when the

corresponding counter overflows.

To prevent erroneous reading of the event counter data, read

out the counter data multiple times for comparison, and use

the matching data for the result.

– I/O Ports

– Stopwatch Counter

– Event Counter

II-120 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 7: SUMMARY OF NOTES

(1)To keep the current consumption low, set the analog

comparator to OFF when it is not needed.

(2)After AMPON is set to "1", allow a wait of at least 5 ms for

the analog comparator's operation to stabilize before

reading out the analog comparator's output data AMPDT.

(1)When using the serial interface in the master mode, the

synchronous clock uses the CPU system clock. Accord-

ingly, do not change the system clock (fosc1 ↔ fosc3)

while the serial interface is operating.

(2)Perform data writing/reading to data registers SD0–SD7

only while the serial interface is halted (i.e., the synchro-

nous clock is neither being input or output).

(3)As a trigger condition, it is required that data writing or

reading on data registers SD0–SD7 be performed prior to

writing "1" to SCTRG. (The internal circuit of the serial

interface is initiated through data writing/reading on

data registers SD0–SD7.) Supply trigger only once every

time the serial interface is placed in the RUN state.

Moreover, when the synchronous clock SCLK is external

clock, start to input the external clock after the trigger.

(4)If the bit data of SE2 changes while SCLK is in the mas-

ter mode, a hazard will be output to the SCLK pin. If this

poses a problem for the system, be sure to set the SCLK

to the external clock mode if the bit data of SE2 is to be

changed.

(5)Reading the interrupt factor flag (ISIO) can be done only

in the DI status (interrupt flag = "0"). Reading during EI

status (interrupt flag = "1") will cause malfunction.

(6)Writing the interrupt mask register (EISIO) can be done

only in the DI status (interrupt flag = "0"). Writing during

EI status (interrupt flag = "1") will cause malfunction.

(7)SCTRG resides in the same bit at the same address as

SIOF, and one or the other is selected by write or read

operation. When writing a "1" to SCTRG use the OR

command, and when writing a "0" use the AND com-

mand. No other commands should be used for this

purpose.

– Analog Comparator

– Serial Interface

S1C62N33 TECHNICAL SOFTWARE EPSON II-121

CHAPTER 8: CPU

CPU

The S1C62N33 Series employs the four-bit core CPU

S1C6200 for the CPU, so that register configuration, in-

structions and so forth are virtually identical to those in

other family processors using the S1C6200.

Refer to "S1C6200/6200A Core CPU Manual" for details

about the S1C6200.

S1C62N33 Restrictions

Note the following points with regard to the S1C62N33

Series:

(1)The SLEEP operation is not assumed, so that SLP in-

struction cannot be used.

(2)Because the ROM capacity is 3,072 words, bank bits are

unnecessary and PCB and NBP are not used.

(3)Since RAM is set for up to 1 page, only the subordinate 1

bit of the page section of the index register which speci-

fies address is effective. (The 3 superordinate bits are

ignored.)

Instruction Set

The S1C62N33 Series has some 108 types of instructions

including arithmetical instructions.

All instructions consist of one word (= 12 bits).

The following pages contain tables of the instruction set of

the 4-bit Core CPU, S1C6200.

CHAPTER 8

8.1

8.2

II-122 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 8: CPU

Table 8.2(a) Instruction set (1)

C, s

NC, s

Z, s

NZ, s

X, x

Y, y

XP, r

XH, r

XL, r

YP, r

YH, r

YL, r

r, XP

r, XH

r, XL

r, YP

r, YH

r, YL

XH, i

XL, i

YH, i

YL, i

PSET

JPBA

CALL

CALZ

RET

RETS

RETD

NOP5

NOP7

HALT

INC

ADC

Branch

instructions

System

control

instructions

Index

operation

instructions

Classification Operand IDZC

↑

Clock

Operation Code Flag

NBP p4, NPP p3~p0

PCB NBP, PCP NPP, PCS s7~s0

PCB NBP, PCP NPP, PCS s7~s0 if C=1

PCB NBP, PCP NPP, PCS s7~s0 if C=0

PCB NBP, PCP NPP, PCS s7~s0 if Z=1

PCB NBP, PCP NPP, PCS s7~s0 if Z=0

←

←←

←

PCB NBP, PCP NPP, PCSH B, PCSL A

M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1

SP SP-3, PCP NPP, PCS s7~s0

M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1

SP SP-3, PCP 0, PCS s7~s0

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3, PC PC+1

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3, M(X) 3~ 0, M(X+1) 7~ 4, X X+2

No operation (5 clock cycles)

No operation (7 clock cycles)

Halt (stop clock)

X X+1

Y Y+1

XH x7~x4, XL x3~x0

YH y7~y4, YL y3~y0

r XP

r XH

r XL

r YP

r YH

r YL

←←

←←←

←←← ←←←

←←←

←←← ←

←← ←← ←

←←←←

←

←←

←

←←

←

Mne-

monic Operation

XH+i3~i0+C

XL+i3~i0+C

YH+i3~i0+C

YL+i3~i0+C

↓

l llllllll

ll ll

S1C62N33 TECHNICAL SOFTWARE EPSON II-123

CHAPTER 8: CPU

Table 8.2(b) Instruction set (2)

XH, i

XL, i

YH, i

YL, i

r, i

r, q

A, Mn

B, Mn

Mn, A

Mn, B

MX, i

r, q

MY, i

r, q

MX,

F, i

LDPX

LDPY

LBPX

SET

RST

SCF

RCF

SZF

RZF

SDF

RDF

INC

DEC

PUSH

POP

Index

operation

instructions

Data

transfer

instructions

Flag

operation

instructions

Stack

operation

instructions

Classification Operand

IDZC

↑

↓

↑

↓

↑

↓

↑

↓

↑

↓

↑

↓

Clock

Operation Code Flag

XH-i3~i0

XL-i3~i0

YH-i3~i0

YL-i3~i0

r i3~i0

r q

M(n3~n0) A

M(n3~n0) B

M(X) i3~i0, X X+1

r q, X X+1

M(Y) i3~i0, Y Y+1

r q, Y Y+1

M(X) 3~ 0, M(X+1) 7~ 4, X X+2

←

←←

←

←← ←←

Mne-

monic Operation

↓

↑

↓

↑

↓

SP SP+1

SP SP-1

SP SP-1, M(SP) r

SP SP-1, M(SP) XP

SP SP-1, M(SP) XH

SP SP-1, M(SP) XL

SP SP-1, M(SP) YP

SP SP-1, M(SP) YH

SP SP-1, M(SP) YL

SP SP-1, M(SP) F

r M(SP), SP SP+1

←

M(n3~n0)

←

←←

←

F i3~i0

1 (Decimal Adjuster ON)

0 (Decimal Adjuster OFF)

1 (Enables Interrupt)

0 (Disables Interrupt)

←

←←

←

M(SP), SP SP+1

←

l llllllll l l l l

II-124 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 8: CPU

Table 8.2(c) Instruction set (3)

d3 d2, d2 d1, d1 d0, d0 C, C d3

d3 C, d2 d3, d1 d2, d0 d1, C d0

M(n3~n0) M(n3~n0)+1

M(n3~n0) M(n3~n0)-1

↓

SPH, r

SPL, r

r, SPH

r, SPL

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

MX, r

MY, r

MX, r

MY, r

POP

ADD

ADC

SUB

SBC

AND

XOR

FAN

RLC

RRC

INC

DEC

ACPX

ACPY

SCPX

SCPY

NOT

Stack

operation

instructions

Arithmetic

instructions

Classification Operand

IDZC

↑↑

↑

Clock

Operation Code Flag

F M(SP), SP SP+1

SPH

SPL

r SPH

r SPL

←

Mne-

monic Operation

↓

↑

←

↓↓

★

r r+i3~i0

r r+q

r r+i3~i0+C

r r+q+C

r r-q

r r-i3~i0-C

r r-q-C

r r i3~i0

r r q

r r i3~i0

r r q

r r i3~i0

r r q

r-i3~i0

r-q

r i3~i0

r q

M(X) M(X)+r+C, X X+1

M(Y) M(Y)+r+C, Y Y+1

M(X) M(X)-r-C, X X+1

M(Y) M(Y)-r-C, Y Y+1

r r

M(SP), SP SP+1

←

←←

←

←←← ←

←← ← ←←

←

S1C62N33 TECHNICAL SOFTWARE EPSON II-125

CHAPTER 8: CPU

Abbreviations used in the explanations have the following

meanings.

A .............. A register

B .............. B register

X .............. XHL register (low order eight bits of index register

IX)

Y .............. YHL register (low order eight bits of index

XH ........... XH register (high order four bits of XHL register)

XL ............ XL register (low order four bits of XHL register)

YH............ YH register (high order four bits of YHL register)

YL ............ YL register (low order four bits of YHL register)

XP ............ XP register (high order four bits of index

YP ............ YP register (high order four bits of index

SP ............ Stack pointer SP

SPH.......... High-order four bits of stack pointer SP

SPL .......... Low-order four bits of stack pointer SP

MX, M(X) .. Data memory whose address is specified with

index register IX

MY, M(Y)... Data memory whose address is specified with

index register IY

Mn, M(n) .. Data memory address 000H–00FH (address

specified with immediate data n of 00H–0FH)

M(SP) ....... Data memory whose address is specified with

stack pointer SP

r, q ........... Two-bit register code

r, q is two-bit immediate data; according to the

contents of these bits, they indicate registers A,

B, and MX and MY (data memory whose ad-

dresses are specified with index registers IX and

IY) rq

r1 r0 q1 q0

0000 A

0101 B

1010 MX

1111 MY

Registers specified

Symbols associated with

registers and memory

II-126 EPSON S1C62N33 TECHNICAL SOFTWARE

CHAPTER 8: CPU

Symbols associated with

program counter

Symbols associated with

flags

Associated with

immediate data

Associated with

arithmetic and other

operations

NBP..... New bank pointer

NPP ..... New page pointer

PCB..... Program counter bank

PCP ..... Program counter page

PCS..... Program counter step

PCSH .. Four high order bits of PCS

PCSL ... Four low order bits of PCS

F ......... Flag register (I, D, Z, C)

C ......... Carry flag

Z ......... Zero flag

D......... Decimal flag

I .......... Interrupt flag

↓............. Flag reset

↑............. Flag set

↕.......... Flag set or reset

p ......... Five-bit immediate data or label 00H–1FH

s.......... Eight-bit immediate data or label 00H–0FFH

l .......... Eight-bit immediate data 00H–0FFH

i .......... Four-bit immediate data 00H–0FH

+ ......... Add

- .......... Subtract

∧............. Logical AND

∨............. Logical OR

∀ ............ Exclusive-OR

★......... Add-subtract instruction for decimal operation

when the D flag is set

S1C62N33 TECHNICAL SOFTWARE EPSON II-127

APPENDIX

• Table of cross assembler pseudo-instructions

Item No. Pseudo-instruction Meaning Example of Use

1 EQU To allocate data to label ABC EQU 9

(Equation) BCD EQU ABC+1

2 ORG To define location counter ORG 100H

(Origin) ORG 256

3 SET To allocate data to label ABC SET 0001H

(Set) (data can be changed) ABC SET 0002H

4 DW To define ROM data ABC DW 'AB'

(Define word) BCD DW 0FFBH

5 PAGE To define boundary of page PAGE 1H

(Page) PAGE 11

6 SECTION To define boundary of section SECTION

(Section)

7 END To terminate assembly END

(End)

8 MACRO To define macro CHECK 1

(Macro)

9 LOCAL To make local specification of CHECK MACRO DATA

(Local) label during macro definition LOCAL LOOP

LOOP CP MX,DATA

JP NZ,LOOP

10 ENDM To end macro definition

(End Macro) ENDM

APPENDIX

II-128 EPSON S1C62N33 TECHNICAL SOFTWARE

APPENDIX

• Table of ICE commands

Assemble

Disassemble

Dump

Fill

Set

Run Mode

Trace

Break

Move

Data Set

Change CPU

Internal

Registers

#A,a

#L,a1,a2

#DP,a1,a2

#DD,a1,a2

#FP,a1,a2,d

#FD,a1,a2,d

#G,a

#TIM

#OTF

#T,a,n

#U,a,n

#BA,a

#BAR,a

#BD

#BDR

#BR

#BRR

#BM

#BMR

#BRES

#BC

#BE

#BSYN

#BT

#BRKSEL,REM

#MP,a1,a2,a3

#MD,a1,a2,a3

#SP,a

#SD,a

#DR

#SR

#DXY

#SXY

Assemble command mnemonic code and store at address "a"

Contents of addresses a1 to a2 are disassembled and displayed

Contents of program area a1 to a2 are displayed

Content of data area a1 to a2 are displayed

Data d is set in addresses a1 to a2 (program area)

Data d is set in addresses a1 to a2 (data area)

Program is executed from the "a" address

Execution time and step counter selection

On-the-fly display selection

Executes program while displaying results of step instruction

from "a" address

Displays only the final step of #T,a,n

Sets Break at program address "a"

Breakpoint is canceled

Break condition is set for data RAM

Breakpoint is canceled

Break condition is set for Evaluation Board CPU internal registers

Breakpoint is canceled

Combined break conditions set for program data RAM address

and registers

Cancel combined break conditions for program data ROM

address and registers

All break conditions canceled

Break condition displayed

Enter break enable mode

Enter break disable mode

Set break stop/trace modes

Set BA condition clear/remain modes

Contents of program area addresses a1 to a2 are moved to

addresses a3 and after

Contents of data area addresses a1 to a2 are moved to addresses

a3 and after

Data from program area address "a" are written to memory

Data from data area address "a" are written to memory

Item No. Function Command Format Outline of Operation

Display Evaluation Board CPU internal registers

Set Evaluation Board CPU internal registers

Reset Evaluation Board CPU

Display X, Y, MX and MY

Set data for X and Y display and MX, MY

S1C62N33 TECHNICAL SOFTWARE EPSON II-129

APPENDIX

History

File

Coverage

ROM Access

Terminate

ICE

Command

Display

Self

Diagnosis

#H,p1,p2

#HB

#HG

#HP

#HPS,a

#HC,S/C/E

#HA,a1,a2

#HAR,a1,a2

#HAD

#HS,a

#HSW,a

#HSR,a

#RF,file

#RFD,file

#VF,file

#VFD,file

#WF,file

#WFD,file

#CL,file

#CS,file

#CVD

#CVR

#RP

#VP

#ROM

#HELP

#CHK

Display history data for pointer 1 and pointer 2

Display upstream history data

Display 21 line history data

Display history pointer

Set history pointer

Sets up the history information acquisition before (S),

before/after (C) and after (E)

Sets up the history information acquisition from program area

a1 to a2

Sets up the prohibition of the history information acquisition

from program area a1 to a2

Indicates history acquisition program area

Retrieves and indicates the history information which executed

a program address "a"

Retrieves and indicates the history information which wrote or

read the data area address "a"

Save contents of memory to program file

Save contents of memory to data file

Load ICE set condition from file

Save ICE set condition to file

Terminate ICE and return to operating system control

Display ICE instruction

Report results of ICE self diagnostic test

Move program file to memory

Move data file to memory

Compare program file and contents of memory

Compare data file and contents of memory

Indicates coverage information

Clears coverage information

Move contents of ROM to program memory

Compare contents of ROM with contents of program memory

Set ROM type

Item No. Function Command Format Outline of Operation

means press the RETURN key.

AMERICA

EPSON ELECTRONICS AMERICA, INC.

- HEADQUARTERS -

1960 E. Grand Avenue

EI Segundo, CA 90245, U.S.A.

Phone: +1-310-955-5300 Fax: +1-310-955-5400

- SALES OFFICES -

West

150 River Oaks Parkway

San Jose, CA 95134, U.S.A.

Phone: +1-408-922-0200 Fax: +1-408-922-0238

Central

101 Virginia Street, Suite 290

Crystal Lake, IL 60014, U.S.A.

Phone: +1-815-455-7630 Fax: +1-815-455-7633

Northeast

301 Edgewater Place, Suite 120

Wakefield, MA 01880, U.S.A.

Phone: +1-781-246-3600 Fax: +1-781-246-5443

Southeast

3010 Royal Blvd. South, Suite 170

Alpharetta, GA 30005, U.S.A.

Phone: +1-877-EEA-0020 Fax: +1-770-777-2637

EUROPE

EPSON EUROPE ELECTRONICS GmbH

- HEADQUARTERS -

Riesstrasse 15

80992 Munich, GERMANY

Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110

SALES OFFICE

Altstadtstrasse 176

51379 Leverkusen, GERMANY

Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10

UK BRANCH OFFICE

Unit 2.4, Doncastle House, Doncastle Road

Bracknell, Berkshire RG12 8PE, ENGLAND

Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701

FRENCH BRANCH OFFICE

1 Avenue de l' Atlantique, LP 915 Les Conquerants

Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE

Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355

BARCELONA BRANCH OFFICE

Barcelona Design Center

Edificio Prima Sant Cugat

Avda. Alcalde Barrils num. 64-68

E-08190 Sant Cugat del Vallès, SPAIN

Phone: +34-93-544-2490 Fax: +34-93-544-2491

ASIA

EPSON (CHINA) CO., LTD.

28F, Beijing Silver Tower 2# North RD DongSanHuan

ChaoYang District, Beijing, CHINA

Phone: 64106655 Fax: 64107319

SHANGHAI BRANCH

4F, Bldg., 27, No. 69, Gui Jing Road

Caohejing, Shanghai, CHINA

Phone: 21-6485-5552 Fax: 21-6485-0775

EPSON HONG KONG LTD.

20/F., Harbour Centre, 25 Harbour Road

Wanchai, Hong Kong

Phone: +852-2585-4600 Fax: +852-2827-4346

Telex: 65542 EPSCO HX

EPSON TAIWAN TECHNOLOGY & TRADING LTD.

10F, No. 287, Nanking East Road, Sec. 3

Taipei

Phone: 02-2717-7360 Fax: 02-2712-9164

Telex: 24444 EPSONTB

HSINCHU OFFICE

13F-3, No. 295, Kuang-Fu Road, Sec. 2

HsinChu 300

Phone: 03-573-9900 Fax: 03-573-9169

EPSON SINGAPORE PTE., LTD.

No. 1 Temasek Avenue, #36-00

Millenia Tower, SINGAPORE 039192

Phone: +65-337-7911 Fax: +65-334-2716

SEIKO EPSON CORPORATION KOREA OFFICE

50F, KLI 63 Bldg., 60 Yoido-dong

Youngdeungpo-Ku, Seoul, 150-763, KOREA

Phone: 02-784-6027 Fax: 02-767-3677

SEIKO EPSON CORPORATION

ELECTRONIC DEVICES MARKETING DIVISION

Electronic Device Marketing Department

IC Marketing & Engineering Group

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624

ED International Marketing Department Europe & U.S.A.

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564

ED International Marketing Department Asia

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110

International Sales Operations

In pursuit of “Saving” Technology, Epson electronic devices.

Our lineup of semiconductors, liquid crystal displays and quartz devices

assists in creating the products of our customers’ dreams.

Epson IS energy savings.

http://www.epson.co.jp/device/

Technical Manual

S1C62N33

EPSON Electronic Devices Website

ELECTRONIC DEVICES MARKETING DIVISION

First issue January, 1992

Printed March, 2001 in Japan B