DD-42900DC-120 - Data Device Corporation (DDC)

DD-42900

DESCRIPTION

DDC's DD-42900 provides a com-

plete and flexible interface between a

microprocessor and ARINC 429 data

bus. The 42900 interfaces to a

processor through a 128 x 32 bit stat-

ic RAM as well as f our 32 x 32 receiv e

FIFO's and two 32 x 32 transmit

FIFO's.The 42900 can be easily inter-

faced to 8- or 16-bit processors via a

buffered shared RAM configuration.

The 42900 supports four ARINC 429

Receive channels (Rx0, Rx1, Rx2

and Rx3) and each receive data inde-

pendently.The recieve data rates

(high or low speed) for channel Rx0

and Rx1 can be programmed inde-

pendently from Rx2 and Rx3.The

42900 can decode and sort data

based on the ARINC 429 Label and

SDI bits via the Data Match

Processor and store it in RAM and/or

FIFO's via the Data Store Processor.

The 42900 supports two ARINC 429

Transmit channels (Tx0 and Tx1) and

can transmit data independently.The

transmit data rate can be prog rammed

independently as well.There are two

32 x 32 bit FIFO's for each of the

transmitters for sending out data.

The device has the capability of pro-

gramming three general purpose

interrupts as well as generating an

interrupt based on an error condi-

tion.The general purpose interrupts

can be programmed to trigger other

external hardware.They can either be

LEVELtriggered or PULSE tr iggered.

The features built into the DD-42900

enable the user to off-load the host

processor and use that processing

time to do other more important

duties than polling the ARINC 429

Bus.The decoding and sorting of data

allows the user to gather data much

quicker that past designs. If the user

requires a microprocessor in the

avionics box, this device will enable a

clean and quick design.

ARINC 429 Microprocessor Interface Device

FEATURES

•

Four ARINC 429 Receive

Channels

•

128 x 32 Shared RAM Interface

•

Label and Destination Decoding

and Sorting

•

Two ARINC 429 Transmit Channels

•

Two 32 x 32 Transmit FIFO's

•

Interfaces Easily to 8- or 16-Bit

Microprocessors

•

Built-in Fault Detection Circuitry

DATA ADDR

STATIC RAM

Rx RAM

CTRL

128 X 32

128 X 16

STATIC RAM

DATA ADDR

DMT RAM

CTRL

ARINC 429 ARINC 429 Rx DATA DATA DATA

DMP

DATA Rx0 FIFO

Rx1 FIFO

32 WORDS

STORE

DATA ADDR

PROCESSOR

ADDR

MATCH

PROCESSOR

DATA ADDR

ARINC

Rx LOGIC

429

WRAPAROUND

ARINC 429

RECEIVE 1

RECEIVE 0

RECEIVE 2

RECEIVE 3

ARINC 429

ARINC

Rx LOGIC

ARINC

Rx LOGIC

429

ADDR 32 WORDS

Rx2 FIFO

Rx3 FIFO

32 WORDS

CPU INTERFACE

DATA

INTERRUPT

CONTROLLER

Tx FIFO

32 WORDS

ARINC 429

Tx LOGIC

ARINC 429

TRANSMIT 0

TRANSMIT 1 Tx LOGIC 32 WORDS

CONTROL

MICROPROCESSOR

DATA

OR CPU

ADDRIRQ

416

812

WRAPAROUND

DATA

FIGURE 1. DD-42900 BLOCK DIAGRAM

This Preliminary data sheet provides detailed functional capabilities for product currently in prototype production.

These specifications are being provided to allow for electrical design, layout and operation.

ARINC 429 RECEIVERS

The DD-42900 supports four ARINC 429 inputs, designated

Receive channels 0 through 3 (Rx0, Rx1, Rx2 and Rx3). The

architecture of each of the four receiver circuits is identical and

each receive data independently. ARINC 429 data is directly

received into the DD-42900 with no additional circuitry required.

Input protection, IAW the ARINC 429 specification, is provided

as well as the voltage level translation from +5 V Bipolar nonre-

turn to zero Data to conventional +5 V logic levels used internal

to the DD-42900 device.

Receive Data Rates can be programmed for channels 0 and 1

independently of channels 2 and 3 via bits 2 and 3 of Arinc

Control Register 2. The receiver circuitry will successfully

decode an incoming ARINC 429 data stream as long as the data

rate is within ±5% of the nominal rate as determined by the Hi

Speed/Lo Speed Bit and the associated ARINC Clock input

(ARINC CLK 0 or ARINC CLK 1).The two 1 MHz ARINC clock

inputs may be tied to the 1 MHz receive clock output or may be

connected to another clock source .The ARINC CLK input should

nominally be 10 times (f or High Speed Mode) or 80 times (for lo w

speed mode) the desired ARINC Data Rate. ARINC CLK 0 is

used by channels Rx0 and Rx1 while ARINC CLK 1 is used by

channels Rx2 and Rx3.

Filtering and Sorting Rx Data: The receiver circuitry converts

the serial data stream to a 32 bit wide parallel data word.The 32

bit word is processed internally by a Data Match Processor

(DMP). It compares the incoming data to a table of data initial-

ized b y the processor which determines what incoming data is to

be saved, where it is going to be saved, and if any interrupts are

to be generated.The table of data is stored in a 128 word x 16

bit Data Match Table (DMT) RAM.When a match between the

received ARINC 429 data and the criteria stored in a DMT entr y

is f ound, the received data, the storage address and modes , and

interrupt parameters are passed to the Data Store Processor

(DSP).The storage address in the Receive RAM is the address

of the first matching DMT entr y minus 200 hex.

There are three requirements to matching incoming ARINC-429

data to each DMT entr y.

1) System Address Label:Bits 0-7 of the DMT are compared

to the System Address Label (SAL) of the incoming ARINC

429 data word.If the DMT SAL entr y is zero then the SAL of

the incoming data word is ignored (or considered a match).

2) Source/Destination Bits:Bits 8 and 9 of each DMT entry

are compared to the Source/Destination bits of the incoming

ARINC-429 data word.If these bits match or if Bit 10 of the

DMT entr y is set to a one then the S/D bit comparison is

considered a match.It is also possible through the DMP

Control Register 1 to enable “All Call Mode”as defined in

ARINC 429 specification.When enabled for a particular

receive channel, the S/D bits will be considered a match

when the incoming ARINC 429 data contains a 00 in its S/D

bit pair.

3) Receive Channel Number:Bits 12 and 13 of each DMT

entr y are compared to the number of the channel which

received the ARINC 429 data.

If and when all of the above conditions are satisfied then a Data

Match has occurred and the data will be stored in a RAM loca-

tion whose address equals the matching DMT entry minus 200

hex.

Bit 11 of each DMT entry, when set, will cause the incoming

ARINC 429 data to stored in the corresponding receive channel

FIFO (as well as the Rx RAM) when the data match conditions

are met.

Bits 14 and 15 of each DMT entry provide the ability to cause

one of three general purpose interr upts upon a data match con-

dition.If set to “00”then no interrupt will occur upon a data match

condition.(more information on interrupts is descr ibed later)

ARINC-429 TRANSMITTER(S)

The DD-42900 supports two ARINC 429 transmitters. Each

transmitter channel transmits data independently and are desig-

nated Tx0 and Tx1.The transmit output of the DD-42900 is a TTL

encoded digital data stream which can be connected directly to

DDC’s DD-03182 ARINC 429 line dr iver.

Transmit data rates can be programmed for channels 0 and 1

independently. The transmit data rate is determined by the Hi

Speed/Lo Speed Bit for each of the Tx channels in Arinc Control

0 or ARINC CLK 1).The two 1 MHz ARINC clock inputs may be

tied to the 1 MHz clock output or may be connected to another

clock source to achieve transmit data rates other than 100 kHz

or 12.5 kHz.The transmit clock input should be 10 times (f or High

Speed Mode) or 80 times (for low speed mode) the desired

ARINC transmit data rate.

Transmit FIFOs: Each transmitter channel is provided with an

output FIFO which is 32 words deep by 32 bits wide.When wr it-

ing data to the Tx FIFO the associated Disable Txn bit in Arinc

Control Register 1 can be set to a logic zero until the FIFO is

loaded with the desired data. Upon setting the Disable Txn low

the transmit channel will send the 32 bit message words with

appropriate interword gaps on the ARINC 429 output. A status

bit indicating that the FIFO is empty is supplied for each trans-

mitter in the Arinc Status Register.

Wraparound testing can be performed from Tx0 to Rx0 and Rx1

and from Tx1 to Rx2 and Rx3.Wraparound testing is enabled by

setting the appropriate bits in Ar inc Control Register 2.The par-

ity of the transmitted word can be altered to even parity (instead

of the normally odd parity) by setting the associated Txn Parity

bit in the Arinc Control Register 2 which is useful to verify prop-

er operation of the parity check circuitry each of the receive cir-

cuits during wraparound test mode.

PROCESSOR INTERFACE

The processor interface allows for the use of either a 8- or 16-bit

data bus. Also Intel or Motorola control signal formats can be

used.

INTERRUPT OPERATIONAL MODES

The DD-42900 provides 4 interrupt outputs.Three of these inter-

rupt outputs (IRQ1, IRQ2, and IRQ3) are general pur pose pro-

grammable interrupts. The fourth interrupt is an Error interrupt

output which is specifically used to provide indications of various

error conditions and is nonmaskable.

ERROR INTERRUPT OPERATION

When an error condition occurs the ERROR* output pin goes lo w

to indicate the presence of an error. The error pin will go high

again when the Error Status Register is clear.Each of these bits

is cleared by either reading the Error Status Register or remov-

ing the error condition.

GENERAL PURPOSE INTERRUPTS

The three general purpose interrupt outputs can be used for m ul-

tilevel interrupts or to trigger other external hardware on var ious

conditions. Each condition can be mapped to any one of the

three general purpose interrupts or disabled (by mapping to

IRQ0 which does not exist). Each interrupt output can be pro-

grammed to be either a LEVEL interrupt or PULSE interrupt via

IRQ Control Register 2. When programmed for pulse interrupt

mode the associated interupt pin will go low for 1 µS and return

high again. When programmed for LEVEL interrupt mode the

interrupt will remain until the associated IRQ Status Register is

read thus clearing the associated bits in each interr upt register.

Each of the individual interrupt registers can be masked by set-

ting their corresponding bit in IRQ Control Register 1.It should be

noted that the masking function only pre v ents the associated IRQ

pin from becoming active.When the mask bit is cleared an inter-

rupt can occurr in LEVEL IRQ mode if one or more interr upt con-

ditions occurred during the time when the mask was set. If the

user needs to ensure the interrupt will not occur upon clearing the

mask bit the CPU should be programmed to read the associated

interrupt status register immediately prior to clearing the IRQ

mask bit.

Zero W ait Mode Operation:When Zero Wait Mode is enabled b y

grounding the ZER O W AIT pin the host microprocessor may read

data from the DD-42900 shared memory resources (DMT and Rx

RAM) without using the READY or DTACK signals to insert wait

states into the microprocessor cycle.This is accomplished by an

additional “dummy read”of the desired address.This dummy read

causes the DD-42900 to f etch the data from the source and place

it in a latch.The data can then be read from the latch (word by

word or byte by byte) by reading the same addresses.Thus for a

32 bit read in 8 bit mode the microprocessor would perf orm a total

of 5 read operations. The first read would be the dummy read,

subsequent reads would transfer the data.

FIGURE 2A. DD-03282 DIP MECHANICAL OUTLINE

±0.025

2.050 

[52.07]

0.520

[13.21]

19 EQ SP @

0.100 = 1.900

[2.54] = [48.26]

(TOL NONCUM)

(TYP)

±0.025

0.200 

[5.08]

0.100

[2.54]

(TYP)

0.018

[0.46]

(TYP)

0.051

[1.30]

(TYP)

±0.022

0.037 

[0.94]

±0.025

0.150 

[3.81]

0.011

[0.28]

(TYP)

0.605

[15.37]

1 LEAD CLUSTER TO BE CENTRALIZED

ABOUT CASE CENTERLINE WITHIN +0.010

FIGURE 2B. DD-03282 PLCC MECHANICAL OUTLINE

FIGURE 2C. DD-03282GP MECHANICAL OUTLINE

0.020/0.012

[0.51/0.31]

(TYP)

D2/E2

ORIENTATION MARK

DENOTES PIN 1

0.44/0.025 R

[11.18/0.64] R

0.020/[0.51]

MIN(TYP)

0.031/0.025

[0.79/0.02]

E3



E1E

D3

e

(TYP)

INCHES

A A1 D1 D2 D3 E1 E1 E3 e D E

MIN 0.165 0.090 0.649 0.590 0.500 0.650 0.590 0.500 0.500 0.685 0.685

MAX 0.180 0.119 0.655 0.630 0.500 0.655 0.630 0.500 0.500 0.694 0.694

MIN 4.20 2.29 16.51 14.99 12.70 16.51 14.99 12.70 1.27 17.40 17.40

MAX 4.57 3.04 16.66 16.00 BSC 16.66 16.00 BSC BSC 17.65 17.65

1 LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN ±0.010

2 DIMENSIONS SHOWN ARE IN INCHES [MILLIMETERS]

MIN

(TYP)

0.005 [0.13] R

ABOUT CASE CENTERLINE WITHIN

9.90

10.10

0.398

0.390

LEAD CLUSTER TO BE CENTRALIZED

MAX

MIN

MIN INCHES

DA2A1 A

2.35 0.25

0.093

-0.010

0.10

0.004

14.152.10 13.65

0.557

0.537

0.083

1.95

0.077

(TYP)

A1 (TYP)

MIN

eLE1E

14.15 10.10

13.65

0.557

0.537 0.398

9.90

0.390

0.95 BSC

0.037

0.65

0.026 BSC

0.80

0.031

(TYP) H

CHB

0.23

0.13

0.009

0.005

[0.00039]

REF0.45 1.95

0.077

REF0.018

0.30

0.012

0.016 [0.40]

E1 1

DENOTES PIN 1

ORIENTATION MARK

22 23

0.012 [0.3] R

(TYP)

2 DIMENSIONS SHOWN ARE IN INCHES [MILLIMETERS]

1.102 ±0.011

(27.99 ±0.27)



39 EQ. SP. @

0.0256 = 0.998

(0.65 = 25.36)

(TOL. NONCUM)

1.102 ±0.011

(27.99 ±0.1)



39 EQ. SP. @

0.0256 = 0.998

(0.65 = 25.36)

(TOL. NONCUM)

PIN NO. 1

INDEX

160

120

121

PIN NUMBERS

FOR REF. ONLY

0.012 +0.002

-0.001

(0.3 +0.05)

-0.03

(TYP)

0.0256

(.65)

(TYP)

NOTES:LEAD CLUSTER TO BE CENTRALIZED ABOUT

CASE CENTERLINE WITHIN ±0.010 (±0.25).

DIMENSIONS IN INCHES (MILLIMETERS). 



0.103 

(2.61)



0.077(1.96)

(TYP)

1.256 ±0.01

(31.9) (TYP)



SEE DETAIL "A"

DETAIL "A"

NTS

0.046(1.17)

(REF)

0.008 ±0.003

(0.18 ±0.08 )

(TYP)



0.025 x 45˚

(0.64 x 45˚)

CHAMFER

(4 PLCS)

1.194 (30.3)

(REF)



0.085 ±0.009

(2.159 ±0.23)



0.006 +0.002

 -0.001

(0.15 +0.05 )

(TYP)-0.03 



0.040(1.01)

(TYP)

0.031(0.79)

(TYP)

FIGURE 3A. DD-42900 ASIC MECHANICAL OUTLINE (CERAMIC)

FIGURE 3B. DD-42900 ASIC MECHANICAL OUTLINE (PLASTIC)

1.102 ±0.004

(27.99 ±0.1)



39 EQ. SP. @

0.0256 = 0.998

(0.65 = 25.36)

(TOL. NONCUM)

1.102 ±0.004

(27.99 ±0.1)



39 EQ. SP. @

0.0256 = 0.998

(0.65 = 25.36)

(TOL. NONCUM)

PIN NO. 1

INDEX

160

120

121

PIN NUMBERS

FOR REF. ONLY

0.012 ±0.003

(0.3 ±0.08)

(TYP)

0.0256

(.65)

(TYP)

NOTES:LEAD CLUSTER TO BE CENTRALIZED ABOUT

CASE CENTERLINE WITHIN ±0.010 (±0.25).

DIMENSIONS IN INCHES (MILLIMETERS). 

0.133 (3.38)

(REF)

0.013 +0.000

(0.33) -0.003

0.077(1.96)

(TYP)

1.256 ±0.01

(31.9) (TYP)



0.146 +0.008

(3.71) -0.000



SEE DETAIL "A"

DETAIL "A"

NTS

0.016 (0.41)

(MIN) (TYP)

0.031(.79)

(TYP)

0.007 ±0.002

(0.18) (TYP)



FIGURE 4B. DD-42900 FLAT PACK MECHANICAL ASSEMBLY

±.010

2.400

0.550

24 25 32 33

0.185

±.010

ENVELOPE

COMPONENT

(MAX)

0.040

(TYP)

2.170

±.010

0.200

SEE DETAIL "A"

0.065

(TYP)

DETAIL "A"

(REF)

NTS

(TYP)

0.075

0.185

(TYP)

0.040

0.015

(TYP)

0.080

(TYP)

±.002

(TYP)

0.010

0.020 R MAX

FOR REF ONLY

PIN NUMBERS

23 EQ. SP. @

(TOL NON CUM)

0.100 = 2.300

164 57

0.100

(TYP)

0.020

±.010

(TOL NON CUM)

7 EQ. SP. @

.010

0.100=0.700

1.800

(TYP)

LEAD CLUSTER TO BE CENTRALIZED

1ABOUT PWB CENTERLINE WITHIN

.010

NOTES:

±.003

0.100=0.700

7 EQ. SP. @

(TOL NON CUM)

1.800

2.400

.010

0.550

±.010

(TYP)

0.100

57 56

0.020

0.100 = 2.300

(TOL NON CUM)

23 EQ. SP. @

±.010

FOR REF ONLY

PIN NUMBERS

(TYP)

±.003

SEE DETAIL "A"

DETAIL "A"

NTS

(TYP)

0.015

0.070 (TYP)

0.080

(TYP)

(TYP) 0.010

0.020 R MAX

(TYP)

0.34

(MIN)

±.002

0.100

(REF)

2.000

(TYP)

0.100

±.010

0.040

ENVELOPE

COMPONENT

±.010

0.200(MAX)

FIGURE 4A. DD-42900 DIP MECHANICAL ASSEMBLY

ORDERING INFORMATION

Full Assembly:

DD-42900XY-300

Burn-in

0 = No Burn-in

2 = Burn-in (Ceramic Only)

Temperature Range

3 = 0 - 70°C

2 = -40 - +85°C

1 = -55 - +125°C (Ceramic Only)

ASIC Package Type

P = Plastic

C = Ceramic

Lead Type

D = Dip

F = Flat Pack

Chip Set:

DD-429X0XY-300

Burn-in

0 = No Burn-in

2 = Burn-in (Ceramic Only)

Temperature Range

3 = 0 - 70°C

2 = -40 - +85°C

1 = -55 - +125°C (Ceramic Only)

Transceiver Package Type

P = Plastic

C = Ceramic

Lead Type

D = Dip (Ceramic Only)

P = PLCC (Plastic Only)

G = PQFP (Plastic Only)

Chip Set

42910 = ASIC + one transceiver

42920 = ASIC + two transceivers

Note:“ASIC” is a QFP package.

DD-42900 PINOUTS (DIP AND FLAT PACK)

PIN NO. FUNCTION PIN NO. FUNCTION

1 POL SEL A1 33 D0

2POL SEL A0 34 D1

3INTEL / MOTO* 35 D2

48/16* BIT 36 D3

5Tx0 A 37 D4

6Tx0 B 38 D5

7Tx1 A 39 D6

8Tx1 B 40 D7

9A0 41 D8

10 A1 42 D9

11 A2 43 D10

12 A3 44 D11

13 A4 45 D12

14 A5 46 D13

15 A6 47 D14

16 A7 48 D15

17 A8 49 IRQ3*

18 A9 50 IRQ2*

19 A10 51 IRQ1*

20 CS0* 52 1 MHz OUT

21 CS1* 53 ARINC CLK 1

22 CS2 54 ARINC CLK 0

23 GND 55 +5 V

24 GND 56 +5 V

25 ZERO WAIT MODE 57 Rx3 B

26 READY 58 Rx3 A

27 RD* (DS*) 59 Rx2 B

28 WR* (RD/WR*) 60 Rx2 A

29 DTACK* 61 Rx1 B

30 ERROR* 62 Rx1 A

31 MASTER RESET* 63 Rx0 B

32 16 MHz CLOCK 64 Rx0 A

The information in this data sheet is believed to be accurate;however, no responsibility

is assumed by ILC Data Device Cor poration for its use, and no license or rights are

granted by implication or otherwise in connection therewith.

Specifications are subject to change without notice.

105 Wilbur Place, Bohemia, New York 11716-2482

For technical support: 1-800-DDC-1772, ext.7402 or 7384 (outside N.Y.)

1-800-245-3413, ext.7402 or 7384 (in Canada)

Headquarters - Tel: (516) 567-5600, ext.7402 or 7384,

Fax: (516) 567-7358

West Coast - Tel: (714)895-9777, Fax:(714) 895-4988

Europe - Tel: 44 (1635) 40158, Fax: 44 (1635) 32264

Asia/Pacific - Tel: 81 (3) 3814-7688, Fax:81 (3) 3814-7689

PRE-01-09/95-1M