10 Gb/s 3.3V QuadPort™
DSE Family
CY7C0430BV
CY7C04312BV
CY7C04314BV
Cypress Semiconductor Corporation •3901 North First Street •San Jose •CA 95134 •408-943-2600
Document #: 38-060 27 Rev. *A Revised May 14, 2002
Features
•QuadPort™ datapath switching element (DSE) family
allows four independent ports of access for data path
manage ment and switc hing
• High-bandwidth data throughput up to 10 Gb/s
• 133-MHz[1] port speed x 18-bit-wide interface × 4 ports
• High-speed clock to data access 4.2 ns (max.)
•Synchronous pipelined devices
—1-Mb, ½-Mb, and ¼-Mb switch arrays
—64K/32K/16K × 18 device options
•0.25-micron CMOS for optimum speed/power
•IEEE 1149.1 JTAG boundary scan
•Width and depth expansion capabilities
•BIST (Built-In Self-Test) controller
•Dual Chip Enables on all ports for easy depth expansion
•Separate upper-byte and lower-byte controls on all
ports
•Simple array partitioning (CY7C0430BV only)
—Internal mask register controls counter wrap-around
—Counter-Interrupt flags to indicate wrap-around
—Counter and mask registers readback on address
•272-ball BGA package (27-mm × 27-mm × 1.27-mm ball
pitch)
•Commercial and industrial temperature ranges
•3.3V low operating power
—Active = 750 mA (maximum)
—Standb y = 15 mA (maximum
Note:
1. fMAX2 for commercial is 135 MHz and for industrial is 133 MHz.
BUFFERED SWITCH
REDUNDANT DATA MIRROR
PORT 1 PORT 3
PORT 4
PORT 2
PORT 1
PORT 2
PORT 3
PORT 4
QuadPort DSE Family Applications
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 2 of 37
Functional Description
The CY7C043XXBV is a family of 10 Gb/s, true four-ported
Datapath Switching Elements with port speeds of up to
133 MHz[1]. The members of the family include 1-Mb
(64K ×18), ½-Mb (32K x18) , and ¼-Mb (16K × 18) options. All
four ports may be clocked at independent frequencies from
one anoth er. Simul tane ou s read s are al low e d for acc es se s to
the same address location; however, simultaneous reading
and w riti ng t o th e sa me ad dres s is not allo we d. An y po rt ca n
write to a certain location while other ports are reading that
locati on simultan eously, if the ti ming spec f or port to port dela y
(tCCS) is met. The result of writing to the same location by more
than one port at the same time is undefined.
Data is registered for decreased cycle time. Clock to data valid
tCD2 = 4.2 ns. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address the counter will self-increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle time s.
A HIGH on CE0 or LOW on CE1 fo r one cl ock cyc le wi ll power
down the internal circuitry to reduce the static power
consumption. One cycle is required with chip enables asserted
to react ivate the out puts .
The CY7C0430BV (64K × 18 device) is the only member of
the fami ly which contains burs t contains fo r simple arra y parti-
tioning. Counter enable inputs are provided to stall the
oper atio n of the ad dres s in put and util iz e the internal addres s
generate d by the inte rnal coun ter for fas t interleaved me mo ry
DATA PATH AGGREG ATOR
PORT 1
PORT 2
PORT 3
PORT 4
DATA PATH MANAG ER FOR
PARALLEL PACKET PROCESSING
Processor 2
Processor 1
Pre-processed DATA Path Processed DATA Path
DATA CLASSIFICATION ENGINE
PORT 2 PORT 4
PORT 1 PORT 3
Queue #1
Queue #2
QuadPort
DSE Family
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 3 of 37
applications. A port’s burst counter is loaded with an external
address when the port’s Counter Load pin (CNTLD) is
asserted LOW. When the port’s Counter Increment pin
(CNTINC) is asserted, the address counter will increment on
each subsequent LOW-to- HIGH transition of that port’s clock
signal. This will read/write one word from/into each su ccessive
address location until CNTINC is deasse rted. The count er can
addr es s the ent ire sw i tch array and will loo p back to the start.
Counter Reset (CNTRST) is used to reset the burst counter.
A counter-mask register is used to control the counter wrap.
The counter and mask register operations are described in
more detai ls in the fol low i ng sections.
The counter or mask register values can be read back on the
bidirectional address lines by activating MKRD or CNTRD,
respectively.
The new features included for the QuadPort DSE family
include: readback of burst-counter internal address value on
address lines, counter-mask registers to control the counter
wrap-around, readback of mask register value on address
lines, interrupt flags for message passing, BIST, JTAG for
boundary scan, and asynchronous Master Reset.
Notes:
2. Port 1 Control Logic Block is detailed on page 4.
3. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
4. Counter functionality applies only to CY7C0430BV (64K × 18) device option. These pins are either GND or NC for CY7C04312BV and CY7C04314BV.
Port-1
Control
Logic
Port 1
Counter/
Mask Reg/
Address
Decode
Port 1
I/O
18
Top Level Logic Block Diagram
16K/32K/64K × 18
QuadPort DSE
Array
Port 1 Operation-control Logic Blocks[2]
Port 2 Logic Blocks[3]
Port 4 Logic Blocks[3]
Port 3 Logic Blocks[3]
CNTLDP1[4]
CNTINCP1[4]
CNTRSTP1[4]
MKLDP1[4]
CNTINTP1[4]
MKRDP1[4]
CNTRDP1[4]
INTP1
CE1P1
CE0P1
R/WP1
OEP1
UBP1
LBP1
I/O0P1- I/O17P1
A0P1–A15P1 16
TMS
TCK
TDI TDO
BIST
MRST Reset
Logic
JTAG
Controller
CLKP1
CLKP1
CLKBIST
Port 1
Port 2 Port 3
Port 4
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 4 of 37
Addr.
Read
Port 1 Operation-Control Logic Block Diagram
R/WP1
CE0P1
CE1P1
LBP1
OEP1
UBP1
I/O9P1–I/O17P1
I/O0P1–I/O8P1
I/O
Control
Counter/
A0P1–A15P1
CLKP1
CNTLDP1[4]
CNTINCP1[4]
CNTRSTP1[4]
16
9
9
MKLDP1[4]
CNTINTP1[4]
MKRDP1[4]
Mask Register
Port-1
Port 1
Port 1
16K/32K/64K ×18
QuadPort
DSE Array
Port 1
Port 2
Port 4
Port 3
Address
Register
Readback
Register
Port 1
CNTRDP1[4]
Port 1
Address
Decode
Port 1
Interrupt
Logic
R/WP1
CE0P1
CE1P1
OEP1 INTP1
CLKP1
MRST
MRST
Priority
Decision
Logic
MRST
(Address Readback is independent of CEs)
W
LBP1
UBP1
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 5 of 37
Pin Configuration
272-ball Grid Array (BGA)
Top View
Notes:
5. Central Leads are for thermal dissipation only. They are connected to device VSS.
6. Pin is VSS for CY7C04312BV and CY7C04314BV devices.
7. Pin is NC for CY7C04312BV and CY7C04314BV devices.
8. Pin is VSS for CY7C04312BV and CY7C04314BV devices.
9. Pin is VSS for CY7C04314BV devices.
1234567891011121314151617181920
ALB
P1 I/O17
P2 I/O15
P2 I/O13
P2 I/O11
P2 I/O9
P2 I/O16
P1 I/O14
P1 I/O12
P1 I/O10
P1 I/O10
P4 I/O12
P4 I/O14
P4 I/O16
P4 I/O9
P3 I/O11
P3 I/O13
P3 I/O15
P3 I/O17
P3 LB
P4
BVDD1 UB
P1 I/O16
P2 I/O14
P2 I/O12
P2 I/O10
P2 I/O17
P1 I/O13
P1 I/O11
P1 TMS TDI I/O11
P4 I/O13
P4 I/O17
P4 I/O10
P3 I/O12
P3 I/O14
P3 I/O16
P3 UB
P4 VDD1
CA14
P1[9] A15
P1[8] CE1
P1 CE0
P1 R/W
P1 I/O15
P1 VSS2 VSS2 I/O9
P1 TCK TDO I/O9
P4 VSS2 VSS2 I/O15
P4 R/W
P4 CE0
P4 CE1
P4 A15
P4[8] A14
P4[9]
D VSS1 A12
P1 A13
P1 OE
P1 VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE
P4 A13
P4 A12
P4 VSS1
EA10
P1 A11
P1 MKRD
P1 CNTRD
P1[6] CNTRD
P4 [6] MKRD
P4 A11
P4 A10
P4
FA7
P1 A8
P1 A9
P1 CNTINT
P1[7] CNTINT
P4[7] A9
P4 A8
P4 A7
P4
GVSS1 A5
P1 A6
P1 CNTINC
P1[6] CNTINC
P4[6] A6
P4 A5
P4 VSS1
HA3
P1 A4
P1 MKLD
P1 CNTLD
P1[6] CNTLD
P4[6] MKLD
P4[6] A4
P4 A3
P4
JVDD1 A1
P1 A2
P1 VDD GND[5] GND[5] GND[5] GND[5] VDD A2
P4 A1
P4 VDD1
KA0
P1 INT
P1 CNTRST
P1[6] CLK
P1 GND[5] GND[5] GND[5] GND[5] CLK
P4 CNTRST
P4[6] INT
P4 A0
P4
LA0
P2 INT
P2 CNTRST
P2[6] VSS GND[5] GND[5] GND[5] GND[5] VSS CNTRST
P3[6] INT
P3 A0
P3
M VDD1 A1
P2 A2
P2 CLK
P2 GND[5] GND[5] GND[5] GND[5] CLK
P3 A2
P3 A1
P3 VDD1
NA3
P2 A4
P2 MKLD
P2 CNTLD
P2[6] CNTLD
P3[6] MKLD
P3[6] A4
P3 A3
P3
PVSS1 A5
P2 A6
P2 CNTINC
P2[6] CNTINC
P3[6] A6
P3 A5
P3 VSS1
RA7
P2 A8
P2 A9
P2 CNTINT
P2[7] CNTINT
P3[7] A9
P3 A8
P3 A7
P3
TA10
P2 A11
P2 MKRD
P2 CNTRD
P2[6] CNTRD
P3[6] MKRD
P3[6] A11
P3 A10
P3
U VSS1 A12
P2 A13
P2 OE
P2 VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE
P3 A13
P3 A12
P3 VSS1
VA14
P2[9] A15
P2[8] CE1
P2 CE0
P2 R/W
P2 I/O6
P2 VSS2 VSS2 I/O0
P2 NC NC I/O0
P3 VSS2 VSS2 I/O6
P3 R/W
P3 CE0
P3 CE1
P3 A15
P3[8] A14
P3[9]
W VDD1 UB
P2 I/O7
P1 I/O5
P1 I/O3
P1 I/O1
P1 I/O8
P2 I/O4
P2 I/O2
P2 MRST CLKBIST I/O2
P3 I/O4
P3 I/O8
P3 I/O1
P4 I/O3
P4 I/O5
P4 I/O7
P4 UB
P3 VDD1
YLB
P2 I/O8
P1 I/O6
P1 I/O4
P1 I/O2
P1 I/O0
P1 1/O7
P2 I/O5
P2 I/O3
P2 I/O1
P2 I/O1
P3 I/O3
P3 I/O5
P3 I/O7
P3 I/O0
P4 I/O2
P4 I/O4
P4 I/O6
P4 I/O8
P4 LB
P3
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 6 of 37
Selection Gu ide
CY7C04312BV
-133 CY7C04312BV
-100 Unit
fMAX2 133[1] 100 MHz
Max Access Time (Clock to Data) 4.2 5.0 ns
Max Operating Current ICC 750 600 mA
Max Standby Current for ISB1 (All ports TTL Level) 200 150 mA
Max Standby Current for ISB3 (All ports CMOS Level) 15 15 mA
Pin Definitions
Port 1 Port 2 Port 3 Port 4 Description
A0P1–A15P1 A0P2–A15P2 A0P3–A15P3 A0P4–A15P4 Address I nput/Output.
I/O0P1–I/O17P1 I/O0P2–I/O17P2 I/O0P3–I/O17P3 I/O0P4–I/O17P4 Data Bus Input/Output.
CLKP1 CLKP2 CLKP3 CLKP4 Clock Input. This input can be free running or strobed.
Maximum clock input rate is fMAX.
LBP1 LBP2 LBP3 LBP4 Lower Byte Select Input. Asserting this signal LOW
enable s read and wri te operation s to the lower by te. For
read operations both the LB and OE signals must be
asserted to drive output data on the lower byte of the data
pins.
UBP1 UBP2 UBP3 UBP4 Upper Byte Select Input. Same function as LB, but to
the upper byte.
CE0P1,CE1P1 CE0P2,CE1P2 CE0P3,CE1P3 CE0P4,CE1P4 Chip Enable Input. To select any port, both CE0 AND
CE1 must be asserted to their active states (CE0 ≤ VIL
and CE1 ≥ VIH).
OEP1 OEP2 OEP3 OEP4 Output Enable Input. This signal must be asserted LOW
to enable the I/O data lines during read operations. OE
is asynchronous inpu t.
R/WP1 R/WP2 R/WP3 R/WP4 Read/Write Enabl e Inp ut. Th is si gna l is asserte d LO W
to write to the dual port memory array. For read opera-
tions, assert this pin HIGH.
MRST Master Reset Input. This is one signal for All Ports.
MRST is an asynch ronous input. As sertin g MRST LOW
performs all of the reset functions as described in the text.
A MRST operati on is requ ire d at power-up .
CNTRSTP1[6] CNTRSTP2[6] CNTRSTP3[6] CNTRSTP4[6] Co unter Reset Inpu t. Asserting th is sig nal LOW res ets
the burst address counter of its respective port to zero.
CNTRST is second to MRST in priority with respect to
counter and mask register operations.
MKLDP1[6] MKLDP2[6] MKLDP3[6] MKLDP4[6] Mask Register Load Input. Asserting this signal LOW
loads the mask register with the external address
available on the address lines. MKLD operation has
higher priority over CNTLD operation.
CNTLDP1[6] CNTLDP2[6] CNTLDP3[6] CNTLDP4[6] Counter Load Input. Asserting this signal LOW loads
the burst counter with the external address present on
the address pins.
CNTINCP1[6] CNTINCP2[6] CNTINCP3[6] CNTINCP4[6] Counter Increment Input. Asserting this signal LOW
increments the burst address counter of its respective
port on each rising edge of CLK .
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 7 of 37
CNTRDP1[6] CNTRDP2[6] CNTRDP3[6] CNTRDP4[6] Counter Readback Input. When asserted LOW, the
internal address value of the counter will be read back on
the address lines. During CNTRD operation, both
CNTLD and CNT INC must be HIGH. Counter readback
operation has higher priority over mask register readback
operation. Counter readback operation is independent of
port chip ena bles. If address readback ope ration occur s
with chi p enabl es ac tive (CE0 = LOW, CE1 = HIGH), the
data lines (I/Os) will be three-stated. The readback timing
will be valid after one no-operation cycle plus tCD2 from
the rising edge of the next cycle.
MKRDP1[6] MKRDP2[6] MKRDP3[6] MKRDP4[6] Mask Register Readba ck Input. When as serted LOW,
the value of the mask register will be readback on
addr ess lines. During mask register rea dback opera tion,
all counter and MKLD inputs must be HIGH (see Counter
and Mask Register Operations truth table). Mask register
readbac k ope ration is in depen dent of po rt chip enab les.
If address readback operation occurs with chip enables
active (CE0 = LOW, CE1 = HIGH), the data lines (I/Os)
will be thre e-stated. The readba ck will be valid afte r one
no-operation cycle plus tCD2 from the rising edge of the
next cycle.
CNTINTP1[7] CNTINTP2[7] CNTINTP3[7] CNTINTP4[7] Counter Interrupt Flag Output. Flag is asserted LOW
for one clock cycle when the counter wraps around to
location zero.
INTP1 INTP2 INTP3 INTP4 Interrupt Flag Output. Interrupt permits communica-
tions between all four ports. The upper four memory
locati ons can be used for m essage pass ing. Exam ple of
operation: INTP4 is asserted LOW when another port
writes to the mailbox location of Port 4. Flag is cleared
when Po rt 4 reads the co ntents of its mai lbox. The sam e
operation is applicable to ports 1, 2, and 3.
TMS JTAG Test Mode Select Input. It controls the advance
of JTAG TAP state machine. State machine transit ions
occur on the rising edge of TCK.
TCK JTAG Test Clock Input. This ca n be CLK of any po rt or
an external clock connected to the JTAG TAP.
TDI JTAG Test Data Input. This is the only data input. TDI
inputs will shift data serially in to the selected register.
TDO JTAG Test Data Output. This is the only data outpu t.
TDO transitions occur on the falling edge of TCK. TDO
normall y thre e-s tate d except w hen captu red data is
shifted out of the JTAG TAP.
CLKBIST BIST Clock Input.
GND Thermal Ground for Heat Dissipation.
VSS Ground Input.
VDD Power Input.
VSS1 Address Lines Ground Input.
VDD1 Address Lines Power Input.
VSS2 Data Lines Ground Input.
VDD2 Data Lines Power Input.
Pin Definitions (continued)
Port 1 Port 2 Port 3 Port 4 Description
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 8 of 37
Maximum Ratings
(Abov e wh ic h th e useful life may be im pa ired. For user guide-
lines, not tested.)
Storage Temperature................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Supply Voltage to Ground Potential..............–0.5V to + 4.6V
DC Voltage Applied to
Outputs in High-Z State .........................–0.5V to VCC + 0.5V
DC Input Voltage................... .................–0.5V to VCC + 0.5V
Output Current into Outpu ts (LO W)............... ...... ..... ...20 mA
Static Discharge Voltage ..........................................> 2200V
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient T emperature VDD
Commercial 0°C to +70°C3.3V ± 150 mV
Industrial –40°C to +85°C 3.3V ± 150 mV
Electri cal Characteristics Over the Operating Range
Parameter Description
CY7C043XXBV
Unit
-133 -100
Min. Typ. Max. Min. Typ. Max.
VOH Output HIGH Voltage
(VCC = Min., IOH = –4.0 mA) 2.4 2.4 V
VOL Output LOW Voltage
(VCC = Min., IOH = +4.0 mA) 0.4 0.4 V
VIH Input HIGH Voltage 2.0 2.0 V
VIL Input LOW Voltage 0.8 0.8 V
IOZ Output Leakage Current –10 10 –10 10 µA
ICC Operating Current (VCC = Max., IOUT = 0 mA)
Outputs Disabled, CE = VIL, f = fmax 350 700 300 550 mA
ISB1 Standby Current (four ports toggling at TTL
Levels,0 active)
CE1-4 ≥ VIH, f = fMAX
80 200 60 150 mA
ISB2 Standby Current (four ports toggling at TTL
Levels, 1 active) CE1 | CE2 | C E3 | C E4 < VIL,
f = fMAX
150 300 125 250 mA
ISB3 Standby Current (four ports CMOS Level, 0
active) CE1–4 ≥ VIH, f = 0 1.5 15 1.5 15 mA
ISB4 Standby Current (four ports CMOS Level, 1
active and toggling) CE1 | CE2 | CE3 | CE4 <
VIL, f = fMAX
110 290 85 240 mA
JTAG TAP Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
VOH1 Output HIGH Voltage IOH = −4.0 mA 2.4 V
VOL1 Output LOW Voltage IOL = 4.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
IXInput Leakage Current GND ≤ VI ≤ VDD –100 100 µA
Capacitance
Parameter Description Test Conditions Max. Unit
CIN (All Pins) Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V 10 pF
COUT (All Pins) Output Capacitance 10 pF
CIN (CLK Pins) Input Capacitance 15 pF
COUT (CLK Pins) Output Capacitance 15 pF
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 9 of 37
AC Test Load
Note:
10. Test conditions: C = 10 pF.
V
TH
=1.5V
OUTPUT
C
(a) Normal Load
R = 50
Ω
Z
0
= 50
Ω
[10]
3.0V
GND 90% 90%
10%
tRtF
10%
All Input Pulses
(b) Thre e -State D elay
V
TH
=1.5V
OUTPUT
5 pF
R = 50
Ω
Z
0
= 50
Ω
(c) TAP Load
TDO
C= 10 pF
Z0=50Ω
GND
1.5V
50Ω
V
TH
=3.3V
OUTPUT
5 pF
R = 50
Ω
Z
0
= 50
Ω
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 10 of 37
Switching Characteristics Over the Indu strial Operatin g Ran ge [11]
Parameter Description
CY7C04312BV
Unit
-133 -100
Min. Max. Min. Max.
fMAX2[12] Maximum Frequency 133 100 MHz
tCYC2[12] Clock Cyc le Time 7.5 10 ns
tCH2 Clock HIGH T ime 3 4 ns
tCL2 Clock LOW Time 3 4 ns
tRClock Rise Time 2 3 ns
tFClock Fal l Time 2 3 ns
tSA Address Set-up Time 2.3 3 ns
tHA Address Hold Time 0.7 0.7 ns
tSC Chip Enable Set-up Time 2.3 3 ns
tHC Chip Enable Hold Time 0.7 0.7 ns
tSW R/W Set-up Time 2.3 3 ns
tHW R/W Hold Time 0.7 0.7 ns
tSD Input Data Set-up Time 2.3 3 ns
tHD Input Data Hold Time 0.7 0.7 ns
tSB Byte Set-up Time 2.3 3 ns
tHB Byte Hold Time 0.7 0.7 ns
tSCLD CNTLD Set-up Time 2.3 3 ns
tHCLD CNTLD Hold Time 0.7 0.7 ns
tSCINC CNTINC Set-up Time 2.3 3 ns
tHCINC CNTINC Hold Time 0.7 0.7 ns
tSCRST CNTRST Set-up Time 2.3 3 ns
tHCRST CNTRST Hold Time 0.7 0.7 ns
tSCRD CNTRD Set-up Time 2.3 3 ns
tHCRD CNTRD Hold Time 0.7 0.7 ns
tSMLD MKLD Set-up Time 2.3 3 ns
tHMLD MKLD Hold Time 0.7 0.7 ns
tSMRD MKRD Set-up Ti me 2.3 3 ns
tHMRD MKRD Hold Time 0.7 0.7 ns
tOE Output Enable to Data Valid 6.5 8 ns
tOLZ[13] OE to Low-Z 1 1 ns
tOHZ[13] OE to High-Z 1 6 1 7 ns
tCD2 Clock to Data Valid 4.2 5 ns
tCA2 Clock to Count er Addres s R ead bac k Valid 4.7 5 ns
tCM2 Clock to Mask Register Readback Valid 4.7 5 ns
tDC Data Output Hold After Clock HIGH 1 1 ns
tCKHZ[14] Clock HIGH to Output High-Z 1 4.8 1 6.8 ns
tCKLZ[14] Clock HIGH to Output Low-Z 1 1 ns
Notes:
11. If data is simultaneously written and read to the same address location and tCCS is violated, the data read from the address, as well as the subsequent data
remaining in the address is undefined.
12. fMAX2 for commercial is 135 MHz. tCYC2 Min. for commercial is 7.4 ns.
13. This parameter is guaranteed by design, but it is not production tested.
14. Valid for both address and data outputs.
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 11 o f 37
tSINT Clock to INT Set Time 1 7.5 1 10 ns
tRINT Clock to INT Reset Time 1 7.5 1 10 ns
tSCINT Clock to CNTINT Set Time 1 7.5 1 1 0 ns
tRCINT Clock to CNTINT Reset Time 1 7.5 1 1 0 ns
Master Reset Timing
tRS Master Reset Pulse Width 7.5 10 ns
tRSR Master Reset Recovery Time 7.5 10 ns
tROF Master Reset to Output Flags Reset Time 6.5 8 ns
Port to Port Delays
tCCS[11] Clock to Clock Set-up Time (time required after a write
before you can read the same address location) 6.5 9 ns
JTAG T iming and Switching Waveforms
Parameter Description
CY7C043XXBV
Unit
–133/–100
Min. Max.
fJTAG Maximum JTAG TAP Controller Frequency 10 MHz
tTCYC TCK Clock Cycle Time 100 ns
tTH TCK Clock High Time 40 ns
tTL TCK Clock Low Time 40 ns
tTMSS TMS Set-up to TCK Clock Rise 20 ns
tTMSH TMS Hold After TCK Clock Rise 20 ns
tTDIS TDI Set-up to TCK Clock Rise 20 ns
tTDIH TDI Hold after TCK Clock Rise 20 ns
tTDOV TCK Clock Low to TDO Valid 20 ns
tTDOX TCK Clock Low to TDO In valid 0 ns
fBIST Maximum CLKBIST Frequency 50 MHz
tBH CLKBIST High Time 6 ns
tBL CLKBIST Low Ti me 6 ns
Switching Characteristics Over the Industrial Operating Range (continued)[11]
Parameter Description
CY7C04312BV
Unit
-133 -100
Min. Max. Min. Max.
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 12 of 37
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
TDO
tTCYC
tTMSH
tTL
tTH
tTMSS
tTDIS tTDIH
tTDOX
tTDOV
Switching Waveforms
Master Reset [15]
Notes:
15. tS is the set-up time required for all input control signals.
16. To Reset the test port without resetting the device, TMS must be held low for five clock cycles.
MRST
tRSR
tRS
INACTIVE ACTIVE
TDO
INT
CNTINT
tRSF
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
tCH2 tCL2
tCYC2
CLK
tS
TMS[16]
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 13 of 37
Read Cycle [17, 18, 19, 20, 21]
Notes:
17. OE is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge.
18. CNTLD = VIL, MKLD = VIH, CNTINC = x, and MRST = CNTRST = VIH.
19. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
20. Addresses do not have to be accessed sequentially . Note 18 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are for reference
only.
21. CE is internal signal. CE = VIL if CE0 = VIL and C E1 = VIH.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
tSC tHC
tSW tHW
tSA tHA
AnAn+1
CLK
CE
R/W
ADDRESS
DATAOUT
OE
An+2 An+3
tSC tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
QnQn+1 Qn+2
1 Latency
LB
UB
tSB tHB
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 14 of 37
Bank Select Read[22, 23]
Read-to-W ri te-to-Re ad (OE = VIL)[24, 25, 26, 27]
Notes:
22. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each bank consists of one QuadPort DSE device from this data sheet.
ADDRESS(B1) = ADDRESS(B2).
23. LB = UB = OE = CNTLD = VIL; MRST = CNTRST= MKLD = VIH.
24. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
25. LB = UB = CNTLD = VIL; MRST = CNTRST = MKLD = VIH.
26. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference only .
27. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Switching Waveforms (continued)
Q3
Q1
Q0
Q2
A0A1A2A3A4A5
Q4
A0A1A2A3A4A5
tSA tHA
tSC tHC
tSA tHA
tSC tHC
tSC tHC
tSC tHC tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2 tCD2 tCKHZ
tCKLZ
tCD2 tCKHZ
tCKLZ
tCD2
tCH2 tCL2
tCYC2
CLK
ADDRESS(B1)
CE(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE(B2)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2 tCKHZ
tSD tHD
tCKLZ
tCD2
No Operation WriteRead Read
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
AnAn+1 An+2 An+2
Dn+2
An+3 An+4
QnQn+3
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 15 of 37
Read-to-W ri te-to-Re ad (OE Controlled) [2 4, 25, 26 , 27 ]
Read with Address Counter Advance[28, 29]
Notes:
28. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH.
29. The “Internal Addr ess ” is equal to the “External Address” when CNTLD = VIL.
Switching Waveforms (continued)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
AnAn+1 An+2 An+3 An+4 An+5
tHW
tSW
tSD tHD
Dn+2
tCD2
tOHZ
Read ReadWrite
Dn+3
Qn
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
OE
tCKLZ
tCD2
Qn+4
Counter Hold
Read with Counter
tSA tHA
tSCLD tHCLD
tSCINC tHCINC
tCH2 tCL2
tCYC2
Qx–1QxQnQn+1 Qn+2 Qn+3
tDC
tCD2
Read with Counter
Read
External
Address
CLK
ADDRESS
CNTLD
DATAOUT
CNTINC
An
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 16 of 37
Write with Address Counter Advance [29, 30, 31]
Notes:
30. CE0 = LB = UB = R/W = VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH.
31. Counter operation is only available on the CY7C0430BV. The CY7C04312BV and CY7C04314BV do not support the counter functions.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
AnAn+1 An+2 An+3 An+4
Dn+1 Dn+1 Dn+2 Dn+3 Dn+4
An
Dn
tSCLD tHCLD
tSCINC tHCINC
tSD tHD
Write External Write with Counter
Address Write with
Counter Write Counter
Hold
CLK
ADDRESS
INTERNAL
CNTINC
CNTLD
DATAIN
ADDRESS
tSA tHA
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 17 of 37
Counter Reset [26, 31, 32, 33]
Notes:
32. CE0 = LB = UB = VIL; CE1 = MRST = MKLD = MKRD = CNTRD = VIH.
33. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
CLK
ADDRESS
INTERNAL
CNTINC
CNTLD
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT Q0Q1Qn
D0
AXA0A1AnAn+1
tSCRST tHCRST
tSD tHD
tSW tHW
AnAn+1
tSA tHA
Counter
Reset Write
Address 0 Read
Address 0 Read
Address 1 Read
Address n
tSCLD tHCLD
An+2
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 18 of 37
Load and Read Address Counter[31, 34]
Notes:
34. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = VIH.
35. Address in output mode. Host must not be driving address bus after time tCKLZ in next clock cycle.
36. Address in input mode. Host can drive address bus after tCKHZ.
37. This is the value of the address counter being read out on the address lines.
Switching Waveforms (continued)
Read Data with Counter
tSA tHA
tSCLD tHCLD
tSCINC tHCINC
tCH2 tCL2
tCYC2
Qx–1QxQnQn+1 Qn+2
Read
Internal
Address
CLK
A
0
-A
15
CNTLD
DATAOUT
CNTINC
An
tSCRD tHCRD
CNTRD
AnAn+1 An+2
INTERNAL
ADDRESS
An+2
An+2 An+2
Qn+2
tCD2 tDC
tCKLZ
tCKLZ
tCKHZ
tCKHZ
t
CA2
Load
External
Address
Not e 3 5 Note 36
[37]
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 19 of 37
Load and Read Mask Register [31, 38]
Notes:
38. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =VIH.
39. This is the value of the Mask Register read out on the address lines.
Switching Waveforms (continued)
tSA tHA
tSMLD tHMLD
tCH2 tCL2
tCYC2
Read
Mask Register
Value
CLK
A
0
-A
15
MKLD
An
tSMRD tHMRD
MKRD
AnAnAn
INTERNAL
VALUE
An
AnAn
tCKLZ tCKHZ
tCA2
Load
Mask Register
Value
MASK
[39]
Note 35 Note 36
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 20 of 37
Port 1 Write to Port 2 Read[40, 41 , 42 ]
Notes:
40. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =VIH.
41. This timing is valid when one port is writing, and one or more of the three other ports is reading the same location at the same time. If tCCS is violated, indeterminate
data will be read out.
42. If tCCS< minimum specified value, then Port 2 will read the most recent data (written by Port 1) only (2*tCYC2 + tCD2) after the rising edge of Port 2’s clock. If
tCCS > minimum specified value, then Port 2 will read the most recent data (written by Port 1) (tCYC2 + tCD2) after the rising edge of Port 2’s clock.
Switching Waveforms (continued)
tSA tHA
tSW tHW
tCH2 tCL2
tCYC2
CLKP1
R/WP1
An
Dn
tCKHZ tHD
tSA
An
tHA
Qn
tDC
tCCS
tSD tCKLZ
tCH2
tCL2
tCYC2
tCD2
PORT-1
ADDRESS
PORT-1
DATAIN
CLKP2
R/WP2
PORT-2
ADDRESS
PORT-2
DATAOUT
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 21 of 37
Counter Interrupt [31, 43, 44, 45]
Mailbox Interrupt Timing[46 , 47 , 48 , 49, 5 0]
Notes:
43. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTRD = MKRD = VIH.
44. CNTINT is always driven.
45. CNTINC goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h. The “x” is “Don’t Care.”
46. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = CNTRD = CNTINC = MKRD = MKLD =VIH.
47. Address “FFFE” is the mailbox location for Port 2.
48. Port 1 is configured for Write operation, and Port 2 is configured for Read operation.
49. Port 1 and Port 2 are used for simplicity. All four ports can write to or read from any mailbox.
50. Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock.
Switching Waveforms (continued)
tSMLD tHMLD
tSCLD tHCLD
tCH2 tCL2
tCYC2
CLK
MKLD
CNTLD
Anxx7Eh
INTERNAL
ADDRESS xx7Fh xx00h
xx7Dh
EXTERNAL
ADDRESS
tSCINC tHCINC
CNTINC
COUNTER
007Fh
xx7Dh xx00h
CNTINT tSCINT tRCINT
t
CH2
t
CL2
t
CYC2
CLK
P1
tCH2 tCL2
tCYC2
CLKP2
FFFE
tSA tHA
An+3
AnAn+1 An+2
PORT-1
ADDRESS
AmAm+4
Am+1 FFFE Am+3
PORT-2
ADDRESS
INTP2
tSA tHA
tSINT tRINT
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 22 of 37
Table 1. Read/Write and Enable Operation (Any Port)[51, 52, 53]
Inputs Outputs OperationOE CLK CE0CE1R/W I/O0–I/O17
X H X X High-Z Deselected
X X L X High-Z Deselected
XLHLD
IN Write
LLHHD
OUT Read
H X L H X High-Z Outputs Disabled
Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port)[31, 51, 54, 55]
CLK MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD Mode Operation
XL X X X X X XMaster-
Reset Counter/Address Register Reset and Mask
Register Set (resets entire chip as per reset
state table)
H L X X X X X Reset Counter/ Address Register Reset
H H L X X X X Load Load of Address Lines into Mask Register
H H H L X X X Load Load of Address Lines into Counter/Address
Register
H H H H L X X Increment Co unter Increment
H H H H H L X Readback Readback Counter on Address Lines
H H H H H H L Readback Readback Mask Register on Address Lines
H H H H H H H Hold Counter Hold
Notes:
51. “X” = “Don’t Care,” “H” = VIH, “L” = VIL.
52. OE is an asynchronous input signal.
53. When CE changes state, deselection and read happen after one cycle of latency.
54. CE0 = OE = VIL; CE1 = R/W = VIH.
55. Counter operation and mask register operation are independent of Chip Enables.
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 23 of 37
Master Reset
The QuadPort DSE device undergoes a complete reset by
taking its Master Reset (MRST) input LOW. The Ma ster Res et
input can switch asynchronously to the clocks. A Master Reset
initializes the internal burst counters to zero, and the counter
mask registers to all ones (completely unmasked). A Master
Reset also forces the Mailbox Interrupt (INT) flags and the
Counter Interrupt (CNTINT) flags HIGH, resets the BIST
controller, and takes all registered control signals to a
deselected read state.[56] A Master Reset must be performed
on the QuadPort DSE device after power-up.
Interrupts
The upper four memory locations may be used for message
passing and permit communications between ports. Table 3
shows the interrupt operation for all ports. For the 1-Mb
QuadPort DSE device, the highest memory location FFFF is
the mail box for Port 1, FFFE is the mailbox for Port 2, FFFD is
the mailbox for Port 3, and FFFC is the mailbox for Port 4.
Table 3 shows that in or der to set Port 1 INTP1 fla g, a wri te b y
any oth er port t o address FFFF will asse rt INTP1 LOW . A read
of FFFF location by Port 1 will reset INTP1 HIGH. When one
port writ es t o the o the r po rt’s mailbox, the Interrupt flag (INT)
of the port th at the mailbo x belo ngs to i s asser ted LO W. Th e
Interrupt is reset when the owner (port) of the mailbox reads
the contents of the mailbox. The interrupt flag is set in a
flow-th rough m ode (i .e., it fo llows th e clock edge o f the wr iting
port). Also, the flag is reset in a flow-through mode (i.e., it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. If an application does not require message
passi ng, INT pins should be treated as no-co nnect and shou ld
be left floating. When two ports or more write to the same
mailbox at the same time INT will be assert ed but the conten ts
of the mailbox are not guaranteed to be valid.
Note:
56. During Master Reset the control signals will be set to a deselected read state: CE0I = LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI =
CNTINCI = VIH; CE1I = VIL. The “I” suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals.
Address Counter Control Operations[31]
Counter enable inputs are p rovided to stall t he operation of the
address input and utilize the internal address generated by the
internal counter for the fast interleaved memory applications.
A por t’s burst counter is loaded with the port’s Counter Load
pin (CNTLD). When the port’s Counter Incr ement (CNTINC) is
asserted, the address counter will increment on each LOW to
HIGH transition of that port’s clock signal. This will read/write
one word from/into each successive address location until
CNTINC is deass erted. Dependi ng on the mas k register sta te,
the cou nter can add ress the entire m emory array an d will loop
back to start. Counter Reset (CNTRST) is used to reset the
Burst Counter (the Mask Register value is unaffected). When
using the counter in readback mode, the internal address
value of the counter will be read back on the address lines
when Counter Readback Signal (CNTRD) is asserted.
Figure 1 provides a block diagram of the readback operation.
Table 2 lists control signals required for counter operations.
The signals are listed based on their priority. For example,
Master Reset takes precedence over Counter Reset, and
Counter Load has lower priority than Mask Register Load
(described below). All counter operations are independent of
Chip Enables (CE0 and CE1). When the address readback
operation is performed the data I/Os are three-stated (if CEs
are active) and o ne-clo ck cyc le (no-op erat ion cyc le) l atency i s
experienced. The address will be read at time tCA2 from the
rising edge of the clock following the no-operation cycle. The
read back address can be either of the burst counter or the
mask register based on the levels of Counter Read signal
(CNTRD) and Mask Register Read signal (MKRD). Both
signals are synchronized to the port's clock as shown in
Table 2. Counter read has a higher priority than mask read.
Table 3. Interrupt Operation Example
Function
Port 1 Port 2 Port 3 Port 4
A0P1–15P1 INTP1 A0P2–15P2 INTP2 A0P3–15P3 INTP3 A0P4–15P4 INTP
4
Set Port 1 INTP1 Flag X L FFFF XFFFF XFFFF X
Reset Port 1 INTP1 Flag FFFF H X X X X X X
Set Port 2 INTP2 Flag FFFE X X L FFFE XFFFE X
Reset Port 2 INTP2 Flag X X FFFE H X X X X
Set Port 3 INTP3 Flag FFFD XFFFD X X L FFFD X
Reset Port 3 INTP3 Flag X X X X FFFD H X X
Set Port 4 INTP4 Flag FFFC XFFFC XFFFC XXL
Reset Port 4 INTP4 Flag XXXXXXFFFC H
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 24 of 37
Counter-Mask Regist er[31]
The burst counter has a mask re gis ter that controls whe n a nd
where the counter wraps. An interrupt flag (CNTINT) is
asserted for one clock cycle when the unmasked portion of the
counter address wraps around from all ones (CNTINC must be
asserted) to all zeros. The example in Figure 2 shows the
counter mask register loaded with a mask value of 003F
unmasking the first 6 bits with bit “0” as the LSB and bit “15”
as the MSB. The maximum value the mask register can be
loaded with is FFFF. Setting the mask register to this value
allows the counter to access the entire memory space. The
address counter is then loaded with an initial value of XXX8.
The “blocked” addresses (in this case, the 6th address through
Addr.
Readback
Counter/
Address
Register
CLK
CNTLD = 1
CNTINC = 1
CNTRST = 1
MKLD = 1
MKRD
CNTRD
Memory
Array
Mask
Register
Readback
Register
Bidirectional
Address Lines
Figure 1. Counter and Mask Register Read Back on Address Lines
215 214 2621
2522
242320
215 214 2621
2522
242320
215 214 2621
2522
242320
215 214 2621
2522
242320
H
H
H
L
11
0’s1
01
0101
00
X’s1
X0
X0X0
11
X’s1
X1
X1X1
00
X’s0
X0
X0X0
Blocked Address Counter Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Regis ter = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
Figure 2. Programmable Counter-Mask Register Operation[57]
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 25 of 37
the 15th address) are loaded with an address but do not
increment once loaded. The counter address will start at
addre ss XXX8 . Wit h CNT IN C asserted LOW, the counter will
increment its internal address value till it reaches the mask
register value of 3F and wraps around the memory block to
locati on X XX0. Th ere fore, the counter uses th e m as k-regis ter
to define wrap-around point. The mask register of every port
is loaded when MKLD (mask register load) for that port is
LOW . When MKRD is LOW, th e value o f the mask register can
be read out on address lines in a manner similar to counter
read back operation (see Table 2 for required conditions).
When the bu rst counter is loa ded wi th an addr ess hig her than
the mask register value, the higher addresses will form the
mask ed portion of th e counter add ress and are called block ed
addresses. The blocked addresses will not be changed or
affected by the counter increment operation. The only
excep tion is ma sk regis ter bit 0. It can be ma sked to all ow the
addr ess cou nter to incr ement by two. If the mask re giste r bit 0
is loaded with a logic value of “0,” then address counter bit 0
is masked and can not be changed during counter increment
operation. If the loaded value for address counter bit 0 is “0,”
the counter will increment by two and the address values are
even. If the loaded value for address counter bit 0 is “1,” the
counte r will incr ement by tw o and the add ress values are odd.
This operations allows the user to achieve a 36-bit interface
using any two ports, where the counter of one port counts even
addresses and the counter of the other port counts odd
addr es ses . Thi s ev en-o dd ad dres s sc he me store s one half of
the 36-bit word in even memory locations, and the other half
in odd m emory loca tions. CNTINT w ill be as serted whe n the
unmasked portion of the counter wraps to all zeros. Loading
mask reg ister bit 0 with “1” allows th e counter to increme nt the
address value sequentially.
Table 2 groups the operations of the mask register with the
oper ations of the ad dress coun ter . Addr ess counter and mask
register signals are all synchronized to the port's clock CLK.
Master reset (MRST) is the only asynchron ous signal l isted on
Table 2. Signals are listed based on their priority going from
left column to right column with MRST being the highest. A
LOW on MRST will reset bo th counter r egister to a ll zeros a nd
mask register to all ones. On the other hand, a LOW on
CNTRST will only clear the address counter register to zeros
and the mask register will r emain intact.
There are four operations for the counter and mask register:
1. Load operation: When CNTLD or MKLD is LOW, the ad-
dress counter or the mask register is loaded with the ad-
dress value presented at the address lines. This value rang-
es from 0 to FF FF (64K). The mask regi ster load operatio n
has a higher priority over the address counter load opera-
tion.
2. Inc rement: Once th e addre ss counte r is load ed with an ex-
ternal a ddress, the coun ter can intern ally increment the ad-
dress value by asserting CNTINC LOW. The coun ter c an
address the entire memory array (depend on the value of
the mask register) and loop back to location 0. The incre-
ment operation is second in priority to load operation.
3. Re adb ac k: th e in tern al v al ue of eith er th e burst counter o r
the mask register can be read out on the address lines when
CNTRD or MKRD is LOW. Counter readback has higher
prio rity over mask regist er readback . A no-operation de lay
cycl e is experienced when read bac k ope rati on is per-
formed. The address will be valid after tCA2 (for counter
readbac k) or tCM2 (for mask readback) from the following
port's clock rising edge. Address readback operation is in-
depend ent of the port's chi p ena bl es (CE 0 and CE1). If ad-
dress readback occurs while the port is enabled (chip en-
ables active), the data lines (I/Os) will be three-stated.
4. Hold operation: In order to hold the value of the address
counte r at certain a ddress, all signals in Table 2 have to be
HIGH. This operation has the least priority. This operation
is useful in many applications where wait states are needed
or when address is available few cycles ahead of data.
The counter and mask register operations are totally
independent of port chip enables.
IEEE 1149.1 Serial Boundary Scan (JTAG) and
Memory Built-In-Self-Test (MBIST)
The CY7C0430BV incorporates a serial boundary scan test
access port (TAP). This port is fully compatible with IEEE
Standard 1149.1-2001[58]. The TAP operates using JEDEC
standard 3.3V I/O logic levels. It is composed of three input
connections and one output connection required by the test
logic defined by the standard. Memory BIST circuitry will also
be controlled through the T AP interface. All MBIST instructions
are compliant to the JTAG standard. An external clock
(CLKBIST) is p rovided to allow the us er to run BIST at sp eeds
up to 50 MHz . CLKBIST is multiple xed interna lly with the ports
clocks duri ng BIST opera tio n.
Disabling the JTAG Feature
It is possible to operate the QuadPort DSE device without
using the JTAG feature. To disable the TAP controller, TCK
must be ti ed L OW (VSS) to preven t clocking of the device. TDI
and TMS are internally pulled up and may be unconnected.
They may alternately be connected to VDD through a pull-up
resistor. TDO should be left unconnected. CLKBIST must be
tied LOW to disable the MBIST. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
Test Access Port (TAP)–Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are cap t ure d on the ris in g ed ge of T C K. All ou tput s are driv en
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registe rs. The register be tween TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Notes:
57. The “X” in this diagram represents the counter upper-bits.
58. Master Reset will reset the JTAG controller.
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 26 of 37
Test Data Out (TDO)
The TD O outp ut pin is used to s eri all y c lo ck da ta-o ut from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram (FSM)). The output changes on the falling edge of
TCK. TDO is connected to the least s ignificant bit (LSB) of any
register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the QuadPort DSE device and may be performed while the
device is operating. At power-up, the TAP is reset internally to
ensure that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the QuadPort DSE
device test circuitry. Only one register can be selected at a
time through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK. Data is output on
the TDO pin on the falling edge of TCK.
Instruction Regis ter
Four- bit i ns truc tio ns ca n be serially loa ded int o the ins truction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the following JTAG/BIST
Controller diagram. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with the
IDCO DE instr ucti on if th e cont roller is pl aced i n a reset stat e
as described in the previous section.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save tim e w h en se rial ly shifting dat a th rou gh registe rs, it is
somet imes advan tageou s t o skip c ert ain de vices . The bypas s
regi ster is a single-bit registe r that ca n be plac ed between TDI
and TDO pins. This allows data to be shifted through the
QuadPo rt DSE device with minima l delay. The bypass re gister
is set LOW (VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output p ins on t he Q ua dPort DSE dev ic e. Th e bo und ary sc an
register is loaded with the contents of the QuadPort DSE
device Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, and SAMPLE/PRELOAD instructions can be
used to capture the contents of the Input and Output ring.
Ident ifica tion (ID) Regi ster
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the QuadPort DSE device and can be shifted out when the
TAP controller is in the Shift-DR state. The ID register has a
vendor code and other information described in the Identifi-
cation Register Definitions table.
TAP Instruction Set
Sixteen different instructions are possible with the 4-bit
instruction register. All combinations are listed in Table 6,
Instruction Codes. Seven of these instructions (codes) are
listed as RESER VED an d sh oul d not be us ed. The oth er ni ne
instructions a re describ ed in detail bel ow.
The TAP controller used in this QuadPort DSE device is fully
compatible[58] with the 1149.1 convention. The TAP controller
can be used to load address, data or control signals into the
QuadPort DSE device and can preload the Input or output
buffers. The QuadPort DSE device implements all of the
1149.1 instructions except INTEST. Table 6 lists all instruc-
tions.
Instructions are loaded into the TAP controller during the
Shif t-IR stat e wh en the inst ruc tion regi ste r is pl aced bet ween
TDI and TDO. During this state, instructions are shifted
through th e instruction reg ister through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all 0s.
EXTEST allows circuitry external to the QuadPort DSE device
package to be tested. Boundary-scan register cells at output pins
are use d to appl y test stim uli, while thos e at in put pins captur e
test results.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the identification register. It also places the
identification register between the TDI and TDO pins and
allows the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state. The IDCODE
instruction is loaded into the instruction register upon
power-up or whenever the TAP controller is given a test logic
reset state.
High-Z
The High-Z instruction causes the bypass register to be
connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all QuadPort
DSE device outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PR ELOAD i s a 1149.1 mand atory instru ction. When
the SAMPLE/PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The us er must b e aware that the TAP c ontroller clo ck can only
oper ate at a frequen cy up to 10 MHz, while the QuadPort DS E
devic e clock operate s more than an order o f magnitude fast er .
Becaus e there is a larg e dif fer ence in the clock frequ encie s, it
is possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal w hi le in tran si tio n (m eta st abl e s tate). This w i ll not ha rm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the QuadPort DSE device signal
must be stabilized long enough to meet the TAP controller’s
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 27 of 37
capture set-up plus hold times. Once the data is captured, it is
possible to shift out the data by putting the TAP into the
Shift-DR state. This places the boundary scan register
betwe en the TDI and T DO pins. If th e TAP controlle r goes into
the Update-DR state, the sampled data will be updated.
BYPASS
When the BYPASS instruction is loaded in the instruction
regi ste r and th e TAP is pla ce d in a Shi ft-DR sta te, the by pas s
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
CLAMP
The optional CLAMP ins truction allows the state of t he signal s
driven from Qua dPort DSE devic e pins to be de termin ed from
the boundary-scan register while the BYPASS register is
selected as the serial path between TDI and TDO. CLAMP
controls boundary cells to 1 or 0.
CYBIST
CYBIST i nstruc tion p rovi des t he use r wit h a me ans o f runni ng
a user-accessible self-test function within the QuadPort DSE
device as a result of a single instruction. This permits all
components on a board that offer the CYBIST instruction to
execute their self-tests concurrently, providing a quick check
for the boa rd. The Q uadPort DSE de vice M BIST provi des two
modes o f o pera tio n once the TAP controller is l oa ded with the
CYBIST instruction:
Non-Debug Mode (Go-NoGo)
The non-debug mode is a go-nogo test used simply to run
BIST and obtain pass-fail information after the test is run. In
addition to that, the total number of failures encountered can
be obtained. This information is used to aid the debug mode
(explained next) of operation. The pass-fail information and
failure count is scanned out using the JTAG interface. An
MBIST Result Register (MRR) will be used to store the
pass-fail results. The MRR is a 25-bit register that will be
connected between TDI and TDO during the internal scan
(INT_SCAN) operatio n. The MRR will contain the total number
of fail read cycles of the entire MBIST sequence. MRR[0] (bit
0) is the Pass/Fail bit. A “1” indicates some type of failure
occurred, and a “0” indicates entire memory pass.
In order to run BIST in non-debug mode, the two-bit MBIST
Control Register (MCR) is loaded with the default value “00”,
and the TAP controller ’s finite state machine (FSM), which is
synchronous to TCK, transitions to Run Test/Idle state. The
entire MBIST test will be performed with a deterministic
number of TCK cycles depending on the TCK and CLKBIST
frequency.
tCYC is total number of TCK cycles required to run MBIST.
SPC is the Synchronization Padding Cycles (4–6 cycles).
m is a constant represents the number of read and write opera-
tions required to run MBIST algorithms (31195136).
Once the entire MBIST sequence is completed, supplying
extra TCK o r CLKBIST cycles will have no ef fect on the MBIST
controller state or the pass-fail status.
Debug Mode
With the C YBIST in struction lo ade d and the MCR lo ade d w i th
the val ue of “01,” and the FSM transitions to RUN_TEST/IDLE
state, the MBIST goes into CYBIST-debug mode. The debug
mode will be used to provide complete failure analysis infor-
mation at the board level. It is recommended that the user run s
the no n-debug mode first and then the debu g mode in order to
save test time and to set an upper bound on the number of
scan outs that will b e needed . The fai lure data will b e scanned
out automatically once a failure occurs using the JTAG TAP
interface. The failure data will be represented by a 100-bit
packet given below. The 100-bit Memory Debug Register
(MDR) will be connected between TDI and TDO, and will be
shifted out on TDO, which is synchronized to TCK.
tCYC tCYC CLKBIST[]
tCYC TCK[]
-------------------------------------------- mSPC+×=
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 28 of 37
Figure 3 is a representation of the 100-bit MDR packet. The
packe t fol low s a tw o-bi t hea de r that has a logic “1” value, and
represents two TCK cycles. MDR[97:26] represent the BIST
comparator values of all four ports (each port has 18 data
lines). A value of “1” indicates a bit failure. The scanned out
data is from LSB to MSB. MDR[25:10] represent the failing
address (MSB to LSB). The state of the BIST controller is
scanned out using MDR[9:4]. Bit 2 is the Test Done bit. A “0”
in bit 2 means test no t com ple te. The user has to mon ito r this
bit at every packet to determine if more failure packets need
to be scanned out at the end of the BIST operations. If the
value is “0” then BIST must be repeated to capture the next
failing packet. If it is “1,” it means that the last failing packets
have been scanned out. A trailer similar to the header repre-
sents the end of a packet.
MCR_SCAN
This instruction will connect the Memory BIST Control
Register (MCR) between TDI and TDO. The default value
(upon m aster reset ) is “00.” Sh ift_DR state will allow modifying
the MCR to extend the MBIST functionality.
MBIST Control States
Thirty-five states are listed in Table 7. Four data algorithms are
used in debug mode: moving inversion (MIA), march_ 2 (M2A),
checkerboard (CBA), and unique address algorithm (UAA).
Only Port 1 can write MIA, M2A, and CBA data to the memory.
All four ports can read any algorithm data from the QuadPort
DSE device memory . Ports 2, 3, and 4 will only write UAA data.
Boundary Scan Cells (BSC)
Table 9 lists all QuadPort DSE family I/Os with their associated
BSC. Note that the cells have even numbers. Every I/O has
two boundary scan cells. Bidirectional signals (address lines,
datalines) require two cells so that one (the odd cell) is used
to control a three-state buffer. Input only and output only
signals have an extra dummy cell (odd cells) that are used to
ease device layout.
1 1
1 1
97
99 98
P4_IO(17-9) P3_IO(17-9) P1_IO(17-9)P2_IO(17-9)
P4_IO(8-0) P3_IO(8-0) P1_IO(8-0)P2_IO(8-0)
A(15-0)
MBIST_State
P/F
62
61 26
25 10
94
3
2
10
TD
Figure 3. MBIST Debug Register Packet
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 29 of 37
TAP Contr oller State Diagram (FSM)[59]
Note:
59. The “0”/”1” next to each state represents the va lue at TMS at the rising edge of TCK.
TEST-LOGIC
RESET
RUN_TEST/
IDLE SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
01
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 30 of 37
JTAG/BIST TAP Controller Block Diagram
Table 4. I dentification Regist er Definition s
Instruction Field Value Description
Revision N umber (31:28) 1h Reserved for version number
Cypress Device ID (27:12) C000h Defines Cypress part number
Cypress JED EC ID (11:1) 34h Allows uni que iden tifi ca tio n of QuadPo rt DS E device v end or
ID Register Presence (0) 1Indicate the presence of an ID register
0
3 2 1 0
24 23 0
31 30 29 0
99 0
0391
Bypass Register (BYR)
Instructi on Register (IR)
Identification Register (IDR)
Boundary Scan Register (BSR)
MBIST Result Register (MRR)
MBIST Debug Register (MDR)
TDI Selection
Circuitry TDO
TCK
TMS
TAP
CONTROLLER
BIST
CONTROLLER
MRST
MEMORY
CELL
CLKBIST
MBIST Control Register (MCR)
(MUX)
1 0
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 31 of 37
Table 5. Scan Regis t ers Si ze s
Register Name Bit Size
Instruction (IR) 4
Bypass (BYR) 1
Identification (IDR) 32
MBIST Control (MCR) 2
MBIST Result (MRR) 25
MBIST Debug (MDR) 100
Boundary Scan (BSR) 392
Table 6. Instruct ion Iden tifica tion Codes
Instruction Code Description
EXTEST 0000 Captures the Input/Output ring contents. Places the bo undary scan register (BSR)
betwe en the TDI and TD O.
BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.
IDCODE 0111 Loads the ID register (IDR) with the vendor ID code and places the register
betwee n TDI and TDO.
HIGHZ 0110 Places the BYR between TDI and TDO. Forces all QuadPort DSE device output
drivers to a High-Z state.
CLAMP 0101 Controls boundary to 1/0. Uses BYR.
SAMPLE/PRELOAD 0001 Captures the Input/Output ring contents. Places the boundary scan register (BSR)
between TDI and TDO.
CYBIST 1000 Invokes MBIST. Places the MBIST Debug register (MDR) between TDI and TDO.
INT_SCAN 0010 Scans out pass-fail information. Places MBIST Result Register (MRR) between TDI
and TDO.
MCR_SCAN 0011 Presets CYBIST mode. Places MBIST Control Register (MCR) between TDI and
TDO.
RESERVED All other codes Seven combinations are reserved. Do not use other than the above.
Table 7. MBIST Control States
States Code State Name Description
000001 movi_zeros Port 1 write all zeros to the QuadPort DSE device memory using Moving
Inversion Algo rith m (MIA).
000011 movi_1_upcnt Up count from 0 to 64K (depth of QuadPort DSE device). All ports read 0s,
then Port 1 writes 1s to all memory locations using MIA, then all ports read
1s. MIA read0_write1_read1 (MIA_r0w1r1).
000010 movi_0_upcnt Up count from 0 to 64K. All ports rea d 1s, then Port 1 write s 0s, then all ports
read 0s (MIA _r1w0 r0).
000110 movi_1_downcnt Down count from 64K to 0. MIA_r0w1r1.
000111 movi_0_downcnt Down count MIA_r1w0r0.
000101 movi_read Read all 0s.
000100 mar2_zeros Port 1 write all zeros to memory using March2 Algorithm (M2A).
001100 mar2_1_upcnt Up count M2A_r0w1r1.
001101 mar2_0_upcnt Up count M2A_r1w0r0.
001111 mar2_1_downcnt Down count M2A_r0w1r1.
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 32 of 37
001110 mar2_0_downcnt Down count M2A_r1w0r0.
001010 mar2_read Read all 0s.
001011 chkr_w Port 1 writes topological checkerboard data to memory.
001001 chkr_r All ports read topological checkerboard data.
001000 n_chkr_w Po rt 1 write invers e topo log ic al che ck erb oard data.
011000 n_chkr_r All ports read inverse topological checkerboard data.
011001 uaddr_zeros2 Port 2 write all zeros to memory using Unique Address Algorithm (UAA).
011011 uaddr_write2 Port 2 writes every address value into its memory location (UAA).
011010 uaddr_read2 All ports read UAA data.
011110 uaddr_ones2 Port 2 writes all ones to memory.
011111 n_uaddr_write2 Port 2 writes inverse address value into memory.
011101 n_uaddr_read2 All ports read inverse UAA data.
011001 uaddr_zeros3 Port 3 write all zeros to memory using Unique Address Algorithm (UAA).
011011 uaddr_write3 Port 3 writes every address value into its memory location (UAA).
011010 uaddr_read3 All ports read UAA data.
011110 uaddr_ones3 Port 3 writes all ones to memory.
011111 n_uaddr_write3 Port 3 writes inverse address value into memory.
011101 n_uaddr_read3 All ports read inverse UAA data.
011001 uaddr_zeros4 Port 4 write all zeros to memory using Unique Address Algorithm (UAA).
011011 uaddr_write4 Port 4 writes every address value into its memory location (UAA).
011010 uaddr_read4 All ports read UAA data.
011110 uaddr_ones4 Port 4 writes all ones to memory.
011111 n_uaddr_write4 Port 4 writes inverse address value into memory.
011101 n_uaddr_read4 All ports read inverse UAA data.
110010 complete Test complete.
Table 7. MBIST Control States (continued)
States Code State Name Description
Table 8. MBIST Control Register (MCR)
MCR[1:0] Mode
00 Non-Debug
01 Debug
10 Reserved
11 Reserved
Table 9. Boundary Scan Order
Cell # Signal Name Bump (Ball) ID
2A0_P4 K20
4A1_P4 J19
6A2_P4 J18
8A3_P4 H20
10 A4_P4 H19
12 A5_P4 G19
14 A6_P4 G18
16 A7_P4 F20
18 A8_P4 F19
20 A9_P4 F18
22 A10_P4 E20
24 A11_P4 E19
26 A12_P4 D19
28 A13_P4 D18
30 A14_P4 C20
32 A15_P4 C19
34 CNTINT_P4 F17
36 CNTRST_P4 K18
38 MKLD_P4 H18
40 CNTLD_P4 H17
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 33 of 37
42 CNTINC_P4 G17
44 CNTRD_P4 E17
46 MKRD_P4 E18
48 LB_P4 A20
50 UB_P4 B19
52 OE_P4 D17
54 R/W_P4 C16
56 CE1_P4 C18
58 CE0_P4 C17
60 INT_P4 K19
62 CLK_P4 K17
64 A0_P3 L20
66 A1_P3 M19
68 A2_P3 M18
70 A3_P3 N20
72 A4_P3 N19
74 A5_P3 P19
76 A6_P3 P18
78 A7_P3 R20
80 A8_P3 R19
82 A9_P3 R18
84 A10_P3 T20
86 A11_P3 T19
88 A12_P3 U19
90 A13_P3 U18
92 A14_P3 V20
94 A15_P3 V19
96 CNTINT_P3 R17
98 CNTRST_P3 L18
100 MKLD_P3 N18
102 CNTLD_P3 N17
104 CNTINC_P3 P17
106 CNTRD_P3 T17
108 MKRD_P3 T18
110 LB_P3 Y20
112 UB_P3 W19
114 OE_P3 U17
116 R/W_P3 V16
118 CE1_P3 V18
120 CE0_P3 V17
122 INT_P3 L19
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
124 CLK_P3 M17
126 IO0_P4 Y15
128 IO1_P4 W15
130 IO2_P4 Y16
132 IO3_P4 W16
134 IO4_P4 Y17
136 IO5_P4 W17
138 IO6_P4 Y18
140 IO7_P4 W18
142 IO8_P4 Y19
144 IO0_P3 V12
146 IO1_P3 Y11
148 IO2_P3 W12
150 IO3_P3 Y12
152 IO4_P3 W13
154 IO5_P3 Y13
156 IO6_P3 V15
158 IO7_P3 Y14
160 IO8_P3 W14
162 IO0_P1 Y6
164 IO1_P1 W6
166 IO2_P1 Y5
168 IO3_P1 W5
170 IO4_P1 Y4
172 IO5_P1 W4
174 IO6_P1 Y3
176 IO7_P1 W3
178 IO8_P1 Y2
180 IO0_P2 V9
182 IO1_P2 Y10
184 IO2_P2 W9
186 IO3_P2 Y9
188 IO4_P2 W8
190 IO5_P2 Y8
192 IO6_P2 V6
194 IO7_P2 Y7
196 IO8_P2 W7
198 A0_P2 L1
200 A1_P2 M2
202 A2_P2 M3
204 A3_P2 N1
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 34 of 37
206 A4_P2 N2
208 A5_P2 P2
210 A6_P2 P3
212 A7_P2 R1
214 A8_P2 R2
216 A9_P2 R3
218 A10_P2 T1
220 A11_P2 T2
222 A12_P2 U2
224 A13_P2 U3
226 A14_P2 V1
228 A15_P2 V2
230 CNTINT_P2 R4
232 CNTRST_P2 L3
234 MKLD_P2 N3
236 CNTLD_P2 N4
238 CNTINC_P2 P4
240 CNTRD_P2 T4
242 MKRD_P2 T3
244 LB_P2 Y1
246 UB_P2 W2
248 OE_P2 U4
250 R/W_P2 V5
252 CE1_P2 V3
254 CE0_P2 V4
256 INT_P2 L2
258 CLK_P2 M4
260 A0_P1 K1
262 A1_P1 J2
264 A2_P1 J3
266 A3_P1 H1
268 A4_P1 H2
270 A5_P1 G2
272 A6_P1 G3
274 A7_P1 F1
276 A8_P1 F2
278 A9_P1 F3
280 A10_P1 E1
282 A11_P1 E2
284 A12_P1 D2
286 A13_P1 D3
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
288 A14_P1 C1
290 A15_P1 C2
292 CNTINT_P1 F4
294 CNTRST_P1 K3
296 MKLD_P1 H3
298 CNTLD_P1 H4
300 CNTINC_P1 G4
302 CNTRD_P1 E4
304 MKRD_P1 E3
306 LB_P1 A1
308 UB_P1 B2
310 OE_P1 D4
312 R/W_P1 C5
314 CE1_P1 C3
316 CE0_P1 C4
318 INT_P1 K2
320 CLK_P1 K4
322 IO9_P2 A6
324 IO10_P2 B6
326 IO11_P2 A5
328 IO12_P2 B5
330 IO13_P2 A4
332 IO14_P2 B4
334 IO15_P2 A3
336 IO16_P2 B3
338 IO17_P2 A2
340 IO9_P1 C9
342 IO10_P1 A10
344 IO11_P1 B9
346 IO12_P1 A9
348 IO13_P1 B8
350 IO14_P1 A8
352 IO15_P1 C6
354 IO16_P1 A7
356 IO17_P1 B7
358 IO9_P3 A15
360 IO10_P3 B15
362 IO11_P3 A16
364 IO12_P3 B16
366 IO13_P3 A17
368 IO14_P3 B17
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 35 of 37
370 IO15_P3 A18
372 IO16_P3 B18
374 IO17_P3 A19
376 IO9_P4 C12
378 IO10_P4 A11
380 IO11_P4 B12
382 IO12_P4 A12
384 IO13_P4 B13
386 IO14_P4 A13
388 IO15_P4 C15
390 IO16_P4 A14
392 IO17_P4 B14
Table 9. Boundary Scan Order (continued)
Cell # Signal Name Bump (Ball) ID
Order in g In fo rmat io n
10 Gb/s 3.3V QuadPort DSE Family 1 Mb (64K × 18)
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
133 CY7C0430BV-133BGC BG272
272-ball Grid Array (BGA )
Commercial
CY7C0430BV-133BGI BG272
272-ball Grid Array (BGA )
Industrial
100 CY7C0430BV-100BGC BG272
272-ball Grid Array (BGA )
Commercial
CY7C0430BV-100BGI BG272
272-ball Grid Array (BGA )
Industrial
10 Gb/s 3.3V QuadPort DSE Family 1/2 Mb (32K x 18)
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
133 CY7C04312BV-133BGC BG272
272-ball Grid Array (BGA )
Commercial
100 CY7C04312BV-100BGC BG272
272-ball Grid Array (BGA )
10 Gb/s 3.3V QuadPort DSE Family 1/4 Mb (16K x 18)
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
133 CY7C04314BV-133BGC BG272
272-ball Grid Array (BGA )
Commercial
100 CY7C04314BV-100BGC BG272
272-ball Grid Array (BGA )
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 36 of 37
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
QuadPort is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Package Diagram
272-ball Ball Grid Array (27 x 27 x 1.27 mm) BG272
51-85130
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A Page 37 of 37
Document Title: CY7C430BV, CY7C04312BV, CY7C04314BV 10 Gb/s 3.3V QuadPort DSE Family
Document Number: 38-06027
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 109906 09/10/01 SZV Change from Spec number: 38-01052 to 38-06027
*A 115042 05/23/02 FSG Remove Preliminary, TM from DSE.
Change RUNBIST to CYBIST.
Updated ISB values.
Added notes 9 and 14.
Increased commerci al prim e bin to 135 MHz.
