VIN
R1
R2
VREF
VCC
VOUT
+
-
C1 =
0.1µF
C2 =
10µF
LMV7271
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LMV7271/LMV7275/LMV7272 Single & Dual, 1.8V Low Power Comparators with Rail-to-Rail
Input
Check for Samples: LMV7271
1FEATURES DESCRIPTION
The LMV727X are rail-to-rail input low power
2• (VS= 1.8V, TA= 25°C, Typical values unless comparators, which are characterized at supply
specified). voltage 1.8V, 2.7V and 5.0V. They consume only 9uA
• Single or Dual Supplies supply current per channel while achieving a 800ns
• Ultra low supply current 9µA per channel propagation delay.
• Low input bias current 10nA The LMV7271/LMV7275 (single) are available in
SC70 and SOT-23 packages. The LMV7272 (dual) is
• Low input offset current 200pA available in DSBGA package. With these tiny
• Low guaranteed VOS 4mV packages, the PC board area can be significantly
• Propagation delay 880ns (20mV overdrive) reduced. They are ideal for low voltage, low power
• Input common mode voltage range 0.1V and space critical designs.
beyond rails The LMV7271/LMV7272 both feature a push-pull
• LMV7272 is available in DSBGA package output stage which allows operation with minimum
power consumption when driving a load. The
APPLICATIONS LMV7275 features an open drain output stage that
allows for wired-OR configurations. The open drain
• Mobile communications output also offers the advantage of allowing the
• Laptops and PDA's output to be pulled to any voltage up to 5.5V,
regardless of the supply voltage of the LMV7275.
• Battery powered electronics
• General purpose low voltage applications The LMV727X are built with Texas Instruments'
advance submicron silicon-gate BiCMOS process.
They all have bipolar inputs for improved noise
performance and CMOS outputs for rail-to-rail output
swing.
Typical Circuit
Figure 1. Threshold Detector
Part Number Single/Dual Package Output
LMV7271 Single SC70, SOT-23 Push/Pull
LMV7272 Dual DSBGA Push/Pull
LMV7275 Single SC70, SOT-23 Open Drain
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMV7271
SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
ESD Tolerance 2KV (3)
200V (4)
VIN Differential ±Supply Voltage
Supply Voltage (V+- V−) 6V
Voltage at Input/Output pins V++0.1V, V−−0.1V
Soldering Information
Infrared or Convection (20 sec.) 235°C
Wave Soldering (10 sec.) 260°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (5) +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
(3) Human body model, 1.5kΩin series with 100pF.
(4) Machine Model, 0Ωin series with 200pF.
(5) Typical values represent the most likely parametric norm.
Operating Ratings (1)
Supply Voltage Range 1.8V to 5.5V
Temperature Range (2) −40°C to +85°C
Package Thermal Resistance (2)
SOT-23 325°C/W
SC70 265°C/W
8-Bump DSBGA 220°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board.
1.8V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 1.8V, V−= 0V. Boldface limits apply at the temperature
extremes. Min Typ Max
Symbol Parameter Condition Units
(1) (2) (1)
0.3 4
VOS Input Offset Voltage mV
6
TC VOS Input Offset Temperature Drift VCM = 0.9V (3) 20 uV/°C
IBInput Bias Current 10 nA
IOS Input Offset Current 200 pA
9 12
LMV7271/LMV7275 µA
14
ISSupply Current 18 25
LMV7272 µA
28
(1) All limits are guaranteed by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
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1.8V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 1.8V, V−= 0V. Boldface limits apply at the temperature
extremes. Min Typ Max
Symbol Parameter Condition Units
(1) (2) (1)
Sourcing, VO= 0.9V 3.5 6
(LMV7271/LMV7272 only)
ISC Output Short Circuit Current mA
Sinking, VO= 0.9V 4 6
IO= 0.5mA 1.7 1.74
Output Voltage High
VOH V
(LMV7271/LMV7272 only) IO= 1.5mA 1.47 1.63
IO=−0.5mA 52 100
VOL Output Voltage Low mV
IO=−1.5mA 166 220
1.9 V
VCM Input Common Mode Voltage Range CMRR > 45 dB −0.1 V
CMRR Common Mode Rejection Ratio 0 < VCM < 1.8V 46 78 dB
PSRR Power Supply Rejection Ratio V+= 1.8V to 5V 55 80 dB
ILEAKAGE Output Leakage Current VO= 1.8V (LMV7275 only) 2 pA
1.8V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 1.8V, V−= 0V, VCM = 0.5V, VO= V+/2 and RL> 1MΩto
V−.Boldface limits apply at the temperature extremes. Min Typ Max
Symbol Parameter Condition Units
(1) (2) (1)
Input Overdrive = 20mV 880 ns
Load = 50pF//5kΩ
Propagation Delay
tPHL (High to Low) Input Overdrive = 50mV 570 ns
Load = 50pF//5kΩ
Input Overdrive = 20mV 1100 ns
Load = 50pF//5kΩ
Propagation Delay
tPLH (Low to High) Input Overdrive = 50mV 800 ns
Load = 50pF//5kΩ
(1) Machine Model, 0Ωin series with 200pF.
(2) All limits are guaranteed by testing or statistical analysis.
2.7V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 2.7V, V−= 0V. Boldface limits apply at the temperature
extremes. Min Typ Max
Symbol Parameter Conditions Units
(1) (2) (1)
0.3 4
VOS Input Offset Voltage mV
6
TC VOS Input Offset Temperature Drift VCM = 1.35V (3) 20 µV/°C
IBInput Bias Current 10 nA
IOS Input offset Current 200 pA
9 13
LMV7271/LMV7275 µA
15
ISSupply Current 18 25 µA
LMV7272 28
Sourcing, VO= 1.35V 10 15
(LMV7271/LMV7272 only)
ISC Output Short Circuit Current mA
Sinking, VO= 1.35V 10 15
(1) Machine Model, 0Ωin series with 200pF.
(2) All limits are guaranteed by testing or statistical analysis.
(3) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
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2.7V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 2.7V, V−= 0V. Boldface limits apply at the temperature
extremes. Min Typ Max
Symbol Parameter Conditions Units
(1) (2) (1)
IO= 0.5mA 2.63 2.66
Output Voltage High
VOH V
(LMV7271/LMV7272 only) IO= 2.0mA 2.48 2.55
IO=−0.5mA 50 70
VOL Output Voltage Low mV
IO=−2mA 155 220
2.8 V
VCM Input Common Voltage Range CMRR > 45dB −0.1 V
CMRR Common Mode Rejection Ratio 0 < VCM < 2.7V 46 78 dB
PSRR Power Supply Rejection Ratio V+= 1.8V to 5V 55 80 dB
ILEAKAGE Output Leakage Current VO= 2.7V (LMV7275 only) 2 pA
2.7V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = 0.5V, VO= V+/2 and RL> 1MΩto
V−.Boldface limits apply at the temperature extremes. Min Typ Max
Symbol Parameter Condition Units
(1) (2) (1)
Input Overdrive = 20mV 1200 ns
Load = 50pF//5kΩ
Propagation Delay
tPHL (High to Low) Input Overdrive = 50mV 810 ns
Load = 50pF//5kΩ
Input Overdrive = 20mV 1300 ns
Load = 50pF//5kΩ
Propagation Delay
tPLH (Low to High) Input Overdrive = 50mV 860 ns
Load = 50pF//5kΩ
(1) Machine Model, 0Ωin series with 200pF.
(2) All limits are guaranteed by testing or statistical analysis.
5.0V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 5V, V−= 0V. Boldface limits apply at the temperature
extremes. Min Typ Max
Symbol Parameter Conditions Units
(1) (2) (1)
0.3 4
VOS Input Offset Voltage mV
6
TC VOS Input Offset Temperature Drift VCM = 2.5V (3) 20 µV/°C
IBInput Bias Current 10 nA
IOS Input Offset Current 200 pA
10 14
LMV7271/LMV7275 µA
16
ISSupply Current 20 27
LMV7272 µA
30
Sourcing, VO= 2.5V 18 34
(LMV7271/LMV7272 only)
ISC Output Short Circuit Current mA
Sinking, VO= 2.5V 18 34
IO= 0.5mA 4.93 4.96
Output Voltage High
VOH V
(LMV7271/LMV7272 only) IO= 4.0mA 4.675 4.77
(1) Machine Model, 0Ωin series with 200pF.
(2) All limits are guaranteed by testing or statistical analysis.
(3) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
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A1
B1
C1 C3
A3
B3
A2
C2
OUT A
-IN A
+IN A
V+
V-
OUT B
-IN B
+ IN B
V+
VOUT
+IN
-IN
5
4
1
2
3
GND
LMV7271
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SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
5.0V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 5V, V−= 0V. Boldface limits apply at the temperature
extremes. Min Typ Max
Symbol Parameter Conditions Units
(1) (2) (1)
IO=−0.5mA 27 70
VOL Output Voltage Low mV
IO=−4.0mA 225 315
5.1
VCM Input Common Voltage Range CMRR > 45dB V
−0.1
CMRR Common Mode Rejection Ratio 0 < VCM < 5.0V 46 78 dB
PRSS Power Supply Rejection Ratio V+= 1.8V to 5V 55 80 dB
ILEAKAGE Output Leakage Current VO= 5V (LMV7275 only) 2 pA
5.0V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 5.0V, V−= 0V, VCM = 0.5V, VO= V+/2 and RL> 1MΩto
V−.Boldface limits apply at the temperature extremes. Min Typ Max
Symbol Parameter Condition Units
(1) (2) (1)
Input Overdrive = 20mV 2100 ns
Load = 50pF//5kΩ
Propagation Delay
tPHL (High to Low) Input Overdrive = 50mV 1380 ns
Load = 50pF//5kΩ
Input Overdrive = 20mV 1800 ns
Load = 50pF//5kΩ
Propagation Delay
tPLH (Low to High) Input Overdrive = 50mV 1100 ns
Load = 50pF//5kΩ
(1) Machine Model, 0Ωin series with 200pF.
(2) All limits are guaranteed by testing or statistical analysis.
CONNECTION DIAGRAMS
Figure 2. 5-Pin SOT-23/SC70 (LMV7271/LMV7275) Figure 3. 8-Bump DSBGA (LMV7272)
(Top View) (bump side down)
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-2.5 -2 -1 0 1 2 2.5
-800
-400
0
400
800
VOS (PV)
VCM (V)
VSUPPLY = ±2.5V
85°C
-40°C
25°C
1.8 2.44 3.08 3.72 4.36 5.0
0
10
20
30
40
SHORT CIRCUIT OUTPUT CURRENT (mA)
SUPPLY VOLTAGE (V)
SOURCE
SINK
-0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9
-800
-400
0
400
800
VOS (PV)
VCM (V)
VSUPPLY = ±0.9V
25°C
85°C
-40°C
-1.35 -0.9 -0.45 0 0.45 0.9 1.35
-800
-400
0
400
800
VOS (PV)
VCM (V)
VSUPPLY = ±1.35V
85°C
-40°C
25°C
LMV7271
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TYPICAL PERFORMANCE CHARACTERISTICS
(TA= 25°C, Unless otherwise specified).
VOS VOS
vs. vs.
VCM VCM
Figure 4. Figure 5.
VOS Short Circuit
vs. vs.
VCM Supply Voltage
Figure 6. Figure 7.
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1.5 2 2.5 3 3.5 4 4.5
VSUPPLY (V)
0
5
10
15
20
25
SUPPLY CURRENT (PA)
5
VOUT = LOW
85°C
25°C
-40°C
1.5 2 2.5 3 3.5 4 4.5
VSUPPLY (V)
0
5
10
15
20
25
SUPPLY CURRENT (PA)
5
VOUT = HIGH
85°C
25°C
-40°C
1.8 2.44 3.08 3.72 4.36 5.0
5
6
7
8
9
10
SUPPLY CURRENT (PA)
SUPPLY VOLTAGE (V)
85°C
25°C
-40°C
85°C
LMV7271
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SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(TA= 25°C, Unless otherwise specified).
Supply Current Supply Current
vs. vs.
Supply Voltage (LMV7271) Supply Voltage (LMV7272)
Figure 8. Figure 9.
Supply Current Output Positive Swing
vs. vs.
Supply Voltage (LMV7272) VSUPPLY
Figure 10. Figure 11.
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00.5 1 1.5 2 2.5 3 3.5 4
ISINK (mA)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
VOUT - V- (V)
VSUPPLY = 1.8V
85°C
25°C
-40°C
0 0.5 1 1.5 2 2.5 3 3.5 4
0
0.5
V+ - VOUT (V)
ISOURCE (mA)
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45 VSUPPLY = 2.7V
85°C
25°C
-40°
00.5 1 1.5 2 2.5 3 3.5 4
ISOURCE (mA)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
V+ - VOUT (V)
VSUPPLY = 1.8V
85°C
25°C
-40°C
1.8 2.3 2.8 3.3 3.8 4.3 4.8
VSUPPLY (V)
0
100
200
300
400
500
600
VOUT - V- (mV)
ISINK
4mA
2mA 1.5mA
0.5mA
LMV7271
SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(TA= 25°C, Unless otherwise specified).
Output Negative Swing Output Positive Swing
vs. vs.
VSUPPLY ISOURCE
Figure 12. Figure 13.
Output Negative Swing Output Positive Swing
vs. vs.
ISINK ISOURCE
Figure 14. Figure 15.
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00.5 1 1.5 2 2.5 3 3.5 4
ISOURCE (mA)
0
0.1
0.2
0.3
0.4
V+ - VOUT (V)
85°C
25°C
-40°C
VSUPPLY = 5V
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV 20mV
VCC = 1.8V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
0 0.5 1 1.5 2 2.5 3 3.5 4
0
0.5
VOUT - V- (V)
ISINK (mA)
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45 85°C
25°C
-40°C
VSUPPLY = 2.7V
00.5 1 1.5 2 2.5 3 3.5 4
ISINK (mA)
0
0.1
0.2
0.3
0.4
VOUT - V- (V)
85°C
25°C
-40°C
VSUPPLY = 5V
LMV7271
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SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(TA= 25°C, Unless otherwise specified).
Output Negative Swing Output Negative Swing
vs. vs.
ISINK ISINK
Figure 16. Figure 17.
Output Positive Swing
vs.
ISOURCE Propagation Delay (tPLH)
Figure 18. Figure 19.
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010 100 1000
OVERDRIVE (mV)
0
1
2
3
4
5
6
7
8
tPHL (PS)
VS = 1.8V
VS = 2.7V
VS = 5V
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV
20mV
VCC = 5.0 V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV
20mV
VCC = 2.7 V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV
20mV
VCC = 5.0V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV
20mV
VCC = 1.8 V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV
20mV
VCC = 2.7V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
LMV7271
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(TA= 25°C, Unless otherwise specified).
Propagation Delay (tPHL) Propagation Delay (tPLH)
Figure 20. Figure 21.
Propagation Delay (tPHL) Propagation Delay (tPLH)
Figure 22. Figure 23.
tPHL
vs.
Propagation Delay (tPHL) Overdrive
Figure 24. Figure 25.
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110 100 1000
OVERDRIVE (mV)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
tPLH (PS)
VS = 5V
VS = 2.7V
VS = 1.8V
LMV7271
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SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(TA= 25°C, Unless otherwise specified). tPLH
vs.
Overdrive
Figure 26.
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VOLTS
VREF
VO
TIME
VIN
V+
VREF
VIN
VO
-
+
V-
LMV7271
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APPLICATION NOTES
BASIC COMPARATOR
A comparator is often used to convert an analog signal to a digital signal. As shown in Figure 28, the comparator
compares an input voltage (VIN) to a reference voltage (VREF). If VIN is less than VREF, the output (VO) is low.
However, if VIN is greater than VREF, the output voltage (VO) is high.
Figure 27. LMV7271
Figure 28. LMV7271 Basic Comparator
RAIL-TO-RAIL INPUT STAGE
The LMV727X has an input common mode voltage range (VCM) of −0.1V below the V−to 0.1V above V+. This is
achieved by using paralleled PNP and NPN differential input pairs. When the VCM is near V+, the NPN pair is on
and the PNP pair is off. When the VCM is near V−, the NPN pair is off and the PNP pair is on. The crossover point
between the NPN and PNP input stages is around 950mV from V+. Since each input stage has its own offset
voltage (VOS), the VOS of the comparator becomes a function of the VCM. See curves for VOS vs. VCM in Typical
Performance Characteristics section. In application design, it is recommended to keep the VCM away from the
crossover point to avoid problems. The wide input voltage range makes LMV727X ideal in power supply
monitoring circuits, where the comparators are used to sense signals close to ground and power supplies.
OUTPUT STAGE
The LMV7271 and LMV7272 have a push-pull output stage. This output stage keeps the total system power
consumption to the absolute minimum. The only current consumed is the low supply current and the current
going directly into the load. When the output switches, both PMOS and NMOS at the output stage are on at the
same time for a very short time. This allows current to flow directly between V+and V−through output transistors.
The result is a short spike of current (shoot-through current) drawn from the supply and glitches in the supply
voltages. The glitches can spread to other parts of the board as noise. To prevent the glitches in supply lines,
power supply bypass capacitors must be installed. See section for supply bypassing in the Application Notes for
details.
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VA2 = VCC (R2||R3)
R1 + (R2||R3)
VA1 = VCC R2
(R1||R3) + R2
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SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
HYSTERESIS
It is a standard procedure to use hysteresis (positive feedback) around a comparator, to prevent oscillation, and
to avoid excessive noise on the output because the comparator is a good amplifier of its own noise.
Inverting Comparator with Hysteresis
The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage
VCC of the comparator (Figure 29). When VIN at the inverting input is less than VA, the voltage at the non-
inverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VOswitches as high
as VCC). The three network resistors can be represented as R1||R3in series with R2. The lower input trip voltage
VA1 is defined as
(1)
When VIN is greater than VA(VIN > VA), the output voltage is low and very close to ground. In this case the three
network resistors can be presented as R2//R3in series with R1. The upper trip voltage VA2 is defined as
(2)
The total hysteresis provided by the network is defined as
ΔVA= VA1 - VA2 (3)
A good typical value of ΔVAwould be in the range of 5 to 50mV. This is easily obtained by choosing R3as 1000
to 100 times (R1||R2) for 5V operation, or as 300 to 30 times (R1||R2) for 1.8V operation.
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SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
www.ti.com
Figure 29. Inverting Comparator with Hysteresis
Non-Inverting Comparator with Hysteresis
A non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the
inverting input (Figure 30). When VIN is low, the output is also low. For the output to switch from low to high, VIN
must rise up to VIN1, where VIN1 is calculated by
(4)
When VIN is high, the output is also high. To make the comparator switch back to its low state, VIN must equal
VREF before VAwill again equal VREF. VIN can be calculated by:
(5)
The hysteresis of this circuit is the difference between VIN1 and VIN2.
ΔVIN = VCCR1/R2(6)
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Product Folder Links: LMV7271
LMV7271
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SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
Figure 30. Non-Inverting Comparator with Hysteresis
CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS
Feedback to almost any pin of a comparator can result in oscillation. In addition, when the input signal is a slow
voltage ramp or sine wave, the comparator may also burst into oscillation near the crossing point. To avoid
oscillation or instability, PCB layout should be engineered thoughtfully. Several precautions are recommended:
1. Power supply bypassing is critical, and will improve stability and transient response. Resistance and
inductance from power supply wires and board traces increase power supply line impedance. When
supply current changes, the power supply line will move due to its impedance. Large enough supply line
shift will cause the comparator to mis-operate. To avoid problems, a small bypass capacitor, such as
0.1uF ceramic, should be placed immediately adjacent to the supply pins. An additional 6.8μF or greater
tantalum capacitor should be placed at the point where the power supply for the comparator is introduced
onto the board. These capacitors act as an energy reservoir and keep the supply impedance low. In dual
supply application, a 0.1μF capacitor is recommended to be placed across V+and V−pins.
2. Keep all leads short to reduce stray capacitance and lead inductance. It will also minimize any unwanted
coupling from any high-level signals (such as the output). The comparators can easily oscillate if the
output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows
up only during the output voltage transition intervals as the comparator changes states. Try to avoid a long
loop which could act as an inductor (coil).
3. It is a good practice to use an unbroken ground plane on a printed circuit board to provide all components
with a low inductive ground connection. Make sure ground paths are low-impedance where heavier
currents are flowing to avoid ground level shift. Preferably there should be a ground plane under the
component.
4. The output trace should be routed away from inputs. The ground plane should extend between the output
and inputs to act as a guard. This can be achieved by running a topside ground plane between the output
and inputs. A typical PCB layout is shown in Figure 31.
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Product Folder Links: LMV7271
LMV7272 (DSBGA)
(Bottom Layer)
C1 (Top Layer)
LMV7272
OUTB
-INB
+INB
V-
V+
OUTA
-INA
+INA
-INB
+INB
OUT B
-INA
+INA
OUT A
V-
V+
LMV7271
SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
www.ti.com
Figure 31. Typical PCB Layout
5. When the signal source is applied through a resistive network to one input of the comparator, it is usually
advantageous to connect the other input with a resistor with the same value, for both DC and AC
consideration. Input traces should be laid out symmetrically if possible.
6. All pins of any unused comparators should be tied to the negative supply.
DSBGA LIGHT SENSITIVITY
Exposing the DSBGA device to direct sunlight will cause mis-operation of the device. Light sources such as
Halogen lamps can also affect electrical performance if brought near to the device. The wavelengths, which have
the most detrimental effect, are reds and infrareds.
DSBGA MOUNTING
The DSBGA package requires specific mounting techniques, which are detailed in Application Note AN-1112
(SNVA009).
LMV7272 DSBGA to DIP Conversion Board
To facilitate characterization and testing, a DSBGA to DIP conversion board, LMV7272TLCONV, is available. It is
a 2-layer board, with the LMV7272 mounted on the bottom layer, and a capacitor (C1, between the positive and
negative supplies) added to the top layer.
Figure 32. LMV7272TLCONV Diagram
Typical Applications
UNIVERSAL LOGIC LEVEL SHIFTER
The output of LMV7275 is an unconnected drain of an NMOS device, which can be pulled up, through a resistor,
to any desired output level within the permitted power supply range. Hence, the following simple circuit works as
a universal logic level shifter, pulling up the signal to the desired level.
16 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV7271
VIN +
-
+VCC
R1
1k:
R2
1M:
C1
10PF
VOUT
-
+
VA
VB
REXT
LOGIC
OUT
LMV7275
+
-
1k:
1k:
LOGIC
IN
LMV7271
www.ti.com
SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
Figure 33. Logic Level Shifter
POSITIVE PEAK DETECTOR
A positive peak detect circuit is basically a comparator operated in a unity gain follower configuration, with a
capacitor as a load to maintain the highest voltage. A diode is added at the output to prevent the capacitor from
discharging through the pull-up resistor, and a 1MΩresistor added in parallel to the capacitor to provide a high
impedance discharge path. When the input VIN increases, the inverting input of the comparator follows it, thus
charging the capacitor. When it decreases, the cap discharges through the 1MΩresistor. The decay time can be
modified by changing the resistor. The output should be accessed through a follower circuit to prevent loading.
Figure 34. Positive Peak Detector
OR'ING THE OUTPUT
Since the output is an unconnected NMOS drain, many drains can be tied together, pulled up to VDD by a single
resistor to provide an output OR'ing function. If any of the comparator outputs is pulled low the output VOgoes
down.
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMV7271
VIN +
-
+VCC
R1
1M:
VOUT
+
-C1
10PF
-VCC
LMV7271
SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
www.ti.com
Figure 35. OR’ing the Outputs
NEGATIVE PEAK DETECTOR
For the negative detector, the output transistor of the comparator acts as a low impedance current sink. Since
there is no pull-up resistor, the only discharge path will be the 1MΩresistor and any load impedance used.
Decay time is changed by varying the 1MΩresistor.
Figure 36. Negative Peak Detector
SQUARE WAVE GENERATOR
A typical application for a comparator is as a square wave oscillator. The circuit below generates a square wave
whose period is set by the RC time constant of the capacitor C1and resistor R4. The maximum frequency is
limited by the large signal propagation delay of the comparator, and by the capacitive loading at the output,
which limits the output slew rate.
18 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV7271
VA2 = VCC (R2||R3)
R1 + (R2||R3)
VA1 = VCC.R2
R2 + R1||R3
C1 = 750pF
R4 = 100k:
V+
4.3k:
VO
R2 = 100k:
R3 = 100k:
R1 = 100k:VA
+
-
VC
V+
0f |10KHz
LMV7271
www.ti.com
SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
Figure 37. Squarewave Oscillator
To analyze the circuit, consider it when the output is high. That implies that the inverted input (VC) is lower than
the non-inverting input (VA). This causes the C1to get charged through R4, and the voltage VCincreases till it is
equal to the non-inverting input. The value of VAat this point is
(7)
If R1= R2= R3, then VA1 = 2VCC/3
At this point the comparator switches pulling down the output to the negative rail. The value of VAat this point is
(8)
If R1= R2= R3, then VA2 = VCC/3
The capacitor C1now discharges through R4, and the voltage VCdecreases till it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1from 2VCC/3 to VCC/3, which is given by R4C1.ln2. Hence the formula for the frequency is:
F = 1/(2·R4·C1·ln2)
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMV7271
LMV7271
SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
www.ti.com
REVISION HISTORY
Changes from Revision G (February 2013) to Revision H Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 19
20 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV7271
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV7271MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 C25A
LMV7271MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C25A
LMV7271MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C25A
LMV7271MG NRND SC70 DCK 5 1000 TBD Call TI Call TI -40 to 85 C34
LMV7271MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C34
LMV7271MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C34
LMV7272TL/NOPB ACTIVE DSBGA YZR 8 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 C
01
LMV7272TLX/NOPB ACTIVE DSBGA YZR 8 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 C
01
LMV7275MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 C26A
LMV7275MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C26A
LMV7275MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C26A
LMV7275MG NRND SC70 DCK 5 1000 TBD Call TI Call TI -40 to 85 C35
LMV7275MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C35
LMV7275MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C35
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV7271MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7271MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7271MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7271MG SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7271MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7271MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7272TL/NOPB DSBGA YZR 8 250 178.0 8.4 1.7 1.7 0.76 4.0 8.0 Q1
LMV7272TLX/NOPB DSBGA YZR 8 3000 178.0 8.4 1.7 1.7 0.76 4.0 8.0 Q1
LMV7275MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7275MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7275MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7275MG SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7275MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7275MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV7271MF SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV7271MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV7271MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV7271MG SC70 DCK 5 1000 210.0 185.0 35.0
LMV7271MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
LMV7271MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
LMV7272TL/NOPB DSBGA YZR 8 250 210.0 185.0 35.0
LMV7272TLX/NOPB DSBGA YZR 8 3000 210.0 185.0 35.0
LMV7275MF SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV7275MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV7275MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV7275MG SC70 DCK 5 1000 210.0 185.0 35.0
LMV7275MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
LMV7275MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
MECHANICAL DATA
YZR0008xxx
www.ti.com
TLA08XXX (Rev C)
0.600±0.075 D
E
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215045/A 12/12
D: Max =
E: Max =
1.55 mm, Min =
1.55 mm, Min =
1.489 mm
1.489 mm
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