1CY M17 30 CYM1730 64K x 24 Static RAM Module Features using six 32K x 8 static RAMs in SOJ packages mounted onto an epoxy laminate board with pins. * High-density 1.5M SRAM module * High-speed CMOS SRAMs -- Access time of 25 ns * 56-pin, 0.5-inch-high ZIP package * Low active power -- 2.8W (max. for tAA = 25 ns) * SMD technology * TTL-compatible inputs and outputs * Commercial temperature range * Small PCB footprint -- 1.05 sq. in. Writing to the device is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the input/output pins (I/O0 through I/O23) of the device is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the chip select (CS) and output enable (OE) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the input/output pins. The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable is HIGH. Functional Description The CYM1730 is a high-performance 1.5M static RAM module organized as 64K words by 24 bits. This module is constructed Logic Block Diagram A0 - A14 OE Pin Configuration ZIP Top View 15 WE 32K x 8 SRAM A15 32K x 8 SRAM 1 OF 2 DECODER 8 I/O16 - I/O23 CS 32K x 8 SRAM 32K x 8 SRAM 8 32K x 8 SRAM 32K x 8 SRAM 8 Cypress Semiconductor Corporation * I/O8 - I/O15 3901 North First Street * I/O0 - I/O7 San Jose 1730-1 * VCC I/O1 I/O3 I/O5 I/O7 GND A1 A3 A5 A7 NC GND I/O9 I/O11 I/O13 I/O15 NC OE A9 A11 A13 A15 GND I/O17 I/O19 I/O21 I/O23 VCC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 VCC I/O0 I/O2 I/O4 I/O6 GND A0 A2 A4 A6 CS NC I/O8 I/O10 I/O12 I/O14 GND WE A8 A10 A12 A14 GND I/O16 I/O18 I/O20 I/O22 VCC 1730-2 CA 95134 * 408-943-2600 July 1991 - Revised January 1995 CYM1730 Selection Guide 1730-25 1730-30 1730-35 Maximum Access Time (ns) 25 30 35 Maximum Operating Current (mA) 510 510 510 Maximum Standby Current (mA) 180 180 180 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage ........................................... -0.5V to +7.0V Storage Temperature ................................. -55C to +125C Operating Range Ambient Temperature with Power Applied............................................... -10C to +85C Range Ambient Temperature VCC Supply Voltage to Ground Potential ............... -0.5V to +7.0V Commercial 0C to +70C 5V 10% DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current ISB1 ISB2 Min. Max. Unit 2.4 V 0.4 V 2.2 VCC + 0.3 V -0.3 0.8 V -20 +20 A -10 +10 A 510 mA Automatic CS Power-Down Current[1] VCC = Max., IOUT = 0 mA, CS < VIL Max. VCC, CS > VIH, Min. Duty Cycle = 100% 180 mA Automatic CS Power-Down Current[1] Max. VCC, CS > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 180 mA Capacitance[2] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. Unit 50 pF 20 pF Notes: 1. A pull-up resistor to V CC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. 2 CYM1730 AC Test Loads and Waveforms 481 481 5V 5V OUTPUT OUTPUT 255 100 pF ALL INPUT PULSES 3.0V 90% 255 5 pF INCLUDING JIG AND SCOPE GND Equivalent to: (b) 1730-5 10% < 5 ns INCLUDING JIG AND SCOPE (a) 90% 10% < 5 ns 1730-3 1730-4 THEVENIN EQUIVALENT 167 OUTPUT 1.73V Switching Characteristics Over the Operating Range[3] 1730-25 Parameter Description Min. Max. 1730-30 Min. Max. 1730-35 Min. Max. Unit READ CYCLE tRC Read Cycle Time 25 tAA Address to Data Valid tOHA Output Hold from Address Change tACS CS LOW to Data Valid 25 30 35 ns tDOE OE LOW to Data Valid 12 15 20 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z CS LOW to Low tHZCS CS HIGH to High Z[4, 5] WRITE 25 5 35 30 5 3 5 35 5 ns 20 5 15 ns ns 3 15 10 ns 5 3 10 Z[4] tLZCS 30 ns ns 15 ns CYCLE[6] tWC Write Cycle Time 25 30 35 ns tSCS CS LOW to Write End 20 25 30 ns tAW Address Set-Up to Write End 22 25 30 ns tHA Address Hold from Write End 2 2 2 ns tSA Address Set-Up to Write Start 2 2 2 ns tPWE WE Pulse Width 20 23 25 ns tSD Data Set-Up to Write End 13 15 20 ns tHD Data Hold from Write End 2 2 2 ns tLZWE WE HIGH to Low Z 3 3 5 ns tHZWE WE LOW to High Z[5] 0 10 0 10 0 15 ns Notes: 3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/I OH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. 5. tHZOE , tHZCS , and tLZCEare specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 3 CYM1730 Switching Waveforms Read Cycle No. 1 [7, 8] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1730-6 Read Cycle No. 2 [7, 9] tRC CS tACS OE tHZOE tDOE tHZCS tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT tLZCS tPD tPU ICC VCC SUPPLY CURRENT 50% 50% ISB 1730-7 Write Cycle No. 1 (WE Controlled) [6, 10] tWC ADDRESS tSCS CS tAW tHA tSA tPWE WE tSD DATA IN tHD DATA VALID tHZWE tLZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED 1730-8 Notes: 7. WE is HIGH for read cycle. 8. Device is continuously selected, CS = VIL and OE= VIL. 9. Address valid prior to or coincident with CS transition LOW. 10. Data I/O will be high impedance if OE = VIH. 4 CYM1730 Switching Waveforms (continued) Write Cycle No. 2 (CS Controlled) [6, 10, 11] tWC ADDRESS tSA tSCS CS tAW tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED 1730-9 Note: 11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Truth Table CS WE OE Input/Outputs Mode H X X High Z Deselect/Power-Down L H L Data Out Read Word L L X Data In Write Word L H H High Z Deselect Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 25 CYM1730PZ-25C PZ07 56-Pin ZIP Module Commercial 30 CYM1730PZ-30C PZ07 56-Pin ZIP Module Commercial 35 CYM1730PZ-35C PZ07 56-Pin ZIP Module Commercial Document #: 38-M-00049-A 5 CYM1730 Package Diagram 56-Pin ZIP Module PZ07 2.990/3.010 .350 MAX. .485/.495 .125/.175 2.750 REF .100 REF (c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.