Standard Products UT54LVDS217 Serializer Data Sheet June, 2003 FEATURES INTRODUCTION q q q q q q q q q q q The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. 15 to 75 MHz shift clock support Low power consumption Power-down mode <216W (max) Cold sparing all pins Narrow bus reduces cable size and cost Up to 1.575 Gbps throughput Up to 197 Megabytes/sec bandwidth 325 mV (typ) swing LVDS devices for low EMI PLL requires no external components Rising edge strobe Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 300 krad(Si) and 1 Mrad(Si) At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec). The UT54LVDS217 Serializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size. All pins have Cold Spare buffers. These buffers will be high impedance when V DD is tied to VSS . 21 CMOS/TTL INPUTS TRANSMIT CLOCK IN TTL PARALLEL-TO-LVDS TTL PARALLEL -TO- - Latchup immune (LET > 100 MeV-cm2 /mg) q Packaging options: - 48-lead flatpack q Standard Microcircuit Drawing 5962-01534 - QML Q and V compliant part q Compatible with TIA/EIA-644 LVDS standard PLL POWER DOWN Figure 1. UT54LVDS217 Serializer Block Diagram 1 DATA (LVDS) CLOCK (LVDS) 48 TxIN3 2 47 TxIN5 3 46 TxIN2 GND TxIN6 GND 4 45 44 TxIN1 TxIN0 TxIN7 6 43 TxIN8 7 42 VDD TxIN9 8 9 TxIN10 TxIN4 1 VDD PIN DESCRIPTION Description I/O No. TxIN I 21 TTL level input N/C TxOUT+ O 3 Positive LVDS differential data output TxOUT- O 3 Negative LVDS differential data output 41 LVDS GND TxOUT0- TxCLK IN I 1 40 TxOUT0+ TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN 10 39 O 1 GND 11 TxCLK OUT+ Positive LVDS differential clock output TxOUT1- 38 TxOUT1+ 12 13 37 36 O 1 LVDS VDD LVDS GND TxCLK OUT- Negative LVDS differential clock output TxIN11 TxIN12 PWR DWN I 1 TxOUT2- 5 UT54LVDS217 Pin Name 14 35 TxIN13 15 34 TxOUT2+ TxIN14 16 I 4 17 TxCLK OUTTxCLK OUT+ GND I 5 Ground pins for TTL inputs and logic GND 33 32 V DD TTL level input. Assertion (low input) TRISTATEs the clock and data outputs, ensuring low current at power down. Power supply pins for TTL inputs and logic TxIN15 18 31 LVDS GND PLL V DD I 1 Power supply pins for PLL TxIN16 19 30 PLL GND PLL GND I 2 Ground pins for PPL TxIN17 20 29 PLL V DD 21 1 22 PLL GND PWR DWN I TxIN18 28 27 LVDS V DD Power supply pin for LVDS output VD D LVDS GND I 3 Ground pins for LVDS outputs TxIN19 23 26 TxCLK IN GND 24 25 TxIN20 V DD Figure 2. UT54LVDS217 Pinout UT54LVDS217 TxIN LVDS CABLE MEDIA DEPENDENT DATA (LVDS) UT54LVDS218 RxOUT 0 1 2 0 1 2 CMOS/ TTL 18 19 20 18 19 20 CLOCK (LVDS) TxCLK RxCLK GND PCB PCB SHIELD Figure 3. UT54LVDS217 Typical Application 2 ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS ) SYMBOL PARAMETER LIMITS V DD DC supply voltage -0.3 to 4.0V VI/O Voltage on any pin4 -0.3 to (V DD + 0.3V) T STG Storage temperature -65 to +150C PD Maximum power dissipation TJ Maximum junction temperature 2 +150C Thermal resistance, junction-to-case3 10C/W DC input current 10mA JC II 2W Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and lifetest. 3. Test per MIL-STD-883, Method 1012. 4. For cold spare mode (VDD = V SS ), V I/O may be 0.3V to the maximum recommended operating VD D + 0.3V. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS V DD, PLL V DD, LVDS VDD Positive supply voltage 3.0 to 3.6V TC Case temperature range -55 to +125C V IN DC input voltage 0V to V DD 3 DC ELECTRICAL CHARACTERISTICS 1 (V DD = 3.3V-0.3V; -55C < TC < +125C) SYMBOL PARAMETER CONDITION MIN MAX UNIT CMOS/TTL DC SPECIFICATIONS V IH High-level input voltage 2.0 V DD V V IL Low-level input voltage GND 0.8 V IIH High-level input current VIN = 3.6V; VDD = 3.6V -10 +10 A IIL Low-level input current VIN = 0V; VDD = 3.6V -10 +10 A V CL Input clamp voltage ICL = -18mA -1.5 V I CS Cold Spare Leakage current VIN = 3.6V; VDD = V SS -20 +20 A 250 400 mV 35 mV 1.410 V 35 mV LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) VOD 5 Differential Output Voltage RL = 100 (See Figure 14) VOD 5 Change in VOD between complimentary output states RL = 100 (See Figure 14) Offset Voltage Voh + Vol RL = 100, Vos = --------------------------- VOS 5 1.120 2 VOS 5 Change in VOS between complimentary output states RL = 100 IOZ 4 Output Three-State Current PWR DWN = 0V VOUT = 0V or V DD -10 +10 I CSOUT Cold Spare Leakage Current VIN=3.6V, VDD = V SS -20 +20 I OS2,3 Output Short Circuit Current VOUT + or V OUT - = 0V 5mA mA Transmitter supply current with loads RL = 100 all channels (figure 4) 65.0 mA Power down current DIN = VSS 60.0 A Supply Current ICCL 4 ICCZ 4,6 CL = 5pF, f = 50MHz PWR DWN = 0V, f = 0Hz Notes: 1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenc ed to ground. 2. Output short circuit current (I OS ) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. 3. Guaranteed by characterization. 4. Devices are tested @ 3.6V only. 5. Clock outputs guaranteed by design. 6. Post 100Krad and 300Krad, I CCZ = 200A. 4 AC SWITCHING CHARACTERISTICS1 (V DD = 3.0V to 3.6V; TA = -55C to +125C) SYMBOL PARAMETER MIN MAX UNIT LLHT 2 LVDS Low-to-High Transition Time (Figure 5) 1.5 ns LHLT 2 LVDS High-to-Low Transition Time (Figure 5) 1.5 ns TPPos0 2 Transmitter Output Pulse Position for Bit 0 (Figure 13) f=75MHz -0.18 0.270 ns TPPos1 2 Transmitter Output Pulse Position for Bit 1(Figure 13) f=75MHz 1.72 2.17 ns TPPos2 2 Transmitter Output Pulse Position for Bit 2 (Figure 13) f=75MHz 3.63 4.08 ns TPPos3 2 Transmitter Output Pulse Position for Bit 3 (Figure 13) f=75MHz 5.53 5.98 ns TPPos4 2 Transmitter Output Pulse Position for Bit 4 (Figure 13) f=75MHz 7.44 7.89 ns TPPos5 2 Transmitter Output Pulse Position for Bit 5 (Figure 13) f=75MHz 9.34 9.79 ns TPPos6 2 Transmitter Output Pulse Position for Bit 6 (Figure 13) f=75MHz 11.25 11.70 ns 0.45 ns 13.3 66.7 ns TCCS3 TCIP Channel to Channel skew (Figure 7) TxCLK IN Period (Figure 8) TCIH4 TxCLK IN High Time (Figure 8) 0.35Tcip 0.65Tcip ns TCIL 4 TxCLK IN Low Time (Figure 8) 0.35Tcip 0.65Tcip ns TSTC2 TxIN Setup to TxCLK IN (Figure 8) 15MHz 75MHz THTC2 15MHz TxIN Hold to TxCLK IN (Figure 8) 75MHz TCCD TxCLK IN to TxCLK OUT Delay (Figure 9) TPLLS TPDD 1.0 0.5 ns 0.7 0.5 ns 0.5 2.5 ns Transmitter Phase Lock Loop Set (Figure 10) 10 ms Transmitter Powerdown Delay (Figure 12) 100 ns Notes: 1. Recommend transistion time for TXCLK In is 1.0 to 6.0 ns (figure 6). 2. Guaranteed by characterization. 3. Channel to channel skew is defined as the difference between TPPOS max limit and TPPOS minimum limit. 4. Guaranteed by design. 5 T TxCLK IN TxIN Figure 4. Test Pattern AC TIMING DIAGRAMS Vdiff=(TxOUT+) - (TxOUT-) 80% 20% Vdiff TxOUT+ 5pF 80% 20% LLHT 100 LHLT TxOUT- Figure 5. UT54LVDS217 Output Load and Transition Times 90% 90% 10% 10% TXCLK IN TCIT TCIT Figure 6. UT54LVDS217 Input Clock Transition Time 6 TCCS TxOUT0 Vdiff= 0V TxOUT1 TxOUT2 TxCLK OUT TIME Notes: 1. Measurements at V DIFF = 0V 2. TCCS measured between earliest and latest LVDS edges. 3. TxCLK Differential Low-High Edge. Figure 7. UT54LVDS217 Channel-to-Channel Skew TCIP V DD/2 Sample on L-H Edge V DD/2 V DD /2 TxCLK IN TCIH TCIL TSTC TxIN 0-20 V DD/2 THTC SETUP HOLD V DD/2 Figure 8. UT54LVDS217 Setup/Hold and High/Low Times TxCLK IN V DD /2 TCCD Vdiff= 0V TxCLK OUT Figure 9. UT54LVDS217 Clock-to-Clock Out Delay 7 V DD V DD/2 POWER DOWN V DD V DD/2 V DD TPLLS TxCLK IN TxCLK OUT / Vdiff = OV RxCLK IN Figure 10. UT54LVDS217 Phase Lock Loop Set Time TxCLK OUT / RxCLK IN Previous Cycle TxOUT2 / RxIN2 TxOUT1 / Next Cycle TxIN15-1 TxIN14-1 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN8-1 TxIN7-1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN0-1 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 RxIN1 TxOUT0 / TxIN1-1 RxIN0 Figure 11. UT54LVDS217 Parallel TTL Data Inputs Mapped to LVDS Outputs 8 POWER DOWN V DD/2 TxCLK IN TPDD THREE-STATE TxOUT Figure 12. Transmitter Powerdown Delay TCLK TxCLK OUT / Differential Previous Cycle TxOUT2 / (Single ended) TxOUT1 / Next Cycle TxIN15-1 TxIN14-1 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN8-1 TxIN7-1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 Single ended TxOUT0 / TxIN1-1 TxIN0-1 Single ended TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 Figure 13. LVDS Output Pulse Position Measurement 9 TxIN1 TxIN0 D OUT+ 20pF DIN D Generator R L = 100 50 Driver Enabled 20pF DOUT- Figure 14. Driver VOD and V O S Test Circuit or Equivalent Circuit 10 V OD PACKAGING 5 6 4 6 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Lead position and colanarity are not measured. 5. ID mark symbol is vendor option. 6. With solder, increase maximum by 0.003. Figure 15. 48-Lead Flatpack 11 ORDERING INFORMATION UT54LVDS217 Serializer: UT 54LVDS217 - * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow Package Type: (U) = 48-lead Flatpack (dual-in-line) Access Time: Not applicable Device Type: UT54LVDS217 Serializer Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25 C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55 C, room temp, and 125 C. Radiation neither tested nor guaranteed. 12 UT54LVDS217 Serializer: SMD 5962 - 01534 ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 48 lead Flatpack (dual-in-line) Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 01 = 50MHz LVDS Serializer (contacat factory) 02 = 75MHz LVDS Serializer Drawing Number: 01534 Total Dose (R) = 1E5 rad(Si) (F) = 3E5 rad(Si) (G) = 5E5 rad(Si) (contact factory for availability) (H) = 1E6 rad(Si) (contact factory for availability) Federal Stock Class Designator: No Options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 13