BUK1M200-50SGTD,11 - NXP Semiconductors

BUK1M200-50SGTD

Quad channel logic level TOPFET

Rev. 01 — 31 March 2003 Product data

1. Product proﬁle

1.1 Description

Quad temperature and overload protected power switch based on TOPFET™ Trench

technology in a 20-pin surface mount plastic package.

Product availability:

BUK1M200-50SGTD in SOT163-1 (SO20).

1.2 Features

1.3 Applications

1.4 Quick reference data

[1] All devices active.

■Power TrenchMOS™ ■5V logic compatible

■Overtemperature protection ■Current trip protection

■Overload protection ■ESD protection for all pins

■Input-source voltage resets latched

protection circuitry. ■Overvoltage clamping for turn off of

inductive loads

■Control of output stage and supply of

overload protection circuits derived

from input

■Low operating input current permits

direct drive by micro-controller.

■Low-side driver ■DC switching

■Pulse Width Modulation ■General purpose switch for driving

lamps, motors, solenoids and heaters.

Table 1: Quick reference data

Symbol Parameter Min Max Unit

RDSon drain-source on-state resistance - 200 mΩ

IDdrain current - 2.7 A

Ptot total power dissipation [1] - 9.4 W

Tjjunction temperature - 150 °C

VDS drain-source voltage - 50 V

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 2 of 15

2. Pinning information

2.1 Pin description

Fig 1. Pinning; SOT163-1 (SO20). Fig 2. Symbol; Quad channel low-side TOPFETTM

book, halfpage

Top view

MGX361

110

MBL801

D4I4

D3I3

D2I2

D1I1

Table 2: Pin description

Symbol Pin Description

n.c. 1, 11, 10, 20 not connected

D1 2,19 drain 1

I1 3 input 1

D2 4,17 drain 2

I2 5 input 2

D3 6,15 drain 3

I3 7 input 3

D4 8, 13 drain 4

I4 9 input 4

S4 12 source 4

S3 14 source 3

S2 16 source 2

S1 18 source 1

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 3 of 15

3. Block diagram

Fig 3. Elements of the quad channel TOPFET switch.

OVER

VOLTAGE

REGULATOR

gate sense

I1 RIG

CHANNEL 1

CHANNEL 2

internal circuitry

identical to

CHANNEL1

CHANNEL 3

internal circuitry

identical to

CHANNEL1

CHANNEL 4

internal circuitry

identical to

CHANNEL1

CONTROL

LOGIC

OVER

TEMPERATURE

SHORT CIRCUIT

PROTECTION CROWBAR

AND

CURRENT

TRIP

03pb04

BUK1M200-50SGTD

2,19

4,17

6,15

8,13

Philips Semiconductors BUK1M200-50SGTD
Quad channel logic level TOPFET
Product data Rev. 01 — 31 March 2003 4 of 15
9397 750 10955 © Koninklijke Philips Electronics N.V. 2003. All rights reserved.
4. Limiting values
[1] Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
[2] Refer to overload protection characteristics.in Table 5.
[3] For a single active device.
[4] For all devices active.
[5] Not in an overload condition with drain current limiting.
[6] At a drain-source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
[7] With the protection supply provided via the input pin, the TOPFET is protected from short circuit loads. Overload protection operates by
means of drain current trip or by activating the overtemperature protection.
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage [1] -50V
IDdrain current Tsp =25 °C; Figure 5 [2][3] - 2.7 A
IIinput current clamping - 3 mA
IIMS non-repetitive peak input current tp≤1 ms - 10 mA
Ptot total power dissipation Tsp =25 °C; Figure 4 [4] - 9.4 W
Tstg storage temperature −55 +150 °C
Tjjunction temperature normal operation [5] - 150 °C
Overvoltage clamping [6]
EDS(CL)S non-repetitive drain-source clamping energy Tamb =25°C; IDM ≤ID(th)(trip); inductive
load [3] - 100 mJ
EDS(CL)R repetitive drain-source clamping energy Tsp ≤125 °C; IDM = 1 A; f = 250 Hz [3] -5 mJ
Overload protection [7]
VDS(prot) protected drain-source voltage VIS ≥4V - 35 V
Reverse diode
ISsource (diode forward) current Tsp ≤25 °C; VIS =0V - 2 A
Electrostatic discharge
Vesd electrostatic discharge voltage C = 250 pF; R = 1.5 kΩ-2 kV

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 5 of 15

5. Thermal characteristics

Fig 4. Normalized total power dissipation as a

function of solder point temperature. Fig 5. Continuous drain current as a function of

solder point temperature.

03aa17

120

0 50 100 150 200

(%)

Tsp (°C)

Pder

03pa87

0.00

1.00

2.00

3.00

0 40 80 120 160

Tsp (°C)

(A)

Pder Ptot

Ptot 25 C

()

----------------------- 100%×=

Table 4: Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-sp) thermal resistance from junction to

solder point. mounted on thermo clad board

one device active - - 45 K/W

all devices active - - 13.3 K/W

Philips Semiconductors BUK1M200-50SGTD
Quad channel logic level TOPFET
Product data Rev. 01 — 31 March 2003 6 of 15
9397 750 10955 © Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6. Static characteristics
[1] The supply for the logic and overload protection is taken from the input.
[2] The input voltage below which the overload protection circuits will be reset.
[3] To reset the protection circuitry from the latched state, VIS is reduced from 5 V to 1 V.
[4] Not directly measurable from device terminals.
[5] The TOPFET switches off to protect itself when one of the overload thresholds is exceeded. It remains latched off until reset by the
input.
Table 5: Static characteristics
Limits are valid for
−
40
°
C
≤
T
sp
≤
+150
°
C and typical values for T
sp
=25
°
C unless otherwise speciﬁed.
Symbol Parameter Conditions Min Typ Max Unit
Off-state output characteristics
VDS(CL) drain-source clamping voltage VIS =0V; I
D=10mA 50 - - V
VIS =0V; I
D= 200 mA; tp≤300 µs;
δ≤0.01; Figure 18 50 62 70 V
IDSS drain-source leakage current VIS =0V; V
DS =40V - - 100 µA
Tsp =25°C; Figure 19 - 0.05 10 µA
On-state output characteristic
RDSon drain-source on-state resistance VIS ≥4 V; tp≤300 µs; δ≤0.01;
ID= 100 mA - - 380 mΩ
Tsp =25°C; Figure 8 and 9- 150 200 mΩ
Input characteristics [1]
VIS(th) input-source threshold voltage VDS =5V; I
D= 1 mA 0.6 - 2.4 V
Tsp =25°C; Figure 13 1.1 1.6 2.1 V
IIS input supply current normal operation
VIS = 5 V 100 220 400 µA
VIS = 4 V 80 195 330 µA
protection latched
VIS = 5 V 1.4 2 2.5 mA
VIS =3 V;Figure 14 and 16 0.7 1.1 1.5 mA
VIS(rst) input-source reset voltage trst ≥100 µs; Figure 17 [2] 1.5 2 2.5 V
trst(latch) latch reset time [3] 10 40 100 µs
VIS(CL) input-source clamping voltage II= 1.5 mA; Figure 15 5.5 - 8.5 V
RIG input-gate resistance [4] - 2.5 - kΩ
Overload protection characteristic [5]
ID(th)(trip) drain current trip threshold 4 V ≤VIS ≤5.5 V
Tsp =25C;Figure 11 4 6.1 8 A
Figure 10 3 6.1 9 A
Overtemperature protection characteristic
Tj(th) threshold junction temperature 4 V ≤VIS ≤5.5 V; Figure 12 150 170 - °C
Source drain diode characteristic
VSD source-drain (diode forward)
voltage IS= 2 A; VIS =0V; t
p= 300 µs - 0.83 1.1 V

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 7 of 15

Tj=25°C; ID= 100 mA; tp= 300 µs

Fig 6. Normalized drain-source on-state resistance

factor as a function of junction temperature. Fig 7. Drain-source on-state resistance as a function

of input-source voltage; typical values.

Fig 8. Output characteristics; drain current as a

function of drain-source voltage; typical values. Fig 9. Transfer characteristics; drain current as a

function of input-source voltage; typical values.

03pa71

0.5

1.5

2.5

-50 0 50 100 150

Tj (°C)

03pa73

125

250

375

500

02468

VIS (V)

RDSon

(mΩ)

aRDSon

RDSon 25°C()

------------------------------

03pa89

02468

VDS (V)

(A)

VIS = 2. 2 V 2. 4 V

2.6 V

2.8 V

3 V

3.2 V

3.4 V

4 V

5 V

03pa88

01234

VIS (V)

(A)

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 8 of 15

Tj=25°C; tp= 300 µsT

j=25°C; VDS = 10 V; tp= 300 µs

Fig 10. Drain current trip threshold as a function of

junction temperature; typical values. Fig 11. Drain current trip threshold as a function of

input-source voltage; typical values.

03pb02

-50 0 50 100 150

Tj (°C)

ID(th)(trip)

(A)

03pb01

0246

VIS (V)

ID(th)(trip)

(A)

VDS =5V; V

IS =5V; t

p= 300 µsT

j=25°C; VDS =5V; t

p= 300 µs

Fig 12. Overtemperature protection characteristic;

threshold junction temperature as a function of

input-source voltage; typical values.

Fig 13. Input-source threshold voltage as a function of

junction temperature.

03pa76

160

170

180

190

200

0246810

VIS (V)

Tj(th)

(°C)

03pa77

0.5

1.5

2.5

-50 0 50 100 150

Tj (°C)

VIS(th)

(V)

min.

typ.

max.

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 9 of 15

Tj=25°C

(1) Input-source current; protection latched.

(2) Input-source current; normal operation.

Tj=25°C

Fig 14. Input-source current as a function of

input-source voltage; typical values. Fig 15. Input clamping characteristic; input current as

a function of input-source voltage; typical

values.

(1) VIS = 5 V; protection latched

(2) VIS = 3 V; protection latched

(3) VIS = 5 V; normal operation

(4) VIS = 4 V; normal operation

tr= 100 µs

Fig 16. Input-source current as a function of junction

temperature; typical values. Fig 17. Input-source reset voltage as a function of

junction temperature; typical values.

03pa91

02468

VIS (V)

IIS

(mA)

(1)

(2)

03pa79

02468

VIS (V)

(mA)

03pa86

0.8

1.6

2.4

-50 0 50 100 150

Tj (°C)

IIS

(mA)

(1)

(2)

(3)

(4)

03pa82

1.8

2.2

2.4

-50 20 90 160

Tj (°C)

VIS(rst)

(V)

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 10 of 15

VIS =0V; t

p= 300 µsV

DS =40V; V

IS =0 V

Fig 18. Overvoltage clamping characteristic; drain

current as a function of drain-source voltage;

typical values.

Fig 19. Drain-source leakage current as a function of

junction temperature; typical values.

03pa83

100

200

300

400

57 59 61 63 65 67

VDS (V)

(mA)

03pa84

10-8

10-7

10-6

10-5

-50 0 50 100 150

Tj (°C)

IDSS

(A)

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 11 of 15

7. Dynamic characteristics

Table 6: Switching characteristics

Symbol Parameter Conditions Min Typ Max Unit

Switching

td(on) turn-on delay time RL=50Ω; ID= 250 mA; VIS =5V;

Tsp =25°C; Figure 20 and 21 - 0.5 0.9 µs

trrise time - 0.7 1.5 µs

td(off) turn-off delay time - 3.2 6.5 µs

tffall time - 1.6 3.5 µs

Fig 20. Test circuit for resistive load switching times. Fig 21. Resistive load switching waveforms.

VIS

VDD

VDS

MBL853

VIS

VDS

td(on) td(off)

10%

90%

10%

90%

tftr

MBL854

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 12 of 15

8. Package outline

Fig 22.

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

inches

2.65 0.30

0.10 2.45

2.25 0.49

0.36 0.32

0.23 13.0

12.6 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1

0.4

SOT163-1

detail X

0.25

075E04 MS-013

pin 1 index

0.10 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.51

0.49 0.30

0.29 0.050

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

vMA

(A )

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

97-05-22

99-12-27

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 13 of 15

9. Revision history

Table 7: Revision history

Rev Date CPCN Description

01 20030331 - Product data (9397 750 10955)

9397 750 10955

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 14 of 15

9397 750 10955

Philips Semiconductors BUK1M200-50SGTD

Quad channel logic level TOPFET

Product data Rev. 01 — 31 March 2003 14 of 15

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.Fax: +31 40 27 24825

10. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

11. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

12. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

13. Trademarks

TOPFET — is a trademark of Koninklijke Philips Electronics N.V.

TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.

Level Data sheet status[1] Product status[2][3] Deﬁnition

I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheetcontains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

© Koninklijke Philips Electronics N.V. 2003.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 31 March 2003 Document order number: 9397 750 10955
Contents
Philips Semiconductors BUK1M200-50SGTD
Quad channel logic level TOPFET
1 Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . .  1
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
1.3 Applications  . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . .  1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . .  2
2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . .  2
3 Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . .  3
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . .  4
5 Thermal characteristics. . . . . . . . . . . . . . . . . . .  5
6 Static characteristics. . . . . . . . . . . . . . . . . . . . .  6
7 Dynamic characteristics . . . . . . . . . . . . . . . . .  11
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . .  12
9 Revision history. . . . . . . . . . . . . . . . . . . . . . . .  13
10 Data sheet status. . . . . . . . . . . . . . . . . . . . . . .  14
11 Deﬁnitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
12 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .  14