Philips Semiconductors RF Wideband Transistors General section * Acceptance tests on finished products to verify conformance with the device specification. The test results are used for quality feedback and corrective actions. The inspection and test requirements are detailed in the general quality specifications. QUALITY Total Quality Management Philips Semiconductors is a Quality Company, renowned for the high quality of our products and service. We keep alive this tradition by constantly aiming towards one ultimate standard, that of zero defects. This aim is guided by our Total Quality Management (TQM) system, the basis of which is described in the following paragraphs. * Periodic inspections to monitor and measure the conformance of products. Product reliability PPM co-operations, design-in agreements, ship-to-stock, just-in-time and self-qualification programmes, and application support. With the increasing complexity of Original Equipment Manufacturer (OEM) equipment, component reliability must be extremely high. Our research laboratories and development departments study the failure mechanisms of semiconductors. Their studies result in design rules and process optimization for the highest built-in product reliability. Highly accelerated tests are applied to the products reliability evaluation. Rejects from reliability tests and from customer complaints are submitted to failure analysis, to result in corrective action. PARTNERSHIPS WITH SUPPLIERS Customer responses Ship-to-stock, statistical process control and ISO 9000 audits. Our quality improvement depends on joint action with our customer. We need our customer's inputs and we invite constructive comments on all aspects of our performance. Please contact our local sales representative. QUALITY ASSURANCE Based on ISO 9000 standards, customer standards such as Ford TQE and IBM MDQ. Our factories are certified to ISO 9000 by external inspectorates. PARTNERSHIPS WITH CUSTOMERS QUALITY IMPROVEMENT PROGRAMME Continuous process and system improvement, design improvement, complete use of statistical process control, realization of our final objective of zero defects, and logistics improvement by ship-to-stock and just-in-time agreements. Recognition Advanced quality planning PRO ELECTRON TYPE NUMBERING SYSTEM During the design and development of new products and processes, quality is built-in by advanced quality planning. Through failure-mode-and-effect analysis the critical parameters are detected and measures taken to ensure good performance on these parameters. The capability of process steps is also planned in this phase. Basic type number Product conformance FIRST LETTER The assurance of product conformance is an integral part of our quality assurance (QA) practice. This is achieved by: The first letter gives information about the material for the active part of the device. * Incoming material management through partnerships with suppliers. A Germanium or other material with a band gap of 0.6 to 1 eV * In-line quality assurance to monitor process reproducibility during manufacture and initiate any necessary corrective action. Critical process steps are 100% under statistical process control. B Silicon or other material with a band gap of 1 to 1.3 eV C Gallium arsenide (GaAs) or other material with a band gap of 1.3 eV or more R Compound materials, e.g. cadmium sulphide. 1997 Nov 26 The high quality of our products and services is demonstrated by many Quality Awards granted by major customers and international organizations. This type designation code applies to discrete semiconductor devices (not integrated circuits), multiples of such devices, semiconductor chips and Darlington transistors. 34 Philips Semiconductors RF Wideband Transistors General section SECOND LETTER Version letter The second letter indicates the function for which the device is primarily designed. The same letter can be used for multi-chip devices with similar elements. A letter may be added to the basic type number to indicate minor electrical or mechanical variants of the basic type. In the following list low power types are defined by Rth j-mb > 15 K/W and power types by Rth j-mb 15 K/W. RATING SYSTEMS The rating systems described are those recommended by the IEC in its publication number 134. A Diode; signal, low power B Diode; variable capacitance C Transistor; low power, audio frequency Definitions of terms used D Transistor; power, audio frequency ELECTRONIC DEVICE E Diode; tunnel F Transistor; low power, high frequency G Multiple of dissimilar devices/miscellaneous devices; e.g. oscillators. Also with special third letter; see under Section "Serial number" An electronic tube or valve, transistor or other semiconductor device. This definition excludes inductors, capacitors, resistors and similar components. CHARACTERISTIC H Diode; magnetic sensitive L Transistor; power, high frequency N Photocoupler P Radiation detector; e.g. high sensitivity photo-transistor; with special third letter A characteristic is an inherent and measurable property of a device. Such a property may be electrical, mechanical, thermal, hydraulic, electro-magnetic or nuclear, and can be expressed as a value for stated or recognized conditions. A characteristic may also be a set of related values, usually shown in graphical form. Q Radiation generator; e.g. LED, laser; with special third letter BOGEY ELECTRONIC DEVICE R Control or switching device; e.g. thyristor, low power; with special third letter S Transistor; low power, switching T Control or switching device; e.g. thyristor, low power; with special third letter U Transistor; power, switching RATING W Surface acoustic wave device X Diode; multiplier, e.g. varactor, step recovery Y Diode; rectifying, booster Z Diode; voltage reference or regulator, transient suppressor diode; with special third letter. A value that establishes either a limiting capability or a limiting condition for an electronic device. It is determined for specified values of environment and operation, and may be stated in any suitable terms. Limiting conditions may be either maxima or minima. An electronic device whose characteristics have the published nominal values for the type. A bogey electronic device for any particular application can be obtained by considering only those characteristics that are directly related to the application. RATING SYSTEM SERIAL NUMBER The set of principles upon which ratings are established and which determine their interpretation. The rating system indicates the division of responsibility between the device manufacturer and the circuit designer, with the object of ensuring that the working conditions do not exceed the ratings. The number comprises three figures running from 100 to 999 for devices primarily intended for consumer equipment, or one letter (Z, Y, X, etc.) and two figures running from 10 to 99 for devices primarily intended for industrial or professional equipment.(1) Absolute maximum rating system (1) When the supply of these serial numbers is exhausted, the serial number may be expanded to three figures for industrial types and four figures for consumer types. 1997 Nov 26 Absolute maximum ratings are limiting values of operating and environmental conditions applicable to any electronic 35 Philips Semiconductors RF Wideband Transistors General section applications, taking responsibility for normal changes in operating conditions due to rated supply voltage variation, equipment component variation, equipment control adjustment, load variation, signal variation, environmental conditions, and variations in the characteristics of all electronic devices. device of a specified type, as defined by its published data, which should not be exceeded under the worst probable conditions. These values are chosen by the device manufacturer to provide acceptable serviceability of the device, taking no responsibility for equipment variations, environmental variations, and the effects of changes in operating conditions due to variations in the characteristics of the device under consideration and of all other electronic devices in the equipment. The equipment manufacturer should design so that, initially, no design centre value for the intended service is exceeded with a bogey electronic device in equipment operating at the stated normal supply voltage. The equipment manufacturer should design so that, initially and throughout the life of the device, no absolute maximum value for the intended service is exceeded with any device, under the worst probable operating conditions with respect to supply voltage variation, equipment component variation, equipment control adjustment, load variations, signal variation, environmental conditions, and variations in characteristics of the device under consideration and of all other electronic devices in the equipment. LETTER SYMBOLS The letter symbols for transistors detailed in this section are based on IEC publication number 148. Basic letters In the representation of currents, voltages and powers, lower-case letter symbols are used to indicate all instantaneous values that vary with time. All other values are represented by upper-case letters. Design maximum rating system Electrical parameters(1) of external circuits and of circuits in which the device forms only a part are represented by upper-case letters. Lower-case letters are used for the representation of electrical parameters inherent in the device. Inductances and capacitances are always represented by upper-case letters. Design maximum ratings are limiting values of operating and environmental conditions applicable to a bogey electronic device of a specified type as defined by its published data, and should not be exceeded under the worst probable conditions. These values are chosen by the device manufacturer to provide acceptable serviceability of the device, taking responsibility for the effects of changes in operating conditions due to variations in the characteristics of the electronic device under consideration. The following is a list of basic letter symbols used with semiconductor devices: The equipment manufacturer should design so that, initially and throughout the life of the device, no design maximum value for the intended service is exceeded with a bogey electronic device, under the worst probable operating conditions with respect to supply voltage variation, equipment component variation, variation in characteristics of all other devices in the equipment, equipment control adjustment, load variation, signal variation and environmental conditions. B, b Susceptance (imaginary part of an admittance) C Capacitance G, g Conductance (real part of an admittance) H, h Hybrid parameter I, i Current L Inductance P, p Power R, r Resistance (real part of an impedance) V, v Voltage X, x Reactance (imaginary part of an impedance) Design centre rating system Y, y Admittance Design centre ratings are limiting values of operating and environmental conditions applicable to a bogey electronic device of a specified type as defined by its published data, and should not be exceeded under normal conditions. Z, z Impedance. (1) For the purpose of this publication, the term `electrical parameters' applies to four-pole matrix parameters, elements of electrical equivalent circuits, electrical impedances and admittances, inductances and capacitances. These values are chosen by the device manufacturer to provide acceptable serviceability of the device in average 1997 Nov 26 36 Philips Semiconductors RF Wideband Transistors General section repetitive, recovery. As third subscript: with a specified resistance between the terminal not mentioned and the reference terminal Subscripts Upper-case subscripts are used for the indication of: * Continuous (DC) values (without signal), e.g. ID, IB * Instantaneous total values, e.g. iD, iB * Average total values, e.g. ID(AV), IB(AV) * Peak total values, e.g. IDM, IBM * Root-mean-square total values, e.g. ID(RMS); IB(RMS). (OV) Overload P, p Pulse Q, q Turn-off R, r As first subscript: reverse (or reverse transfer), rise. As second subscript: repetitive, recovery. As third subscript: with a specified resistance between the terminal not mentioned and the reference terminal Lower-case subscripts are used for the indication of values applying to the varying component alone: * Instantaneous values, e.g. ib (RMS), (rms) Root-mean-square value * Root-mean-square values, e.g. Id(rms) * Peak values, e.g. Ibm S, s As first subscript: series, source, storage, stray, switching. As second subscript: surge (non-repetitive). As third subscript: short circuit between the terminal not mentioned and the reference terminal stg Storage th Thermal TO Threshold tot Total W Working X, x Specified circuit Z, z Reference or regulator (zener) 1 Input (four-pole matrix) 2 Output (four-pole matrix). * Average values, e.g. Id(av). The following is a list of subscripts used with basic letter symbols for semiconductor devices: A, a anode amb ambient (AV), (av) average value B, b base (BO) breakover (BR) breakdown case case C, c collector C controllable D, d drain E, e emitter F, f fall, forward (or forward transfer) G, g gate H holding h heatsink I, i input j-a junction to ambient TRANSISTOR VOLTAGES j-mb junction to mounting base K, k cathode L load M, m peak value A voltage is indicated by the first two subscripts: the first identifies the terminal at which the voltage is measured and the second the reference terminal or the circuit node. The second subscript may be omitted when there is no possibility of confusion. (min) minimum (max) maximum mb mounting base SUPPLY VOLTAGES OR CURRENTS O, o As first subscript: reverse (or reverse transfer), rise. As second subscript: Supply voltages or supply currents are indicated by repeating the appropriate terminal subscript. 1997 Nov 26 Applications and examples TRANSISTOR CURRENTS The first subscript indicates the terminal carrying the current (conventional current flow from the external circuit into the terminal is positive). Examples: ID, IB, iD, iB, id, ib, Idm, ibm. Examples: VGS, vGS, vgs, Vgsm, VBE, vBE, vbe, Vbem. 37 Philips Semiconductors RF Wideband Transistors General section Examples: VDD, ISS, VCC; IEE. Examples: A reference terminal is indicated by a third subscript. gfs Small-signal value of the short-circuit forward transconductance in common-source configuration DEVICES WITH MORE THAN ONE TERMINAL OF THE SAME KIND hfe If a device has more than one terminal of the same kind, the subscript is formed by the appropriate letter for the terminal, followed by a number. Hyphens may be used to avoid confusion in multiple subscripts. Small-signal value of the short-circuit forward current transfer ratio in common-emitter configuration Zi = Ri + jXi Small-signal value of the input impedance. Example: VDDS, VCCE. If more than one subscript is used, subscripts for which a choice of style is allowed, the subscripts chosen are all upper-case or all lower-case. Examples: ID2 Continuous (DC) current flowing into the second gate terminal Examples: hFE, yRE, hfe, gFS. VB2-E Continuous (DC) voltage between the terminals of second base and emitter. FOUR-POLE MATRIX PARAMETERS MULTIPLE DEVICES The first letter subscript (or double numeric subscript) indicates input, output, forward transfer or reverse transfer. For multiple unit devices, the subscripts are modified by a number preceding the letter subscript. Hyphens may be used to avoid confusion in multiple subscripts. Examples: hi (or h11), ho (or h22), hf (or h21), hr (or h12). A further subscript is used for the identification of the circuit configuration. When no confusion is possible, this further subscript may be omitted. Examples: I2B V1D-2D Continuous (DC) current flowing into the base terminal of the second unit Examples: hfe (or h21e), hFE (or h21E). Continuous (DC) voltage between the drain terminals of the first and second units. DISTINCTION BETWEEN REAL AND IMAGINARY PARTS The upper-case variant of a subscript is used for the designation of static (DC) values. If it is necessary to distinguish between real and imaginary parts of electrical parameters, no additional subscripts are used. If basic symbols for the real and imaginary parts exist, these may be used. Examples: Examples: Zi = Ri + jXi, yfe = gfe + jbfe. ELECTRICAL PARAMETERS gFS Static value of forward transconductance in common-source configuration (DC current gain) hFE Static value of forward current transfer in common-emitter configuration (DC current gain) RDS DC value of the drain-source resistance. RE DC value of the external emitter resistance. If such symbols do not exist or are not suitable, the notation shown in the following examples is used. Examples: Re (hib) etc. for the real part of hib Im (hib) etc. for the imaginary part of hib. S-PARAMETER DEFINITIONS The static value is the slope of the line from the origin to the operating point on the appropriate characteristic curve, i.e. the quotient of the appropriate electrical quantities at the operating point. The S-parameter symbols in this section are based on IEC publication 747 - 7. S-parameters (return losses or reflection coefficients) of a module can be defined as the S11 and S22 of a two-port network (see Fig.1). The lower-case variant of a subscript is used for the designation of small-signal values. 1997 Nov 26 38 Philips Semiconductors RF Wideband Transistors General section In (5), a2 = 0 means output port terminated with Z0 (derived from formula (4)). a1 S11 In (6), a1 = 0 means input port terminated with Z0 (derived from formula (3)). a2 Measurement S 22 b1 D.U.T. Fig.1 b2 The return losses are measured with a network analyzer after calibration, where the influence of the test jig is eliminated. The necessary termination of the other port with Z0 is done automatically by the network analyzer. MLB335 Two-port network with reflection coefficients S11 and S22. b 1 = S 11 x a 1 + S 12 x a 2 (1) b 2 = S 21 x a 1 + S 22 x a 2 (2) The network analyser must have a directivity of at least 40 dB to obtain an accuracy of 0.5 dB when measuring return loss figures of 20 dB. A full two-port correction method can be used to improve the accuracy. TAPE AND REEL PACKING where: Tape and reel packing meets the feed requirements of automatic pick and place equipment (packing conforms to IEC publication 286-2 and 286-3). Additionally, the tape is an ideal shipping container. 1 a 1 = -------------------- x ( V 1 + Z 0 x i 1 ) = signal into port 1 (3) 2 x Z0 1 a 2 = -------------------- x ( V 2 + Z 0 x i 2 ) = signal into port 2 2 x Z0 1 b 1 = -------------------- x ( V 1 + Z 0 x i 1 ) = signal out port 1 2 x Z0 Packing TO-92 (SOT54) leaded types (4) The transistors are supplied on tape in boxes (ammopack) or on reels. The number per reel and per ammopack is 2000. The ammopack has 80 layers of 25 transistors each. Each layer contains 25 transistors, plus one empty position in order to fold the layer correctly.The ammopack is accessible from both sides, enabling the user to choose between `normal' (see Fig.3) and `reverse' tape. `Normal' is indicated by a plus sign (+) on the ammopack and `reverse' by a minus sign (-). In the European version, the leading pin is the emitter. 1 b 2 = -------------------- x ( V 2 + Z 0 x i 2 ) = signal out port 2 2 x Z0 From (1) and (2) formulae for the return losses can be derived: b S 11 = -----1- a 2 = 0 (5) a1 b S 22 = -----2- a 1 = 0 a2 1997 Nov 26 (6) 39 Philips Semiconductors RF Wideband Transistors General section P handbook, full pagewidth T A1 h (p) h A H2 W2 H1 H0 W0 L W1 W F1 MEA940 F2 D0 F t P2 P0 Fig.2 TO-92 (SOT54) transistors on tape. 1997 Nov 26 t1 40 Philips Semiconductors RF Wideband Transistors Table 1 General section Tape specification TO-92 (SOT54) leaded types SPECIFICATIONS SYMBOL DIMENSION REMARKS MIN. NOM. MAX. TOL. UNIT A1 body width 4 - 4.8 - mm A body height 4.8 - 5.2 - mm T body thickness 3.5 - 3.9 - mm P pitch of component - 12.7 - 1 mm P0 feed hole pitch - 12.7 - 0.3 mm cumulative pitch error - - - 0.1 note 1 P2 feed hole centre to component - centre 6.35 - 0.4 mm F distance between outer leads - 5.08 - +0.6/-0.2 mm h component alignment - 0 1 - mm W tape width - 18 - 0.5 mm W0 hold-down tape width - 6 - 0.2 mm W1 hole position - 9 - +0.7/-0.5 mm W2 hold-down tape position - 0.5 - 0.2 mm H0 lead wire clinch height - 16.5 - 0.5 mm H1 component height - - 23.25 - mm L length of snipped leads - - 11 - mm D0 feed hole diameter - 4 - 0.2 mm t total tape thickness - - 1.2 - mm F1, F2 lead-to-lead distance - - - +0.4/-0.2 mm H2 clinch height - - - - mm (p) pull-out force 6 - - - N to be measured at bottom of clinch at top of body t1 = 0.3 to 0.6 Note 1. Measured over 20 devices. Dropouts Tape splicing A maximum of 0.5% of the specified number of transistors in each packing may be missing. Up to 3 consecutive components may be missing provided the gap is followed by 6 consecutive components. Splice the carrier tape on the back and/or front so that the feed hole pitch (P0) is maintained (see Figs 2 and 4). 1997 Nov 26 41 Philips Semiconductors RF Wideband Transistors General section 55 max handbook, full pagewidth O 15 min O 380 min A (1) (1) packing label 55 max 350 max A (1) A-A MEA473 direction of unreeling Dimensions in mm. Fig.3 Dimensions of reel and box. 1997 Nov 26 42 Philips Semiconductors RF Wideband Transistors General section handbook, full pagewidth MEA941 30 mm min Fig.4 Joining tape with splicing patch. handbook, full pagewidth 0.40 min 4.2 max 1.7 1.4 5.2 max 12.7 min 0.48 0.40 1 4.8 max 2.54 2 3 0.66 0.56 2.0 max (1) Dimensions in mm. (1) Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. Fig.5 TO-92 (SOT54) with straight leads. 1997 Nov 26 43 MBC014 - 1 Philips Semiconductors RF Wideband Transistors General section handbook, full pagewidth 0.40 min 4.2 max 1.7 1.4 5.2 max 12.7 min 0.48 0.40 1 4.8 max 2 2.54 3 0.66 0.56 2.5 max (1) MBC015 - 1 Dimensions in mm. (1) Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. Fig.6 TO-92 (SOT54) with delta pinning. Packing types Table 2 Packing quantities per reel TAPE WIDTH (mm) REEL SIZE (mm) QUANTITY PER REEL 12NC (note 1) ends with: 8 180 3000 ...215 330 10000 ...235 180 3000 ...215 SOT143R 330 10000 ...235 SOT143 (cross emitter pinning) 180 3000 ...215 SOT143R (cross emitter pinning) 330 10000 ...235 PACKAGE SOT23 SOT143 SOT323 8 8 180 3000 ...115 330 10000 ...135 SOT343 8 180 3000 ...115 SOT353 8 180 3000 ...115 SOT363 8 180 3000 ...115 SOT89 12 180 3000 ...115 SOT223 12 180 3000 ...115 Notes 1. 12NC is the Philips twelve-digit ordering code. 1997 Nov 26 44 Philips Semiconductors RF Wideband Transistors General section K handbook, full pagewidth SOT23 T1 SOT143R/343R G SOT143/343 B 1 B 0 D1 W1 W F E D0 , ,,, , ,,, , ,,, , ,,, , ,,, ,,, K0 A0 P2 P P0(1) T MBE547 - 1 direction of unreeling For dimensions see Table 3. (1) Tolerance over any 10 pitches: 0.2 mm. Fig.7 Specification for 8 mm tape (SOT23, SOT143, SOT143R, SOT343 and SOT343R). K handbook, full pagewidth SOT323 T1 SOT353 G SOT363 B 1 B 0 D1 W1 W F E D0 P P0(1) P2 MSA450 direction of unreeling For dimensions see Table 3. (1) Tolerance over any 10 pitches: 0.2 mm. Fig.8 Specification for 8 mm tape (SOT323, SOT353 and SOT363). 1997 Nov 26 ,, ,,, ,,, ,, ,,, ,,, , ,,, ,,, K0 A0 45 T Philips Semiconductors RF Wideband Transistors General section K K0 A0 T1 G B1 B 0 W1 D1 W F E D0 P2 P P 0 (1) MEA466 - 1 direction of unreeling For dimensions see Table 3. (1) Tolerance over any 10 pitches: 0.2 mm. Fig.9 Specification for 12 mm tape (SOT89). 1997 Nov 26 46 T Philips Semiconductors RF Wideband Transistors General section K K0 A0 T1 G B1 B 0 W1 D1 W F E D0 P2 P P 0 (1) MEA467 - 1 direction of unreeling For dimensions see Table 3. (1) Tolerance over any 10 pitches: 0.2 mm. Fig.10 Specification for 12 mm tape (SOT223). 1997 Nov 26 47 T Philips Semiconductors RF Wideband Transistors Table 3 General section SMD packages: tape dimensions (in mm) CARRIER TAPE DIMENSION (Figs 7 to 12) TOLERANCE 8 mm 12 mm 16 mm Overall dimensions W 8.0 12.0 16.0 0.2 K <1.5 <2.4 <2.2 - G >0.75 >0.75 >1.65 - D0 1.5 1.5 1.5 +0.1/-0 E 1.75 1.75 1.75 0.1 P0 4.0 4.0 4.0 0.1 Sprocket holes; note 1 Relative placement compartment P2 2.0 2.0 2.0 0.1 F 3.5 5.5 7.5 0.05 Compartment A0 B0 B1 Compartment dimensions depend on package size. Maximum clearance between device and compartment is 0.3 mm; the minimum clearance ensures that the device is not totally restrained within the compartment. K0 D1 >1.0 >1.5 >1.5 - P 4.0 8.0 12.0 0.1 <15 <15 - - W1 <5.4 <9.5 - - T1 <0.1 <0.1 - - W 8.0 12.0 16.0 0.2 T <0.2 <0.2 <0.4 - <0.3 <0.3 <0.3 - Cover tape; note 2 Carrier tape Notes 1. Tolerance over any 10 pitches 0.2 mm. 2. The cover tape shall not overlap the tape or sprocket holes. 1997 Nov 26 48 Philips Semiconductors RF Wideband Transistors General section t handbook, full pagewidth W O U E C B A trailer leader fixing tape MEA942 For dimensions see Table 2. Fig.11 Reel specification. Table 4 Reel dimensions (in mm) CARRIER TAPE DIMENSION (see Fig.11) TOLERANCE 8 mm 12 mm 16 mm Flange A 180(1) - 286 or 330 180 or 330 180 or 330 0.5 t 1.5 1.5 1.5 +0.5/-0.1 W 8.4 12.4 18 18.0+0.2 B 62 62 62 1.5 C 12.75 12.75 12.75 +0.15/-0.2 E 2 2 2 0.2 U 4 4 4 0.5 O 120 120 120 - Hub Key slot Note 1. Large reel diameter depends on individual package (286 or 350). 1997 Nov 26 49 Philips Semiconductors RF Wideband Transistors General section direction of unreeling handbook, full pagewidth top view e b c e c b c b e b c c e e e b e e c c e b e e b MEA471 SOT23 SOT323 SOT23 (reversed) SOT143 SOT143R SOT143 (cross emitter pinning) SOT143R (cross emitter pinning) Fig.12 Orientation of components: SOT23, SOT143, SOT143R and SOT323 (8 mm tape). direction of unreeling handbook, full pagewidth top view e b e b c e c MEA472 SOT223 SOT89 Fig.13 Orientation of components: SOT223 and SOT89 (12 mm tape). 1997 Nov 26 50 Philips Semiconductors RF Wideband Transistors General section MOUNTING AND SOLDERING Screen printing Mounting methods This is the best high-volume production method of solder paste application. An emulsion-coated, fine mesh screen with apertures etched in the emulsion to coincide with the surfaces to be soldered is placed over the substrate. A squeegee is passed across the screen to force solder paste through the apertures and on to the substrate. The layer thickness of screened solder paste is usually between 150 and 200 m. There are two basic forms of electronic component construction, those with leads for through-hole mounting and microminiature types for surface mounting (SMD). Through-hole mounting gives a very rugged construction and uses well established soldering methods. Surface mounting has the advantages of high packing density plus high-speed automated assembly. Surface mounting techniques are complex and this chapter gives only a simplified overview of the subject. Stencilling In this method a stencil with etched holes to pass the paste is used. The thickness of the stencil determines the amount of amount of solder paste that is deposited on the substrate. This method is also suited to high-volume work. Although many electronic components are available as surface mounting types, some are not and this often leads to the use of through-hole as well as surface mounting components on one substrate (a mixed print). The mix of components affects the soldering methods that can be applied. A substrate having SMDs mounted on one or both sides but no through-hole components is likely to be suitable for reflow or wave soldering. A double sided mixed print that has through-hole components and some SMDs on one side and densely packed SMDs on the other normally undergoes a sequential combination of reflow and wave soldering. When the mixed print has only through-hole components on one side and all SMDs on the other, wave soldering is usually applied. Dispensing A computer-controlled pressure syringe dispenses small doses of paste to where it is required. This method is mainly suitable for small production runs and laboratory use. Pin transfer A pin picks up a droplet of solder paste from a reservoir and transfers it to the surface of the substrate or component. A multi-pin arrangement with pins positioned to match the substrate is possible and this speeds up the process time. Reflow soldering SOLDER PASTE Most reflow soldering techniques utilize a paste that is a mixture of flux and solder. The solder paste is applied to the substrate before the components are placed. It is of sufficient viscosity to hold the components in place and, therefore, an application of adhesive is not required. Drying of the solder paste by preheating increases the viscosity and prevents any tendency for the components to become displaced during the soldering process. Preheating also minimizes thermal shock and drives off flux solvents. 1997 Nov 26 REFLOW TECHNIQUES Thermal conduction The prepared substrates are carried on a conveyor belt, first through a preheating stage and then through a soldering stage. Heat is transferred to the substrate by conduction through the belt. Figure 14 shows a theoretical time/temperature relationship for thermal conduction reflow soldering. This method is particularly suited to thick film substrates and is often combined with infrared heating. 51 Philips Semiconductors RF Wideband Transistors General section Infrared An infrared oven has several heating elements giving a broad spectrum of infrared radiation, normally above and below a closed loop belt system. There are separate zones for preheating, soldering and cooling. Dwell time in the soldering zone is kept as short as possible to prevent damage to components and substrate. A typical heating. profile is shown in Fig.15. This reflow method is often applied in double-sided prints. MBC938 250 T ( o C) 200 150 Vapour phase 100 A substrate is immersed in the vapours of a suitable boiling liquid. The vapours transfer latent heat of condensation to the substrate and solder reflow takes place. Temperature is controlled precisely by the boiling point of the liquid at a given pressure. Some systems employ two vapour zones, one above the other. An elevator tray, suspended from a hoist mechanism passes the substrate vertically through the first vapour zone into the secondary soldering zone and then hoists it out of the vapour to be cooled. A theoretical time/temperature relationship for this method is shown in Fig.16. 50 0 0 50 100 150 t (s) 200 Fig.14 Theoretical time/temperature curve for a typical thermal conductive reflow cycle. MBC939 MBC937 250 215 20 o / s T ( o C) T ( o C) 75 o / s 175 free air cooling 48 25 0 0 preheating max. 45 s soldering 8s cooling 20 s 10 - 30 s entering phase soldering zone 60 % of time in soldering zone Fig.15 Typical temperature profile of an infrared oven operating at a belt speed of 0.41 mm/min. 1997 Nov 26 45 s removal phase 150 % of time in soldering zone Fig.16 Theoretical time/temperature curve relationship for dual vapour reflow soldering. 52 Philips Semiconductors RF Wideband Transistors General section suited to low volume production. An advantage is the flexibility provided by computer programmability. Wave soldering This soldering technique is not recommended for SOT89. FLUXING ADHESIVE APPLICATION The quality of the soldered connections between components and substrate is critical for circuit performance and reliability. Flux promotes solderability of the connecting surfaces and is chosen for the following attributes: Since there are no connecting wires to retain them, leadless and short-leaded components are held in place with adhesive for wave soldering. A spot of adhesive is carefully placed between each SMD and the substrate. The adhesive is then heat-cured to withstand the forces of the soldering process, during which the components are fully immersed in solder. There are several methods of adhesive application. * Removal of surface oxides * Prevention of reoxidation * Transference of heat from source to joint area * Residue that is non-corrosive or, if residue is corrosive, should be easy to clean away after soldering Pin transfer method A pin is used to transfer a droplet of adhesive from a reservoir to a precise position on the surface where it is required. The size of the droplet depends on pin diameter, depth to which the pin is dipped in the reservoir, rheology of the adhesive, and the temperature of adhesive and surrounds. The pin can be part of a pin array (bed of nails) that corresponds exactly with the required adhesive positions on the substrate. With this method, adhesive can be applied to the whole of one side of a substrate in one operation and is therefore suitable for high-volume production and can be used with pre-loaded mixed prints. * Ability to improve wettability (readiness of a metal surface to form an alloy at its interface with the solder) to ensure strong joints with low electrical resistance * Suitability for the desired method of flux application. In wave soldering, liquified flux is usually applied as a foam, a spray or in a wave. Foam Alternatively, pins can be used to transfer adhesive to the components before they are placed on the substrate. This adds flexibility to production runs where variations in layout must be accommodated. Flux foam is made by forcing low-pressure, water-free clean air through an aerator immersed in liquid flux. Fine bubbles of flux are directed onto the substrate/component surfaces where they burst and form a thin, even layer. The flux also penetrates any plated-through holes. The flux has to be chosen for its foaming capabilities. Screen printing method Spray A fine mesh screen is coated with emulsion except in the positions where the adhesive is required to pass. The screen is placed on the substrate and a squeegee passing across it forces adhesive through the uncoated parts of the screen. The amount of adhesive printed-through depends on the size of the uncoated screen areas, the thickness of the screen coating, the rheology of the adhesive and various machine parameters. With this method, the substrate must be flat and pre-loaded mixed prints cannot be accommodated. Several methods of spray fluxing exist, the most common involves a mesh drum rotating in liquid flux. Air is blown into the drum which, when passing through the fine mesh, directs a spray of flux onto the underside of the substrate. The amount of flux deposited is controllable by the speed of the substrate passing through the spray, the speed of rotation of the drum and the density of the flux. Wave A wave fluxer creates a double flowing wave of liquid flux which adheres to the surface as the substrate passes through. Wave height control is essential and a soft wipe-off brush is usually incorporated to remove excess flux from the substrate. Pressure syringe method A computer-controlled syringe dispenses adhesive from an enclosed reservoir by means of pulses of compressed air. The adhesive dot size depends on the size of the syringe nozzle, the duration and pressure of the pulsed air and the viscosity of the adhesive. This method is most 1997 Nov 26 53 Philips Semiconductors RF Wideband Transistors General section surfaces. A smooth laminar solder wave is required to avoid bridging and a high pressure wave is needed to completely cover the areas that are difficult to wet. These conflicting demands are difficult to attain in a single wave but dual wave techniques go a long way in overcoming the problem. PRE-HEATING Pre-heating of the substrate and components is performed immediately before soldering. This reduces thermal shock as the substrate enters the soldering process, causes the flux to become more viscous and accelerates the chemical action of the flux and so speeds up the soldering action. In a dual wave machine (see Fig.18), the substrate first comes into contact with a turbulent wave which has a high vertical velocity. This ensures good solder contact with both edges of the components and prevents joints from being missed. The second smooth laminar wave completes the formation of the solder fillet, removes excess solder and prevents bridging. Figure 19 indicates the time/temperature relationship measured at the soldering site in dual wave soldering. SOLDERING Wave soldering is usually the best method to use when high throughput rates are required. The single wave soldering principle (see Fig.17) is the most straight forward method and can be used on simple substrates with two-terminal SMD components. More complex substrates with increased circuit density and closer spacing of conductors can pose the problems of nonwetting (dry joints) and solder bridging. Bridging can occur across the closely spaced leads of multi-leaded devices as well as across adjacent leads on neighbouring components. Nonwetting is usually caused by components with plastic bodies. The plastic is not wetted by solder and creates a depression in the solder wave, which is augmented by surface tension. This can cause a shadow behind the component and prevent solder from reaching the joint New methods of wave soldering are developing continually. For example, the Omega System is a single wave agitated by pulses, which combines the functions of smoothness and turbulence. In another, a lambda wave injects air bubbles in the final part of the wave. A further innovation is the hollow jet wave in which the solder wave flows in the opposite direction to the substrate. board travel board travel handbook, halfpage SMDs MBC935 MBC934 solder solder Fig.17 Single wave soldering principle. 1997 Nov 26 Fig.18 Dual wave soldering principle. 54 Philips Semiconductors RF Wideband Transistors General section Footprint design The footprint design of a component for surface mounting is influenced by many factors: * Features of the component, its dimensions and tolerances MBC936 handbook, halfpage 300 T o ( C) * Circuit board manufacturing processes 250 * Desired component density * Minimum spacing between components 200 * Circuit tracks under the component 1 K/s 200 K/s * Component orientation (if wave soldering) 150 * Positional accuracy of solder resist to solder lands * Positional accuracy of solder paste to solder lands (if reflow soldering) 100 * Component placement accuracy 50 * Soldering process parameters 0 0 50 100 * Solder joint reliability parameters. time (s) 150 Fig.19 Typical time-temperature curve measured at the soldering site. 1997 Nov 26 55 Philips Semiconductors RF Wideband Transistors General section SOT23 FOOTPRINTS 2.90 2.50 handbook, full pagewidth 2 0.85 1.30 3.00 0.85 ,, ,, ,, ,, , , solder lands solder resist 1 2.70 3 occupied area solder paste 0.60 (3x) 0.50 (3x) 0.60 (3x) 1.00 3.30 MSA439 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.20 Reflow soldering footprint for SOT23; typical dimensions. 3.40 handbook, full pagewidth ,,,,,, ,,, ,,, ,,, ,,, ,,,, ,,,, ,,,, 1.20 (2x) 2 4.60 4.00 1.20 solder lands solder resist occupied area 1 3 2.80 4.50 preferred transport direction during soldering MSA427 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.21 Wave soldering footprint for SOT23; typical dimensions. 1997 Nov 26 56 Philips Semiconductors RF Wideband Transistors General section SOT143 FOOTPRINTS 3.25 0.60 (3x) 0.50 (3x) handbook, full pagewidth ,,,, ,, ,, ,,,, ,,,, 0.60 (4x) 4 2.70 solder lands solder resist 3 1 1.30 3.00 2 0.90 1.00 occupied area solder paste MSA441 2.50 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.22 Reflow soldering footprint for SOT143; typical dimensions. handbook, full pagewidth ,, ,, ,, ,, ,, ,, 4.45 ,, ,, ,, ,, ,, ,, 1.20 (3x) 4 3 1 solder lands solder resist occupied area 1.15 4.00 4.60 2 preferred transport direction during soldering MSA422 1.00 3.40 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.23 Wave soldering footprint for SOT143; typical dimensions. 1997 Nov 26 57 Philips Semiconductors RF Wideband Transistors General section SOT89 FOOTPRINTS 4.75 2.25 2.00 1.90 1.20 handbook, full pagewidth ,,,, ,,,, ,,,, ,,,, ,,,,,, ,, ,, ,,,, ,, ,,,,,, ,, 0.85 0.20 1.20 4.60 1.20 1.00 (3x) 2 3 solder lands solder resist occupied area 1.70 solder paste 4.85 0.50 1.20 1 MSA442 0.60 (3x) 0.70 (3x) 3.70 3.95 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.24 Reflow soldering footprint for SOT89; typical dimensions. 1997 Nov 26 58 Philips Semiconductors RF Wideband Transistors General section ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 6.60 2.40 handbook, full pagewidth solder lands solder resist 7.60 0.50 2 1.50 1 occupied area 3.50 3 1.20 3.00 transport direction during soldering MSA423 0.70 5.30 We do not recommend SOT89 for wave soldering, SOT223 is preferred. Dimensions in mm. Placement accuracy: 0.25 mm. Fig.25 Wave soldering footprint for SOT89: typical dimensions. 1997 Nov 26 59 Philips Semiconductors RF Wideband Transistors General section SOT223 FOOTPRINTS 7.00 3.85 3.60 3.50 handbook, full pagewidth ,,,, ,,,, 0.30 1.20 (4x) solder lands solder resist 4 occupied area solder paste 7.40 3.90 4.80 7.65 ,, ,, ,, ,,,,,, 1 2 3 1.20 (3x) 1.30 (3x) 5.90 6.15 MSA443 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.26 Reflow soldering footprint for SOT223; typical dimensions. 1997 Nov 26 60 Philips Semiconductors RF Wideband Transistors General section ,,,,,,, ,,,,,,, ,,,,,,, 8.90 6.70 handbook, full pagewidth solder lands solder resist occupied area 4 4.30 8.10 8.70 ,,, ,, ,,,,, ,,, ,,, ,,, ,,,,, 1 2 1.90 (2x) 3 1.10 7.30 preferred transport direction during soldering MSA424 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.27 Wave soldering footprint for SOT223; typical dimensions. 1997 Nov 26 61 Philips Semiconductors RF Wideband Transistors General section SOT323 FOOTPRINTS 2.65 0.75 1.325 1.30 handbook, full pagewidth solder lands 2 solder resist 0.60 2.35 0.85 (3x) 0.50 (3x) 1.90 3 occupied area 1 0.55 (3x) solder paste MSA429 2.40 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.28 Reflow soldering footprint for SOT323; typical dimensions. 4.60 4.00 1.15 handbook, full pagewidth solder lands solder resist 2 occupied area 3.65 2.10 3 2.70 0.90 (2x) 1 MSA419 preferred transport direction during soldering Dimensions in mm. Placement accuracy: 0.25 mm. Fig.29 Wave soldering footprint for SOT323; typical dimensions. 1997 Nov 26 62 Philips Semiconductors RF Wideband Transistors General section SOT343 FOOTPRINTS 2.50 handbook, full pagewidth 0.60 (3x) ,,,, ,,,, ,,,, 0.50 (3x) 0.55 (4x) 3 solder lands solder resist 4 1.30 2.40 2.70 1 occupied area 2 solder paste MSA430 0.70 0.80 1.90 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.30 Reflow soldering footprint for SOT343; typical dimensions. handbook, full pagewidth 3.65 0.90 (3x) ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,,,, 4 1 solder lands 3 2 2.30 solder resist occupied area 1.15 4.00 3.00 transport direction during soldering MSA421 1.00 2.70 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.31 Wave soldering footprint for SOT343; typical dimensions. 1997 Nov 26 63 Philips Semiconductors RF Wideband Transistors General section SOT353 FOOTPRINTS 2.65 2.40 1.30 handbook, full pagewidth solder lands 5 1 solder resist 2 2.10 0.90 0.40 0.50 2.35 (4x) 3 4 occupied area solder paste MSA431 0.55 (5x) Dimensions in mm. Placement accuracy: 0.25 mm. Fig.32 Reflow soldering footprint for SOT353; typical dimensions. A + 1.00 handbook, full pagewidth 2.30 A 2.00 1.15 solder lands solder resist 1 occupied area 5 2 4.00 1.00 0.30 0.90 2.70 4.60 transport direction during soldering 4 3 A = 2.00 for carrier soldering A = 2.50 for carrier less soldering MSA425 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.33 Wave soldering footprint for SOT353; typical dimensions. 1997 Nov 26 64 Philips Semiconductors RF Wideband Transistors General section SOT363 FOOTPRINTS 2.65 2.40 1.30 handbook, full pagewidth solder lands 2.35 0.50 (4x) 1 6 2 5 3 0.40 (2x) solder resist 0.90 2.10 occupied area 4 solder paste 0.55 (6x) MSA432 Dimensions in mm. Placement accuracy: 0.25 mm. Fig.34 Reflow soldering footprint for SOT363; typical dimensions. A + 2.00 handbook, full pagewidth A 1.15 solder lands solder resist 1 6 occupied area 4.60 4.00 2 5 3 4 0.30 1.00 transport direction during soldering A = 4.00 for carrier soldering A = 5.00 for carrier less soldering MSA426 Dimensions in mm. Placement accuracy: Fig.35 Wave soldering footprint for SOT363; typical dimensions. 1997 Nov 26 65 Philips Semiconductors RF Wideband Transistors General section The peak temperature of the die depends on the ability of the package and its mounting to transfer heat from this die to ambient environment (see Fig.38). The basic relationship between die temperature (junction temperature) and power dissipation is: Hand soldering microminiature components It is possible to solder microminiature components with a light-weight hand-held soldering iron, but this method has obvious drawbacks and should be restricted to laboratory use and/or incidental repairs on production circuits: Tj max = Tamb + Pd max x [Rth j-s + Rth s-a] * Hand-soldering is time-consuming and therefore expensive ,, ,, * The component cannot be positioned accurately and the connecting tags may come into contact with the substrate and damage it , , ,, , , * There is a risk of breaking the substrate and internal connections in the component could be damaged handbook, halfpage * The component package could be damaged by the iron. THERMAL CONSIDERATIONS Thermal resistance die collector lead or anode lead solder point MBG387 printed circuit board Circuit performance and long-term reliability are affected by the temperature of the transistor die. Normally, both are improved by keeping the die temperature (junction temperature) low. Fig.36 Assembly of SMD package and PCB. Electrical power dissipated in any semiconductor device is a source of heat. This increases the temperature of the die above a certain reference point. The most relevant reference point of the semiconductor device is the soldering point (i.e. the point on the printed-circuit board where the collector lead is soldered to a heat-draining point see Figs 36 and 37). handbook, halfpage solder point The temperature rise as a function of dissipation power, `thermal resistance', is given in the data sheets as the Rth j-s value. The heat is drained by conduction via the leadframe, soldering point and substrate (printed-circuit board) to ambient. The amount of radiated and convected heat is negligible in comparison to the conducted heat. MBG386 printed circuit board Fig.37 Assembly of SOD80-like package and PCB. The elements of thermal resistance are defined as follows: Pd Power dissipation (W) Rth j-s Thermal resistance from junction to soldering point (K/W) Rth s-a Thermal resistance from soldering point to ambient (K/W) Rth j-a Thermal resistance from junction to ambient (K/W) Tj Junction temperature of the die (C) Ts Soldering point temperature (C) Tamb Ambient temperature (C) Tref Temperature of the reference point (C) 1997 Nov 26 Thermal resistance from junction to soldering point [Rth(j-s)] In the example for Tj max, only Tamb and Rth s-a can be varied by the user. The construction of the printed-circuit board (PCB) and the ambient condition (as there is air flow) affect Rth s-a. The device power dissipation can be controlled to a limited extent, under recommended usage. The supply voltage and circuit loading dictate a fixed power maximum. The Rth j-s value is essentially independent of external mounting method and cooling air, but is sensitive to the materials used in the package construction, the die mount and the die area, all of which are fixed. 66 Philips Semiconductors RF Wideband Transistors General section Values of Tj max and Rth j-s, or Rth j-c are given in the device data sheets. For applications where Ts is known, Tj can be calculated from: Tj = Ts + Pd x Rth j-s MBC389 10 4 ESR (m) Thermal resistance from soldering point to ambient [Rth s-a] 500 MHz 103 There is a limiting value for the soldering point temperature. For the normal tin alloy (Sn-Pb 60% - 40%): Ts max = 110 C. The value of Ts can be calculated from: 200 MHz Ts = Ta + Pd x Rth s-a. 100 MHz 102 The thermal resistance from soldering point to ambient depends on the shape and material of the tracks on a printed-circuit board as illustrated in Fig.39. 50 MHz 10 Summary of the SMD envelopes 1 10 102 C (pF) 103 These thermal considerations are valid for the following envelopes: (1) (2) (3) (4) SOD80, SOD87, SOD106, SOD110, SOD123, SOD323, SC59, SC70, SOT23, SOT89, SOT123, SOT143, SOT223, SOT323, SOT343, SOT346 and SO8 (SOT96-1). Single-sided, unplated. Single-sided, plated. Double-sided, unplated. Double-sided, plated. Fig.39 Thermal resistance (Rth s-a) as a function of pad area on different configurations of FR4 epoxy fibre-glass circuit board. Temperature calculation under pulsed conditions In pulsed power conditions, the peak temperature of the die depends on the pulse time and duty factor as well as the ability of the package and its mounting to disperse heat. junction handbook, halfpage Rth j-s soldering point When power is applied in repetitive square-wave pulses with a certain duty factor (), the variation in junction temperature has a sawtooth characteristic. R th j-a The average steady-state junction temperature is: Rth s-a Tj(av) = Tref + x Pd x Rth j-ref ambient The peak junction temperature, however, is the most relevant to performance reliability. This can be calculated by heating and cooling step functions that result in heating and cooling curves shifted in time as shown in Fig.40. MBG385 The peak value of Tj is reached at the end of a power pulse and the minimum value immediately before the next power pulse. The thermal ripple is the difference between Tj(peak) and Tj(min). Fig.38 Representation of thermal resistance paths of a device mounted on a substrate or printed board. Calculation of Tj(peak) after n pulses: 1997 Nov 26 67 Philips Semiconductors RF Wideband Transistors a= n - 1 T j(peak) = T ref + P d x General section [ Z th ( at - w ) - Z th ( at ) ] a= 0 where a is an integer number. Pd (W) halfpage handbook, Pd (av) d-w/t w t Tj-ref (K) Pd handbook, Pd (w) halfpage T(av)1 = d x Pd x Rth j-ref d-w/t w T2 = Pd x Zth (t+w) T3 = Pd x Zth (w) t power Pd + Pd 0 - T(av)2 = d x Pd x Zth (2t+w) T4 = Pd x Zth (+) Pd Tj (oC) Pd Pd Tj (av) Tj (peak) thermal-ripple Tj Tj (min) Tj T1 T2 T3 MBG390 Tj (peak) = Ta + T1 + T2 + T3 + T4 - T5 - T6 - T7 Ta T4 T5 Tj Fig.41 Two-pulse approximation method of finding peak steady-state junction temperature [Tj(peak)]. Tj (peak) thermal-ripple Tj (min) The junction temperature at the end of the second pulse is: MBG391 Tj(peak) = Tref + Pd x [ x Rth(j-ref) + (1 - ) x Zth(t+w) + Zth(w) - Zth(t)] The junction temperature immediately before the second power pulse is: Fig.40 Heating effect of three identical power pulses after thermal stabilization. Tj(min) = Tref + Pd x [ x Rth(j-ref) + (1 - ) x Zth(t) + Zth(w) - Zth(t-w)] Approximation method of finding Tj(peak) The thermal ripple is: With this method it is assumed that the average load is immediately followed by two square power pulses as shown in Fig.41. This two-pulse approximation method is accurate enough for finding Tj(peak). Tj = Tj(peak) - Tj(min) Tj = Pd x [ x (Zth(t) - Zth(t+w) - 2 x Zth(t) + Zth(w) + Zth(t-w)] Reducing calculation time To be able to point out the junction peak temperature at a certain pulse time and duty cycle, a graph similar to that shown in Fig.42 is included in relevant data sheets. In this example, the curves have been derived using the formula 1997 Nov 26 68 Philips Semiconductors RF Wideband Transistors General section Tj(peak) = Tref + Pd x [ x Rth(j-ref) + (1 - ) x Zth(t+w) + Zth(w) - Zth(t)], with typical values inserted. Soldering point temperature provides a better reference point than ambient temperature as this is subject to many uncontrolled variables. Therefore, the thermal resistance from junction to soldering point [Rth(j-s)] is becoming a more relevant measurement path. The pulse width along the X-axis meets a particular duty cycle curve, indicating the Zth value in K/W along the Y-axis. Tj(peak) = Pd(peak) x Zth(j-s) + Pd(av) x Rth(s-a) + Ta (C) MBG388 103 handbook, full pagewidth Zth j-a (K/W) = 0.75 0.5 10 2 0.3 0.2 0.1 tp = T P 0.05 0 t tp T 10 10-6 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Fig.42 Direct reading of thermal impedance from junction to soldering point for calculation of junction temperature at pulsed power condition. 1997 Nov 26 69 Philips Semiconductors RF Wideband Transistors General section ELECTROSTATIC CHARGES RECEIPT AND STORAGE Electrostatic charges can exist in many things; for example, man-made-fibre clothing, moving machinery, objects with air blowing across them, plastic storage bins, sheets of paper stored in plastic envelopes, paper from electrostatic copying machines, and people. The charges are caused by friction between two surfaces, at least one of which is non-conductive. The magnitude and polarity of the charges depend on the different affinities for electrons of the two materials rubbing together, the friction force and the humidity of the surrounding air. Our devices are packed for dispatch in antistatic/conductive containers, usually boxes, tubes or blister tape. The fact that the contents are sensitive to electrostatic discharge is shown by warning labels on both primary and secondary packing. The devices should be kept in their original packing whilst in storage. If a bulk container is partially unpacked, the unpacking should be performed at a protected work station. Any devices that are stored temporarily should be packed in conductive or antistatic packing or carriers. Electrostatic discharge is the transfer of an electrostatic charge between bodies at different potentials and occurs with direct contact or when induced by an electrostatic field. Our devices can be damaged if the following precautions are not taken. ASSEMBLY The devices must be removed from their protective packing with earthed component pincers or short-circuit clips. Short-circuit clips must remain in place during mounting, soldering and cleansing/drying processes. Do not remove more devices from the storage packing than are needed at any one time. Production/assembly documents should state that the product contains electrostatic sensitive devices and that special precautions need to be taken. WORK STATION Figure 43 shows a working area suitable for safely handling electrostatic sensitive devices. It has a work bench, the surface of which is conductive or covered by an antistatic sheet. Typical resistivity for the bench surface is between 1 and 500 k per cm2. The floor should also be covered with antistatic material. All tools used during assembly, including soldering tools and solder baths, must be earthed. All hand tools should be of conductive or antistatic material and, where possible, should not be insulated. The following precautions should be observed: * Persons at a work bench should be earthed via a wrist strap and a resistor Measuring and testing of completed circuit boards must be done at a protected work station. Place the soldered side of the circuit board on conductive or antistatic foam and remove the short-circuit clips. Remove the circuit board from the foam, holding the board only at the edges. Make sure the circuit board does not touch the conductive surface of the work bench. After testing, replace the circuit board on the conductive foam to await packing. * All mains-powered electrical equipment should be connected via an earth leakage switch * Equipment cases should be earthed * Relative humidity should be maintained between 50 and 65% * An ionizer should be used to neutralize objects with immobile static charges. 1997 Nov 26 Assembled circuit boards should be handled in the same way as unmounted devices. They should also carry warning labels and be packed in conductive or antistatic packing. 70 Philips Semiconductors RF Wideband Transistors General section (1) handbook, full pagewidth (2) (2) (2) (3) (7) (6) (8) (5) (4) ,,,,,,,,,, (9) (1) (2) (3) (4) (5) (6) (7) (8) (9) Earthing rail. Resistor (500 k 10%, 0.5 W). Ionizer. Work bench. Chair. Wrist strap. Electrical equipment. Conductive surface/antistatic sheet. Antistatic floor. Fig.43 Protected work station. 1997 Nov 26 71 MLB049