1997 Nov 26 34
Philips Semiconductors
RF Wideband Transistors General section
QUALITY
Total Quality Management
Philips Semiconductors is a Quality Company, renowned
for the high quality of our products and service. We keep
alive this tradition by constantly aiming towards one
ultimate standard, that of zero defects. This aim is guided
by our Total Quality Management (TQM) system, the basis
of which is described in the following paragraphs.
QUALITY ASSURANCE
Based on ISO 9000 standards, customer standards such
as Ford TQE and IBM MDQ. Our factories are certified to
ISO 9000 by external inspectorates.
PARTNERSHIPS WITH CUSTOMERS
PPM co-operations, design-in agreements, ship-to-stock,
just-in-time and self-qualification programmes, and
application support.
PARTNERSHIPS WITH SUPPLIERS
Ship-to-stock, statistical process control and ISO 9000
audits.
QUALITY IMPROVEMENT PROGRAMME
Continuous process and system improvement, design
improvement, complete use of statistical process control,
realization of our final objective of zero defects, and
logistics improvement by ship-to-stock and just-in-time
agreements.
Advanced quality planning
During the design and development of new products and
processes, quality is built-in by advanced quality planning.
Through failure-mode-and-effect analysis the critical
parameters are detected and measures taken to ensure
good performance on these parameters. The capability of
process steps is also planned in this phase.
Product conformance
The assurance of product conformance is an integral part
of our quality assurance (QA) practice. This is achieved by:
•Incoming material management through partnerships
with suppliers.
•In-line quality assurance to monitor process
reproducibility during manufacture and initiate any
necessary corrective action. Critical process steps are
100% under statistical process control.
•Acceptance tests on finished products to verify
conformance with the device specification. The test
results are used for quality feedback and corrective
actions. The inspection and test requirements are
detailed in the general quality specifications.
•Periodic inspections to monitor and measure the
conformance of products.
Product reliability
With the increasing complexity of Original Equipment
Manufacturer (OEM) equipment, component reliability
must be extremely high. Our research laboratories and
development departments study the failure mechanisms of
semiconductors. Their studies result in design rules and
process optimization for the highest built-in product
reliability. Highly accelerated tests are applied to the
products reliability evaluation. Rejects from reliability tests
and from customer complaints are submitted to failure
analysis, to result in corrective action.
Customer responses
Our quality improvement depends on joint action with our
customer. We need our customer’s inputs and we invite
constructive comments on all aspects of our performance.
Please contact our local sales representative.
Recognition
The high quality of our products and services is
demonstrated by many Quality Awards granted by major
customers and international organizations.
PRO ELECTRON TYPE NUMBERING SYSTEM
Basic type number
This type designation code applies to discrete
semiconductor devices (not integrated circuits), multiples
of such devices, semiconductor chips and Darlington
transistors.
FIRST LETTER
The first letter gives information about the material for the
active part of the device.
A Germanium or other material with a band gap of
0.6 to 1 eV
B Silicon or other material with a band gap of
1 to 1.3 eV
C Gallium arsenide (GaAs) or other material with a
band gap of 1.3 eV or more
R Compound materials, e.g. cadmium sulphide.
1997 Nov 26 35
Philips Semiconductors
RF Wideband Transistors General section
SECOND LETTER
The second letter indicates the function for which the
device is primarily designed. The same letter can be used
for multi-chip devices with similar elements.
In the following list low power types are defined by
Rth j-mb > 15 K/W and power types by Rth j-mb ≤15 K/W.
A Diode; signal, low power
B Diode; variable capacitance
C Transistor; low power, audio frequency
D Transistor; power, audio frequency
E Diode; tunnel
F Transistor; low power, high frequency
G Multiple of dissimilar devices/miscellaneous
devices; e.g. oscillators. Also with special third
letter; see under Section “Serial number”
H Diode; magnetic sensitive
L Transistor; power, high frequency
N Photocoupler
P Radiation detector; e.g. high sensitivity
photo-transistor; with special third letter
Q Radiation generator; e.g. LED, laser; with special
third letter
R Control or switching device; e.g. thyristor, low
power; with special third letter
S Transistor; low power, switching
T Control or switching device; e.g. thyristor, low
power; with special third letter
U Transistor; power, switching
W Surface acoustic wave device
X Diode; multiplier, e.g. varactor, step recovery
Y Diode; rectifying, booster
Z Diode; voltage reference or regulator, transient
suppressor diode; with special third letter.
SERIAL NUMBER
The number comprises three figures running from
100 to 999 for devices primarily intended for consumer
equipment, or one letter (Z, Y, X, etc.) and two figures
running from 10 to 99 for devices primarily intended for
industrial or professional equipment.(1)
(1) When the supply of these serial numbers is exhausted, the
serial number may be expanded to three figures for industrial
types and four figures for consumer types.
Version letter
A letter may be added to the basic type number to indicate
minor electrical or mechanical variants of the basic type.
RATING SYSTEMS
The rating systems described are those recommended by
the IEC in its publication number 134.
Definitions of terms used
ELECTRONIC DEVICE
An electronic tube or valve, transistor or other
semiconductor device. This definition excludes inductors,
capacitors, resistors and similar components.
CHARACTERISTIC
A characteristic is an inherent and measurable property of
a device. Such a property may be electrical, mechanical,
thermal, hydraulic, electro-magnetic or nuclear, and can
be expressed as a value for stated or recognized
conditions. A characteristic may also be a set of related
values, usually shown in graphical form.
BOGEY ELECTRONIC DEVICE
An electronic device whose characteristics have the
published nominal values for the type. A bogey electronic
device for any particular application can be obtained by
considering only those characteristics that are directly
related to the application.
RATING
A value that establishes either a limiting capability or a
limiting condition for an electronic device. It is determined
for specified values of environment and operation, and
may be stated in any suitable terms. Limiting conditions
may be either maxima or minima.
RATING SYSTEM
The set of principles upon which ratings are established
and which determine their interpretation. The rating
system indicates the division of responsibility between the
device manufacturer and the circuit designer, with the
object of ensuring that the working conditions do not
exceed the ratings.
Absolute maximum rating system
Absolute maximum ratings are limiting values of operating
and environmental conditions applicable to any electronic
1997 Nov 26 36
Philips Semiconductors
RF Wideband Transistors General section
device of a specified type, as defined by its published data,
which should not be exceeded under the worst probable
conditions.
These values are chosen by the device manufacturer to
provide acceptable serviceability of the device, taking no
responsibility for equipment variations, environmental
variations, and the effects of changes in operating
conditions due to variations in the characteristics of the
device under consideration and of all other electronic
devices in the equipment.
The equipment manufacturer should design so that,
initially and throughout the life of the device, no absolute
maximum value for the intended service is exceeded with
any device, under the worst probable operating conditions
with respect to supply voltage variation, equipment
component variation, equipment control adjustment, load
variations, signal variation, environmental conditions, and
variations in characteristics of the device under
consideration and of all other electronic devices in the
equipment.
Design maximum rating system
Design maximum ratings are limiting values of operating
and environmental conditions applicable to a bogey
electronic device of a specified type as defined by its
published data, and should not be exceeded under the
worst probable conditions.
These values are chosen by the device manufacturer to
provide acceptable serviceability of the device, taking
responsibility for the effects of changes in operating
conditions due to variations in the characteristics of the
electronic device under consideration.
The equipment manufacturer should design so that,
initially and throughout the life of the device, no design
maximum value for the intended service is exceeded with
a bogey electronic device, under the worst probable
operating conditions with respect to supply voltage
variation, equipment component variation, variation in
characteristics of all other devices in the equipment,
equipment control adjustment, load variation, signal
variation and environmental conditions.
Design centre rating system
Design centre ratings are limiting values of operating and
environmental conditions applicable to a bogey electronic
device of a specified type as defined by its published data,
and should not be exceeded under normal conditions.
These values are chosen by the device manufacturer to
provide acceptable serviceability of the device in average
applications, taking responsibility for normal changes in
operating conditions due to rated supply voltage variation,
equipment component variation, equipment control
adjustment, load variation, signal variation, environmental
conditions, and variations in the characteristics of all
electronic devices.
The equipment manufacturer should design so that,
initially, no design centre value for the intended service is
exceeded with a bogey electronic device in equipment
operating at the stated normal supply voltage.
LETTER SYMBOLS
The letter symbols for transistors detailed in this section
are based on IEC publication number 148.
Basic letters
In the representation of currents, voltages and powers,
lower-case letter symbols are used to indicate all
instantaneous values that vary with time. All other values
are represented by upper-case letters.
Electrical parameters(1) of external circuits and of circuits
in which the device forms only a part are represented by
upper-case letters. Lower-case letters are used for the
representation of electrical parameters inherent in the
device. Inductances and capacitances are always
represented by upper-case letters.
The following is a list of basic letter symbols used with
semiconductor devices:
B, b Susceptance (imaginary part of an admittance)
C Capacitance
G, g Conductance (real part of an admittance)
H, h Hybrid parameter
I, i Current
L Inductance
P, p Power
R, r Resistance (real part of an impedance)
V, v Voltage
X, x Reactance (imaginary part of an impedance)
Y, y Admittance
Z, z Impedance.
(1) For the purpose of this publication, the term ‘electrical
parameters’ applies to four-pole matrix parameters, elements
of electrical equivalent circuits, electrical impedances and
admittances, inductances and capacitances.
1997 Nov 26 37
Philips Semiconductors
RF Wideband Transistors General section
Subscripts
Upper-case subscripts are used for the indication of:
•Continuous (DC) values (without signal), e.g. ID, IB
•Instantaneous total values, e.g. iD, iB
•Average total values, e.g. ID(AV), IB(AV)
•Peak total values, e.g. IDM, IBM
•Root-mean-square total values, e.g. ID(RMS); IB(RMS).
Lower-case subscripts are used for the indication of values
applying to the varying component alone:
•Instantaneous values, e.g. ib
•Root-mean-square values, e.g. Id(rms)
•Peak values, e.g. Ibm
•Average values, e.g. Id(av).
The following is a list of subscripts used with basic letter
symbols for semiconductor devices:
A, a anode
amb ambient
(AV), (av) average value
B, b base
(BO) breakover
(BR) breakdown
case case
C, c collector
C controllable
D, d drain
E, e emitter
F, f fall, forward (or forward transfer)
G, g gate
H holding
h heatsink
I, i input
j-a junction to ambient
j-mb junction to mounting base
K, k cathode
L load
M, m peak value
(min) minimum
(max) maximum
mb mounting base
O, o As first subscript: reverse (or reverse
transfer), rise. As second subscript:
repetitive, recovery. As third subscript: with a
specified resistance between the terminal
not mentioned and the reference terminal
(OV) Overload
P, p Pulse
Q, q Turn-off
R, r As first subscript: reverse (or reverse
transfer), rise. As second subscript:
repetitive, recovery. As third subscript: with a
specified resistance between the terminal
not mentioned and the reference terminal
(RMS), (rms) Root-mean-square value
S, s As first subscript: series, source, storage,
stray, switching. As second subscript: surge
(non-repetitive). As third subscript: short
circuit between the terminal not mentioned
and the reference terminal
stg Storage
th Thermal
TO Threshold
tot Total
W Working
X, x Specified circuit
Z, z Reference or regulator (zener)
1 Input (four-pole matrix)
2 Output (four-pole matrix).
Applications and examples
TRANSISTOR CURRENTS
The first subscript indicates the terminal carrying the
current (conventional current flow from the external circuit
into the terminal is positive).
Examples: ID, IB, iD, iB, id, ib, Idm, ibm.
TRANSISTOR VOLTAGES
A voltage is indicated by the first two subscripts: the first
identifies the terminal at which the voltage is measured
and the second the reference terminal or the circuit node.
The second subscript may be omitted when there is no
possibility of confusion.
Examples: VGS, vGS, vgs, Vgsm, VBE, vBE, vbe, Vbem.
SUPPLY VOLTAGES OR CURRENTS
Supply voltages or supply currents are indicated by
repeating the appropriate terminal subscript.
1997 Nov 26 38
Philips Semiconductors
RF Wideband Transistors General section
Examples: VDD, ISS, VCC; IEE.
A reference terminal is indicated by a third subscript.
Example: VDDS, VCCE.
DEVICES WITH MORE THAN ONE TERMINAL OF THE SAME KIND
If a device has more than one terminal of the same kind,
the subscript is formed by the appropriate letter for the
terminal, followed by a number. Hyphens may be used to
avoid confusion in multiple subscripts.
Examples:
ID2 Continuous (DC) current flowing into the
second gate terminal
VB2-E Continuous (DC) voltage between the
terminals of second base and emitter.
MULTIPLE DEVICES
For multiple unit devices, the subscripts are modified by a
number preceding the letter subscript. Hyphens may be
used to avoid confusion in multiple subscripts.
Examples:
I2B Continuous (DC) current flowing into the
base terminal of the second unit
V1D-2D Continuous (DC) voltage between the drain
terminals of the first and second units.
ELECTRICAL PARAMETERS
The upper-case variant of a subscript is used for the
designation of static (DC) values.
Examples:
gFS Static value of forward transconductance in
common-source configuration (DC current
gain)
hFE Static value of forward current transfer in
common-emitter configuration (DC current
gain)
RDS DC value of the drain-source resistance.
REDC value of the external emitter resistance.
The static value is the slope of the line from the origin to
the operating point on the appropriate characteristic curve,
i.e. the quotient of the appropriate electrical quantities at
the operating point.
The lower-case variant of a subscript is used for the
designation of small-signal values.
Examples:
gfs Small-signal value of the short-circuit
forward transconductance in
common-source configuration
hfe Small-signal value of the short-circuit
forward current transfer ratio in
common-emitter configuration
Zi = Ri + jXiSmall-signal value of the input impedance.
If more than one subscript is used, subscripts for which a
choice of style is allowed, the subscripts chosen are all
upper-case or all lower-case.
Examples: hFE, yRE, hfe, gFS.
FOUR-POLE MATRIX PARAMETERS
The first letter subscript (or double numeric subscript)
indicates input, output, forward transfer or reverse
transfer.
Examples: hi (or h11), ho (or h22), hf (or h21), hr (or h12).
A further subscript is used for the identification of the circuit
configuration. When no confusion is possible, this further
subscript may be omitted.
Examples: hfe (or h21e), hFE (or h21E).
DISTINCTION BETWEEN REAL AND IMAGINARY PARTS
If it is necessary to distinguish between real and imaginary
parts of electrical parameters, no additional subscripts are
used. If basic symbols for the real and imaginary parts
exist, these may be used.
Examples: Zi = Ri + jXi,y
fe = gfe + jbfe.
If such symbols do not exist or are not suitable, the
notation shown in the following examples is used.
Examples:
Re (hib) etc. for the real part of hib
Im (hib) etc. for the imaginary part of hib.
S-PARAMETER DEFINITIONS
The S-parameter symbols in this section are based on
IEC publication 747 −7.
S-parameters (return losses or reflection coefficients) of a
module can be defined as the S11 and S22 of a two-port
network (see Fig.1).
1997 Nov 26 39
Philips Semiconductors
RF Wideband Transistors General section
(1)
(2)
where:
(3)
(4)
From (1) and (2) formulae for the return losses can be
derived:
(5)
(6)
Fig.1 Two-port network with reflection coefficients
S11 and S22.
D.U.T.
S11 S22
a1
b1
b2
a2
MLB335
b1S11 a1
×S12 a2
×+=
b2S21 a1S22 a2
×+×=
a11
2Z
0
×
-------------------- V1
(Z0i1)×+×signal into port 1==
a
2
1
2Z
0
×
-------------------- V2Z0i2)×+(× signal into port 2==
b
1
1
2Z
0
×
-------------------- V1Z0i1)×+(× signal out port 1==
b
2
1
2Z
0
×
-------------------- V2Z0i2)×+(× signal out port 2==
S
11 b1
a1
------ a20==
S
22 b2
a2
------ a10==
In (5), a2= 0 means output port terminated with Z0
(derived from formula (4)).
In (6), a1= 0 means input port terminated with Z0
(derived from formula (3)).
Measurement
The return losses are measured with a network analyzer
after calibration, where the influence of the test jig is
eliminated. The necessary termination of the other port
with Z0 is done automatically by the network analyzer.
The network analyser must have a directivity of at least
40 dB to obtain an accuracy of 0.5 dB when measuring
return loss figures of 20 dB. A full two-port correction
method can be used to improve the accuracy.
TAPE AND REEL PACKING
Tape and reel packing meets the feed requirements of
automatic pick and place equipment (packing conforms to
IEC publication 286-2 and 286-3). Additionally, the tape is
an ideal shipping container.
Packing TO-92 (SOT54) leaded types
The transistors are supplied on tape in boxes (ammopack)
or on reels. The number per reel and per ammopack is
2000. The ammopack has 80 layers of 25 transistors
each. Each layer contains 25 transistors, plus one empty
position in order to fold the layer correctly.The ammopack
is accessible from both sides, enabling the user to choose
between ‘normal’ (see Fig.3) and ‘reverse’ tape. ‘Normal’
is indicated by a plus sign (+) on the ammopack and
‘reverse’ by a minus sign (−). In the European version, the
leading pin is the emitter.
1997 Nov 26 40
Philips Semiconductors
RF Wideband Transistors General section
Fig.2 TO-92 (SOT54) transistors on tape.
handbook, full pagewidth
MEA940
(p)
A1
P
H2
A
L
H0
H1
F
F12
F
P
2
P
0
D
0
W
2
W
0
W
1
W
t
t
1
∆h∆h
T
1997 Nov 26 41
Philips Semiconductors
RF Wideband Transistors General section
Table 1 Tape specification TO-92 (SOT54) leaded types
Note
1. Measured over 20 devices.
SYMBOL DIMENSION SPECIFICATIONS REMARKS
MIN. NOM. MAX. TOL. UNIT
A1body width 4 −4.8 −mm
A body height 4.8 −5.2 −mm
T body thickness 3.5 −3.9 −mm
P pitch of component −12.7 −±1mm
P
0feed hole pitch −12.7 −±0.3 mm
cumulative pitch error −−−±0.1 note 1
P2feed hole centre to component
centre −6.35 −±0.4 mm to be measured at bottom
of clinch
F distance between outer leads −5.08 −+0.6/−0.2 mm
∆h component alignment −01−mm at top of body
W tape width −18 −±0.5 mm
W0hold-down tape width −6−±0.2 mm
W1hole position −9−+0.7/−0.5 mm
W2hold-down tape position −0.5 −±0.2 mm
H0lead wire clinch height −16.5 −±0.5 mm
H1component height −−23.25 −mm
L length of snipped leads −−11 −mm
D0feed hole diameter −4−±0.2 mm
t total tape thickness −−1.2 −mm t1= 0.3 to 0.6
F1, F2lead-to-lead distance −−−+0.4/−0.2 mm
H2clinch height −−−− mm
(p) pull-out force 6 −−− N
Dropouts
A maximum of 0.5% of the specified number of transistors
in each packing may be missing. Up to 3 consecutive
components may be missing provided the gap is followed
by 6 consecutive components.
Tape splicing
Splice the carrier tape on the back and/or front so that the
feed hole pitch (P0) is maintained (see Figs 2 and 4).
1997 Nov 26 42
Philips Semiconductors
RF Wideband Transistors General section
Fig.3 Dimensions of reel and box.
Dimensions in mm.
handbook, full pagewidth
(1)
O 15
min
380
min
O
55 max
55 max
350
max
(1)
A
A
MEA473
direction of unreeling
A - A
(1) packing label
1997 Nov 26 43
Philips Semiconductors
RF Wideband Transistors General section
Fig.4 Joining tape with splicing patch.
handbook, full pagewidth
MEA941
30 mm min
Fig.5 TO-92 (SOT54) with straight leads.
Dimensions in mm.
(1) Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
handbook, full pagewidth
MBC014 - 1
2.54
4.8
max
4.2 max
1.7
1.4
0.66
0.56
1
2
3
5.2 max 12.7 min
2.0 max (1)
0.48
0.40
0.40
min
1997 Nov 26 44
Philips Semiconductors
RF Wideband Transistors General section
Fig.6 TO-92 (SOT54) with delta pinning.
Dimensions in mm.
(1) Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
handbook, full pagewidth
MBC015 - 1
2.54
4.8
max
4.2 max
0.66
0.56
1
2
3
5.2 max 12.7 min
2.5 max (1)
0.48
0.40
0.40
min
1.7
1.4
Packing types
Table 2 Packing quantities per reel
Notes
1. 12NC is the Philips twelve-digit ordering code.
PACKAGE TAPE WIDTH
(mm) REEL SIZE
(mm) QUANTITY PER
REEL
12NC
(note 1)
ends with:
SOT23 8 180 3000 ...215
330 10000 ...235
SOT143 8 180 3000 ...215
SOT143R 330 10000 ...235
SOT143 (cross emitter pinning) 180 3000 ...215
SOT143R (cross emitter pinning) 330 10000 ...235
SOT323 8 180 3000 ...115
330 10000 ...135
SOT343 8 180 3000 ...115
SOT353 8 180 3000 ...115
SOT363 8 180 3000 ...115
SOT89 12 180 3000 ...115
SOT223 12 180 3000 ...115
1997 Nov 26 45
Philips Semiconductors
RF Wideband Transistors General section
Fig.7 Specification for 8 mm tape (SOT23, SOT143, SOT143R, SOT343 and SOT343R).
For dimensions see Table 3.
(1) Tolerance over any 10 pitches: ±0.2 mm.
handbook, full pagewidth
MBE547 - 1
E
P
D0P0
P2
F
W1
W
direction of unreeling
,,,
,,,
,,,
,,,
,,,
,,,
,
,
,
,
,
T
δδ
B
1
B
0
D
1
K
K
0
SOT143R/343R SOT143/343
A0
θ
T1
SOT23 G
(1)
Fig.8 Specification for 8 mm tape (SOT323, SOT353 and SOT363).
For dimensions see Table 3.
(1) Tolerance over any 10 pitches: ±0.2 mm.
handbook, full pagewidth
MSA450
E
P
D0P0
P2
F
W1
W
direction of unreeling
,,,
,,,
,,,
,,,
,,,
,,,
,
,
,
,
,
T
δδ
B
1
B
0
D
1
K
K
0
SOT353 SOT363
A0
θ
T1
SOT323 G
(1)
1997 Nov 26 46
Philips Semiconductors
RF Wideband Transistors General section
For dimensions see Table 3.
(1) Tolerance over any 10 pitches: ±0.2 mm.
Fig.9 Specification for 12 mm tape (SOT89).
MEA466 - 1
D1
B0
B1
G
K
T1
0
K
δδ T
F
E
W1
W
A0θ
D0PP2
P0(1)
direction of unreeling
1997 Nov 26 47
Philips Semiconductors
RF Wideband Transistors General section
Fig.10 Specification for 12 mm tape (SOT223).
For dimensions see Table 3.
(1) Tolerance over any 10 pitches: ±0.2 mm.
F
E
W1
W
A0
θ
D0PP2
P0(1)
direction of unreeling
MEA467 - 1
D1
B0
B1
G
K
T1
0
K
δδ T
1997 Nov 26 48
Philips Semiconductors
RF Wideband Transistors General section
Table 3 SMD packages: tape dimensions (in mm)
Notes
1. Tolerance over any 10 pitches ±0.2 mm.
2. The cover tape shall not overlap the tape or sprocket holes.
DIMENSION
(Figs 7 to 12) CARRIER TAPE TOLERANCE
8mm 12mm 16mm
Overall dimensions
W 8.0 12.0 16.0 ±0.2
K <1.5 <2.4 <2.2 −
G >0.75 >0.75 >1.65 −
Sprocket holes; note 1
D01.5 1.5 1.5 +0.1/−0
E 1.75 1.75 1.75 ±0.1
P04.0 4.0 4.0 ±0.1
Relative placement compartment
P22.0 2.0 2.0 ±0.1
F 3.5 5.5 7.5 ±0.05
Compartment
A0Compartment dimensions depend on package size. Maximum clearance between
device and compartment is 0.3 mm; the minimum clearance ensures that the device
is not totally restrained within the compartment.
B0
B1
K0
D1>1.0 >1.5 >1.5 −
P 4.0 8.0 12.0 ±0.1
θ<15°<15°− −
Cover tape; note 2
W1<5.4 <9.5 −−
T
1<0.1 <0.1 −−
Carrier tape
W 8.0 12.0 16.0 ±0.2
T <0.2 <0.2 <0.4 −
δ<0.3 <0.3 <0.3 −
1997 Nov 26 49
Philips Semiconductors
RF Wideband Transistors General section
Fig.11 Reel specification.
For dimensions see Table 2.
handbook, full pagewidth
MEA942
O
E
U
leader
fixing
tape
trailer
CBA
W
t
Table 4 Reel dimensions (in mm)
Note
1. Large reel diameter depends on individual package (286 or 350).
DIMENSION
(see Fig.11) CARRIER TAPE TOLERANCE
8mm 12mm 16mm
Flange
A 180(1) −286 or 330 180 or 330 180 or 330 ±0.5
t 1.5 1.5 1.5 +0.5/−0.1
W 8.4 12.4 18 18.0+0.2
Hub
B626262±1.5
C 12.75 12.75 12.75 +0.15/−0.2
Key slot
E222±0.2
U444±0.5
O 120°120°120°−
1997 Nov 26 50
Philips Semiconductors
RF Wideband Transistors General section
Fig.12 Orientation of components: SOT23, SOT143, SOT143R and SOT323 (8 mm tape).
handbook, full pagewidth
MEA471
direction of unreeling
SOT23
eb
c
eb
cbe
cbc
ee
cb
ee
ec
be
ce
eb
SOT323 SOT23
(reversed) SOT143 SOT143R SOT143
(cross
emitter
pinning)
SOT143R
(cross
emitter
pinning)
top view
Fig.13 Orientation of components: SOT223 and SOT89 (12 mm tape).
handbook, full pagewidth
MEA472
direction of unreeling
eb
SOT223
top view
SOT89
e
c
b
c
e
1997 Nov 26 51
Philips Semiconductors
RF Wideband Transistors General section
MOUNTING AND SOLDERING
Mounting methods
There are two basic forms of electronic component
construction, those with leads for through-hole mounting
and microminiature types for surface mounting (SMD).
Through-hole mounting gives a very rugged construction
and uses well established soldering methods. Surface
mounting has the advantages of high packing density plus
high-speed automated assembly. Surface mounting
techniques are complex and this chapter gives only a
simplified overview of the subject.
Although many electronic components are available as
surface mounting types, some are not and this often leads
to the use of through-hole as well as surface mounting
components on one substrate (a mixed print). The mix of
components affects the soldering methods that can be
applied. A substrate having SMDs mounted on one or both
sides but no through-hole components is likely to be
suitable for reflow or wave soldering. A double sided mixed
print that has through-hole components and some SMDs
on one side and densely packed SMDs on the other
normally undergoes a sequential combination of reflow
and wave soldering. When the mixed print has only
through-hole components on one side and all SMDs on the
other, wave soldering is usually applied.
Reflow soldering
SOLDER PASTE
Most reflow soldering techniques utilize a paste that is a
mixture of flux and solder. The solder paste is applied to
the substrate before the components are placed. It is of
sufficient viscosity to hold the components in place and,
therefore, an application of adhesive is not required.
Drying of the solder paste by preheating increases the
viscosity and prevents any tendency for the components to
become displaced during the soldering process.
Preheating also minimizes thermal shock and drives off
flux solvents.
Screen printing
This is the best high-volume production method of solder
paste application. An emulsion-coated, fine mesh screen
with apertures etched in the emulsion to coincide with the
surfaces to be soldered is placed over the substrate. A
squeegee is passed across the screen to force solder
paste through the apertures and on to the substrate.
The layer thickness of screened solder paste is usually
between 150 and 200 µm.
Stencilling
In this method a stencil with etched holes to pass the paste
is used. The thickness of the stencil determines the
amount of amount of solder paste that is deposited on the
substrate. This method is also suited to high-volume work.
Dispensing
A computer-controlled pressure syringe dispenses small
doses of paste to where it is required. This method is
mainly suitable for small production runs and laboratory
use.
Pin transfer
A pin picks up a droplet of solder paste from a reservoir
and transfers it to the surface of the substrate or
component. A multi-pin arrangement with pins positioned
to match the substrate is possible and this speeds up the
process time.
REFLOW TECHNIQUES
Thermal conduction
The prepared substrates are carried on a conveyor belt,
first through a preheating stage and then through a
soldering stage. Heat is transferred to the substrate by
conduction through the belt. Figure 14 shows a theoretical
time/temperature relationship for thermal conduction
reflow soldering. This method is particularly suited to thick
film substrates and is often combined with infrared
heating.
1997 Nov 26 52
Philips Semiconductors
RF Wideband Transistors General section
Infrared
An infrared oven has several heating elements giving a
broad spectrum of infrared radiation, normally above and
below a closed loop belt system. There are separate zones
for preheating, soldering and cooling. Dwell time in the
soldering zone is kept as short as possible to prevent
damage to components and substrate. A typical heating.
profile is shown in Fig.15. This reflow method is often
applied in double-sided prints.
Vapour phase
A substrate is immersed in the vapours of a suitable boiling
liquid. The vapours transfer latent heat of condensation to
the substrate and solder reflow takes place. Temperature
is controlled precisely by the boiling point of the liquid at a
given pressure. Some systems employ two vapour zones,
one above the other. An elevator tray, suspended from a
hoist mechanism passes the substrate vertically through
the first vapour zone into the secondary soldering zone
and then hoists it out of the vapour to be cooled.
A theoretical time/temperature relationship for this method
is shown in Fig.16. Fig.14 Theoretical time/temperature curve for a
typical thermal conductive reflow cycle.
MBC938
250
0
T
( C)
o200
150
100
50
0 50 100 150 200
t (s)
Fig.15 Typical temperature profile of an infrared
oven operating at a belt speed of
0.41 mm/min.
MBC937
preheating
max. 45 s soldering
8 s cooling
20 / s
o
75 / s
o
250
175
0
T
( C)
o
Fig.16 Theoretical time/temperature curve
relationship for dual vapour reflow
soldering.
MBC939
215
48
0
T
( C)
o
20 s
25
10 - 30 s 45 s
free air
cooling
entering phase
60 % of time in
soldering zone
soldering zone removal phase
150 % of time in
soldering zone
1997 Nov 26 53
Philips Semiconductors
RF Wideband Transistors General section
Wave soldering
This soldering technique is not recommended for SOT89.
ADHESIVE APPLICATION
Since there are no connecting wires to retain them,
leadless and short-leaded components are held in place
with adhesive for wave soldering. A spot of adhesive is
carefully placed between each SMD and the substrate.
The adhesive is then heat-cured to withstand the forces of
the soldering process, during which the components are
fully immersed in solder. There are several methods of
adhesive application.
Pin transfer method
A pin is used to transfer a droplet of adhesive from a
reservoir to a precise position on the surface where it is
required. The size of the droplet depends on pin diameter,
depth to which the pin is dipped in the reservoir, rheology
of the adhesive, and the temperature of adhesive and
surrounds. The pin can be part of a pin array (bed of nails)
that corresponds exactly with the required adhesive
positions on the substrate. With this method, adhesive can
be applied to the whole of one side of a substrate in one
operation and is therefore suitable for high-volume
production and can be used with pre-loaded mixed prints.
Alternatively, pins can be used to transfer adhesive to the
components before they are placed on the substrate. This
adds flexibility to production runs where variations in
layout must be accommodated.
Screen printing method
A fine mesh screen is coated with emulsion except in the
positions where the adhesive is required to pass. The
screen is placed on the substrate and a squeegee passing
across it forces adhesive through the uncoated parts of the
screen. The amount of adhesive printed-through depends
on the size of the uncoated screen areas, the thickness of
the screen coating, the rheology of the adhesive and
various machine parameters. With this method, the
substrate must be flat and pre-loaded mixed prints cannot
be accommodated.
Pressure syringe method
A computer-controlled syringe dispenses adhesive from
an enclosed reservoir by means of pulses of compressed
air. The adhesive dot size depends on the size of the
syringe nozzle, the duration and pressure of the pulsed air
and the viscosity of the adhesive. This method is most
suited to low volume production. An advantage is the
flexibility provided by computer programmability.
FLUXING
The quality of the soldered connections between
components and substrate is critical for circuit
performance and reliability. Flux promotes solderability of
the connecting surfaces and is chosen for the following
attributes:
•Removal of surface oxides
•Prevention of reoxidation
•Transference of heat from source to joint area
•Residue that is non-corrosive or, if residue is corrosive,
should be easy to clean away after soldering
•Ability to improve wettability (readiness of a metal
surface to form an alloy at its interface with the solder)
to ensure strong joints with low electrical resistance
•Suitability for the desired method of flux application.
In wave soldering, liquified flux is usually applied as a
foam, a spray or in a wave.
Foam
Flux foam is made by forcing low-pressure, water-free
clean air through an aerator immersed in liquid flux. Fine
bubbles of flux are directed onto the substrate/component
surfaces where they burst and form a thin, even layer. The
flux also penetrates any plated-through holes. The flux has
to be chosen for its foaming capabilities.
Spray
Several methods of spray fluxing exist, the most common
involves a mesh drum rotating in liquid flux. Air is blown
into the drum which, when passing through the fine mesh,
directs a spray of flux onto the underside of the substrate.
The amount of flux deposited is controllable by the speed
of the substrate passing through the spray, the speed of
rotation of the drum and the density of the flux.
Wave
A wave fluxer creates a double flowing wave of liquid flux
which adheres to the surface as the substrate passes
through. Wave height control is essential and a soft
wipe-off brush is usually incorporated to remove excess
flux from the substrate.
1997 Nov 26 54
Philips Semiconductors
RF Wideband Transistors General section
PRE-HEATING
Pre-heating of the substrate and components is performed
immediately before soldering. This reduces thermal shock
as the substrate enters the soldering process, causes the
flux to become more viscous and accelerates the chemical
action of the flux and so speeds up the soldering action.
SOLDERING
Wave soldering is usually the best method to use when
high throughput rates are required. The single wave
soldering principle (see Fig.17) is the most straight forward
method and can be used on simple substrates with
two-terminal SMD components. More complex substrates
with increased circuit density and closer spacing of
conductors can pose the problems of nonwetting (dry
joints) and solder bridging. Bridging can occur across the
closely spaced leads of multi-leaded devices as well as
across adjacent leads on neighbouring components.
Nonwetting is usually caused by components with plastic
bodies. The plastic is not wetted by solder and creates a
depression in the solder wave, which is augmented by
surface tension. This can cause a shadow behind the
component and prevent solder from reaching the joint
surfaces. A smooth laminar solder wave is required to
avoid bridging and a high pressure wave is needed to
completely cover the areas that are difficult to wet. These
conflicting demands are difficult to attain in a single wave
but dual wave techniques go a long way in overcoming the
problem.
In a dual wave machine (see Fig.18), the substrate first
comes into contact with a turbulent wave which has a high
vertical velocity. This ensures good solder contact with
both edges of the components and prevents joints from
being missed. The second smooth laminar wave
completes the formation of the solder fillet, removes
excess solder and prevents bridging. Figure 19 indicates
the time/temperature relationship measured at the
soldering site in dual wave soldering.
New methods of wave soldering are developing
continually. For example, the Omega System is a single
wave agitated by pulses, which combines the functions of
smoothness and turbulence. In another, a lambda wave
injects air bubbles in the final part of the wave. A further
innovation is the hollow jet wave in which the solder wave
flows in the opposite direction to the substrate.
Fig.17 Single wave soldering principle.
board travel
MBC935
solder
Fig.18 Dual wave soldering principle.
handbook, halfpage
board travel
MBC934
solder
SMDs
1997 Nov 26 55
Philips Semiconductors
RF Wideband Transistors General section
Fig.19 Typical time-temperature curve measured
at the soldering site.
handbook, halfpage
0
300
200
100
050 100 150
MBC936
time (s)
T
o
( C) 250
150
50
200 K/s 1 K/s
Footprint design
The footprint design of a component for surface mounting
is influenced by many factors:
•Features of the component, its dimensions and
tolerances
•Circuit board manufacturing processes
•Desired component density
•Minimum spacing between components
•Circuit tracks under the component
•Component orientation (if wave soldering)
•Positional accuracy of solder resist to solder lands
•Positional accuracy of solder paste to solder lands
(if reflow soldering)
•Component placement accuracy
•Soldering process parameters
•Solder joint reliability parameters.
1997 Nov 26 56
Philips Semiconductors
RF Wideband Transistors General section
SOT23 FOOTPRINTS
Fig.20 Reflow soldering footprint for SOT23; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
,
,
MSA439
1.00
0.60
(3x)
1.30
12
3
2.50
3.00 0.85 2.70
,,
,,
,,
,,
2.90
0.50 (3x)
0.60 (3x)
3.30
0.85
solder lands
solder resist
occupied area
solder paste
Fig.21 Wave soldering footprint for SOT23; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA427
4.00
4.60
2.80
4.50
1.20
,,,,
,
,,
,
,,,,
,,,
,
,
,
,,,
,,,
,
,
,
,,,
3.40
3
21
1.20 (2x)
preferred transport direction during soldering
solder lands
solder resist
occupied area
1997 Nov 26 57
Philips Semiconductors
RF Wideband Transistors General section
SOT143 FOOTPRINTS
Fig.22 Reflow soldering footprint for SOT143; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
,,
,,
MSA441
0.60
(4x)
1.30
2.50
3.00
2.70
0.50 (3x)
0.60 (3x)
3.25
43
21
,,
,,
,,
,,
,,
,,
0.90
1.00
solder lands
solder resist
occupied area
solder paste
Fig.23 Wave soldering footprint for SOT143; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA422
4.00 4.60
1.20 (3x)
4.45
12
34
1.15
,,
,,
,,
3.40 1.00
preferred transport direction during soldering
,,
,,
,,
,,
,,
,,
,,
,,
,,
solder lands
solder resist
occupied area
1997 Nov 26 58
Philips Semiconductors
RF Wideband Transistors General section
SOT89 FOOTPRINTS
Fig.24 Reflow soldering footprint for SOT89; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA442
1.00
(3x)
4.85
4.60
1.20
4.75
0.60 (3x)
0.70 (3x)
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
,,
,,
,,
,,
,,
,,
3.70
3.95
1.20
0.50
1.70
123
0.20
0.85
1.20
1.20
1.90
2.00
2.25
solder lands
solder resist
occupied area
solder paste
1997 Nov 26 59
Philips Semiconductors
RF Wideband Transistors General section
Fig.25 Wave soldering footprint for SOT89: typical dimensions.
We do not recommend SOT89 for wave soldering, SOT223 is preferred.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA423
3.00
7.60
6.60
1.20
5.30
1.50
,,,
,,,
,,,
,,,
,,,
,,,
,,,
,,,
0.50
3.50
2.40
12
3
0.70
,,,
,
,
,
,,,
,,,
,
,
,
,,,
solder lands
solder resist
occupied area
transport direction during soldering
1997 Nov 26 60
Philips Semiconductors
RF Wideband Transistors General section
SOT223 FOOTPRINTS
Fig.26 Reflow soldering footprint for SOT223; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA443
1.20
(4x)
3.90
5.90
4.80
7.40
4
231
3.85
1.20 (3x)
1.30 (3x)
,,
,,
,,
,,
,,
,,
,,,,
,,,,
0.30
3.60
3.50
7.00
6.15
7.65
solder lands
solder resist
occupied area
solder paste
1997 Nov 26 61
Philips Semiconductors
RF Wideband Transistors General section
Fig.27 Wave soldering footprint for SOT223; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA424
8.70
8.90
7.30
1.90 (2x)
6.70
4
123
1.10
,,,,,,,
,
,,,,,
,
,,,,,,,
,,,
,
,
,
,,,
,,
,
,
,,
,,,
,
,
,
,,,
8.104.30
preferred transport direction during soldering
solder lands
solder resist
occupied area
1997 Nov 26 62
Philips Semiconductors
RF Wideband Transistors General section
SOT323 FOOTPRINTS
Fig.28 Reflow soldering footprint for SOT323; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA429
0.852.35
0.55
(3x)
1.3250.75
2.40
2.65
1.30
3
2
1
0.60
(3x) 0.50
(3x) 1.90
solder lands
solder resist
occupied area
solder paste
Fig.29 Wave soldering footprint for SOT323; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA419
4.00
4.60
2.103.65
1.15
2.70
3
2
10.90
(2x)
preferred transport direction during soldering
solder lands
solder resist
occupied area
1997 Nov 26 63
Philips Semiconductors
RF Wideband Transistors General section
SOT343 FOOTPRINTS
Fig.30 Reflow soldering footprint for SOT343; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA430
2.50
34
21
0.55
(4x)
2.40
,,
,,
,,
1.30
0.50
(3x)
1.90
,,
,,
,,
2.70
0.70
0.80
0.60
(3x)
solder lands
solder resist
occupied area
solder paste
Fig.31 Wave soldering footprint for SOT343; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA421
4.00
3.00
2.30
0.90 (3x)
3.65
12
43
1.15
,,
,,
,,
2.70
1.00
transport direction during soldering
,,
,,
,,
,,
,,
,,
,,
,,
,,
solder lands
solder resist
occupied area
1997 Nov 26 64
Philips Semiconductors
RF Wideband Transistors General section
SOT353 FOOTPRINTS
Fig.32 Reflow soldering footprint for SOT353; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA431
2.35
0.55
(5x)
2.40
1.30
1
2
34
5
0.50
(4x)
2.10
2.65
0.400.90
solder lands
solder resist
occupied area
solder paste
Fig.33 Wave soldering footprint for SOT353; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA425
4.00 1.00
1.15
2.30
2.00A
1
2
3
4
5
A = 2.00 for carrier soldering
A = 2.50 for carrier less soldering
0.30 4.602.700.90
A + 1.00
solder lands
solder resist
occupied area
transport direction during soldering
1997 Nov 26 65
Philips Semiconductors
RF Wideband Transistors General section
SOT363 FOOTPRINTS
Fig.34 Reflow soldering footprint for SOT363; typical dimensions.
Dimensions in mm.
Placement accuracy: ±0.25 mm.
handbook, full pagewidth
MSA432
2.35
0.55
(6x)
2.40
1.30
0.50
(4x) 2.10
2.65
0.40
(2x)
solder lands
solder resist
occupied area
solder paste
0.90
1
2
3
6
5
4
Fig.35 Wave soldering footprint for SOT363; typical dimensions.
Dimensions in mm.
Placement accuracy:
handbook, full pagewidth
MSA426
4.60 4.00 1.00
1.15
0.30
A
1
2
3
6
5
4
A + 2.00
solder lands
solder resist
occupied area
A = 4.00 for carrier soldering
A = 5.00 for carrier less soldering
transport direction during soldering
1997 Nov 26 66
Philips Semiconductors
RF Wideband Transistors General section
Hand soldering microminiature components
It is possible to solder microminiature components with a
light-weight hand-held soldering iron, but this method has
obvious drawbacks and should be restricted to laboratory
use and/or incidental repairs on production circuits:
•Hand-soldering is time-consuming and therefore
expensive
•The component cannot be positioned accurately and the
connecting tags may come into contact with the
substrate and damage it
•There is a risk of breaking the substrate and internal
connections in the component could be damaged
•The component package could be damaged by the iron.
THERMAL CONSIDERATIONS
Thermal resistance
Circuit performance and long-term reliability are affected
by the temperature of the transistor die. Normally, both are
improved by keeping the die temperature (junction
temperature) low.
Electrical power dissipated in any semiconductor device is
a source of heat. This increases the temperature of the die
above a certain reference point. The most relevant
reference point of the semiconductor device is the
soldering point (i.e. the point on the printed-circuit board
where the collector lead is soldered to a heat-draining
point see Figs 36 and 37).
The temperature rise as a function of dissipation power,
‘thermal resistance’, is given in the data sheets as the
Rth j-s value. The heat is drained by conduction via the
leadframe, soldering point and substrate (printed-circuit
board) to ambient. The amount of radiated and convected
heat is negligible in comparison to the conducted heat.
The elements of thermal resistance are defined as follows:
PdPower dissipation (W)
Rth j-s Thermal resistance from junction to
soldering point (K/W)
Rth s-a Thermal resistance from soldering point to
ambient (K/W)
Rth j-a Thermal resistance from junction to ambient
(K/W)
TjJunction temperature of the die (°C)
TsSoldering point temperature (°C)
Tamb Ambient temperature (°C)
Tref Temperature of the reference point (°C)
The peak temperature of the die depends on the ability of
the package and its mounting to transfer heat from this die
to ambient environment (see Fig.38). The basic
relationship between die temperature (junction
temperature) and power dissipation is:
Tj max =T
amb +P
d max ×[Rth j-s +R
th s-a]
Thermal resistance from junction to soldering point
[Rth(j-s)]
In the example for Tj max, only Tamb and Rth s-a can be
varied by the user. The construction of the printed-circuit
board (PCB) and the ambient condition (as there is air
flow) affect Rth s-a. The device power dissipation can be
controlled to a limited extent, under recommended usage.
The supply voltage and circuit loading dictate a fixed
power maximum. The Rth j-s value is essentially
independent of external mounting method and cooling air,
but is sensitive to the materials used in the package
construction, the die mount and the die area, all of which
are fixed.
Fig.36 Assembly of SMD package and PCB.
handbook, halfpage
,
,
,
MBG387
,,
,,
solder point
collector lead
or anode lead
printed circuit board
die
Fig.37 Assembly of SOD80-like package and PCB.
handbook, halfpage
,
,
,
MBG386
,,
,,
solder point
printed circuit board
1997 Nov 26 67
Philips Semiconductors
RF Wideband Transistors General section
Values of Tj max and Rth j-s, or Rth j-c are given in the device
data sheets. For applications where Ts is known, Tj can be
calculated from:
Tj=T
s+P
d×R
th j-s
Thermal resistance from soldering point to ambient
[Rth s-a]
There is a limiting value for the soldering point
temperature. For the normal tin alloy (Sn-Pb 60% - 40%):
Ts max = 110 °C. The value of Ts can be calculated from:
Ts=T
a+P
d×R
th s-a.
The thermal resistance from soldering point to ambient
depends on the shape and material of the tracks on a
printed-circuit board as illustrated in Fig.39.
Summary of the SMD envelopes
These thermal considerations are valid for the following
envelopes:
SOD80, SOD87, SOD106, SOD110, SOD123, SOD323,
SC59, SC70, SOT23, SOT89, SOT123, SOT143,
SOT223, SOT323, SOT343, SOT346 and SO8
(SOT96-1).
Fig.38 Representation of thermal resistance paths
of a device mounted on a substrate or
printed board.
handbook, halfpage
MBG385
Rth j−s
ambient
junction
soldering
point Rth j−a
Rth s−a
Temperature calculation under pulsed conditions
In pulsed power conditions, the peak temperature of
the die depends on the pulse time and duty factor as well
as the ability of the package and its mounting to disperse
heat.
When power is applied in repetitive square-wave pulses
with a certain duty factor (δ), the variation in junction
temperature has a sawtooth characteristic.
The average steady-state junction temperature is:
Tj(av) =T
ref +δ×P
d×R
th j-ref
The peak junction temperature, however, is the most
relevant to performance reliability. This can be calculated
by heating and cooling step functions that result in heating
and cooling curves shifted in time as shown in Fig.40.
The peak value of Tj is reached at the end of a power
pulse and the minimum value immediately before the next
power pulse. The thermal ripple is the difference between
Tj(peak) and Tj(min).
Calculation of Tj(peak) after n pulses:
Fig.39 Thermal resistance (Rth s-a) as a function of
pad area on different configurations of FR4
epoxy fibre-glass circuit board.
(1) Single-sided, unplated.
(2) Single-sided, plated.
(3) Double-sided, unplated.
(4) Double-sided, plated.
MBC389
11010
2103
10
104
102
103
ESR
(mΩ)
C (pF)
500
MHz
200
MHz 100
MHz
50
MHz
1997 Nov 26 68
Philips Semiconductors
RF Wideband Transistors General section
where a is an integer number.
Approximation method of finding Tj(peak)
With this method it is assumed that the average load is
immediately followed by two square power pulses as
shown in Fig.41. This two-pulse approximation method is
accurate enough for finding Tj(peak).
Tj(peak) Tref Pd
+Zth at w–()
Z
th at()
–[]
a0=
an 1–=
∑
×=
Fig.40 Heating effect of three identical power pulses
after thermal stabilization.
handbook, halfpage
d−w/t
Pd (w)
power
+
0
Ta
−
∆Tj
Tj
∆T1
∆T2
∆T3
∆T4
∆T5
MBG391
Pd
Pd
Pd
Pd
Pd
Pd
t
w
Tj (peak)
thermal-ripple
Tj (min) The junction temperature at the end of the second pulse is:
Tj(peak) =T
ref +P
d×[δ×R
th(j-ref) +(1−δ)×Z
th(t+w)
+ Zth(w) −Zth(t)]
The junction temperature immediately before the second
power pulse is:
Tj(min) =T
ref +P
d×[δ×R
th(j-ref) +(1−δ)×Z
th(t)
+Z
th(w) −Zth(t−w)]
The thermal ripple is:
∆Tj=T
j(peak) −Tj(min)
∆Tj=P
d×[δ×(Zth(t) −Zth(t+w)−2×Zth(t) +Z
th(w) +Z
th(t−w)]
Reducing calculation time
To be able to point out the junction peak temperature at a
certain pulse time and duty cycle, a graph similar to that
shown in Fig.42 is included in relevant data sheets. In this
example, the curves have been derived using the formula
Fig.41 Two-pulse approximation method of finding
peak steady-state junction temperature
[Tj(peak)].
handbook, halfpage
MBG390
wd−w/t
t
Pd (W)
Pd (av)
∆Tj-ref
(K) ∆T2 = Pd x Zth (t+w)
∆T3 = Pd x Zth (w)
∆T4 = Pd x Zth (+)
∆T(av)1 = d x Pd x Rth j-ref
∆T(av)2 = d x Pd x Zth (2t+w)
Tj (oC)
Tj (av)
Tj (peak)
Tj (peak) = Ta + ∆T1 + ∆T2 + ∆T3 + ∆T4 − ∆T5 − ∆T6 − ∆T7
thermal-ripple ∆Tj
Tj (min)
1997 Nov 26 69
Philips Semiconductors
RF Wideband Transistors General section
Tj(peak) =T
ref +P
d×[δ×R
th(j-ref) +(1−δ)×Z
th(t+w)
+ Zth(w) −Zth(t)], with typical values inserted.
The pulse width along the X-axis meets a particular duty
cycle curve, indicating the Zth value in K/W along the
Y-axis.
Tj(peak) =P
d(peak) ×Zth(j-s) +P
d(av) ×Rth(s-a) +T
a(°C)
Soldering point temperature provides a better reference
point than ambient temperature as this is subject to many
uncontrolled variables. Therefore, the thermal resistance
from junction to soldering point [Rth(j-s)] is becoming a more
relevant measurement path.
Fig.42 Direct reading of thermal impedance from junction to soldering point for calculation of junction temperature
at pulsed power condition.
handbook, full pagewidth
10−5
10−610−410−310−210−11
MBG388
103
102
10
Zth j-a
(K/W)
tpT
P
t
tp
T
δ=
tp (s)
δ =
0.75
0.5
0.3
0.2
0.1
0.05
0
1997 Nov 26 70
Philips Semiconductors
RF Wideband Transistors General section
ELECTROSTATIC CHARGES
Electrostatic charges can exist in many things; for
example, man-made-fibre clothing, moving machinery,
objects with air blowing across them, plastic storage bins,
sheets of paper stored in plastic envelopes, paper from
electrostatic copying machines, and people. The charges
are caused by friction between two surfaces, at least one
of which is non-conductive. The magnitude and polarity of
the charges depend on the different affinities for electrons
of the two materials rubbing together, the friction force and
the humidity of the surrounding air.
Electrostatic discharge is the transfer of an electrostatic
charge between bodies at different potentials and occurs
with direct contact or when induced by an electrostatic
field. Our devices can be damaged if the following
precautions are not taken.
WORK STATION
Figure 43 shows a working area suitable for safely
handling electrostatic sensitive devices. It has a work
bench, the surface of which is conductive or covered by an
antistatic sheet. Typical resistivity for the bench surface is
between 1 and 500 kΩ per cm2. The floor should also be
covered with antistatic material.
The following precautions should be observed:
•Persons at a work bench should be earthed via a wrist
strap and a resistor
•All mains-powered electrical equipment should be
connected via an earth leakage switch
•Equipment cases should be earthed
•Relative humidity should be maintained between
50 and 65%
•An ionizer should be used to neutralize objects with
immobile static charges.
RECEIPT AND STORAGE
Our devices are packed for dispatch in
antistatic/conductive containers, usually boxes, tubes or
blister tape. The fact that the contents are sensitive to
electrostatic discharge is shown by warning labels on both
primary and secondary packing.
The devices should be kept in their original packing whilst
in storage. If a bulk container is partially unpacked, the
unpacking should be performed at a protected work
station. Any devices that are stored temporarily should be
packed in conductive or antistatic packing or carriers.
ASSEMBLY
The devices must be removed from their protective
packing with earthed component pincers or short-circuit
clips. Short-circuit clips must remain in place during
mounting, soldering and cleansing/drying processes. Do
not remove more devices from the storage packing than
are needed at any one time. Production/assembly
documents should state that the product contains
electrostatic sensitive devices and that special precautions
need to be taken.
All tools used during assembly, including soldering tools
and solder baths, must be earthed. All hand tools should
be of conductive or antistatic material and, where possible,
should not be insulated.
Measuring and testing of completed circuit boards must be
done at a protected work station. Place the soldered side
of the circuit board on conductive or antistatic foam and
remove the short-circuit clips. Remove the circuit board
from the foam, holding the board only at the edges. Make
sure the circuit board does not touch the conductive
surface of the work bench. After testing, replace the circuit
board on the conductive foam to await packing.
Assembled circuit boards should be handled in the same
way as unmounted devices. They should also carry
warning labels and be packed in conductive or antistatic
packing.
1997 Nov 26 71
Philips Semiconductors
RF Wideband Transistors General section
Fig.43 Protected work station.
(1) Earthing rail.
(2) Resistor (500 kΩ± 10%, 0.5 W).
(3) Ionizer.
(4) Work bench.
(5) Chair.
(6) Wrist strap.
(7) Electrical equipment.
(8) Conductive surface/antistatic sheet.
(9) Antistatic floor.
,,,,,,,,,,
handbook, full pagewidth
(1)
(2)
(3)
(4)
(2)
(6)
(2)
(7) (8)
MLB049
(5)
(9)
