July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Am29LV640D/Am29LV641D
Data Sheet
Publication Number 22366 Revision BAmendment +8 Issue Date September 20, 2002
Publication# 22366 Rev: BAmendment/+8
Issue Date: September 20, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
Am29LV640D/Am29LV641D
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileIO Control
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— 3.0 to 3.6 volt read, erase, and program operations
■VersatileIO con tro l
— Device generates output voltages and tolerates data
input voltages on the DQ input/ouputs as determined
by the voltage on VIO
■High performance
— Access times as fast as 90 ns
■Manufactured on 0.23 µm process technology
■CFI (Common Flash Interface) compliant
—Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
■SecSi (Secured Silicon) Sector region
—128-word sector for permanent, secure identification
through an 8-w ord rando m Elec tron ic Serial Number
—May be programmed and locked at the factory or by
the customer
—Accessib le thro ugh a comm a nd sequence
■Ultra low power consumption (typical values at 3.0 V,
5 MHz)
—9 mA typical active read current
—26 mA typical erase/program current
—200 nA typical standby mode current
■Flexible sector architecture
—One hundred twenty-eight 32 Kword sectors
■Sector Protection
—A hardware method to lock a sector to prevent
program or erase operations within that sector
—Sectors can be locked in-system or via programming
equipment
—Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■Embedded Algorithms
—Embedd ed Era se alg orith m aut oma tic ally
preprograms and erases the entire chip or any
combination of designated sectors
—Embedded Program algorithm automatically writes
and verifies data at specified addresses
■Compatibility with JEDEC standards
—Pinout and software compatible with single-power
supply Flash
—Superior inadvertent write protection
■Minimum 1 million erase cycle guarantee per sector
■Package options
—48-pin TSOP (Am29LV641DH/DL only)
—56-pin SSOP (Am29LV640DH/DL only)
—63-ball Fine-Pitch BGA (Am29LV640DU only)
—64-ball Fortified BGA (Am29LV640DU only)
■Erase Suspend/Erase Resume
—Suspends an erase operation to read data from, or
program data to, a sect27
—or that is not being erased, then resumes the erase
operation
■Data# Polling and toggle bits
—Provides a software method of detecting program or
erase operation completion
■Unlock Bypass Program command
—Reduces overall programming time when issuing
multiple program command sequences
■Ready/Busy# pin (RY/BY#) (Am29LV640DU in FBGA
package only)
—Provides a hardware method of detecting program or
erase cycle completion
■Hardware reset pin (RESET#)
—Hardware method to reset the device for reading array
data
■WP# pin (Am29LV641DH/DL in TSOP,
Am29LV640DH/DL in SSOP only)
—At VIL, protects the first or last 32 Kword sector,
regardless of sector protect/unprotect status
—At VIH, allows removal of sector protection
—An internal pull up to VCC is provided
■ACC pin
—Accelerates programming time for higher throughput
during system production
■Program and Erase Performance (VHH not applied to
the ACC input pin)
—Word program time: 11 µs typical
—Sector erase time: 0.9 s typical for each 32 Kword
sector
2 Am29LV640D/Am29LV641D September 20, 2002
GENERAL DESCRIPTION
The Am29LV640DU/Am29LV641DU is a 64 Mbit, 3.0
Volt (3.0 V to 3.6 V) single power supply flash memory
device s organized a s 4,194,304 wo rds. Da ta appears
on DQ0-DQ15. The device is designed to be pro-
grammed i n-system with the stand ard system 3.0 volt
VCC supply. A 12.0 volt VPP is not required for program
or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
Access times of 90 and 120 ns are available for appli-
cations where VIO ≥ VCC. Access times of 100 and 120
ns are available for applications where VIO < VCC. The
device is offered in 48-pin TSOP, 56-pin SSOP, 63-ball
Fine-Pitch BGA and 64-ball Fortified BGA packages.
To eliminate bus contention each device has separate
chip enable (CE#), write enable (WE#) and output en-
able (OE#) controls.
Each device requires only a single 3.0 Volt power
supply (3.0 V to 3.6 V) for both read and write func-
tions. Internally generated and re gulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the JEDEC single-po wer-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the pr ogram
command sequence. This initiates the Embedded
Program algorithm—an intern al algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
gramme d) before exec uting the eras e operation. Du r-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The VersatileIO™ (VIO) control allows th e host sy stem
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/O s to the same voltage
level that is asserted on VIO. VIO is available in two
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various system environments.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by readin g the DQ7 (Data# Polling) , or DQ6 (tog-
gle) status b its. After a program or erase cycle has
been completed, the dev ice is ready to read a rray data
or accept another command.
The secto r erase archite cture allow s memory sec-
tors to be erased and reprogrammed without affecting
the da ta con tents o f other se ctors. T he dev ice is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The Eras e Susp end/Erase Resum e feature enables
the user to put erase on hold for any period of time to
read d ata from, or pr ogram data to, any sector tha t is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# p in terminates any operation
in progress and resets the interna l state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boo t-up firmware from the F lash mem-
ory device.
The device offers a standby mode as a power-saving
feature. O nce the system place s the device into th e
standby mode power consumption is greatly reduced.
The SecSi (Secured Silicon) Sector provides an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The Write Protect (WP#) feat ure p rotect s the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming.
The accelerat ed program (ACC) feature allow s the
system to program the device at a much faster rate.
When ACC is pulled high to VHH, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is inte nded to incr ease factory throughp ut during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
September 20, 2002 Am29LV640D/Am29LV641D 3
TABLE OF CONTENTS
Product Selecto r Guide . . . . . . . . . . . . . . . . . . . . .4
Bloc k Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagram s . . . . . . . . . . . . . . . . . . . . . . .5
Special Handling I nstructions for FBGA/fBGA Pack a g es ...... ...8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Orderin g Information . . . . . . . . . . . . . . . . . . . . . .10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .11
Table 1. Dev ice Bus Operati on s ....................... ..................... .........11
VersatileIO (VIO) Cont ro l ..... ......... ... ......... ... ......... ... ......... .. .1 1
Requirements for Reading Array Data .......... .. ................. .. ....11
Writing Commands/Command Sequences .......... ................ ..12
Accelerated Program Operation ......................................................12
Autose l ect Funct ion s .... ............ ......................... ......................... .....12
Standby Mode ........................................ .............. ..................12
Automatic Sleep Mode ................... ............................. ......... ..12
RESET#: Hardware Reset Pin ...............................................12
Output Disable Mode ..............................................................13
Table 2. Se cto r Ad d re ss Ta b le .......................... ......................... .....13
Autoselect Mode ........ .. ............... ......... .. ............... ......... .. .......17
Table 3 . Au to se l e ct Co des, (High Vo ltage Method) ....................... 17
Sector Group Protection and Unprotection ........... .. ......... .......18
Table 4. Sector Group Protection/Unprotection Address Table .....18
Write Protect (WP#) ................................................................19
Temporary Sector Group Unprotect .......................................19
Figure 1. Temporary Sector Group Unprotect Operation................ 19
Figure 2. In-System Sector Group Protect/Unprotect Algorit hm s ... 20
SecSi (Secured Silicon) Sector Flash Memory Region ..........21
Table 5. SecSi Sector Contents ......................................................21
Hardware Data Protection ......................................................21
Low VCC Write Inhibit .....................................................................21
Write Puls e “Gli tch ” Pro te ction ...................... ................ ................ ..22
Logical Inhibit ........................................ ....... ................ ......... ....... ...2 2
Power-Up Write In h ibit ........ ............ ................ .................... ............22
Common Flash Memor y Interface (CFI). . . . . . . 22
Table 6. CFI Query Identification String.......................................... 22
System Int e rfa ce String............. ......................... ..................... ........ 23
Table 8. Dev ice Geometry Defi n ition...................... ................ ........ 23
Table 9. Primary Vendor-Specific Extended Query........................ 24
Command Definition s . . . . . . . . . . . . . . . . . . . . . 24
Reading Array Data ................................................................24
Reset Command ..... ....... ................... ................... ...................25
Autoselect Command Sequence ...... ......................................25
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..25
Word Program Command Sequence .....................................25
Unlock Bypass Command Sequence ................................ .. ..... .. ..... 26
Figur e 3. Progra m Oper a tion......................... ......................... ........ 26
Chip Erase Command Sequence ...........................................26
Sector Erase Command Sequence ........................................27
Erase Suspend/Erase Resume Commands ...........................27
Figure 4. Erase Operation............................................................... 28
Command Definitions .............................................................29
Command Definitions...................................................................... 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . .30
DQ 7 : Da t a# Po ll i n g ............ ... ......... .......... .. ......... .......... .. ........3 0
Figure 5. Data# Polling Algorithm................................................... 30
RY/BY#: Ready/Busy# ............................................................ 31
DQ6: Toggle Bit I ....................................................................31
Figure 6. Toggle Bit Algorithm........................................................ 31
DQ2: Toggle Bit II ...................................................................32
Reading Toggle Bits DQ6/DQ2 ...............................................32
DQ5: Exceeded Timing Limits ................................................32
DQ3: S e cto r E ra s e Time r ..... ......... ... ......... ... ......... .. .......... .. ...3 2
Table 11. Write Ope r a tion Status ............. .................... .................. 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 7. Maximu m Negat ive Oversho ot Waveform..................... 34
Figure 8. Maximu m Po sitive Overshoot Waveform....................... 34
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. ICC1 Current vs. Time (Showing
ActiveandAu to ma tic SleepCurrents). ............ .................... .......... 36
Figure 10. Typical ICC1 vs. Frequency.................... ..................... ... 36
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figur e 11 . Tes t Se tu p... ......................... .............................. .......... 37
Table 12. Te st Sp e cifications ......... ..................... ...........................37
Key to Switching Waveforms. . . . . . . . . . . . . . . . 37
Figure 12. Input Waveforms and
Measurement Levels...................................................................... 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Read-Only Operations ...........................................................38
Figure 13. Read Operation Timings............................................... 38
Hardware Reset (RESET#) .................................... .. ..............39
Figure 14. Reset Timings............................................................... 39
Erase and Program Operations ..............................................40
Figure 15. Program Operation Timings.......................................... 41
Figure 16. Accelerated Program Timing Diagram.......................... 41
Figure 17. Chip/Sector Erase Operation Timings .......................... 42
Figure 18. Data# Polling Timings
(During Embedded Algorithms)...................................................... 43
Figure 19. Toggle Bit Timings
(During Embedded Algorithms)...................................................... 44
Figur e 20 . DQ2 vs. DQ6............ .................... ..................... ............ 44
Temporary Sector Unprotect ..................................................45
Figure 21. Temporary Sector Group Unprotect Timing Dia gram... 45
Figure 22. Sector Group Protect and Unprotect Timing Diagram.. 46
Alternate CE# Controlled Erase and Program Operations .....47
Figure 23. Alternate CE# Controlled Write
(Erase/Program)Ope ra tion Timings......... ........... ................ .......... 48
Erase And Programming Performance . . . . . . . 49
Latchup C haracteristics. . . . . . . . . . . . . . . . . . . . 49
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 49
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 50
SSO056—56-Pin Shrink Small Outline Package (SSOP) ......50
FBE063—63-Ball Fine-Pitch Ball Grid Array
(FBGA) 12 x 11 mm package .................................................51
LAA064—64-Ball Fortified Ball Grid Array
(FBGA) 13 x 11 mm package ................................................. 52
TS 048—48-Pin Standard TSOP ............................................53
TSR048—48-Pin R everse TS OP .. ... .. .. .......... .. .......... .. ..........54
Re v is ion Sum ma ry . . . . . . . . . . . . . . . . . . . . . . . . 5 5
4 Am29LV640D/Am29LV641D September 20, 2002
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristi cs” for full spe cifications.
BLOCK DIAGRAM
Notes:
1. RY/BY# is only availab le in the FBG A pac kag e.
2. WP# is only available in the TSOP and SSOP packages.
Part Number Am29LV640D/Am29LV641D
Speed Op tion VCC = 3.0–3.6 V, VIO = 3.0–5.0 V 90R 120R
VCC = 3.0–3.6 V, VIO = 1.8–2.9 V 101R 121R
Max Access Time (ns) 90 100 120
CE# Access Time (ns) 90 100 120
OE# Access Time (ns) 35 35 50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
WP#
(Note 2)
ACC
CE#
OE#
STB
STB
DQ0–DQ15
Sector Switches
RY/BY# (Note 1)
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A21
VIO
September 20, 2002 Am29LV640D/Am29LV641D 5
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A15
A18
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A1
A17
A7
A6
A5
A4
A3
A2
A16
DQ2
VIO
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48-Pin Standard TSOP
(Am29LV641DH/DL only)
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A15
A18
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A1
A17
A7
A6
A5
A4
A3
A2
A16
DQ2
VIO
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48-Pin Reverse TSOP
(Am29LV641DH/DL only)
6 Am29LV640D/Am29LV641D September 20, 2002
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
NC
NC
A0
CE#
VSS
OE#
DQ0
DQ8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
RESET#
WE#
A20
A21
A8
A9
A10
A11
A12
A13
A14
A15
NC
NC
NC
NC
A16
VIO
VSS
DQ15
DQ7
DQ14
23
24
25
26
27
28
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
34
33
32
31
30
29
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
56-Pin SSOP
(Am29LV640DH/DL
only)
September 20, 2002 Am29LV640D/Am29LV641D 7
CONNECTION DIAGRAM
C2 D2 E2 F2 G2 H2 J2 K2
C3 D3 E3 F3 G3 H3 J3 K3
C4 D4 E4 F4 G4 H4 J4 K4
C5 D5 E5 F5 G5 H5 J5 K5
C6 D6 E6 F6 G6 H6 J6 K6
C7 D7A7 B7
A8 B8
A1 B1
A2
E7 F7 G7 H7 J7 K7 L7
L8
M7
M8
L1
L2
M1
M2
NC* NC*NC*
NC* NC* NC* NC*
NC* NC*
NC* NC*NC NC
NC NC DQ15 VSSVIO
A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
VCC DQ4DQ12DQ5A19A21RESET#WE#
DQ11 DQ3DQ10DQ2A20A18ACCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# VSSCE#A0A1A2A4A3
* Balls are shorted together via the substrate but not connected to the die.
63-Ball Fine-Pitch BGA (FBGA)
Top View, Balls Facing Down
(Am29LV640DU only)
8 Am29LV640D/Am29LV641D September 20, 2002
CONNECTION DIAGRAMS
Special Handling Instructions for
FBGA/fBGA Packages
Special handling is required for Flash Memory products
in BGA packages.
Flash memory devices in BGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
B3 C3 D3 E3 F3 G3 H3
B4 C4 D4 E4 F4 G4 H4
B5 C5 D5 E5 F5 G5 H5
B6 C6 D6 E6 F6 G6 H6
B7 C7 D7 E7 F7 G7 H7
B8 C8 D8 E8 F8 G8 H8
RFURFURFUVSS
VIO
RFURFU
VSS
DQ15NCA16A15A14A12
DQ6
DQ13DQ14DQ7A11A10A8
DQ4VCC
DQ12DQ5A19A21RESET#
DQ3DQ11DQ10DQ2A20A18ACC
DQ1DQ9DQ8DQ0A5A6A17
A3
A4
A5
A6
A7
A8
RFU
A13
A9
WE#
RY/BY#
A7
B2 C2 D2 E2 F2 G2 H2
VSS
OE#CE#A0A1A2A4
A2
A3
B1 C1 D1 E1 F1 G1 H1
RFURFUVIO
RFURFURFURFU
A1
RFU
64-Ball Fortified BGA (FBGA)
Top View, Balls Facing Down
(Am29LV640DU only)
September 20, 2002 Am29LV640D/Am29LV641D 9
PIN DESCRIPTION
A0–A21 = 22 Addresses inputs
DQ0–DQ15 = 16 Data inputs/outputs
CE# = Chip Enable input
OE# = Output Enable input
WE# = Write Enable input
WP# = Hardware Write Protect input (N/A on
FBGA)
ACC = Acceleration Input
RESET# = Hardware Reset Pin input
RY/B Y# = Ready/Busy output (FBGA only)
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VIO = Output Buffer power
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
Note: WP# is not available on the FBGA package. RY/BY#
is not available on the TSOP and SSOP packages.
22 16
DQ0–DQ15
A0–A21
CE#
OE#
WE#
RESET# RY/BY#
ACC
WP#
VIO
10 Am29LV640D/Am29LV641D September 20, 2002
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Valid Combinations
V alid Combinati ons list configurations planned to be s upported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
Am29LV640D
Am29LV641D H 90R E I N OPTIONAL PROCESSING
Blank= Standard Processing
N = 32-byte ESN de vices
(Contact an AMD representative for more information)
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
E = Extended (–55°C t o +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TS OP) Reverse Pinout (TSR048)
Z = 56-Pin Shrink Sm all Outline Pa ckage (SSO056)
PC = 64-Ball Fortified Ball Grid Array (FBGA),
1.0 mm pitch, 13 x 11 mm pac kage (LAA064)
WH = 63-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 11 x 12 mm package (FBE063)
SPEED OPTION
See Product Selector Guide an d Valid Comb inations
SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0)
H = Uniform sector device, highest address sector protected
L = Uniform sector device, lowest address sector protected
U = Uniform sector device (WP# not available)
DEVICE NUMBER/DESCRIPTION
Am29LV640DU/DH /DL, Am29LV641DH/DL
64 Megabit (4 M x 16-Bit) CMOS Uniform Sec tor Flash Memory with VersatileIO Control
3.0 Volt-only Read, Program, and Erase
Valid Combinations for
TSOP and SSOP Packages Speed/VIO Range
AM29LV640DH90R,
AM29LV640DL90R ZI
90ns,
VIO = 3.0 V – 5.0 V
AM29LV640DH101R,
AM29LV640DL101R 100 ns,
VIO = 1.8 V – 2.9 V
AM29LV641DH90R,
AM29LV641DL90R EI, FI
90 ns
VIO = 3.0 V – 5.0 V
AM29LV641DH101R,
AM29LV641DL101R 100 ns
VIO = 1.8 V – 2.9 V
AM29LV640DH120R,
AM29LV640DL120R ZI, ZE
120 ns,
VIO = 3.0 V – 5.0 V
AM29LV640DH121R,
AM29LV640DL121R 120 ns,
VIO = 1.8 V – 2.9 V
AM29LV641DH120R,
AM29LV641DL120R EI, FI, EE, FE
120 ns,
VIO = 3.0 V – 5.0 V
AM29LV641DH121R,
AM29LV641DL121R 120 ns
VIO = 1.8 V – 2.9 V
Note: LV640/641DH & DL have WP#, but no RY/BY#. U
designator in base part number replaced by H or L.
Valid Combinations for BGA Packages Speed/
VIO Range
Order Number Package
Marking
AM29LV640DU90R PCI L640DU90N
I
90 ns, VIO =
3.0 V – 5.0 V
WHI L640DU90R
AM29LV640DU101R PCI L640DU01N 100 ns, VIO =
1.8 V – 2.9 V
WHI L640DU01R
AM29LV640DU120R
PCI,
PCE L640DU12N
I,
E
120 ns, VIO =
3.0 V – 5.0 V
WHI,
WHE L640DU12R
AM29LV640DU121R
PCI,
PCE L640DU21N 120 ns, VIO =
1.8 V – 2.9 V
WHI,
WHE L640DU21R
Note: LV640DU has RY/BY#, but no WP#.
September 20, 2002 Am29LV640D/Am29LV641D 11
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus o perations, which are in itiated through
the internal command register. The command register
itself doe s not occupy a ny address able memo ry loca-
tion. The register is a latch used to store the com-
mands , along with the ad dress and data in formation
needed to execute the command. The contents of the
regis ter serve as inpu ts to the intern al state machin e.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts an d contro l levels they requir e, and the resultin g
output. The following subsections de scribe each of
these operations in further detail.
Table 1. Device Bus Operations
Legend: L = Lo g i c Lo w = VIL, H = Lo gi c Hig h = V IH, VID = 8.5–12.5 V, VHH = 11. 5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprot ect f unctions may al so be i mplemente d via programmi ng equipmen t. See the “Sector Group
Protection and Un protect ion” section.
3. If WP# = VIL, the f irst or l ast s ector remains protect ed. I f WP# = VIH, t he fi rst or las t sect or wi ll be protec ted or unprot ected as
determined by the method d escribe d in “Sector Group Pr otecti on and Unprotect ion ”. All sector s are unprote cted when shipped
from the factor y (The SecSi Sector may be f actory protec ted depend ing on versi on order ed.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
VersatileIO (VIO) Control
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/O s to the same voltage
level that is asserted on VIO. VIO is available in two
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various system environments.
For ex ample, a VI/O of 4.5–5.0 volts allows for I/O at
the 5 volt level, driving and receiving signals to and
from other 5 V devices on the same data bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
conten t occurs durin g the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
Operation CE# OE# WE# RESET# WP# ACC Addresses
(Note 2) DQ0–
DQ15
Read L L H H XX AIN DOUT
Write (Program/Erase) L H L H (Note 3) X AIN (Note 4)
Accelerated Program L H L H (Note 3) VHH AIN (Note 4)
Standby VCC ±
0.3 V XXVCC ±
0.3 V XH X High-Z
Output Disable L H H H XX X High-Z
Reset X X X L XX X High-Z
Sector Group P rotect (Note 2) L H L VID HX SA, A6 = L,
A1 = H, A0 = L (Note 4)
Sector Group Unprotect
(Note 2) LHL V
ID HX SA, A6 = H,
A1 = H, A0 = L (Note 4)
Temporary Sector Group
Unprotect XXX V
ID HX AIN (Note 4)
12 Am29LV640D/Am29LV641D September 20, 2002
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Requirements for Reading Array Data” for mo re
information. Refer to the AC Read-Only Operations
table for timin g specification s and to Figure 13 for the
timing diagram. ICC1 in the DC Characteristics table
repres ents the ac tive curr ent specifi cation fo r readin g
array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word Program Command Sequence” section has de-
tails on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector , multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies.
ICC2 in the DC Characteristics table represents the ac-
tive current spec ification for the write m ode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated P rog ram Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
If the sy stem as serts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporar ily unprotects any protected se ctors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would us e a two-cycle pro gram comm and sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal op-
eration. Note that the ACC pin must not be at VHH for
operations other than accelerated programming, or
device damage may result.
Autoselect Functions
If the system writes the autoselect command se-
quence, the devic e enters the autoselect mo de. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. R efer to the Auto select Mode and Autose-
lect Comm and Sequence sections for more inform a-
tion.
Standby Mode
When the system is not re ading or writing to the de-
vice, it can place the devic e in the standby mode. In
this mode, current consumption is greatly red uced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a mor e restricted voltage range than
VIH.) I f CE# and RESET# are h eld at VIH, but not within
VCC ± 0.3 V, the de vice will be in the standby mod e,
but the standby current will be gre ater. The devic e re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC4 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin pr ovides a hardware method of re-
setting the device to reading array data. When the RE-
SE T# pin is driv en low for at least a pe riod of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/w rite comm ands for the duration of the RESET #
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
September 20, 2002 Am29LV640D/Am29LV641D 13
The RESET# pin may be tied to the system reset cir-
cuitry. A system res et would thus also res et the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RE SET# is asser ted du ring a progra m or er ase o p-
eration, the RY/BY# pin remains a “0” (busy) unti l the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/ BY# pin is “1”), the reset operation is c om-
pleted within a time of tREADY (not during Embedded
Algorithms). The system c an read data tRH after the
RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET # pa-
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the dev ice is
disabled. The output pins are placed in the high
impedance state.
Table 2. Sector Address Table
Sector A21 A20 A19 A18 A17 A16 A15 16-bit Addre ss Ran g e
(in hexadecimal)
SA0 0000000 000000–007FFF
SA1 0000001 008000–00FFFF
SA2 0000010 010000–017FFF
SA3 0000011 018000–01FFFF
SA4 0000100 020000–027FFF
SA5 0000101 028000–02FFFF
SA6 0000110 030000–037FFF
SA7 0000111 038000–03FFFF
SA8 0001000 040000–047FFF
SA9 0001001 048000–04FFFF
SA10 0001010 050000–057FFF
SA11 0001011 058000–05FFFF
SA12 0001100 060000–067FFF
SA13 0001101 068000–06FFFF
SA14 0001110 070000–077FFF
SA15 0001111 078000–07FFFF
SA16 0010000 080000–087FFF
SA17 0010001 088000–08FFFF
SA18 0010010 090000–097FFF
SA19 0010011 098000–09FFFF
SA20 0010100 0A0000–0A7FFF
SA21 0010101 0A8000–0AFFFF
SA22 0010110 0B0000–0B7FFF
SA23 0010111 0B8000–0BFFFF
SA24 0011000 0C0000–0C7FFF
SA25 0011001 0C8000–0CFFFF
14 Am29LV640D/Am29LV641D September 20, 2002
SA26 0011010 0D0000–0D7FFF
SA27 0011011 0D8000–0DFFFF
SA28 0011100 0E0000–0E7FFF
SA29 0011101 0E8000–0EFFFF
SA30 0011110 0F0000–0F7FFF
SA31 0011111 0F8000–0FFFFF
SA32 0100000 100000–107FFF
SA33 0100001 108000–10FFFF
SA34 0100010 110000–117FFF
SA35 0100011 118000–11FFFF
SA36 0100100 120000–127FFF
SA37 0100101 128000–12FFFF
SA38 0100110 130000–137FFF
SA39 0100111 138000–13FFFF
SA40 0101000 140000–147FFF
SA41 0101001 148000–14FFFF
SA42 0101010 150000–157FFF
SA43 0101011 158000–15FFFF
SA44 0101100 160000–167FFF
SA45 0101101 168000–16FFFF
SA46 0101110 170000–177FFF
SA47 0101111 178000–17FFFF
SA48 0110000 180000–187FFF
SA49 0110001 188000–18FFFF
SA50 0110010 190000–197FFF
SA51 0110011 198000–19FFFF
SA52 0110100 1A0000–1A7FFF
SA53 0110101 1A8000–1AFFFF
SA54 0110110 1B0000–1B7FFF
SA55 0110111 1B8000–1BFFFF
SA56 0111000 1C0000–1C7FFF
SA57 0111001 1C8000–1CFFFF
SA58 0111010 1D0000–1D7FFF
SA59 0111011 1D8000–1DFFFF
SA60 0111100 1E0000–1E7FFF
Table 2. Sector Address Table (Continued)
Sector A21 A20 A19 A18 A17 A16 A15 16-bit Addre ss Ran g e
(in hexadecimal)
September 20, 2002 Am29LV640D/Am29LV641D 15
SA61 0111101 1E8000–1EFFFF
SA62 0111110 1F0000–1F7FFF
SA63 0111111 1F8000–1FFFFF
SA64 1000000 200000–207FFF
SA65 1000001 208000–20FFFF
SA66 1000010 210000–217FFF
SA67 1000011 218000–21FFFF
SA68 1000100 220000–227FFF
SA69 1000101 228000–22FFFF
SA70 1000110 230000–237FFF
SA71 1000111 238000–23FFFF
SA72 1001000 240000–247FFF
SA73 1001001 248000–24FFFF
SA74 1001010 250000–257FFF
SA75 1001011 258000–25FFFF
SA76 1001100 260000–267FFF
SA77 1001101 268000–26FFFF
SA78 1001110 270000–277FFF
SA79 1001111 278000–27FFFF
SA80 1010000 280000–287FFF
SA81 1010001 288000–28FFFF
SA82 1010010 290000–297FFF
SA83 1010011 298000–29FFFF
SA84 1010100 2A0000–2A7FFF
SA85 1010101 2A8000–2AFFFF
SA86 1010110 2B0000–2B7FFF
SA87 1010111 2B8000–2BFFFF
SA88 1011000 2C0000–2C7FFF
SA89 1011001 2C8000–2CFFFF
SA90 1011010 2D0000–2D7FFF
SA91 1011011 2D8000–2DFFFF
SA92 1011100 2E0000–2E7FFF
SA93 1011101 2E8000–2EFFFF
SA94 1011110 2F0000–2F7FFF
SA95 1011111 2F8000–2FFFFF
Table 2. Sector Address Table (Continued)
Sector A21 A20 A19 A18 A17 A16 A15 16-bit Addre ss Ran g e
(in hexadecimal)
16 Am29LV640D/Am29LV641D September 20, 2002
Note: All sectors are 32 Kwords in size.
SA96 1100000 300000–307FFF
SA97 1100001 308000–30FFFF
SA98 1100010 310000–317FFF
SA99 1100011 318000–31FFFF
SA100 1100100 320000–327FFF
SA101 1100101 328000–32FFFF
SA102 1100110 330000–337FFF
SA103 1100111 338000–33FFFF
SA104 1101000 340000–347FFF
SA105 1101001 348000–34FFFF
SA106 1101010 350000–357FFF
SA107 1101011 358000–35FFFF
SA108 1101100 360000–367FFF
SA109 1101101 368000–36FFFF
SA110 1101110 370000–377FFF
SA111 1101111 378000–37FFFF
SA112 1110000 380000–387FFF
SA113 1110001 388000–38FFFF
SA114 1110010 390000–397FFF
SA115 1110011 398000–39FFFF
SA116 1110100 3A0000–3A7FFF
SA117 1110101 3A8000–3AFFFF
SA118 1110110 3B0000–3B7FFF
SA119 1110111 3B8000–3BFFFF
SA120 1111000 3C0000–3C7FFF
SA121 1111001 3C8000–3CFFFF
SA122 1111010 3D0000–3D7FFF
SA123 1111011 3D8000–3DFFFF
SA124 1111100 3E0000–3E7FFF
SA125 1111101 3E8000–3EFFFF
SA126 1111110 3F0000–3F7FFF
SA127 1111111 3F8000–3FFFFF
Table 2. Sector Address Table (Continued)
Sector A21 A20 A19 A18 A17 A16 A15 16-bit Addre ss Ran g e
(in hexadecimal)
September 20, 2002 Am29LV640D/Am29LV641D 17
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, an d sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for pr ogramming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipm ent, the autoselect
mode requires VID (8.5 V to 12.5 V) on address pi n A9.
Address pins A6, A1, and A0 must be as shown in
Table 3. In addition, when verifying sector protection,
the sector address m ust appear on the appropriate
highest order address bits (see Table 2). Table 3
show s the re mainin g addres s bits tha t are don ’t care.
When all necessary bits have been set as required,
the programming equipment may then read the corre-
sponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10. This method
does not require VID. Refer to the Autoselect Com-
mand Sequence section for more information.
Table 3. Autoselect Codes, (High Voltage Method)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Description CE# OE# WE#
A21
to
A15
A14
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0 DQ15 to DQ0
Manufacturer ID: AMD L L H X X VID XLXLL 0001h
Device ID: LV640DU/H/L,
LV641DH/L LLH X XV
ID XLXLH 22D7h
Sector Protection
Verification LLHSAXV
ID XLXHL XX01h (protected),
XX00h (unprotected)
SecSi Sector Indica tor Bit
(DQ7), WP# protects
highest address sector
(LV640DH/641DH), or
no WP# (LV640D U)
LLH X XV
ID XLXHHXX98h (factory locked),
XX18h (not factory locked)
SecSi Sector Indicator Bit
(DQ7), WP# protects
lowest address sector
(LV640DL/641DL)
LLH X XV
ID XLXHHXX88h (factory locked),
XX08h (not factory locked)
18 Am29LV640D/Am29LV641D September 20, 2002
Sector Group Protection and
Unprotection
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this devic e, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Table 4). The hardware sector
group u nprotection feature re-en ables both program
and erase operations in previously protected sector
groups. Sector group protection/unprotection can be
implemented via two methods.
Sector protection/unprotection requires VID on the RE-
SET# pin only, and can be implemented either in-sys -
tem or via progr amming eq uipment. F igure 2 sh ows
the algorithms and Figure 22 shows the timing dia-
gram. This method uses standard microprocessor bus
cycle timing. For sector group unprotect, all unpro-
tected sector groups must first be protected prior to
the first sector group unprotect write cycle.
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and
protecting sector groups at its factory prior to shipping
the device through AMD’s ExpressFlash™ Service.
Contact an AMD representative for details.
It is pos sible to determin e whether a se ctor group is
protected or unprotected. See the Autoselect Mode
section for details.
Table 4. Sector Group Protection/Unprotection
Address Table
Note: All sector groups are 128 Kwords in size.
Sector Group A21–A17
SA0–SA3 00000
SA4–SA7 00001
SA8–SA11 00010
SA12–SA15 00011
SA16–SA19 00100
SA20–SA23 00101
SA24–SA27 00110
SA28–SA31 00111
SA32–SA35 01000
SA36–SA39 01001
SA40–SA43 01010
SA44–SA47 01011
SA48–SA51 01100
SA52–SA55 01101
SA56–SA59 01110
SA60–SA63 01111
SA64–SA67 10000
SA68–SA71 10001
SA72–SA75 10010
SA76–SA79 10011
SA80–SA83 10100
SA84–SA87 10101
SA88–SA91 10110
SA92–SA95 10111
SA96–SA99 11000
SA100–SA103 11001
SA104–SA107 11010
SA108–SA111 11011
SA112–SA115 11100
SA116–SA119 11101
SA120–SA123 11110
SA124–SA127 11111
September 20, 2002 Am29LV640D/Am29LV641D 19
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting the first or last sector without
using VID.
If the system asserts VIL on the WP# pin, the devic e
disables program and erase functions in the first or
last sector independently of whether those sectors
were protec ted or unprotected using the method de-
scribed in “Sector Group Prot ection an d Unprote ction”.
Note that if W P# is at VIL when the device is in the
standby mode, the maximum input load current is in-
creased. See the table in “DC Characteristics”.
If the system asserts VIH on the WP# pin, the device
reverts to whether the first or last sector was previ-
ously set to be protected or unprotected using the
method described in “Se ctor Group Protection and Un-
protection”.
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 4)).
This feature allo ws tempora ry unprotecti on of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Grou p Unprot ect mode is acti vated by
setting the RESET# pin to VID (8.5 V – 12.5 V). During
this mode, formerly protected sector groups can be
programmed or erased by selecting the sector group
addresses. Once VID is removed from the RESET#
pin, all the previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
Figure 21 shows the timing diagrams, for this feature.
Figure 1. Temporary Sector Gr oup
Unprotect Operation
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unp r ot ect
Complet ed (No te 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sector groups unprotected (If WP# = VIL,
the first or last sector will remain protected).
2. All prev iou s ly prot ect ed sec tor gro ups are prote cte d
once again.
20 Am29LV640D/Am29LV641D September 20, 2002
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Sector Group Protect:
Write 60h to sector
group address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
group address
Wait 150 µs
Verify Sector Group
Protect: Write 40h
to sector group
address twith A6 = 0,
A1 = 1, A0 = 0
Read from
sector group address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Group
Protect complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No
Sector Group
Unprotect:
Write 60h to sector
group address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
group address
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector group
address with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
group
verified?
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No All sector
groups
protected?
Yes
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
Set up
next sector group
address
No
Yes
No
Yes
No
No
Yes
No
Sector Group
Protect
Algorithm
Sector Group
Unprotect
Algorithm
First Write
Cycle = 60h?
Protect
another
sector group?
Reset
PLSCNT = 1
September 20, 2002 Am29LV640D/Am29LV641D 21
SecSi (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 words in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the s ecu-
rity of t he ESN once the product is shipped to the field.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locke d version is always protected w hen shippe d
from th e factory, a nd has the SecSi (Secured Silicon )
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to utilize that
sector in any manner th ey choose. The cus tomer-lock-
able version also has the SecSi Sector Indicator Bit
perma nently set to a “0.” Thus, the SecSi Sector Indi-
cator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
The SecSi sector addres s space in this device is allo-
cated as follows:
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the sys tem
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the syst em is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In devices with an ESN, the SecS i Sector is protected
when the device is shipped from the f a ct or y. T h e SecSi
Sector cannot be mo dified in any way. A fa c tory locked
device has an 8-word random ESN at addresses
000000h–000007h.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The de-
vices are then shipped from AMD’s factory with the
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s Express-
Flash service.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 128-word SecSi sector.
Programming and pr otecti ng t he Sec Si Sect or must be
used with caution since, once protected, there is no
procedure availab le for unprotecting the SecSi Secto r
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
The Sec Si Sector area can be pro tected using one of
the following procedures:
■Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is onl y applicabl e to the SecSi
Sector.
■Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sect or protection described in th e “Sector
Group Protection and Unprotection” section.
Once the S ecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region comm and sequence to return to reading and
writing within the remainder of the array.
Hardware Data Protection
The command sequence requirement of unlock cycles
for program ming or erasing provides data prote ction
against inadvertent writes (refer to Table 10 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming , which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
wri tes are igno red until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
greater than VLKO.
Table 5. SecSi Sector Contents
SecS i Sector
Address Range Standard
Fact ory Lo cked ExpressFlash
Fact ory Lo cked Customer
Lockable
000000h–000007h ESN ESN or
determ ined by
customer Determin e d by
customer
000008h–00007Fh Unavailable De t e r m ined by
customer
22 Am29LV640D/Am29LV641D September 20, 2002
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = V IH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical z ero while OE# is a
logical one.
Po we r - Up Wri t e In hibit
If WE# = CE# = VIL and OE# = V IH during power up,
the device does not accept commands on the rising
edge of W E#. The intern al state machine is automati-
cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backw ard-compatible for the specified flash device
famil ies. Flash vendor s can sta ndardi ze their existin g
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addr esses
given in Tables 6–9. To te rminat e readi ng CFI d ata,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CF I query m ode, an d the syst em can read
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the de-
vice to the autoselect mode.
For further information, pleas e refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
Table 6. CFI Query Identification String
Addresses (x16) Data Description
10h
11h
12h
0051h
0052h
0059h Query Unique ASCII string “QRY”
13h
14h 0002h
0000h Primary OEM Command Set
15h
16h 0040h
0000h Addre ss for Prim ary Exten de d Table
17h
18h 0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
September 20, 2002 Am29LV640D/Am29LV641D 23
Table 7. System Interface String
Table 8. Device Geometry Definition
Addresses (x16) Data Description
1Bh 0027h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 0036h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 0004h Typical timeout per single byte/word write 2N µs
20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 000Ah Typical timeout per individual block erase 2N ms
22h 00 00h Typical timeo ut for full chip erase 2N ms (00h = not supported)
23h 0005h Max. timeout for byte/word write 2N times typical
24h 0000h Max. timeout for buffer write 2N times typical
25h 0004h Max. timeout per individual block erase 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
Addresses (x16) Data Description
27h 0017h Device Size = 2N byte
28h
29h 0001h
0000h Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh 0000h
0000h Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch 0001h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
007Fh
0000h
0000h
0001h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
24 Am29LV640D/Am29LV641D September 20, 2002
Table 9. Primary Vendor-Specific Extended Query
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 10 defines the valid register command
seque nces. Writing incorrect address and data val-
ues or writing them in the impr oper sequ ence resets
the device to reading array data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The dev ice is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device a ccepts an Er ase S uspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
Addresses (x16) Data Description
40h
41h
42h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 0031h Major version number, ASCII
44h 0033h Minor version number, ASCII
45h 0000h Address Sensiti ve Unl ock (Bits 1-0)
00b = Required, 01b = Not Required
Silicon Revision Number (Bits 7-2) 000000b = 0.23 µm Process Technology
46h 0002h Erase Suspend
00 = Not Supported, 01 = To Read Only, 02 = To Read & Write
47h 0004h Sector Protect
00 = Not Supported, X = Number of sectors in per group
48h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 0004h Sector Protect/Unprotect scheme
04 = 29LV80 0A mo de
4Ah 0000h Simultaneous Operation
00 = Not Supported, XX = Number of Sectors in Bank
4Bh 0000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh 00B5h ACC (Acceleration) Supply Minimum
Bits 7–4 = Hex Value in Volts, Bits 0–3 = BCD Value in 100 mV
4Eh 00C5h ACC (Acceleration) Supply Maximum
Bits 7–4 = Hex Value in Volts, Bits 0–3 = BCD Value in 100 mV
4Fh 000Xh
Top/Bottom Boot Sector Flag
00h = Uniform Sector, No WP# Control
04h = Uniform Sector, WP# Protects Bottom Sector
05h = Uniform Sector, WP# Protects Top Sector
September 20, 2002 Am29LV640D/Am29LV641D 25
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode
if DQ5 goes high during an active program or erase
operat ion, or if the device is i n the autoselect mod e.
See the next section, Reset Command, for more infor-
mation.
See also Requ irements for Reading A rray Data in the
Device Bus Operations section for more information.
The Read-Only Operations t able provides t he read pa-
rameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the
read or erase-suspen d-read mod e. Address bi ts are
don’t cares for this command.
The reset comm and may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before pro gramming begi ns. This resets the dev ice to
the read mode. If th e program c ommand sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. On ce programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The reset comm and may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice enter ed the autosele ct mode while i n the Erase
Suspend mode, writing the reset c ommand returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or eras e operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 10 shows the addres s and data require ments.
This method is an alternative to that shown in Table 3,
which is intended for PROM programmers and re-
quires VID on address pin A9. The autoselect com-
mand sequence may be written to an address that is
either in th e read or erase-s uspend-rea d mode. The
autosele ct command may not be written while the de-
vice is actively programming or erasing.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autos elect command sequence:
■A read cycle at address XX00h returns the manu-
facturer code.
■A read cycle at address XX01h returns the device
code.
■A read cycle to an address containing a sector
group address (SA), and the address 02h on A7–A0
returns 01h if the sector group is protected, or 00h
if it is unprotected. (Refer to Table 4 for valid sector
addresses).
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 8-word random Electronic Serial Num-
ber (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the de-
vice to norm al op erat ion. Table 10 shows the address
and data requiremen ts for both command sequences.
See also “SecSi (Secured Silicon) Sector Flash
Memory Region” for further information.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
comma nd. The program addr ess and data are wr itten
next, wh ich in tur n initiate the Embedded Progra m al-
gorithm. T he system is not required to pr ovide furthe r
controls or timings. The device automatically provides
internally g enerated program pulse s and verifies the
programmed cell margin. Table 10 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. R efer to the Write Operation
Status section for information on these status bits.
Any co mmands wr itten to the device during the Em-
bedded Program Algorithm are ignored. Note th at a
26 Am29LV640D/Am29LV641D September 20, 2002
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
dat a is still “0.” Only erase ope rations ca n convert a
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock
bypas s command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this m ode. The first
cycle in this sequence cont ains the unlock bypas s pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 10 shows the require-
ments for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Pro gram and Unlock Bypas s Reset comma nds
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
The device offers accelerated program operations
through the ACC pin. When the s ystem assert s VHH on
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quence. The device uses the higher voltage on the
ACC pin to accelerate the operation. Note that the
ACC pin m ust not be at VHH for operatio ns other than
accelerated programming, or device damage may re-
sult.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 15 for timing diagrams.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycl e operat ion. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then foll owed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require t he system to
preprogram prior to era se. The Embedded Erase algo-
rithm automati cally preprograms and verifi es the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note: See Table 10 for program command sequence.
September 20, 2002 Am29LV640D/Am29LV641D 27
When the Embedded Erase algorithm is complete, the
device returns to the read mod e and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to the Write Operation Status section
for information on these status bi ts.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im -
media tely termina tes the erase op eration. If tha t oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Eras e and Program Operation s ta-
bles in the AC Cha racteristics s ection for parameters ,
and Figure 17 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, f ollowed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs an d verifies the en tire memor y for
an all zero da ta pattern prior to electrica l erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
addition al sector addresses and sector erase com-
mands may be writte n. L oading the s ector e rase buffer
may be done in any sequence , and the number o f sec-
tors may be from one sector to all sectors. The time
between these addi tional cycles must be less than 50
µs, otherwise e rasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all comm ands are accepted. Th e
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets the device to the read
mode. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer . ). The t ime-out b egins from th e ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched . The system can determine the
status of the eras e operati on by readin g DQ7, D Q6,
DQ2, or R Y/BY#. Note t hat while the Embedded E rase
operation is in progress, the system can read data
from the non-erasing sector. Refer to the Write Opera-
tion Status sect ion for information on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates th e erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Eras e and Program Operatio ns ta-
bles in the AC Characteristics sectio n for parameters,
and Figure 17 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operat ion and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if writt en dur-
ing the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device im medi-
ately terminates the time-out period and suspends the
erase operation.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Afte r an er ase-s uspen ded pr ogram opera tion is com -
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
28 Am29LV640D/Am29LV641D September 20, 2002
Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. The address
of the erase-suspended sector is required when writ-
ing this command. Further writes of the Resume com-
mand are igno red. Another Erase Suspend c ommand
can be written after the chip has resumed erasing.
Figure 4. Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
September 20, 2002 Am29LV640D/Am29LV641D 29
Command Definitions
Table 10. Command Definitions
Legend:
X = Do n’t care
RA = Address of the me mory l oc ation to b e read .
RD = D ata re ad fr om loc ation RA dur ing read operation.
PA = Address of the memo ry lo catio n to b e pr ogramme d. Addre sses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
eras ed. A ddress bit s A21–A 15 u nique ly s elect any se cto r.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. During unlock cycles, (when lower address bits are 555 or 2AAh
as shown in table) address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when device is in read
mode.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
7. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
8. If WP# protects the highest address sector (or if WP# is not
available), the data is 98h for factory locked and 18h for not
factory locked. If WP# protects the lowest address sector, the
data is 88h for factory locked and 08h for not factor locked.
9. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
11. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
13. The Erase Resume command is valid only during the Erase
Suspend mode.
14. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Command
Sequence
Cycles
Bus Cycles (Notes 1–4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Autoselect (Note 7)
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001
Device ID 4 555 AA 2AA 55 555 90 X01 22D7
SecSi Sector Fa ctory
Protect (Note 8) 4 555 AA 2AA 55 555 90 X03 (see
Note 8 )
Sector Group Protect Verify
(Note 9) 4 555 AA 2AA 55 555 90 (SA)X02 XX00/
XX01
Enter SecSi Sector Region 3 555 AA 2AA 55 555 88
Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3555 AA 2AA 55 555 20
Unlock Bypass Program (Note 10) 2XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 12) 1 BA B0
Erase Resume (Note 13) 1 BA 30
CFI Query (Note 14) 1 55 98
30 Am29LV640D/Am29LV641D September 20, 2002
WRITE OPERATION STATUS
The device provides several bits to determine the st atus of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 and the following subsec tions describe the
function of these bits. DQ7 and DQ6 each offer a method
for determining whether a program or erase operation is
comple te or in pr ogres s. The device als o prov ide s a har d-
ware-based output signal, RY/BY#, to determine whether
an Embedded Pr ogram or Eras e operation is in progress or
has been compl eted.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or comp leted, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the c ommand sequence .
During the Embedded Program algorithm, the device out-
puts on DQ7 t he comp lemen t of t he dat um pr ogr ammed to
DQ7. This DQ7 status also applies to programming during
Erase S uspend. When the Embedded Progr am algorithm i s
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid stat us informa tion on DQ7. If a program address
falls within a protected sector, Data# Po lli ng on DQ7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode.
Durin g the Embedded Era se algorithm, Da ta# Pollin g
produces a “0” on DQ7. Whe n the Embedded Er ase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors s elected for eras ure to read valid s tatus infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unpr otected secto rs, and ign ores the s e-
lected sector s that are protected. Howev er, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to v alid data on DQ7. Depending on
when the system samples the DQ7 output , it may read
the status or valid data. Even if the device has com-
pleted the pr ogram or eras e operation and D Q7 has
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on suc-
cessive read cycles.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 18
in the AC Characteristics section shows the Data#
Polling timing diagram.
Figure 5. Data# Polling Algorithm
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
September 20, 2002 Am29LV640D/Am29LV641D 31
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indica tes whether an Embedded Algor ithm is in
progress or complete. The RY/BY# st atus is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/ BY# is an open-drain output, sev-
eral RY/BY# pins can be tied togeth er in parallel with a
pull-up resistor to VCC.
If the output is low ( Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or the device is in the erase-suspend-read
mode.
Table 11 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Prog ram or E rase alg orithm is in pro gress or com-
plete, or whether the device has entered the Erase
Susp end mode . To ggle B it I may be read at an y ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and d uring the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, success ive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for era sing are prot ected, DQ 6 toggle s for a pproxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sector s t hat a re pr otect ed.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasi ng or is erase-suspend ed.
When the device is acti vely erasing (that is, the Embedded
Erase al gorit hm is in pro gress) , DQ6 tog gles. When t he de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection o n
DQ7: Data# P olling).
If a program address falls within a protected sector,
DQ6 toggles for approx imately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Tabl e 11 shows the ou tputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 19 in
the “AC Characteristics” section shows the toggle bit
timing diagrams . Figure 20 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
Fig ure 6. Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more informa tio n.
32 Am29LV640D/Am29LV641D September 20, 2002
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that i s, the Embedded Eras e algorithm is in prog ress),
or wheth er that sector is erase -suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the s ector is activ ely erasing or i s erase-sus-
pended. D Q6, by comparis on, indicates whether th e
device is actively erasing, or is in Er ase Suspend, but
cannot di stinguish wh ich sect ors are select ed for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare out-
puts for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 19 sho ws the toggle bit timing d iagram. Figure
20 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determ ine whether a toggle bit is toggling. Ty pically,
the system w ould note and store the value of the tog-
gle bit after the first read. After the second re ad, the
system would compare the new value of the toggle bit
with the first. If t he toggle bit is not toggling, the device
has comple ted the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles , the system
determi nes that th e toggle bi t is still togg ling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then de termine again whether the tog gle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. I f it is still tog gling, the de-
vice did not completed the operation successfully, and
the system must write the reset comm and to return to
reading array data.
The rem ainin g scena rio is that t he syste m initia lly de-
termines that the toggle bit is toggling and DQ5 has
not gone hi gh. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determin ing the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a s pecified int ernal pulse cou nt limit. Under t hese
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device ha lts the operation , and when the timi ng limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if the device was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies afte r each a dditional se ctor erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the tim e between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. I f DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device w ill acce pt additio nal sector erase c ommands.
To ens ure the com mand has been acce pted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If D Q3 is high on the second statu s check, the
last command might not have been accepted.
Table 11 shows the status of DQ3 relative to the other
status bits.
September 20, 2002 Am29LV640D/Am29LV641D 33
Table 11. Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid addre ss when r eading status infor mation. Refer to t he appro priate subsect ion f or fur ther detail s.
3. RY/BY# is only available on the FBGA package.
Status DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) RY/BY#
(Note 3)
Standard
Mode Embe dd ed Pro gra m Algo rith m DQ7# Toggle 0 N /A No toggle 0
Embedd ed Era se Alg orith m 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Erase-Suspend-
Read
Erase
Suspended Sector 1 No toggle 0 N/A Toggle 1
Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
34 Am29LV640D/Am29LV641D September 20, 2002
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +15 0°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –65°C to + 12 5°C
Voltage with Respect to Ground
VCC ( N o te 1 ) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +5.5 V
A9, OE#, ACC, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 7. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 8.
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 7. Maximum DC input
voltage o n pin A9 , OE#, A CC, and RESET# is +1 2.5 V
which may overshoot to +14.0 V for periods up to 20 ns.
3. No more tha n one outpu t may be shor ted to ground at a
time. Duration of the short c ircuit should n ot be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; function al operation of the device at
these or any other co nditions above those i ndica ted in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditio ns for exte nd ed per iod s may affe ct dev ice relia bili ty.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
Supply Voltages
VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0–3.6 V
VIO . . . . . . . . . . . . . . . . .eith e r 1. 8 –2.9 V or 3.0–5.0 V
(see Order i n g In fo r matio n section)
Operating ranges define those limits between which the
functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 7. Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 8. Maximum Positive
Overshoot Waveform
September 20, 2002 Am29LV640D/Am29LV641D 35
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. On the WP# pin only, the maximum input load current when WP# = VIL is ± 5.0 µA.
2. The ICC curr ent l isted is t ypical ly l ess t han 2 mA/MHz , wit h OE# at VIH.
3. Maximum ICC specific ations are t ested wi th V CC = VCCmax.
4. ICC active while Embedded Er ase or Embedded Prog ram is in pr ogress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typic al sleep mode current is
200 nA.
6. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, mini mum VIH for CE# and DQ I/Os i s 0.7 VIO. Maximum VIH
for these connect ions is VIO + 0.3 V
7. Not 100% tested.
Parameter
Symbo l Para met er Des cri ptio n Test Cond itio ns Min Typ Max Unit
ILI Input Load Current (Note 1) VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Lea ka ge Cur r en t VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(Not es 2, 3) CE# = VIL, OE# = VIH 5 MHz 9 16 mA
1 MHz 2 4
ICC2 VCC Active Write Current (Notes 3, 4) CE# = VIL, OE# = VIH, WE# = VIL 26 30 mA
ICC3 VCC Standby Current (Note 3) CE#, RESET# = VCC ± 0.3 V,
WP# = VIH 0.2 5 µA
ICC4 VCC Reset Current (Note 3) RESET# = VSS ± 0.3 V, WP# = VIH 0.2 5 µA
ICC5 Automatic Sle ep Mod e (Not es 3, 5) VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V, WP# = VIH 0.2 5 µA
IACC ACC Accelerated Program Current CE# = VIL, OE# = VIH ACC pin 5 10 mA
VCC pin 15 30 m A
VIL Input Low Voltage (Note 6) –0.5 0.8 V
VIH Input High Voltage (Note 6) 0.7 x VCC VCC + 0.3 V
VHH Voltage for ACC Program
Acceleration VCC = 3.0 V ± 10% 11.5 12.5 V
VID Voltage for Autoselect and
Temporary Sector Unpro tec t VCC = 3.0 V ± 10% 8.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.8 VIO V
VOH2 IOH = –100 µA, VCC = VCC m in V
IO–0.4 V
VLKO Low VCC Lock-Out Voltage (Note 7) 2.3 2.5 V
36 Am29LV640D/Am29LV641D September 20, 2002
DC CHARACTERISTICS
Zero-Power Flash
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply C ur re nt in mA
Time in ns
10
8
2
0
12345
Frequency in MHz
Supply Current in mA
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
4
6
12
3.0 V
3.6 V
September 20, 2002 Am29LV640D/Am29LV641D 37
TEST CONDITIONS
Table 12. Test Specifications
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Test
Note: Diodes are IN3064 or equivalent
Figure 1 1. Test Setup
Test Con dit ion 90R,
101R 120R,
121R Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap acit anc e) 30 100 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement
reference leve ls (Se e Note ) 1.5 V
Output timing measurement
reference leve ls 0.5 VIO V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
0.0 V 1.5 V 0.5 VIO V OutputMeasurement LevelInput
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 12. Input Waveforms and
Measurement Levels
38 Am29LV640D/Am29LV641D September 20, 2002
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 12 for test specif icati ons.
Parameter
Description Test Setup
Speed Options
JEDEC Std. 90R 101R 120R,
121R Unit
tAVAV tRC Read Cycle Time (Note 1) Min 90 100 120 ns
tAVQV tACC Addr ess to Output Delay CE #, OE # = VIL Max 90 100 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 120 ns
tGLQV tOE Output Enable to Output Delay Max 35 35 50 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 30 30 30 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 30 30 30 ns
tAXQX tOH Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First Min 0 ns
tOEH Output Enable Hold
Time (Note 1)
Read Min 0 ns
Toggle and
Data# Polling Min 10 ns
tOH
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tRH
tOE
tRH
0 V
RY/BY#
RESET#
tDF
Figure 13. Read Operation Timings
September 20, 2002 Am29LV640D/Am29LV641D 39
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested.
Parameter
Descri ptio n All Speed Options UnitJEDEC Std
tReady RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note) Max 20 µs
tReady RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH Reset High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 14. Reset Timings
40 Am29LV640D/Am29LV641D September 20, 2002
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std. Description 90R 101R 120R,
121R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tASO Address Setup Time to OE# low during toggle bit
polling Min 15 ns
tWLAX tAH Address Hold T ime Min 45 45 50 ns
tAHT Address Hold Time From CE# or OE# high
during toggle bit polling Min 0 ns
tDVWH tDS Data Setup Time Min 45 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOEPH Output Enable High during toggle bit polling Min 20 ns
tGHWL tGHWL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# S etu p Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 35 50 ns
tWHDL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 11 µs
tWHWH1 tWHWH1 Accelerated Word Programming Operation (Note 2) Typ 7 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.9 sec
tVHH VHH Rise and Fall Time (Note 1) Min 250 ns
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Write Recovery Time from RY/BY# Min 0 ns
tBUSY Program/ Era se Valid to RY/BY# Delay Min 90 ns
September 20, 2002 Am29LV640D/Am29LV641D 41
AC CHARACTERISTICS
OE#
WE#
CE#
VCC
Data
Addresses
tDS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h PA PA
Read Status Data (last two cycles)
A0h
t
CS
Status D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
tBUSY
t
CH
PA
otes:
. PA = program address, PD = program data, DOUT is the true data at the program address.
. Illustration shows device in word mode.
Figure 15. Program Operation Timings
ACC tVHH
VHH
VIL or VIH VIL or VIH
tVHH
Figure 16. Accelerated Program Timing Diagram
42 Am29LV640D/Am29LV641D September 20, 2002
AC CHARACTERISTICS
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
tRB
tBUSY
Notes:
1. SA = sector address (for Sector Er ase), VA = Valid Address for readi ng stat us data (see “Write Operation Statu s”.
2. These waveforms are for the word mode.
Figure 17. Chip/Sector Erase Operation Timings
September 20, 2002 Am29LV640D/Am29LV641D 43
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 18. Data# Polling Timings
(During Embedded Algorithms)
44 Am29LV640D/Am29LV641D September 20, 2002
AC CHARACTERISTICS
OE#
CE#
WE#
Addresses
tOEH
tDH
tAHT
tASO
tOEPH
tOE
Valid Data
(first read) (second read) (stops toggling)
tCEPH
tAHT
tAS
DQ6/DQ2 Valid Data
Valid
Status Valid
Status Valid
Status
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 19. Toggle Bit Timings
(During Embedded Algorithms)
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 20. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Pro gra m
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
September 20, 2002 Am29LV640D/Am29LV641D 45
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100% tested.
Parameter
All Speed OptionsJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup Time for Temporary Sector
Unprotect Min 4 µs
tRRB RESET# Hold Time from RY/BY# High for
Temporary Sector Group Unprotect Min 4 µs
RESET#
tVIDR
VID
VSS, VIL,
or VIH
VID
VSS, VIL,
or VIH
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
tRRB
Figure 21. Temporary Sector Group Unprotect Timing Diagram
46 Am29LV640D/Am29LV641D September 20, 2002
AC CHARACTERISTICS
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Group Protect or Unprotect Verify
VID
VIH
For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 22. Sector Group Protect and Unprotect T iming Diagram
September 20, 2002 Am29LV640D/Am29LV641D 47
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std Description 90R 101R 120R,
121R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 45 50 ns
tDVEH tDS Data Setup Time Min 45 45 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low ) Min 0 ns
tWLEL tWS WE# Setu p Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse W idth Min 45 45 50 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 11 µs
tWHWH1 tWHWH1 Accelerated Word Programming Operation
(Note 2) Typ 7 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.9 sec
48 Am29LV640D/Am29LV641D September 20, 2002
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
tBUSY
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = pr ogram add ress, SA = sect or addr ess, PD = prog ram data .
3. DQ7# is the compl ement of the data wri tten to t he devic e. D OUT is the data written to t he devic e.
4. Waveforms are for the word mode.
Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings
September 20, 2002 Am29LV640D/Am29LV641D 49
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 1,000,000 cycle s.
3. The typical chip programming t ime i s consi derabl y less than t he maxi mum chip programmi ng time lis ted, s ince most words
program faster than th e maximum p rogram t imes l isted .
4. In the pre-programming step of the Embed ded Erase algor ithm, all bits are pr ogrammed to 00h bef ore er asure.
5. System-level overhead is the time required to execute the two- or four -bus-c ycle sequence for the program command. See Table
10 for further inf ormati on on command defin ition s.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Era se Time 0.9 15 sec Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time 115 sec
Word Program Time 11 300 µs Excludes system level
overhead (Note 5)
Accelerated Word Program T ime 7 210 µs
Chip Program Time (Note 3) 48 144 sec
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(incl udi ng A9, OE#, and RESE T#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Parameter Description Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C10Years
125°C20Years
50 Am29LV640D/Am29LV641D September 20, 2002
PHYSICAL DIMENSIONS
SSO056—56-Pin Shrink Small Outline Package (SSOP)
Dwg rev AB; 10/99
September 20, 2002 Am29LV640D/Am29LV641D 51
PHYSICAL DIMENSIONS
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm package
Dwg rev AF; 10/99
52 Am29LV640D/Am29LV641D September 20, 2002
PHYSICAL DIMENSIONS
LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm package
September 20, 2002 Am29LV640D/Am29LV641D 53
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOP
Note: For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
54 Am29LV640D/Am29LV641D September 20, 2002
PHYSICAL DIMENSIONS
TSR048—48-Pin Reverse TSOP
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
September 20, 2002 Am29LV640D/Am29LV641D 55
REVISION SUMMARY
Revision A (April 26, 1999)
Initial release.
Revision A+1 (May 4, 1999)
Global
Deleted references to the 4-word unique ESN. Re-
placed references to VCCQ with VIO.
Connection Diagrams
63-ball FBGA: Corrected signal for ball H7 to VIO.
Orderi ng In form ati on
Added “U” designator description.
SecSi (Secured Silicon) Sector Flash Memory
Region
In the third paragraph, repla ced references to boot
sectors w ith SA0. Added table to show Sec Si sector
contents.
DC Characteristics table
Added VIO = VCC as a test condition for ICC1 and ICC2.
Changed VHH minimum specification from 8.5 V to
11.5 V.
Revision A+2 (May 14, 1999)
Orderi ng In form ati on
Clarified the differences between the H, L, and U
designators.
Revision A+3 (June 7, 1999)
Product Selector Guide
Added note under table.
Orderi ng In form ati on
Deleted the “0” f rom the 120 and 15 0 ns part numbers .
Corrected the FBGA package marking for the 150 ns
speed option.
Revision A+4 (June 25, 1999)
Global
Information on the 56-pin SSOP package has been
added: pinout information and physical dimension
drawings.
Comm and Definitions
Corrected the data for SecSi Sector protection in Note
9. Added device ID data to the table.
Revision A+5 (August 2, 1999)
Block Diagram
Separated WP# and ACC.
Ordering Information
Added the valid combinations for the SSOP package.
Revision A+6 (September 28, 1999)
Connection Diagram s
Clarified which pa ckages are available for a particular
part number.
Device Bus Operations
VersatileIO Control: Added comment to contact AMD
for more information on this feature.
DC Chara cteristics
CMOS Compatible table: Added notes (1 and 2) for ILI
and test conditions column.
Test Conditions
In Tes t Specificatio ns table and Input Waveforms an d
Meaurement Levels figure, changed the output mea-
sureme nt level to VIO/2.
AC Chara cteristics
Read-only Operations table: Added note for test setup
column.
Revision B (June 20, 2000)
Global
Deleted refere nces to 150 ns speed op tion. Added
more information and specifications on VIO feature, in-
cluding part number distinctions. At VIO < VCC, the
available speed options are 100 ns and 120 ns. At VIO
≥ VCC, the availab le speed options a re 90 ns and 120
ns. Changed data sheet status to “Preliminary.”
Distinctive Characteristics
Clarified on which devi ces R Y/BY# an d WP# are a vail-
able. Clarified package options for devices.
Ordering Information
Clarified on which devi ces R Y/BY# an d WP# are a vail-
able. Clarified package options for devices. Reinst ated
“0” into the 1 20 ns s peed pa rt numbe r for VIO = 3.0 V
to 5.0 V; added part numbers for V IO = 1.8 V to 2.9 V.
Device Bus Operations table
In the legend, corrected the VHH voltage range.
SecSi Sector Contents table
Corrected ending address in second row to 7Fh.
DC Characteristics table
Redefined VOH1 and VOH2 in terms of VIO. Added note
relative to VIO for V IH and VIL. Deleted note regarding
test condition assumption of V IO = VCC.
56 Am29LV640D/Am29LV641D September 20, 2002
Test Conditions
Test Condition s table: Redefined output timing mea-
surement reference level as 0.5 VIO.
Added note to table and figure.
Erase and Program Opeations table, Alternate CE#
Controlled Erase and Program Operations table,
Erase and Programming Performance table
Changed the typical sector erase time to 1.6 s.
AC Characteristics—Figure 15. Program
Operations Timing and Figure 17. Chip/Sector
Erase Operations
Deleted tGHWL and changed OE# waveform to start at
high.
Physical Dimensions
Replaced figures with more detailed illustrations.
Revision B+1 (August 4, 2000)
Global
Added trademarks for SecSi Sector.
Accelerated Program Operation (page 12), Unlock
Bypass Command Sequence (page 26)
Added caution note regarding ACC pin.
Absolute Maximum Ratings
Corrected the maximum voltage on VIO to +5.5V.
DC Characteristics table
Added WP# = VIH to test conditions for standby cur-
rents ICC3, ICC4, ICC5.
Revision B+2 (October 18, 2000)
Distinctive Characteristics
Corrected package options for 56-pin SSOP as being
available on Am29LV640DH/DL only.
Revision B+3 (January 18, 2001)
Global
Deleted “Preliminary” st atus from document.
General Description
In the second paragraph, corrected references to VIO
voltage ranges. The 90 and 120 speeds are available
where VIO ≥ VCC, and 100 and 120 ns speeds are a vail-
able where VIO < VCC.
Revision B+4 (March 8, 2001)
Table 4, Sector Gr ou p Pr otectio n/U nprotection
Address Table
Corrected the sector group address bits for sectors
64–127.
Revision B+5 (October 11, 2001)
Connection Diagrams, Ordering Information,
Physical Dimensions
Added 64-ball Fortified BGA package information.
Revision B+6 (January 10, 2002)
Global
Clarified description of VersatileIO (VIO) in the follow-
ing sections: Distinctive Characteristics; General De-
scription; VersatileIO (VIO) Control; Operating Ranges;
DC Characteristics; CMOS compatible.
Reduced typical sector erase time from 1.6 s to 0.9 s.
DC Chara cteristics
Changed minimum VOH1 from 0.85VIO to 0.8VIO. De-
leted reference to Note 6 for both VOH1 and VOH2.
Erase and Program Performance table
Reduced typical sector erase time from 1.6 s to 0.9 s.
Changed typical chip program time from 90 s to 115 s.
Revision B+7 (April 15, 2002)
Ordering Information
Added N designator for Fortified BGA package mark-
ings.
Common Flash Interface (CFI)
Rev ised data value at addres s 44h. C larified de scrip-
tion of data for addresses 45–47h, 49, 4A, 4D–4Fh.
Table 10, Comma nd Definition s
Clarified and combined Notes 4 and 5 into Note 4.
Revision B+8 (September 20, 2002)
Sector Erase Command Sequence
Changed sentence arrangement in fourth paragraph.
Trademarks
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
