DTM60136 64MB-8M x 64, 168-Pin Unbuffered PC100 SDRAM DIMM Performance range 1 0 0 M H z ( 1 0 n s @ C L = 2) Features Description Burst mode operation The Dataram DTM60136 Assembly is a 8M bit x 64 Synchronous Dynamic RAM high density memory module. The DTM60136 consists of four CMOS Monolithic 8M x 16 bit Synchronous DRAMs in a TSOP-II 400mil package, and one 2K EEPROM in 8 pin TSSOP package for Serial Presence Detect on a 168-pin glass-epoxy substrate. Synchronous design allows precise cycle control with the use of system clock. The DTM60136 is a Dual in-line Memory Module and is intented for mounting into 168-pin edge connector sockets. Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4 & 8 page) Data scramble (Sequential & Interleave) Serial presence detect with EEPROM 168-pin PC100 DIMM double-sided assembly 5.250" wide by 1.25" high Pin names Pin configurations Front side 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 Vdd DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vdd DQ14 DQ15 *CB0 *CB1 Vss NC NC Vdd WE DQM0 Back side 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 DQM1 CS0 DU Vss A0 A2 A4 A6 A8 A10/AP BA1 Vdd Vdd CLK0 Vss DU CS2 DQM2 DQM3 DU Vdd NC NC *CB2 *CB3 Vss DQ16 DQ17 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ18 DQ19 Vdd DQ20 NC *Vref *CKE1 Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vdd DQ28 DQ29 DQ30 DQ31 Vss CLK2 NC WP **SDA **SCL Vdd 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS DQ32 DQ33 DQ34 DQ35 Vdd DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vdd DQ46 DQ47 *CB4 *CB5 Vss NC NC Vdd CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 *CS1 RAS Vss A1 A3 A5 A7 A9 BA0 A11 Vdd *CLK1 *A12 Vss CKE0 *CS3 DQM6 DQM7 *A13 Vdd NC NC *CB6 *CB7 Vss DQ48 DQ49 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ50 DQ51 Vdd DQ52 NC *Vref REGE Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vdd DQ60 DQ61 DQ62 DQ63 Vss *CLK3 NC **SA0 **SA1 **SA2 Vdd Pin name Function A0-A11 BA0-BA1 DQ0-DQ63 * CB0-CB7 CLK0 CKE0 CS0-CS3 RAS CAS WE DQM0-7 Vdd Vss *Vref REGE SDA SCL SA0-2 DU NC WP Address input (Multiplexed) Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Don't use No connection Write protection * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. DATARAM Corporation P.O. Box 7528, Princeton, NJ 08543-7528; Voice: 609-799-0071, Fax: 609-799-6734, www.dataram.com Document 06055, Revision A, 4/21/00, Dataram Corporation (c) 2000 Page 1 DTM60136 64MB-8M x 64, 168-Pin Unbuffered PC100 SDRAM DIMM Front view 5.250 [133.35] 5.014 [127.35] .157 .004 [4.000 0.100] 1.25 [31.75] .120 [3.048] 0.700 [17.780] A .118DIA 0.004 [3.000DIA 0.100] B .250 [6.35] C 1.450 [36.83] 2.150 [54.61] .450 [11.43] .350 [8.89] .100Min [2.540Min] .250 [6.35] 4.550 [115.57] Detail A Detail B .250 [6.35] 0.123 0.003 [3.125 0.125] Detail C .250 [6.35] .100 Min [2.54 Min] 0.039 0.002 [1.000 0.050] 0.123 0.003 [3.125 0.125] 0.079 0.004 [2.000 0.100] .010 Max [.25 Max] 0.079 0.004 [2.000 0.100] .050 [1.27] Back view Side view .140 Max [3.556 Max] 0.200 Min [5.08 Min] Notes .0500 .004 [1.27 .10] Tolerances on all dimensions except where otherwise indicated are .005 [.13]. All dimensions are expressed: inches [millimeters]. Document 06055, Revision A, 4/21/00 Page 2 DTM60136 64MB-8M x 64, 168-Pin Unbuffered PC100 SDRAM DIMM /CS0 CS DQM I/O (7:0) DQM0 DQ (7:0) DQM4 DQ (39:32) 10 10 DQM1 DQ (15:8) DQM I/O (15:8) DQM5 DQ (47:40) 10 CS DQM I/O (39:32) DQM I/O (47:40) 10 /CS2 CS DQM I/O (23:16) DQM2 DQ(23:16) CS DQM I/O (55:48) DQM6 DQ (55:48) 10 10 DQM I/O (31:24) DQM3 DQ(31:24) DQM I/O (63:56) DQM7 DQ (63:56) 10 10 SERIAL PD SCL SA2 SA1 SA0 SDA WP Clock Wiring Clock Input CK0 CK1 CK2 CK3 Load 2 SDRAMs + 15pF cap TERMINATION 2 SDRAMs + 15pF cap TERMINATION CKE0 /RAS /CAS /WE A (11:0) BA (1:0) CKE: /RAS: /CAS: /WE: A (11:0): BA(1:0): SDRAMs TERMINATION *Wire per clock Loading Table/Wiring Diagrams V DD .1f .33f To Each SDRAM VSS Document 06055, Revision A, 4/21/00 Page 3 DTM60136 64MB-8M x 64, 168-Pin Unbuffered PC100 SDRAM DIMM Absolute maximum ratings Symbol Voltage on any pin relative to VSS V IN , V OUT Voltage on VDD supply relative to VSS V DD V DDQ T stg Storage temperature PD Power dissipation IOS Short-circuit output current Rating -1.0 to 4.6 -1.0 to 4.6 -55 to +150 4 50 Unit V V O C W mA Note: Permanent damage to the device may occur if absolute maximum ratings are exceeded. Operation should be restricted to the conditions detailed in the operational sections of the data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC operating conditions and characteristics (Voltage referenced to VSS= 0V; TA = 0 to 70C) Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current (Inputs) Input leakage current (I/O pins) Symbol VDD VIH VIL VOH VOL IIL IIL Minimum 3.0 2.0 -0.3 2.4 -25 -10 Typical 3.3 3.0 0 - Maximum 3.6 V DDQ+0.3 0.8 0.4 25 10 Unit V V V V V uA uA Note 1 2 IOH=-2mA IOL=2mA 3 3,4 Notes: (1) VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. (2) VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. (3) Any input OV VIN VDDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. (4) Dout is disabled, OV VOUT VDDQ Capacitance (VDD = 3.3V, TA = 23oC, f = 1MHz, VREF = 1.4V 200mV) Address (A0-A11, BA0-BA1) RAS, CAS, WE CKE (CKE0-CKE1) Clock (CLK0-CLK2) CS (CS0, CS2) DQM (DQM0-DQM7) DQ (DQ0-DQ63) Document 06055, Revision A, 4/21/00 Symbol CADD CIN CCKE CCLK CCS CDQM COUT1 Minimum 10 10 10 20 5 2.5 4 Maximum Unit 15 pF 15 pF 15 pF 22 pF 8 pF 4 pF 6 pF Page 4