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  
FEATURES APPLICATIONS
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
PROGRAMMABLE TOUCH SCREEN CONTROLLERWITH STEREO AUDIO CODEC
•SPI™ Serial Interface •Personal Digital Assistants•Touch Screen Controller •Cellular Phones– 4-Wire Touch Screen Interface •MP3 Players– Internal Detection of Screen Touch and •Internet AppliancesKeypad Press
•Smartphones– Touch Pressure Measurement– Ratiometric Conversion– Programmable 8-, 10- or 12-Bit Resolution
The TSC2301 is a highly integrated PDA analog– Programmable Sampling Rates Up to 125
interface circuit. It contains a complete 12-bit A/DkHz
resistive touch screen converter (ADC) includingdrivers, touch pressure measurement capability,– Direct Battery Measurement (0 to 6 V)
keypad controller, and 8-bit D/A converter (DAC)– On-Chip Temperature Measurement
output for LCD contrast control. The TSC2301 offers– 4-by-4 Keypad Interface With
programmable resolution of 8, 10, and 12 bits andProgrammable De-Bounce and Key
sampling rates up to 125 kHz to accommodateMasking
different screen sizes. The TSC2301 interfaces to the– Integrated Touch Screen Processor
host controller through a standard SPI serialReduces Host CPU Interrupts and Overhead
interface.– Internal Timing Control With Programmable
The TSC2301 features a high-performance 20-bit,Delays and Averaging
48-ksps stereo audio codec with highly integrated•Stereo Audio Codec
analog functionality. The audio portion of the– 20-Bit Delta-Sigma ADC/DAC
TSC2301 contains microphone input with built-inpre-amp and microphone bias circuit, an auxiliary– Dynamic Range: 98 dB
stereo analog input, a stereo line-level output, a– Sampling Rate Up to 48 kHz
differential mono line-level output, and a stereo– I
2
S Serial Interface
headphone amplifier output. The digital audio data is– Stereo 16- ΩHeadphone Driver
transferred through a standard I
2
S interface. A fully•Full Power-Down Control programmable PLL for generating audio clocks from awide variety of system clocks is also included.•8-Bit Current Output DAC•On-Chip Crystal Oscillator
The TSC2301 also offers two battery measurementinputs capable of battery voltages up to 6 V, while•Programmable Bass/ Midrange/ Treble EQ
operating at a supply voltage of only 2.7 V. It also hasEffects Processing
an on-chip temperature sensor capable of reading•6 GPIO Pins
0.3 °C resolution. The TSC2301 is available in 64-lead•Single 2.7-V to 3.6-V Supply
TQFP, and 120-ball VFBGA packages.•64-Pin TQFP Package
US Patent No. 6246394•120-Ball MicroStar Junior™ BGA Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.MicroStar Junior is a trademark of Texas Instruments.SPI is a trademark of Motorola.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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Ω
30k
Ω
20k
+20 to -40dB,
0.5dB Steps Σ∆
ADC
Mute, 0db, 6dB, 12dB
Σ∆
DAC
Headphone
Driver
Σ∆
DAC
Headphone
Driver
Digital
Audio
Processing
I2S
INTERFACE
Control
Interface
OSC
AVDD
VCM
AGND
RLINEIN
MICIN
LLINEIN
HPGND
HPVDD
HPR
VOUTR
VOUTL
HPL
COI
COO
SPISEL
SPIDIN
SPICLK
SPIDO
DAV
MCLK
LRCLK
I2SDIN
I2SDOUT
BCLK
PENIRQ
+20 to -40dB,
0.5dB Steps Σ∆
ADC
+12dB to -
35dB
0.5dB steps
X-
X+
Y-
Y+ Touch
Pannel
Drivers
Temp
Sensor
VBAT2
VBAT1
AUX2
AUX1
Battery
Monitor
Battery
Monitor
ADC
SAR
C1 C2 C3 C4 R1 R2 R3 R4
Keypad Scanner and State Control
CONTROL
LOGIC
&
SPI
INTERFACE
DAC
DACOUT
DACSET
Internal 2.5V/
1.25V Reference
VREFIN
MONO+
MONO-
KBIRQ
Digital Gain
0 to -63.5dB
0.5dB Steps
Digital Gain
0 to -63.5dB
0.5dB Steps
POL
RESET
VREF+
VREF-
317Ω
317Ω
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5/CLKO
GPIO
INTERFACE
DGND (2)
DVDD (2)
AFILTR AFILTL
AVDD-1V
MICBIAS
And
PLL
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
2
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ABSOLUTE MAXIMUM RATINGS
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE OPERATING ORDERING TRANSPORT MEDIADESIGNATOR TEMPERATURE RANGE NUMBER QUANTITY
TSC2301IPAG Trays, 160TQFP-64 PAG
TSC2301IPAGR Tape and reel, 1500TSC2301IGQZ Trays, 250TSC2301I GQZ –40 °C to 85 °C
TSC2301IGQZR Tape and reel, 2500VFBGA-120
TSC2301IZQZ Trays, 250ZQZ
TSC2301IZQZR Tape and reel, 2500
over operating free-air temperature range unless otherwise noted
(1)
TSC2301
Supply voltage AVDD, HPVDD, DVDD 4 VGround voltage differences AGND, DGND ±0.1 VDigital input voltage -0.3 V to (DV
DD
+ 0.3 V)Analog input voltage -0.3 V to (AV
DD
+ 0.3 V)Ambient temperature under bias, T
A
-40 °C to 125 °CStorage temperature, T
stg
-55 °C to 150 °CJunction temperature, T
J
150 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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ELECTRICAL CHARACTERISTICS
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
At 25 °C, HPV
DD
= AV
DD
= DV
DD
= +3.3 V, V
REF
= External 2.5 V, unless otherwise noted.
TSC2301Parameter Conditions UnitsMin Typ Max
Auxilary Analog Inputs
Input voltage range 0 +VREFIN VInput capacitance 25 ρFInput leakage current 1 µA
Battery Monitor Input
Input voltage range 0 6.0 VInput capacitance 25 ρFInput leakage current ±1 µA
Temperature Measurement
Temperature range -40 +85 °CTemperature resolution 0.3 °CAccuracy ±2 °C
Touch Screen A/D Converter
Resolution Programmable: 8-, 10-,12-Bits 12 BitsNo missing codes 12-bit resolution 10 BitsIntegral linearity ±6 LSBOffset error ±6 LSBTSC2301IPAG ±6Gain error LSBTSC2301IGQZ ±10
µVNoise <300
RMS
Audio Codec
Sampling frequency 48 kHz
Audio I/O
Audio in Line, Mic inputs 0.15* AVDD 0.65* AVDD VAudio out Line outputs 0.15* AVDD 0.65* AVDD VADC performance measured usingAudio ADC
Fs = 48 kHzSignal-to-noise ratio, A-weighted No input 80 88 dBTotal harmonic distortion 1 kHz, -0.5 dB input -70 -60 dB0.18*Full-scale input voltage VrmsAVDDTransition band 0.45 Fs 0.55 Fs HzStop band 0.55 Fs 127 Fs HzStop band rejection 70dBDAC performance measured at LineAudio DAC
Outputs using Fs = 48 kHz
0.18*Full-scale output voltage VrmsAVDDSignal-to-noise ratio, A-weighted No input 98 dBTotal harmonic distortion 1-kHz, 0-dB input -100 dBFrequency response 20 0.45 Fs HzTransition band 0.45 Fs 0.55 Fs HzStop band 0.55 Fs 3.5 Fs HzStop band rejection 65 dBDAC playback through headphoneHeadphone Driver
driver
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS (continued)At 25 °C, HPV
DD
= AV
DD
= DV
DD
= +3.3 V, V
REF
= External 2.5 V, unless otherwise noted.
TSC2301Parameter Conditions UnitsMin Typ Max
Output power per channel R = 32 Ω14 mWR = 16 Ω27 mWR = 16 ΩV
DD
= 3.6V 32 mWSignal-to-noise ratio, A-weighted 85 96 dBTotal harmonic distortion R = 32 Ω1-kHz, 0-dB input -83 -70 dBR = 16 Ω1-kHz, -3-dB input -77 dB
D/A Converter
Output current range Measured with ARNG floating 0.75 1.10 mAResolution 8 Bits
Voltage Reference
TSC2301IPAG 2.34 2.49 2.54Voltage range Internal 2.5 V VTSC2301IGQZ 2.34 2.49 2.64
ppm/ °Reference drift 50
CCurrent drain 20 µA
Digital Input / Output
Internal clock frequency 8.8 MHzLogic family CMOSLogic level: V
IH
I
IH
= 5 µA 0.7 V
DD
VV
IL
I
IL
= 5 µA -0.3 0.3 V
DD
VV
OH
I
OH
= 2 TTL loads 0.8* DVDD VV
OL
I
OL
= 2 TTL loads 0.2* DVDD V
Power Supply Requirements
Power supply voltageDV
DD
, AV
DD
, HPV
DD
2.7 3.6 VQuiescent current
(1)
Touch screen only 1-kHz SAR sample rate, external V
ref
14 µA20-kHz SAR sample rate, internalTouch screen only 1.7 mAV
ref
Stereo playback only 44.1-kHz Playback, V
DD
= 2.7V 10 mAVoice record only Mono 8-kHz record, V
DD
= 2.7V 5.8 mAPower down Audio fully powered down .05 µA
(1) For more details on power consumption, see the Audio Codec section of the description overview.
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DGND
AFILTL
VREF–
VREF+
VCM
MICIN
LLINEIN
RLINEIN
C4
C3
C2
C1
R4
R3
R2
AFILTR
MICBIAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Y–
X+
MONO+
MONO–
VOUTL
VOUTR
AGND
AVDD
HPL
HPR
HPGND
X–
Y+
HPVDD
AUX1
AUX2
TSC2301
VBAT1
VBAT2
VREFIN
ARNG
AOUT
POL
PENIRQ
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5/CLKO
DVDD
SS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
KBIRQ
DGND
DVDD
I2SDOUT
I2SDIN
LRCLK
BCLK
MCLK
R1
COO
COI
DAV
MISO
MOSI
SCLK
RESET
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
PIN ASSIGNMENT
(TOP VIEW)
PIN DESCRIPTION
VFBGA TQFP I/O NAME DESCRIPTIONBALL PIN
A10 1 I VBAT1 Battery monitor input 1B9 2 I VBAT2 Battery monitor input 2A9 3 I/O VREFIN SAR reference voltageB8 4 ARNG DAC analog output range setA8 5 O AOUT Analog output current from DACA7 6 O PENIRQ Pen interruptB6 7 I POL SPI clock polarityA6 8 I/O GPIO_0 General-purpose input/output pinA5 9 I/O GPIO_1 General-purpose input/output pinB4 10 I/O GPIO_2 General-purpose input/output pinA4 11 I/O GPIO_3 General-purpose input/output pinB3 12 I/O GPIO_4 General-purpose input/output pinA3 13 I/O GPIO_5/CLKO General-purpose input/output pin/buffered oscillator clock outNC 14 I DVDD Digital voltage supplyA2 15 I DGND Digital ground
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
PIN DESCRIPTION (continued)
VFBGA TQFP I/O NAME DESCRIPTIONBALL PIN
Slave select input (active low). Data is not clocked into MOSI unless SS is low.B2 16 I SS
When SS is high, MISO is high impedance.B1 17 I SCLK SPI clock inputC2 18 I MOSI SPI data input. Data is clocked in at SCLK rising edgeSPI data output. Data is clocked out at SCLK falling edge. High impedance whenC1 19 O MISO
SS is high.D2 20 O DAV Data available (active low).D1 21 I COI Crystal inputE2 22 O COO Crystal outputE1 23 I MCLK Master clock input for audio codecF2 24 I BCLK I
2
S bit clockF1 25 I LRCLK I
2
S left/right clockG1 26 I I2SDIN I
2
S serial data inG2 27 O I2SDOUT I
2
S serial data outH1 28 I DVDD Digital voltage supplyJ1 29 I DGND Digital groundJ2 30 O KBIRQ Keypad interrupt (active low). Indicates a key has been depressedK1 31 I RESET Device reset (active high)K2 32 O R1 Keypad row 1L2 33 O R2 Keypad row 2K3 34 O R3 Keypad row 3L3 35 O R4 Keypad row 4K4 36 I C1 Keypad column 1L4 37 I C2 Keypad column 2K5 38 I C3 Keypad column 3L5 39 I C4 Keypad column 4L6 40 I LLINEIN Left-channel analog input to audio codecL7 41 I RLINEIN Right-channel analog input to audio codecK7 42 I MICIN Analog input from microphoneL8 43 O MICBIAS Bias voltage outputK8 44 O VCM Common-mode voltage bypass capacitorL9 45 O AFILTR Right-channel audio ADC antialiasing filter capacitorK9 46 O AFILTL Left-channel audio ADC antialiasing filter capacitorL10 47 I VREF+ Audio codec positive reference voltageK10 48 I VREF- Audio codec negative reference voltageK11 49 O MONO+ Mono differential outputJ10 50 O MONO- Mono differential outputJ11 51 O VOUTR Audio right line outputH10 52 O VOUTL Audio left line outputH11 53 I AGND Analog groundG10 54 I AVDD Analog supplyG11 55 O HPL Headphone amplifier left outputF10 56 O HPR Headphone amplifier right outputF11 57 I HPGND Analog ground for headphone amplifier and touch screen circuitryE11 58 I X- X- position inputE10 59 I Y- Y- position inputD11 60 I X+ X+ position input
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TIMING DIAGRAM
ttd
ta
tsck
tLead tLag
twsck twsck tr
tf
tvtho tdis
thi
tsu
MSB OUT BIT . . . 1 LSB OUT
MSB IN BIT . . . 1 LSB IN
SS
SCLK
MISO
MOSI
TIMING CHARACTERISTICS
(1) (2)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
PIN DESCRIPTION (continued)
VFBGA TQFP I/O NAME DESCRIPTIONBALL PIN
D10 61 I Y+ Y+ position inputC11 62 I HPVDD Analog supply for headphone amplifier and touch screen circuitryB11 63 I AUX1 SAR auxiliary analog input 1B10 64 I AUX2 SAR auxiliary analog input 2
All specifications typical at -40 °C to +85 °C, +V
DD
= +2.7 V, POL = 1
Parameter Symbol Min Max Units
SCLK period t
sck
30 nsEnable lead time t
Lead
15 nsEnable lag time t
Lag
15 nsSequential transfer delay t
td
30 nsData setup time t
su
10 nsData hold time (inputs) t
hi
10 nsData hold time (outputs) t
ho
0 nsSlave access time t
a
15 nsSlave DOUT disable time t
dis
15 nsData valid t
v
10 nsRise time t
r
30 nsFall time t
f
30 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.(2) See timing diagram, above.
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TYPICAL CHARACTERISTICS
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
–50 050 100
Change in Error (LSB)
Temperature (C)
Idd (mA)
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
–50 050 100
Temperature (C)
Idd (mA)Idd (mA)
Change in Error (LSB)
–2
–1.5
–1
–0.5
0
0.5
1
–50 050 100
Temperature (C)
On–Resistance (Ohms)
4
4.5
5
5.5
6
6.5
–50 050 100
Temperature (C)
1.193
1.194
1.195
1.196
1.197
1.198
1.199
1.2
1.201
1.202
–50 050 100
Vref (V)
Temperature (C)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
At T
A
= +25 °C, +V
DD
= +3.3 V, V
REF
= +2.5 V, f
SAMPLE
= 125 kHz, unless otherwise noted.
CHANGE IN GAIN ERROR CHANGE IN OFFSET ERROR CONVERSION SUPPLY CURRENTvs vs vsTEMPERATURE TEMPERATURE TEMPERATURE
Figure 1. Figure 2. Figure 3.
TOUCH SCREEN DRIVER INTERNAL 1.25-V REFERENCE INTERNAL OSCILLATORON-RESISTANCE vs FREQUENCYvs TEMPERATURE vsTEMPERATURE TEMPERATURE
Figure 4. Figure 5. Figure 6.
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2.46
2.465
2.47
2.475
2.48
2.485
2.49
2.495
2.5
–50 050 1001.225
1.23
1.235
1.24
1.245
1.25
1.255
1.26
1.265
1.27
1.275
Vref (V)
Temperature (C)
500
600
700
800
900
–60 –40 –20 0 20 40 60 80 100
Temp2 Voltage (mV)
Temperature (C)
Temperature (C)
DAC Output Current (mA)
0.9
0.95
1
1.05
1.1
1.15
1.2
–50 050 100
–104.00
–103.00
–102.00
–101.00
–100.00
–99.00
–98.00
–97.00
–60 –40 –20 0 20 40 60 80 100
THD (dBm)
Temperature (C)
2.085
2.09
2.095
2.1
2.105
2.11
2.115
2.12
2.125
2.13
–50 050 100
Temperature (C)
Vmicbias (V)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, +V
DD
= +3.3 V, V
REF
= +2.5 V, f
SAMPLE
= 125 kHz, unless otherwise noted.
INTERNAL 2.5-V REFERENCE DAC OUTPUT CURRENT TEMP2 DIODE VOLTAGEvs vs vsTEMPERATURE TEMPERATURE TEMPERATURE
Figure 7. Figure 8. Figure 9.
TEMP1 DIODE VOLTAGE MICBIAS THD OF DAC (LINEOUT)vs vs vsTEMPERATURE TEMPERATURE TEMPERATURE
Figure 10. Figure 11. Figure 12.
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98
98.125
98.25
98.375
98.5
98.625
98.75
98.875
99
–60 –40 –20 0 20 40 60 80 100
SNR (dB)
Temperature (C)
–72.000
–71.000
–70.000
–69.000
–68.000
–67.000
–66.000
–65.000
–64.000
–63.000
–62.000
–60 –40 –20 0 20 40 60 80 100
THD (dB)
Temperature (C)
83
84
85
86
87
88
89
90
–60 –40 –20 0 20 40 60 80 100
SNR (dB)
Temperature (C)
–103.0
–102.0
–101.0
–100.0
–99.0
–98.0
–60 –40 –20 0 20 40 60 80 100
THD (dB)
Temperature ( C)
93
94
95
96
97
98
–60 –40 –20 0 20 40 60 80 100
THD (dB)
Temperature (C)
93
94
95
96
97
98
–60 –40 –20 0 20 40 60 80 100
THD (dB)
Temperature (C)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, +V
DD
= +3.3 V, V
REF
= +2.5 V, f
SAMPLE
= 125 kHz, unless otherwise noted.
SNR OF DAC (LINEOUT) THD OF ADC (LINEIN) SNR OF ADC (LINEIN)vs vs vsTEMPERATURE TEMPERATURE TEMPERATURE
Figure 13. Figure 14. Figure 15.
THD OF DAC (HP DRIVER), SNR OF DAC (HP DRIVER) THD OF BYPASS PATH32- ΩLOAD vs vsvs TEMPERATURE TEMPERATURETEMPERATURE
Figure 16. Figure 17. Figure 18.
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–102
–101
–100
–99
–98
–97
–96
–95
–60 –40 –20 0 20 40 60 80 100
SNR (dB)
Temperature (C)
96
97
98
99
100
–60 –40 –20 0 20 40 60 80 100
SNR (dB)
Temperature (C)
Vref (V)
Vdd (V)
2.483
2.48375
2.4845
2.48525
2.486
2.48675
2.4875
2.5 3 3.5
1.1999
1.2
1.2001
1.2002
1.2003
1.2004
1.2005
2.5 3 3.5
Vref (V)
Vdd (V)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, +V
DD
= +3.3 V, V
REF
= +2.5 V, f
SAMPLE
= 125 kHz, unless otherwise noted.
SNR OF BYPASS PATH THD OF MONO PATH SNR OF MONO PATHvs vs vsTEMPERATURE TEMPERATURE TEMPERATURE
Figure 19. Figure 20. Figure 21.
1.25-V REFERENCE 2.5-V INTERNAL REFERENCE SWITCH ON-RESISTANCEvs vs vsSUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 22. Figure 23. Figure 24.
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609
609.2
609.4
609.6
609.8
610
610.2
610.4
610.6
610.8
611
2.5 3 3.5
Temp1 Voltage (mV)
Vdd (V)
720
722
724
726
728
730
2.5 33.5
Temp2 Voltage (mV)
Vdd (V)
8.5
8.6
8.7
8.8
8.9
9
2.5 3 3.5
Internal Oscillator Frequency (MHz)
Vdd (V)
0
0.075
0.15
0.225
0.3
0.375
0.45
2.5 3 3.5
Supply Current (uA)
Vdd (V)
3
3.25
3.5
3.75
4
4.25
4.5
2.5 3 3.5
INL_Max (LSB)
Vdd (V)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, +V
DD
= +3.3 V, V
REF
= +2.5 V, f
SAMPLE
= 125 kHz, unless otherwise noted.
TEMP2 DIODE VOLTAGE TEMP1 DIODE VOLTAGE INTERNAL OSCILLATORvs vs FREQUENCYSUPPLY VOLTAGE SUPPLY VOLTAGE vsSUPPLY VOLTAGE
Figure 25. Figure 26. Figure 27.
DAC MAXIMUM CURRENT PD SUPPLY CURRENT INL MAXIMUMvs vs vsSUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 28. Figure 29. Figure 30.
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1
1.25
1.5
1.75
2
2.5 33.5
Idd_Total (mA)
Vdd (V)
–3
–2.75
–2.5
–2.25
–2
–1.75
–1.5
2.5 3 3.5
INL_Min (LSB)
Vdd (V)
–77
–76
–75
–74
–73
–72
–71
–70
–69
–68
–67
2.5 3 3.5
THD (dB)
Vdd (V)
THD (dB)
–102
–101
–100
–99
–98
–97
–96
–95
2.5 33.5
Vdd (V)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, +V
DD
= +3.3 V, V
REF
= +2.5 V, f
SAMPLE
= 125 kHz, unless otherwise noted.
INL MINIMUM CONVERSION SUPPLY CURRENT MICBIASvs vs vsSUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 31. Figure 32. Figure 33.
THD OF DAC (LINEOUT) SNR OF DAC (LINEOUT) THD OF ADC (LINEIN)vs vs vsSUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 34. Figure 35. Figure 36.
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92
93
94
95
96
97
98
99
2.5 3 3.5
SNR (dB)
Vdd (V)
83
84
85
86
87
88
89
90
2.5 3 3.5
SNR (dB)
Vdd (V)
–85
–84
–83
–82
–81
–80
–79
–78
2.5 3 3.5
THD (dB)
Vdd (V)
96
97
98
99
100
101
102
2.5 33.5
SNR (dB)
Vdd (V)
–103
–102
–101
–100
–99
–98
2.5 3 3.5
THD (dB)
Vdd (V)
–100
–99
–98
–97
–96
–95
2.5 3 3.5
THD (dB)
Vdd (V)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, +V
DD
= +3.3 V, V
REF
= +2.5 V, f
SAMPLE
= 125 kHz, unless otherwise noted.
SNR OF ADC (LINEIN) THD OF DAC (HP DRIVER) SNR OF DAC (HP DRIVER)vs vs vsSUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 37. Figure 38. Figure 39.
THD OF BYPASS PATH SNR OF BYPASS PATH THD OF MONO PATHvs vs vsSUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 40. Figure 41. Figure 42.
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96
97
98
99
100
101
102
2.5 3 3.5
SNR (dB)
Vdd (V)
OVERVIEW
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, +V
DD
= +3.3 V, V
REF
= +2.5 V, f
SAMPLE
= 125 kHz, unless otherwise noted.
SNR OF MONO PATHvsSUPPLY VOLTAGE
Figure 43.
The TSC2301 is an analog interface circuit for human interface devices. A register-based architecture easesintegration with microprocessor-based systems through a standard SPI bus. All peripheral functions arecontrolled through the registers and onboard state machines.
The TSC2301 consists of the following blocks (refer to the block diagram on p. 2):1. Touch screen interface2. Keypad interface3. Battery monitors4. Auxiliary inputs5. Temperature monitor6. Current output digital-to-analog converter7. Audio codec and signal processing
Communication to the TSC2301 is via a standard SPI serial interface. This interface requires that the slave selectsignal be driven low to communicate with the TSC2301. Data is then shifted into or out of the TSC2301 undercontrol of the host microprocessor, which also provides the serial data clock.
Control of the TSC2301 and its functions is accomplished by writing to different registers in the TSC2301. Asimple command protocol is used to address the 16-bit registers. Registers control the operation of the touchscreen A/D converter, keypad scanner, and audio codec.
The result of measurements made are placed in the TSC2301 memory map and can be read by the host at anytime. Three signals are available from the TSC2301 to indicate that data is available for the host to read. TheDAV output indicates that an analog-to-digital conversion has completed and that data is available. The KBIRQoutput indicates that an unmasked key on the keypad has been pressed and de-bounced. The PENIRQ outputindicates that a touch has been detected on the touch screen.
A typical application of the TSC2301 is shown in Figure 44 .
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1 2 3 4 5 6 78 9 10
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33343536373839404142434445464748
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
MONO+
MONO-
VOUTR
VOUTL
AGND
AVDD
HPL
HPR
HPGND
X-
Y-
X+
Y+
HPVDD
AUX1
AUX2
R1
RESET
KBIRQ
DGND
DVDD
I2SDOUT
I2SDIN
LRCLK
BCLK
MCLK
COO
COI
DAV
SPI_DOUT
SPI_DIN
SPI_CLK
VBAT1
VBAT2
VREFIN
DACset
DACout
PENIRQ
POL
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5/CLK0
DVDD
DGND
SS
VREF-
VREF+
AFILTL
AFILTR
VCM
MICBIAS
MICIN
AUXINR
RLINEIN
C4
C3
C2
C1
R4
R3
R2
TSC2301
TOUCH
SCREEN
MONO
AMP
Voltage
Regulator
Voltage
Regulator
Main
Battery Secondary
Battery
LCD Contrast Control
KEYPAD
HEADPHONE
JACK
MICROPHONE
JACK Rbias
A
A
A A A
A
A
A
AA
A
A
AA
AA
A
A
A
Auxilliary Inputs
D
DD
D
D
DD
D
11 12 13 14 15 16
15 pF
Rrng
1nF
1nF
Line Outputs
Line Inputs
0
15 1314 12
11 10
12
4
3
567
89
D
DVDD
1 to 10
µF0.1 µF
1 µF
1 µF
1 µF
220 µF
220 µF
10 Ω
to 100 Ω
1 µF
1 µF
1 to 10
µF0.1 µF
0.1 µF1 to 10
µF
1 to 10
µF0.1 µF
1 to 10
µF0.1 µF
15 pF
1 to 10
µF
0.1 µF
1 µF
DETAILED DESCRIPTION
OPERATION - TOUCH SCREEN
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
OVERVIEW (continued)
Figure 44. Typical Circuit Configuration
A resistive touch screen works by applying a voltage across a resistor network and measuring the change inresistance at a given point on the matrix where a screen is touched by an input stylus, pen, or finger. The changein the resistance ratio marks the location on the touch screen.
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The 4-Wire Touch Screen Coordinate Pair Measurement
Conductive Bar
Transparent Conductor (ITO)
Bottom Side
X+
X–
Y+
Y–
Transparent Conductor (ITO)
Top Side
Insulating Material (Glass)
ITO= Indium Tin Oxide
Silver Ink
RTOUCH RX–plateX–position
4096 Z2
Z11
(1)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
DETAILED DESCRIPTION (continued)The TSC2301 supports the resistive 4-wire configuration (see Figure 44 ). The circuit determines location in twocoordinate pair dimensions, although a third dimension can be added for measuring pressure.
A 4-wire touch screen is constructed as shown in Figure 45 . It consists of two transparent resistive layersseparated by insulating spacers.
Figure 45. 4-Wire Touch Screen Construction
The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.The ADC converts the voltage measured at the point where the panel is touched. A measurement of the Yposition of the pointing device is made by connecting the X+ input to the ADC input, driving Y+ to +VDD and Y-to GND using switches internal to the TSC2301, and digitizing the voltage seen at the X+ input. The voltagemeasured is determined by the voltage divider developed at the point of touch. For this measurement, thehorizontal panel resistance in the X+ lead does not affect the conversion, due to the high input impedance of theADC.
Voltage is then applied to the other axis, and the ADC converts the voltage representing the X position on thescreen. This provides the X and Y coordinates to the associated processor.
Measuring touch pressure (Z) can also be done with the TSC2301. To determine pen or finger touch, thepressure of the touch needs to be determined. Generally, it is not necessary to have very high performance forthis test, therefore, the 8-bit resolution mode is recommended (however, calculations are shown with the 12-bitresolution mode). There are several different ways of performing this measurement. The TSC2301 supports twomethods. The first method requires knowing the X-plate resistance, measurement of the X-position, and twoadditional cross panel measurements (Z2 and Z1) of the touch screen (see Figure 46 ). Using Equation 1calculates the touch resistance:
The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-position andY-position, and Z
1
. Using Equation 2 also calculates the touch resistance:
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RTOUCH RX–plate X–position
4096 4096
Z11RY–plate1Y–position
4096
(2)
Z2–Position
Touch
X+
X–
Y+
Y–
X-Position
Touch
Measure X-Position
Measure Z1-Position X+
X–
Z-Position
Touch
Y+
Y–
X+
X–
Y+
Y– Measure Z2-Position
A/D CONVERTER
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Figure 46. Pressure Measurement
When the touch panel is pressed or touched, and the drivers to the panel are turned on, the voltage across thetouch panel often overshoots and then slowly settles (decay) down to a stable dc value. This is due tomechanical bouncing, which is caused by vibration of the top layer sheet of the touch panel when the panel ispressed. This settling time must be accounted for, or else the converted value is in error. Therefore, a delay mustbe introduced between the time the driver for a particular measurement is turned on, and the time measurementis made.
In some applications, external capacitors may be required across the touch screen for filtering noise picked up bythe touch screen, i.e. noise generated by the LCD panel or back-light circuitry. The value of these capacitorsprovides a low-pass filter to reduce the noise, but causes an additional settling time requirement when the panelis touched.
Several solutions to this problem are available in the TSC2301. A programmable delay time is available whichsets the delay between turning the drivers on and making a conversion. This is referred to as the panel voltagestabilization time, and is used in some of the modes available in the TSC2301. In other modes, the TSC2301 canbe commanded to turn on the drivers only without performing a conversion. Time can then be allowed before thecommand is issued to perform a conversion.
The TSC2301 touch screen interface can measure position (X,Y) and pressure (Z). Determination of thesecoordinates is possible under three different modes of the A/D converter: conversion controlled by the TSC2301,initiated by detection of a touch; conversion controlled by the TSC2301, initiated by the host responding to thePENIRQ signal; or conversion completely controlled by the host processor.
The analog inputs of the TSC2301 are shown in Figure 47 . The analog inputs (X, Y, and Z touch panelcoordinates, battery voltage monitors, chip temperature, and auxiliary inputs) are provided via a multiplexer to thesuccessive approximation register (SAR) analog-to-digital converter (ADC). The A/D architecture is based oncapacitive redistribution architecture, which inherently includes a sample/hold function.
A unique configuration of low on-resistance switches allows an unselected ADC input channel to provide powerand an accompanying pin to provide ground for driving the touch panel. By maintaining a differential input to theconverter and a differential reference input architecture, it is possible to negate errors caused by the driver switchon-resistances.
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PENIRQ +VCC VREF
TEMP1 TEMP0
Ref ON/OFF
1.25/2.5 V
Reference
+IN
–IN
+REF
–REF
Converter
2.5 kΩ
5.0 kΩ
5.0 kΩ
7.5 kΩ
Battery
on Battery
on
GND
IN2
IN1
VBAT2
VBAT1
Y–
Y+
X–
X+
0V
11...111
11...110
11...101
00...010
00...001
00...000
1 LSB
Output Code
Input Voltage - A
FS = Full-Scale Voltage = VREF
1 LSB = VREF /4096
FS - 1 LSB
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
The ADC is controlled by an ADC control register. Several modes of operation are possible, depending upon thebits set in the control register. Channel selection, scan operation, averaging, resolution, and conversion rate mayall be programmed through this register. These modes are outlined in the sections below for each type of analoginput. The results of conversions made are stored in the appropriate result register.
Figure 47. Simplified Diagram of the Touch Screen Analog Input Section
Data Format
The TSC2301 output data is in straight binary format as shown in Figure 48 . This figure shows the ideal outputcode for the given input voltage and does not include the effects of offset, gain, or noise.
Figure 48. Ideal Input Voltages and Output Codes
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Reference
The TSC2301 has an internal voltage reference that can be set to 1.2 V or 2.5 V, through the reference controlregister. This reference can also be set to automatically power down between conversions to save power, orremain on to reduce settling time.
The internal reference voltage is only used in the single-ended mode for battery monitoring, temperaturemeasurement, and for utilizing the auxiliary inputs. Optimal touch screen performance is achieved when using aratiometric conversion, thus all touch screen measurements are done automatically in the differential mode.
An external reference can also be applied to the VREFIN pin, and the internal reference can be turned off.
Variable Resolution
The TSC2301 provides three different resolutions for the ADC: 8, 10, or 12 bits. Lower resolutions are oftenpractical for measurements such as touch pressure. Performing the conversions at lower resolution reduces theamount of time it takes for the ADC to complete its conversion process, which lowers power consumption.
Conversion Clock and Conversion Time
The TSC2301 contains an internal 8-MHz clock, which is used to drive the state machines inside the device thatperform the many functions of the part. This clock is divided down to generate the actual ADC conversion clock.The division ratio for this clock is set in the ADC control register. The ability to change the conversion clock rateallows the user to choose the optimal value for resolution, speed, and power. If the 8-MHz clock is used directly,the ADC is limited to 8-bit resolution; using higher resolutions at this speed does not result in accurateconversions. Using a 4-MHz conversion clock is suitable for 10-bit resolution; 12-bit resolution requires that theconversion clock run at 1 or 2 MHz.
Regardless of the conversion clock speed, the internal clock runs nominally at 8 MHz. The conversion time of theTSC2301 is dependent upon several functions. While the conversion clock speed plays an important role in thetime it takes for a conversion to complete, a certain number of internal clock cycles is needed for propersampling of the signal. Moreover, additional times, such as the panel voltage stabilization time, can addsignificantly to the time it takes to perform a conversion. Conversion time can vary depending upon the mode inwhich the TSC2301 is used. Throughout this data sheet, internal and conversion clock cycles are used todescribe the times that many functions take. In considering the total system design, these times must be takeninto account by the user.
Touch Detect
The pen interrupt ( PENIRQ) output function is detailed in Figure 49 . While in the touch screen monitoring mode,the Y- driver is ON and connected to GND, the X+ input is connected through a pullup resistor to V
DD
, and thePENIRQ output reflects the state of the X+ input. When the panel is touched, the X+ input is pulled to groundthrough the touch screen and PENIRQ output goes LOW due to the current path through the panel to GND,initiating an interrupt to the processor. During the measurement cycles for X- and Y-position, the X+ input isdisconnected from PENIRQ to eliminate any leakage current from the pullup resistor that might flow through thetouch screen, thus causing no errors.
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High Except
When TEMP1,
TEMP2 Activated
Internal
50 k
VDD
PENIRQ
VDD
TEMP1 TEMP2
TEMP DIODE
Y+ or X+ Drivers on,
or TEMP1, TEMP2
Measurements Activated
Y+
X+
Y– ON
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Figure 49. PENIRQ Functional Block Diagram
In modes where the TSC2301 needs to detect if the screen is still touched (for example, when doing aPENIRQ-initiated X, Y, and Z conversion), the TSC2301 must reconnect the drivers so that the 50-k Ωresistor isconnected again. Because of the high value of this pullup resistor, any capacitance on the touch screen inputscause a long delay time, and may prevent the detection from occurring correctly. To prevent this, the TSC2301has a circuit which allows any screen capacitance to be precharged through a low-resistance connection to VDD,so that the pullup resistor doesn't have to be the only source for the charging current. The time allowed for thisprecharge, as well as the time needed to sense if the screen is still touched, can be set in the configurationcontrol register. All other drivers (X-,Y+, Y-) are off during precharging.
This does point out, however, the need to use the minimum capacitor values possible on the touch screen inputs.These capacitors may be needed to reduce noise, but too large a value increases the needed precharge andsense times, as well as panel voltage stabilization time.
In self-controlled modes where the TSC2301 automatically performs conversions when it detects a pen touch, itis generally not necessary for the host processor to monitor PENIRQ. Instead, the host must monitor DAV, whichgoes low when data is available in the appropriate data register, and returns high when all new data has beenread back by the host.
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DIGITAL INTERFACE
TSC2301 Communication Protocol
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
The TSC2301 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serialcommunication between a host processor (the master) and peripheral devices (slaves). The SPI mastergenerates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to startand synchronize transmissions.
A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on theslave MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte shiftsout on the MISO pin to the master shift register.
When the POL pin of the TSC2301 is tied high (POL=1), the idle state of the serial clock for the TSC2301 is low,which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). When thePOL pin of the TSC2301 is tied low (POL=0), the idle state of the serial clock is high, which corresponds to aclock polarity setting of 1 (typical microprocessor SPI control bit CPOL = 1). The TSC2301 interface is designedso that with a clock phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master beginsdriving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SS pin canremain low between transmissions; however, the TSC2301 only interprets the first 16 bits transmitted after thefalling edge of SS as a command word, and the next 16 bits as a data word only if writing to a register. Reservedregister bits should be written to their default values (see Table 4 ).
The TSC2301 is entirely controlled by registers. Reading and writing these registers is accomplished by the useof a 16-bit command, which is sent prior to the data for that register. The command is constructed as shown inTable 2 .
The command word begins with an R/W bit, which specifies the direction of data flow on the serial bus. Thefollowing 4 bits specify the page of memory this command is directed to, as shown in Table 1 . The next six bitsspecify the register address on that page of memory to which the data is directed. The last five bits are reservedfor future use.
Table 1. Page Addressing
PG3 PG2 PG1 PG0 Page Addressed
0 0 0 0 00 0 0 1 10 0 1 0 20 0 1 1 reserved0 1 0 0 reserved0 1 0 1 reserved0 1 1 0 reserved0 1 1 1 reserved1 0 0 0 reserved1 0 0 1 reserved1 0 1 0 reserved1 0 1 1 reserved1 1 0 0 reserved1 1 0 1 reserved1 1 1 0 reserved1 1 1 1 reserved
To read all the first page of memory, for example, the host processor must send the TSC2301 the command0x8000 - this specifies a read operation beginning at page 0, address 0. The processor can then start clockingdata out of the TSC2301. The TSC2301 automatically increments its address pointer to the end of the page; ifthe host processor continues clocking data out past the end of a page, the TSC2301 simply sends back thevalue 0xFFFF.
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Continuous writing is generally not recommended for the control registers, but for the coefficients of bass-boostfilter coefficient registers, continuous writing works. Writing to these registers consists of the processor writing thecommand 0x10E0, which specifies a write operation, with PG1 set to 1, and the ADDR bits set to 07h. Thisresults in the address pointer pointing at the location of the first bass-boost coefficient in memory see Table 3(Page 2). See the section on the TSC2301 memory map for details of register locations
Table 2. TSC2301 Command WordBit SBBit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0M LS
B
R/ P P P P AD AD AD AD AD AD X X X X XW* G3 G2 G1 G0 DR DR DR DR DR DR543210
Figure 50 shows an example of a complete data transaction between the host processor and the TSC2301.
Figure 50. Write and Read Operation of TSC2301 Interface, POL = 1
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TSC2301 MEMORY MAP
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
The TSC2301 has several 16-bit registers that allow control of the device as well as providing a location forresults from the TSC2301 to be stored until read by the host microprocessor. These registers are separated intothree pages of memory in the TSC2301: a data page (Page 0), a control page (Page 1), and an audio controlpage (Page 2). The memory map is shown in Table 3 .
Table 3. TSC2301 Memory Map
Page 0: Data Registers Page 1: Control Registers Page 2: AudioControl Registers
Addr Register Addr Register Addr Register
00 X 00 ADC 00 Audio control01 Y 01 KEY 01 ADC volume control02 Z1 02 DACCTL 02 DAC volume control03 Z2 03 REF 03 Analog audio bypass volume control04 KPData 04 RESET 04 Keyclick control05 BAT1 05 CONFIG 05 Audio power/ crystal oscillator control06 BAT2 06 CONFIG2 06 GPIO control07 AUX1 07 reserved 07 DAC bass-boost filter coefficients08 AUX2 08 reserved 08 DAC bass-boost filter coefficients09 TEMP1 09 reserved 09 DAC bass-boost filter coefficients0A TEMP2 0A reserved 0A DAC bass-boost filter coefficients0B DAC 0B reserved 0B DAC bass-boost filter coefficients0C reserved 0C reserved 0C DAC bass-boost filter coefficients0D reserved 0D reserved 0D DAC bass-boost filter coefficients0E reserved 0E reserved 0E DAC bass-boost filter coefficients0F reserved 0F reserved 0F DAC bass-boost filter coefficients10 reserved 10 KPMask 10 DAC bass-boost filter coefficients11 reserved 11 reserved 11 DAC bass-boost filter coefficients12 reserved 12 reserved 12 DAC bass-boost filter coefficients13 reserved 13 reserved 13 DAC bass-boost filter coefficients14 reserved 14 reserved 14 DAC bass-boost filter coefficients15 reserved 15 reserved 15 DAC bass-boost filter coefficients16 reserved 16 reserved 16 DAC bass-boost filter coefficients17 reserved 17 reserved 17 DAC bass-boost filter coefficients18 reserved 18 reserved 18 DAC bass-boost filter coefficients19 reserved 19 reserved 19 DAC bass-boost filter coefficients1A reserved 1A reserved 1A DAC bass-boost filter coefficients1B reserved 1B reserved 1B reserved1C reserved 1C reserved 1C reserved1D reserved 1D reserved 1D reserved1E reserved 1E reserved 1E reserved1F reserved 1F reserved 1F reserved
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TSC2301 REGISTER OVERVIEW
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Table 4. Register Summary for TSC2301PAGE ADDR REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET(HEX) NAME VALUE
(HEX)
0 00 X 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 01 Y 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 02 Z1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 03 Z2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 04 KPDATA K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K0 0000
0 05 BAT1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 06 BAT2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 07 AUX1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 08 AUX2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 09 TEMP1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 0A TEMP2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 0B DAC 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0080
0 0C reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 0D reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 0E reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 0F reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 10 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 11 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 12 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 13 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 14 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 15 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 16 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 17 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 18 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 19 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1A reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1B reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1C reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1D reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1E reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1F reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 00 ADC PSM STS AD3 AD2 AD1 AD0 RS1 RS0 AV1 AV0 CL1 CL0 PV2 PV1 PV0 0 4000
1 01 KEY STC SCS DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 4000
1 02 DACCTL DPD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000
1 03 REF 0 0 0 0 0 0 0 0 0 0 0 INT DL1 DL0 PDN RFV 0002
1 04 RESET 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 FFFF
1 05 CONFIG 1 1 1 1 1 1 1 1 1 1 PR2 PR1 PR0 SN2 SN1 SN0 FFC0
1 06 CONFIG2 SDA/ KBC PLL PCT PDC PDC PDC PDC A3 A2 A1 A0 N3 N2 N1 N0 FFFFV/KB 0 O E 3 2 1 0C1
1 07 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 08 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 09 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 0A reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 0B reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 0C reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 0D reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 0E reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Table 4. Register Summary for TSC2301 (continued)PAGE ADDR REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET(HEX) NAME VALUE
(HEX)
1 0F reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 10 KPMASK M15 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 0000
1 11 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 12 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 13 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 14 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 15 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 16 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 17 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 18 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 19 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1A reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1B reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1C reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1D reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1E reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1F reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
2 00 AUDCNTL HPF HPF INML INML INM INM MIC MIC MCL MCL I2SF I2SF I2SF I2SF I2SF I2SF C0031 0 1 0 R1 R0 G1 G0 K1 K0 S3 S2 S1 S0 M1 M0
2 01 ADCVOL ADM ADV ADV ADV ADV ADV ADV ADV ADM ADV ADV ADV ADV ADV ADV ADV D7D7UL L6 L5 L4 L3 L2 L1 L0 UR R6 R5 R4 R3 R2 R1 R0
2 02 DACVOL DAM DAV DAV DAV DAV DAV DAV DAV DAM DAV DAV DAV DAV DAV DAV DAV FFFFUL L6 L5 L4 L3 L2 L1 L0 UR R6 R5 R4 R3 R2 R1 R0
2 03 BPVOL BPM BPV BPV BPV BPV BPV BPV BPV BPM BPV BPV BPV BPV BPV BPV BPV E7E7UL L6 L5 L4 L3 L2 L1 L0 UR R6 R5 R4 R3 R2 R1 R0
2 04 KEYCLICK KEY KCA KCA KCA 0 KCF KCF KCF KCL KCL KCL KCL 0 MON SSR SST 4411ST M2 M1 M0 R2 R1 R0 N3 N2 N1 N0 S TE EP
2 05 PD/MISC APD AVP ABP HAP MOP DAP ADP ADP PDS MIBP OSC BCK SMP OTS BAS DEE FFC4D D D D D DL DR TS D C C D YN S MP
2 06 GPIO 0 0 IO5 IO4 IO3 IO2 IO1 IO0 0 0 GPI GPI GPI GPI GPI GPI 0000O5 O4 O3 O2 O1 O0
2 07 BBCFN0L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 6BE2
2 08 BBCFN1L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 9667
2 09 BBCFN2L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 675D
2 0A BBCFN3L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 6BE2
2 0B BBCFN4L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 9667
2 0C BBCFN5L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 675D
2 0D BBCFD1L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 7D82
2 0E BBCFD2L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 84EF
2 0F BBCFD4L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 7D82
2 10 BBCFD5L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 84EF
2 11 BBCFN0R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 6BE2
2 12 BBCFN1R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 9667
2 13 BBCFN2R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 675D
2 14 BBCFN3R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 6BE2
2 15 BBCFN4R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 9667
2 16 BBCFN5R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 675D
2 17 BBCFD1R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 7D82
2 18 BBCFD2R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 84EF
2 19 BBCFD4R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 7D82
2 1A BBCFD5R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 84EF
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Table 4. Register Summary for TSC2301 (continued)PAGE ADDR REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET(HEX) NAME VALUE
(HEX)
2 1B ADCLKCF 0 0 0 0 0 1 0 0 0 0 0 0 PLP COM 0 0 0400G N K
2 1C reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
2 1D reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
2 1E reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
2 1F reserved 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4000
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TSC2301 TOUCH SCREEN CONTROL REGISTERS
TSC2301 ADC Control Register (Page 1, Address 00H)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
This section describes each of the registers shown in the memory map of Figure 54 . The registers are groupedaccording to the function they control. In the TSC2301, bits in control registers can refer to slightly differentfunctions depending upon whether you are reading the register or writing to it. A summary of all registers and bitlocations is shown in Table 4 .
The ADC in the TSC2301 is shared between all the different functions. A control register determines which inputis selected, as well as other options. The result of the conversion is placed in one of the result registers in Page0 of memory, depending upon the function selected.
The ADC control register controls several aspects of the ADC. The register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
PSM STS AD3 AD2 AD1 AD0 RS1 RS0 AV1 AV0 CL1 CL0 PV2 PV1 PV0 X
Bit 15 — PSM
Pen Status/Control Mode. Reading this bit allows the host to determine if the screen is touched. Writing to this bitdetermines the mode used to read coordinates: host controlled or under control of the TSC2301 responding to ascreen touch. When reading, the PENSTS bit indicates if the pen is down or not. When writing to this register,this bit determines if the TSC2301 controls the reading of coordinates, or if the coordinate conversions arehost-controlled. The default state is host-controlled conversions (0).
Table 5. PSM Bit Operation
PSM
Read/Write Value Description
Read 0 No screen touch detected (default)Read 1 Screen touch detectedWrite 0 Conversions controlled by hostWrite 1 Conversions controlled by TSC2301
Bit 14 — STS
ADC Status. Reading this bit indicates if the converter is busy. Writing a 0 to this bit causes the touch screenscans to continue until either the pen is lifted or the process is stopped. Continuous scans or conversions can bestopped by writing a 1 to this bit. This immediately halts a conversion (even if the pen is still down) and causesthe ADC to power down. The default state is continuous conversions, but if this bit is read after a reset orpower-up, it reads 1.
Table 6. STS Bit Operation
STS
Read/Write Value Description
Read 0 Converter is busyRead 1 Converter is not busy (default)Write 0 Normal operationWrite 1 Stop conversion and power down
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Bits [13:10] — AD3 - AD0
ADC Function Select bits. These bits control which input is to be converted, and what mode the converter isplaced in. These bits are the same whether reading or writing. See Table 7 for a complete listing of how thesebits are used.
Table 7. ADC Function Select
A/D3 A/D2 A/D1 A/D0 Function
0 0 0 0 Invalid. No registers are updated. This is the default state after a reset.0 0 0 1 Touch screen scan function: X and Y coordinates converted and the results returned to X and Y dataregisters. Scan continues until either the pen is lifted or a stop bit is sent.0 0 1 0 Touch screen scan function: X, Y, Z1 and Z2 coordinates converted and the results returned to X, Y, Z1 andZ2 data registers. Scan continues until either the pen is lifted or a stop bit is sent.0 0 1 1 Touch screen scan function: X coordinate converted and the results returned to X data register.0 1 0 0 Touch screen scan function: Y coordinate converted and the results returned to Y data register.0 1 0 1 Touch screen scan function: Z1 and Z2 coordinates converted and the results returned to Z1 and Z2 dataregisters.0 1 1 0 Battery input 1 converted and the results returned to the BAT1 data register.0 1 1 1 Battery input 2 converted and the results returned to the BAT2 data register.1 0 0 0 Auxiliary input 1 converted and the results returned to the AUX1 data register.1 0 0 1 Auxiliary input 2 converted and the results returned to the AUX2 data register.1 0 1 0 A temperature measurement is made and the results returned to the temperature measurement 1 dataregister.1 0 1 1 Port scan function: Battery input 1, Battery input 2, Auxiliary input 1, and Auxiliary input 2 measurements aremade and the results returned to the appropriate data registers1 1 0 0 A differential temperature measurement is made and the results returned to the temperature measurement 2data register.1 1 0 1 Turn on X+, X- drivers1 1 1 0 Turn on Y+, Y- drivers1 1 1 1 Turn on Y+, X- drivers
Bits[9:8] — RS1, RS0
Resolution Control. The ADC resolution is specified with these bits. SeeTable 8 for a description of these bits.These bits are the same whether reading or writing.
Table 8. ADC Resolution Control
RS1 RS0 Function
0 0 12-bit resolution. Power up and reset default.0 1 8-bit resolution1 0 10-bit resolution1 1 12-bit resolution
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DAC Control Register (Page 1, Address 02H)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Bits[7:6] — AV1, AV0
Converter Averaging Control. These two bits (see Table 9 ) allow you to specify the number of averages theconverter performs. Note that when averaging is used, the STS/STP bit and the DAV output indicates that theconverter is busy until all conversions necessary for the averaging are complete. The default state for these bitsis 00, selecting no averaging. These bits are the same whether reading or writing.
Table 9. ADC Conversion Averaging Control
AV1 AV0 Function
0 0 None (one conversion) (default)0 1 4 data averages1 0 8 data averages1 1 16 data averages
Bits[5:4] — CL1, CL0
Conversion Clock Control. These two bits specify the internal clock rate which the ADC uses when performing aconversion. See Table 10 . These bits are the same whether reading or writing.
Table 10. ADC Conversion Clock Control
CL1 CL0 Function
0 0 8-MHz internal clock rate - 8-bit resolution only(default)0 1 4-MHz internal clock rate - 8- or 10-bit resolutiononly1 0 2-MHz internal clock rate1 1 1-MHz internal clock rate
Bits [3:1] — PV2 - PV0
Panel Voltage Stabilization Time Control. These bits allow the user to specify a delay time from when a driver isturned on to the time sampling begins and a conversion is started. In self-controlled mode, when a pen touch isdetected, the part first turns on a driver, waits a programmed delay time set by PV2-PV0, and then beginssampling and A/D conversion. See Table 11 for settings of these bits. The default state is 000, indicating a 0 µsstabilization time. These bits are the same whether reading or writing.
Table 11. Panel Voltage Stabilization Time Control
PV2 PV1 PV0 Stabilization Time
0 0 0 0 µs (default)0 0 1 100 µs0 1 0 500 µs0 1 1 1 ms1 0 0 5 ms1 0 1 10 ms1 1 0 50 ms1 1 1 100 ms
Bit 0
This bit is reserved. When read, it always reads as a zero.
The single bit in this register controls the power down control of the onboard digital-to-analog converter (DAC).This register is formatted as follows:
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Reference Register (Page 1, Address 03H)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
DPD XXXXXXXXXXXXXXX
Bit 15 — DPD
DAC Power Down. This bit controls whether the DAC is powered up and operational, or powered down. If theDAC is powered down, the AOUT pin neither sinks nor sources current.
Table 12. DPD Bit Operation
DPD
Value Description
0 DAC is powered and operational1 DAC is powered down. (default)
This register controls whether the TSC2301 uses an internal or external reference, and if the internal reference isused, the value of the reference voltage, whether it powers down between conversions and the programmablesettling time after reference power-up. This register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSBMSB 11
X X X X X X X X X X X INT DL1 DL0 PDN RFV
Bit 4 —INT
Internal Reference Mode. If this bit is written to a 1, the TSC2301 uses its internal reference; if this bit is a 0, thepart assumes an external reference is being supplied. The default state for this bit is to select an externalreference (0). This bit is the same whether reading or writing.
Table 13. INT Bit Operation
INT
Value Description
0 External reference selected (default)1 Internal reference selected
Bits [3:2] — DL1, DL0
Reference Power-Up Delay. When the internal reference is powered up, a finite amount of time is required forthe reference to settle. If measurements are made before the reference has settled, these measurements are inerror. These bits allow for a delay time for measurements to be made after the reference powers up, therebyassuring that the reference has settled. Longer delays are necessary depending upon the capacitance present atthe VREFIN pin (see Typical Curves). The delays are shown in Table 14 . The default state for these bits is 00,selecting a 0 microsecond delay. These bits are the same whether reading or writing.
Table 14. Reference Power-Up Delay Settings.
DL1 DL0 DELAY TIME
0 0 0us (default)0 1 100 µs1 0 500 µs1 1 1000 µs
Bit 1 —PDN
Reference Power Down. If a 1 is written to this bit, the internal reference are powered down betweenconversions. If this bit is a zero, the internal reference is powered at all times. The default state is to power downthe internal reference, so this bit will be a 1. This bit is the same whether reading or writing.
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TSC2301 Configuration Control Register (Page 1, Address 05H)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Table 15. PDN Bit Operation
PDN
Value Description
0 Internal reference is powered at all times1 Internal reference is powered down between conversions.(default)
Note that the PDN bit, in concert with the INT bit, creates a few possibilities for reference behavior. These aredetailed in Table 16 .
Table 16. Reference Behavior Possibilities
INT PDN Reference Behavior
0 0 External reference used, internal reference powereddown.0 1 External reference used, internal reference powereddown.1 0 Internal reference used, always powered up1 1 Internal reference used, powers up during conversionsand then powers down.
Bit 0 — RFV
Reference Voltage Control. This bit selects the internal reference voltage, either 1.2 V or 2.5 V. The default valueis 1.2 V. This bit is the same whether reading or writing.
Table 17. RFV Bit Operation
RFV
Value Description
0 1.2-V reference voltage (default)1 2.5-V reference voltage
This control register controls the configuration of the precharge and sense times for the touch detect circuit. Theregister is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
RES RES RES RES RES RES RES RES RES RES PRE2 PRE1 PRE0 SNS2 SNS1 SNS0
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Bits [5:3] — PRE[2:0]
Precharge time selection bits. These bits set the amount of time allowed for precharging any pin capacitance onthe touch screen prior to sensing if the screen is being touched.
Table 18. Precharge Times
PRE[2:0]
PRE2 PRE1 PRE0 Time
0 0 0 20 µs (default)0 0 1 84 µs0 1 0 276 µs0 1 1 340 µs1 0 0 1.044 ms1 0 1 1.108 ms1 1 0 1.300 ms1 1 1 1.364 ms
Bits [2:0] — SNS[2:0]
Sense time selection bits. These bits set the amount of time the TSC2301 waits to sense a screen touchbetween coordinate axis conversions in self-controlled mode.
Table 19. Sense Times
SNS[2:0]
SNS2 SNS1 SNS0 Time
0 0 0 32 µs (default)0 0 1 96 µs0 1 0 544 µs0 1 1 608 µs1 0 0 2.080 ms1 0 1 2.144 ms1 1 0 2.592 ms1 1 1 2.656 ms
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TSC2301 KEYPAD REGISTERS
Keypad Control Register (Page 1, Address 01H)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
The keypad scanner hardware in the TSC2301 is controlled by two registers: the keypad control register and thekeypad mask register. The keypad control register controls general keypad functions such as scanning andde-bouncing, while the keypad mask register allows you to mask certain keys from being detected at all.
The Keypad Control register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
STC SCS DB2 DB1 DB0 X X X X X X X X X X X
Bit 15 — STC
Keypad Status. This bit reflects the operation of the KBIRQ pin, with inverted logic. This bit goes high when a keyis pressed and debounced. The default value for this bit is 0.
Table 20. STC Bit Operation
STC
Value Description
0 No keys are pressed (default)1 Key pressed and debounced
Bit 14 — SCS
Keypad Scan Status. When reading, this bit indicates if the scanner or de-bouncer is busy. Writing a 0 to this bitcauses keypad scans to continue until either the key is lifted or the process is stopped. Continuous scans can bestopped by writing a 1 to this bit. This immediately halts a conversion (even if a key is still down). The defaultvalue for this bit when read is 1.
Table 21. SCS Bit Operation
SCS
Read/Write Value Description
Read 0 Scanner or de-bouncer busyRead 1 Scanner not busy (default)Write 0 Normal operationWrite 1 Stop scans
Bits [13:11] — KBDB2-KBDB0
Keypad De-bounce Control. These bits set the length of the de-bounce time for the keypad, as shown inTable 22 . The default setting is a 2-ms de-bounce time (000).
Table 22. Keypad De-Bounce Control
KBDB2 KBDB1 KBDB0 Function
0 0 0 De-bounce: 2 ms (default)0 0 1 De-bounce: 10 ms0 1 0 De-bounce: 20 ms0 1 1 De-bounce: 50 ms1 0 0 De-bounce: 60 ms1 0 1 De-bounce: 80 ms1 1 0 De-bounce: 100 ms1 1 1 De-bounce: 120 ms
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Keypad Mask Register (Page 1, Address 10H)
Secondary Configuration Register (Page 1, Address 06H):
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
The Keypad Mask register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
M15 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
This is the same format as used in the keypad data register (Page 0, Address 04H). Each bit in these registersrepresents one key on the keypad. In the mask register, if a bit is set (1), then that key is not detected in keypadscans. Pressing that key on the keypad also does not cause a KBIRQ, if the bit is set. If the bit is cleared (0), thecorresponding key is detected when pressed. A 16-key keypad is mapped into the keypad mask (and keypaddata) register as shown in Table 23 . The default value for this register is 0000H, detecting all key presses.
Table 23. Keypad to Key Bit Mapping
C1 C2 C3 C4
R1 K0 K1 K2 K3
R2 K4 K5 K6 K7
R3 K8 K9 K10 K11
R4 K12 K13 K14 K15
The result of a keypad scan appears in the keypad data register. Each bit is set in this register, corresponding tothe key(s) actually pressed. For example, if only key 1 was pressed on a particular scan, the data in the registerwould read as 0x0002; however, if keys 6, 8, and 13 were all pressed simultaneously on that scan, the datawould read as 0x2140.
Multiple keys can be pressed simultaneously and are generally decoded correctly by the keypad scan circuitry.However, keys that land on three corners of a rectangle can cause a false reading of a key on the fourth cornerof the rectangle. For example, if keys 0, 3, and 11 were pressed simultaneously, the KEY0, KEY3, and KEY11bits are set, but the KEY8 bit is also set. Thus, when considering using multiple-key combinations in anapplication, try to avoid combinations that put three keys on the corners of a rectangle.
This register allows the user to read the status of the DAV pin through the SPI interface. It controls the behaviorof the KBIRQ signal, as well as provides control of the audio codec PLL.Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
SDAV/K KBC0 PLLO PCTE PDC3 PDC2 PDC1 PDC0 A3 A2 A1 A0 N3 N2 N1 N0BC1
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Bit 13 — PLLO
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Bit 15 — SDAV (write only)
SPI Data Available. This read-only bit mirrors the function of the DAV pin. This bit is provided so that the hostprocessor can poll the SPI interface to see whether data is available, without dedicating a GPIO pin from the hostprocessor to the TSC2301 DAV pin. This bit is normally high, goes low when touch screen or keypad data isavailable, and is reset high when all the new data has been read. When written to, this bit becomes KBC1,operation detailed below.
Table 24. SPI Data Available (Read Only)
SDAV Description
0 Touchscreen data is available.1 No new data available (default)
Bits [15:14] — KBC1-KBC0 (write mode)
KBIRQ Control (write-only mode). These bits control the behavior of the KBIRQ signal. There are four possibleways to de-assert the KBIRQ signal once it goes low. These bits control which particular events cause theKBIRQ signal to be de-asserted (go high). The four de-assertion possibilities are:A. Hardware or software reset. Hardware reset—RESET pin asserted (high) and subsequently de-asserted.Software reset—writing BB00h to register 04h, page 1.B. Writing 1 to the SCS bit. Bit 14 of register 01h, page 1C. Releasing the pressed key on the keypad.D. Reading the keypad data register (register 04h, page0).
Refer to the table below to see which settings of the KBC1 - KBC0 correspond to the KBIRQ reset events. Whenread, KBC1 becomes SDAV operation detailed above. KBC0 operates the same as in read and write modes.
Table 25. KBIRQ Behavior Possibilities
KBC1 KBC0 KBIRQ Reset Event
0 0 De-assertion possibility A or B or C.0 1 De-assertion possibility A or B.1 0 De-assertion possibility A or B or C or D.1 1 De-assertion possibility A or B or D (default).
PLL Output on GPIO_0. This bit allows the user to receive the output of the audio codec internal PLL. This bit isprovided so the host processor can use the output of the PLL, to generate its I
2
S signals in sync with an externalMCLK or crystal oscillator. Writing a 0 to this bit connects the output of the PLL to the GPIO_0 pin. Otherwise,the GPIO_0 pin operates as normal.
Table 26. PLL Output
PLLO Description
0 Output PLL on GPIO_0.1 GPIO_0 operates as normal (default).
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Bit 12 — PCTE
Bit [11:8] — PDC3 - PDC0
Bit [7:4] — A3 - A0
Bit [3:0] — N3 - N0
FOUT MCLK
P(4N A)
3,(N A),MCLK
P1MHz
(3)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
PLL Control Enable. This bit allows the user to manually control the audio codec internal PLL. This allows theuser to modify the contents of bits [11-0] to control the audio codec PLL. Writing a 0 to this bit enables manualcontrol of the PLL. Otherwise, the PLL is set automatically based on the settings of MCLK [1:0] and I2SFS[3:0] inthe audio control register (bits 7-2 in register 00h, page 2).
Table 27. PLL Control Enable
PLLO Description
0 Allows modification of bits [11:0].1 PLL operates as normal, no manual override (default).
PLL Predivider Control. This bit controls the predivider to the internal PLL. These bits represent a 4-bit straightbinary number corresponding to the variable P in the PLL control equation discussed later in this section. Thelegal range of these bits is 1h to Fh. The default of these bits is Fh.
AControl. This bit represent a 4-bit straight binary number corresponding to the variable A in the PLL controlequation discussed later in this section. The legal range of these bits is 0h to Fh. The default of these bits is Fh.
NControl. This bit represents a 4-bit straight binary number corresponding to the variable N in the PLL controlequation discussed later in this section. The legal range of these bits is 0h to Fh. The default of these bits is Fh.
When using a nonaudio standard MCLK frequency or crystal that is not covered by any of the automatic PLLsettings in MCLK[1:0], the user must manually configure the TSC2301 PLL to generate the proper clock for theaudio data converters. The proper clock for any sampling rates that are submultiples of 44.1 kHz is 512 x 44.1kHz = 22.5792 MHz. This frequency is valid for 44.1 kHz, 22.05 kHz, and 11.025 kHz. The proper clock for anysampling rates that are submultiples of 48 kHz is 512 x 48 kHz = 24.576 MHz. This frequency is valid for 48 kHz,32 kHz, 24 kHz, 16 kHz, 12 kHz, and 8 kHz. Equation 3 is used to obtain the proper frequency. Since variablesP, N, and Aare integers, the exact proper clock frequencies can not always be obtained. However, examples areprovided for common MCLK/crystal frequencies that minimize the error of the PLL output. One constraint is the Nmust always be greater than or equal to A. Another constraint is that the output of the MCLK predivider (theMCLK/P term) should be greater than 1 MHz. Pcan be any integer from 1 to 15, inclusive. Nand Acan be anyinteger from 0 to 15, inclusive. In some situations, settings outside of these constraints may work, but should beverified by the user beforehand. Table 28 shows some settings that have been tested and confirmed to work byTI.
Table 28. PLL Settings
MCLK (MHz) Desired P A N Actual F
out
(MHz) % ErrorF
out
(MHz)
12 24.576 7 7 9 24.57143 -0.01913 24.576 9 7 11 24.55556 -0.08316 24.576 13 12 12 24.61538 0.16019.2 24.576 13 10 10 24.61538 0.16019.68 24.576 12 9 9 24.60000 0.0973.6869 22.5792 3 7 12 22.53106 -0.21312 22.5792 11 10 13 22.54545 -0.14913 22.5792 14 13 15 22.59524 0.07116 22.5792 13 11 11 22.56410 -0.06719.2 22.5792 15 9 11 22.61333 0.151
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TSC2301 DATA REGISTERS
X, Y, Z1, Z2, BAT1, BAT2, AUX1, AUX2, TEMP1, and TEMP2 REGISTERS
Keypad Data Register (Page 0, Address 04H)
DAC Data Register (Page 0, Address 0BH)
OPERATION - TOUCH SCREEN MEASUREMENTS
Conversion Controlled by TSC2301 Initiated at Touch Detect
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Table 28. PLL Settings (continued)
MCLK (MHz) Desired P A N Actual F
out
(MHz) % ErrorF
out
(MHz)
19.68 22.5792 9 3 7 22.59556 0.072
The data registers of the TSC2301 hold data results from conversions or keypad scans, or the value of the DACoutput current. All of these registers default to 0000H upon reset, except the DAC register, which is set to 0080H,representing the midscale output of the DAC.
The results of all A/D conversions are placed in the appropriate data register, as described in Table 5 andTable 3 . The data format of the result word, R, of these registers is right-justified, as follows (assuming a 12-bitconversion):
Bit 15 Bit 14 Bit Bit Bit Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB 13 12 11 LSB
0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0MSB LSB
The keypad data register (Page 0, Address 04H) is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K0
This is the same format as used in the keypad mask register (Page 1, Address 10H). Each bit in these registersrepresents one key on the keypad. A 16-key keypad is mapped into the keypad data register as shown inTable 23 .
The data to be written to the DAC is written into the DAC data register, which is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
RES RES RES RES RES RES RES RES D7 D6 D5 D4 D3 D2 D1 D0
There are three different touch screen conversion modes available in the TSC2301: self-controlled orPENIRQ-Initiated, host-initiated, and host-controlled. These three modes are described below.
In this mode, the TSC2301 detects when the touch panel is touched and causes the PENIRQ line to go low. Atthe same time, the TSC2301 powers up its internal clock. It then turns on the Y-drivers, and after a programmedpanel voltage stabilization time, powers up the ADC and convert the Y coordinate. If averaging is selected,several conversions may take place; when data averaging is complete, the Y coordinate result is stored in the Yregister.
This mode is recommended to fully utilize the integrated touch screen processing of the TSC2301 andreduce the processing overhead and number of interrupts to the host processor. In this mode, the hostprocessor does not need to monitor PENIRQ, instead the host needs only to configure the TSC2301 once atpower-up, and then monitor DAV and read back data after a falling edge on DAV.
If the screen is still touched at this time, the X-drivers are enabled, and the process repeats, but measuresinstead the X coordinate, storing the result in the X register.
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tcoordinate 2.5 s2tPVS tPRE tSNS2NAVGNBITS 1
fconv 4.4 s
(4)
tcoordinate 4.75 s3tPVS tPRE tSNS4NAVGNBITS 1
fconv 4.4 s
(5)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
If only X and Y coordinates are to be measured, then the conversion process is complete. Figure 51 shows aflowchart for this process. The time it takes to go through this process depends upon the selected resolution,internal conversion clock rate, averaging selected, panel voltage stabilization time, and precharge and sensetimes.
The time needed to get a complete X/Y coordinate reading can be calculated by:
where:
•t
coordinate
= time to complete X/Y coordinate reading;•t
PVS
= panel voltage stabilization time, as given in Table 11 ;•t
PRE
= precharge time, as given in Table 18 ;•t
SNS
= sense time, as given in Table 19 ;•N
AVG
= number of averages, as given in Table 9 ; for no averaging, NAVG = 1;•N
BITS
= number of bits of resolution, as given in Table 8 ;•f
conv
= A/D converter clock frequency, as given in Table 10 .
If the pressure of the touch is also to be measured, the process continues after the X-conversion is complete,measuring the Z1 and Z2 values, and placing them in the Z1 and Z2 registers. This process is illustrated inFigure 52 . As before, this process time depends upon the settings described above. The time for a completeX/Y/Z1/Z2 coordinate reading is given by:
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Turn On Drivers: Y+, Y-
Issue Interrupt
PENIRQ
Is PENSTS =1
Start Clock
Is Panel Voltage
Stabilization Done
Convert Y coordinates
Store Y Coordinates in Y
Register
Is Screen Touched
Turn On Drivers: X+, X-
Is Panel Voltage
Stabilization Done
Convert X coordinates
Store X Coordinates in X
Register
Set /DAV = 0
Is Screen Touched
Turn off clock
Reset PENIRQ and Scan
Trigger
Screen
Touch
Done
Go To Host Controlled
Conversion
N
Turn off clock
Reset PENIRQ and Scan
Trigger
Done
Power up ADC
Power Down ADC
Power up ADC
Power Down ADC
Is Data
Averaging
Is Data
Averaging
N
Y
Y
N
Y
N
Y
Y
N
N
Y
Y
N
Done
Done
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Touch Screen Scan X and Y PENIRQ Initiated
Figure 51. X & Y Coordinate Touch Screen Scan, Initiated by Touch
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Issue Interrupt
PENIRQ
Turn On Drivers: Y+, Y-
Is PENSTS =1
Start Clock
Is
Panel Voltage
Stabilization
Done
Convert Y
coordinates
Store Y Coordinates
in Y Register
Is Screen
Touched
Turn On Drivers: X+, X-
Is
Panel Voltage
Stabilization
Done
Convert X
coordinates
Store X Coordinates
in X Register
Is Screen
Touched
Turn off clock
Reset PENIRQ and
Scan Trigger
Screen
Touch
Done
Go To Host
Controlled
Conversion
N
Turn off clock
Reset PENIRQ and
Scan Trigger
Done
Power up ADC
Power Down ADC
Power up ADC
Power Down ADC
Is Data
Averaging
Done
Is Data
Averaging
Done
N
Y
N
Y
N
Y
Y
N
N
Y
Y
N
Turn On Drivers: Y+, X-
Is
Panel Voltage
Stabilization
Done
Convert Z1
coordinates
Store Z1 Coordinates
in Z1 Register
Set /DAV = 0
Power up ADC
Power Down ADC
Is Data
Averaging
Done
N
Y
Y
N
Convert Z2
coordinates
Store Z2 Coordinates
in Z2 Register
Is Data
Averaging
Done
N
Y
Turn off clock
Reset PENIRQ and
Scan Trigger
Done
Is Screen
Touched
Y
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Touch Screen Scan X, Y and Z PENIRQ Initiated
Figure 52. X,Y and Z Coordinate Touch Screen Scan, Initiated by Touch
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Conversion Controlled by TSC2301 Initiated By Host Responding to PENIRQ
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
This mode is provided for users who want more control over the A/D conversion process. This mode requiresmore overhead from the host processor, so it is generally not recommended.
In this mode, the TSC2301 detects when the touch panel is touched and causes the PENIRQ line to go low. Thehost recognizes the interrupt request, and then writes to the ADC control register to select one of the touchscreen scan functions (single X-, Y-, or Z-conversions, continuous X/Y or X/Y/Z1/Z2 Conversions). Theconversion process then proceeds as described above, and as outlined in Figure 53 through Figure 57 .
The main difference between this mode and the previous mode is that the host, not the TSC2301, decides whenthe touch screen scan begins after responding to a PENIRQ. In this mode, the host must either monitor bothPENIRQ and DAV, or wait a minimum time after writing to the A/D converter control register. This wait time canbe calculated from Equation 6 in the case of single conversions, or from Equation 4 or Equation 5 in the case ofmultiple conversions. The nominal conversion times calculated by these equations should be extended byapproximately 12% to account for variation in the internal oscillator frequency.
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Issue Interrupt
PENIRQ
Turn On Drivers: Y+, Y-
Is PENSTS =1
Start Clock
Is Panel Voltage
Stabilization Done
Convert Y coordinates
Store Y Coordinates in Y
Register
Is Screen Touched
Turn On Drivers: X+, X-
Is Panel Voltage
Stabilization Done
Convert X coordinates
Store X Coordinates in X
Register
Set /DAV = 0
Is Screen Touched
Turn off clock
Screen
Touch
Done
Go To Host Controlled
Conversion
N
Turn off clock
Reset PENIRQ and Scan
Trigger
Done
Power up ADC
Power Down ADC
Power up ADC
Power Down ADC
Is Data
Averaging
Done
Is Data
Averaging
Done
N
Y
N
Y
N
Y
N
N
Y
Y
N
Done
Host Writes A/D
Converter
Control Register
Reset PENIRQ
Y
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Touch Screen Scan X and Y Host Initiated
Figure 53. X and Y Coordinate Touch Screen Scan, Initiated by Host
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Turn On Drivers: Y+, Y-
Issue Interrupt
PENIRQ
Is PENSTS =1
Start Clock
Is Panel Voltage
Stabilization
Done
Convert Y
coordinates
Store Y Coordinates
in Y Register
Is Screen
Touched
Turn On Drivers: X+, X-
Is
Stabilization
Done
Convert X
coordinates
Store X Coordinates
in X Register
Is Screen
Touched
Turn off clock
Screen
Touch
Done
Go To Host
Controlled
Conversion
N
Turn off clock
Reset PENIRQ and
Scan Trigger
Done
Power up ADC
Power Down ADC
Power up ADC
Power Down ADC
Is Data
Averaging
Done
Is Data
Averaging
Done
N
Y
N
Y
N
Y
Y
N
N
Y
Y
N
Turn On Drivers: Y+, X-
Is
Panel Voltage
Stabilization
Done
Convert Z1
coordinates
Store Z1 Coordinates
in Z1 Register
Set /DAV = 0
Power up ADC
Power Down ADC
Is Data
Averaging
Done
N
Y
Y
N
Convert Z2
coordinates
Store Z2 Coordinates
in Z2 Register
Is Data
Averaging
Done
N
Y
Turn off clock
Reset PENIRQ and
Scan Trigger
Done
Is Screen
Touched
Done
Host Writes A/D
Converter
Control Register
Reset PENIRQ
Panel Voltage
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Touch Screen Scan X, Y and Z Host Initiated
Figure 54. X,Y and Z Coordinate Touch Screen Scan, Initiated by Host
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Turn On Drivers: X+, X-
Issue Interrupt
PENIRQ
Is PENSTS =1
Start Clock
Is Panel Voltage
Stabilization Done
Convert X coordinates
Store X Coordinates in X
Register
Set /DAV = 0
Turn off clock
Screen
Touch
Done
Go To Host Controlled
Conversion
N
Power up ADC
Power Down ADC
Is Data
Averaging
N
N
Y
Done
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Start Clock
Are Drivers On
Y
N
Y
Done
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Touch Screen Scan X Coordinate Host Initiated
Figure 55. X Coordinate Reading Initiated by Host
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Turn On Drivers: Y+, Y-
IssueInterrupt
PENIRQ
Is PENSTS =1
Start Clock
Is Panel Voltage
Stabilization Done
Convert Y coordinates
Store Y Coordinates in Y
Register
Set /DAV = 0
Turn off clock
Screen
Touch
Done
Go To Host Controlled
Conversion
N
Power up ADC
Power Down ADC
Is Data
Averaging Done
N
N
Done
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Start Clock
Are Drivers On
Y
N
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Touch Screen Scan Y Coordinate Host Initiated
Figure 56. Y Coordinate Reading Initiated by Host
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Issue Interrupt
PENIRQ
Is PENSTS =1
Start Clock
Turn off clock
Screen
Touch
Go To Host
Controlled
Conversion
N
Turn On Drivers: Y+, X-
Is Panel
Voltage
Stabilization
Done
Convert Z1
coordinates
Store Z1 Coordinates
in Z1 Register
Set /DAV = 0
Power up ADC
Power Down ADC
Is Data
Averaging
Done
N
Y
Y
N
Convert Z2
coordinates
Store Z2 Coordinates
in Z2 Register
Is Data
Averaging
Done
N
DONE
Y
DONE
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Are Drivers On
Start Clock
N
Conversion Controlled by the Host
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Touch Screen Scan Z Coordinate Host Initiated
Figure 57. Z Coordinate Reading Initiated by Host
In this mode, the TSC2301 detects when the touch panel is touched and causes the PENIRQ line to go low. The
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tcoordinate 2.125 stPVS NAVGNBITS 1
ƒconv 4.4 s
(6)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
host recognizes the interrupt request. Instead of starting a sequence in the TSC2301, which then reads eachcoordinate in turn, the host now must control all aspects of the conversion. An example sequence would be: (a)PENIRQ goes low when screen is touched. (b) Host writes to TSC2301 to turn on X-drivers. (c) Host waits adesired delay for panel voltage stabilization. (d) Host writes to TSC2301 to begin X-conversion. After waiting forthe settling time, the host then addresses the TSC2301 again, this time requesting an X coordinate conversion.
The process is then repeated for Y and Z coordinates. The processes are outlined in Figure 58 throughFigure 60 .
The time needed to convert any single coordinate under host control (not including the time needed to send thecommand over the SPI bus) is given by:
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Turn On Drivers: X+, X-
Issue Interrupt
PENIRQ
Is PENSTS =1
Is Panel Voltage
Stabilization Done
Convert X coordinates
Store X Coordinates in X
Register
Issue Data Available
Turn off clock
Screen
Touch
Done
Go To Host Controlled
Conversion
Power up ADC
Power Down ADC
Is Data
Averaging
N
N
Y
Done
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Done
Host Writes A/D
Converter Control
Register
Start Clock
Are Drivers On
Turn On Drivers: X+, X-
Y
N
Y
N
Start Clock
Done
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Host Controlled X Coordinate
Figure 58. X Coordinate Reading Controlled by Host
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Turn On Drivers: Y+, Y-
Issue Interrupt
PENIRQ
Is PENSTS =1
Is Panel Voltage
Stabilization Done
Conver Y coordinates
Store Y Coordinates in Y
Register
Set /DAV = 0
Turn off clock
Screen
Touch
Done
Go To Host Controlled
Conversion
Power up ADC
Power Down ADC
Is Data
Averaging
N
N
Y
Done
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Done
Host Writes A/D
Converter Control
Register
Start Clock
Are Drivers On
Y
N
Y
N
Start Clock
Turn On Drivers: Y+, Y-
Done
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Host Controlled Y Coordinate
Figure 59. Y Coordinate Reading Controlled by Host
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Start Clock
Turn off clock
N
Turn On Drivers: Y+, X-
Is Panel Voltage
Stabilization
Done
Convert Z1
coordinates
Store Z1 Coordinates
in Z1 Register
Set /DAV = 0Power up ADC
Power Down ADC
Is Data
Averaging
Done
N
Y
Y
N
Convert Z2
coordinates
Store Z2 Coordinates
in Z2 Register
Is Data
Averaging
Done
N
DONE
Y
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Are Drivers On
Start Clock
N
Y
Issue Interrupt
PENIRQ
Is PENSTS =1
Screen
Touch
Go To Host
Controlled Conversion
N
DONE
Turn On Drivers: X+, X-
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Done
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Host Controlled Z Coordinate
Figure 60. Z Coordinate Reading Controlled by Host
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OPERATION - TEMPERATURE MEASUREMENT
X+
MUX A/D
Converter
Temperature Select
TEMP1 TEMP2
°KqV
kn(N)
(7)
VVI82–VI1
(8)
°KqV
kn(N)
(9)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
In some applications, such as estimating remaining battery life or setting RAM refresh rate, a measurement ofambient temperature is required. The temperature measurement technique used in the TSC2301 relies on thecharacteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (V
BE
) hasa well-defined characteristic versus temperature. The ambient temperature can be predicted in applications byknowing the 25 °C value of the V
BE
voltage and then monitoring the delta of that voltage as the temperaturechanges.
The TSC2301 offers two modes of temperature measurement. The first mode requires calibration at a knowntemperature, but only requires a single reading to predict the ambient temperature. A diode, as shown inFigure 61 , is used during this measurement cycle. The voltage across this diode is typically 600 mV at 25 °Cwhile conducting a 20 -µA current. The absolute value of this diode voltage can vary several millivolts, but thetemperature coefficient (TC) of this voltage is very consistent at -2.1 mV/ °C. During the final test of the endproduct, the diode voltage would be measured by the TSC2301 ADC at a known room temperature, and thecorresponding digital code stored in system memory, for calibration purposes by the user. The result is anequivalent temperature measurement resolution of 0.3 °C/LSB. This measurement of what is referred to asTemperature 1 is illustrated in Figure 62 .
Figure 61. Functional Block Diagram of Temperature Measurement Mode
The second mode does not require a test temperature calibration, but uses a two-measurement (differential)method to eliminate the need for absolute temperature calibration, and achieves a 2 °C/LSB accuracy. This moderequires a second conversion with a current 82 times larger than the first 20- µA current. The voltage differencebetween the first (TEMP1) and second (Temp2) conversion, using 82 times the bias current, is represented bykT/q ln (N), where N is the current ratio = 82, k = Boltzmann's constant (1.38054 x 10
-23
electron volts/degreeKelvin), q = the electron charge (1.602189 x 10
-19
C), and T = the temperature in degrees Kelvin. This methodcan provide much improved absolute temperature measurement without calibration, with resolution of 2 °C/LSB.The resultant equation for solving for °K is:
where:
(in mV)
Temperature 2 measurement is illustrated in Figure 63 .
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Start Clock
Turn off clock
Convert Temperature
Input 1
Store Temperature
Input 1 in TEMP1
Register
Set /DAV = 0
Power up ADC
Power Down
Reference
Is Data
Averaging
Done
N
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Programmed
Delay)
Y
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Temperature Input 1
Figure 62. Single Temperature Measurement Mode
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Start Clock
Turn off clock
Convert Temperature
Input 2
Store Temperature
Input 2 in TEMP2
Register
Power up ADC
Power Down
Reference
Is Data
Averaging
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
Set /DAV = 0
OPERATION - BATTERY MEASUREMENT
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Temperature Input 2
Figure 63. Additional Temperature Measurement for Differential Temperature Reading
An added feature of the TSC2301 is the ability to monitor the battery voltage which may be much larger than thesupply voltage of the TSC2301. An example of this is shown in Figure 64 , where a battery voltage ranging up to6 V may be regulated by a dc/dc converter or low-dropout regulator to provide a lower supply voltage to theTSC2301. The battery voltage can vary from 0.5 V to 6 V while maintaining the voltage to the TSC2301 at a levelof 2.7 V-3.6 V. The input voltage on V
BAT1
is divided down by 4 so that a 6.0-V battery voltage is represented as1.5 V to the A/D, while the input voltage on V
BAT2
is divided by 2 so that 3.0-V battery voltage is represented as1.5 V to the A/D. If the battery voltage is low enough, the 1.2 V internal reference can be used to decrease LSBsize, potentially improving accuracy. The battery voltage on V
BAT1
must be below 4* V
REF
, and the voltage onV
BAT2
must be below 2* V
REF
. Due to constraints of the internal switches, the input to the A/D after the voltagedivider cannot be above 1.5 V or V
REF
, whichever is lower. In order to minimize the power consumption, thedivider is only ON during the sampling of the battery input.
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+
DC/DC
Converter 2.7 V
0.125 V to 1.5 V
VCC
7.5 k
2.5 k
Battery
0.5 V+
to 6.0 V
VBAT1 ADC
+
DC/DC
Converter 2.7 V
0.125 V to 1.5 V
VCC
5.0 k
5.0 k
Battery
0.25 V+
to 3.0 V
VBAT2 ADC
tcoordinate 2.625 stREF NAVGNBITS 1
ƒconv 4.4 s
(10)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Figure 64. VBAT Example Battery Measurement Functional Block Diagrams, VDD = 2.7 V, V
REF
= 2.5 V
Flowcharts which detail the process of making a battery input reading are shown in Figure 65 and Figure 66 .
The time needed to make temperature, auxiliary, or battery measurements is given by:
where t
REF
is the reference delay time as given in Table 14 .
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Start Clock
Turn off clock
Convert Battery Input
1
Store Battery Input 1
in BAT1 Register
Set /DAV = 0
Power up ADC
Power Down
Reference
Is Data
Averagin
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Battery Input 1
Figure 65. V
BAT1
Measurement Process
This assumes the reference control register is configured to power up the internal reference when needed.
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Start Clock
Turn off clock
Convert Battery Input
2
Store Battery Input 2
in BAT2 Register
Set /DAV = 0
Power up ADC
Power Down
Reference
Is Data
Averaging
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
OPERATION - AUXILIARY MEASUREMENT
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Battery Input 2
Figure 66. V
BAT2
Measurement Process
The two auxiliary voltage inputs can be measured in similar fashion to the battery inputs, with no voltage dividers.The input range of the auxiliary inputs is 0 V to V
REF
.Figure 67 and Figure 68 illustrate the process. Applicationsfor this feature may include external temperature sensing, ambient light monitoring for controlling an LCDback-light, or sensing the current drawn from the battery.
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Start Clock
Turn off clock
Convert Auxiliary
Input 1
Store Auxiliary Input
Set /DAV = 0
Power up ADC Power Down
Reference
Is Data
Averaging
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
1 in AUX1 Register
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Auxiliary Input 1
Figure 67. AUX1 Measurement Process
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Start Clock
Turn off clock
Convert Auxiliary
Input 2
Store Auxiliary Input
Set /DAV = 0
Power up ADC Power Down
Reference
Is Data
Averaging
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
2 in AUX2 Register
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Auxiliary Input 2
Figure 68. AUX2 Measurement Process
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OPERATION - PORT SCAN
tcoordinate 7.5 stREF 4NAVGNBITS 1
ƒconv 4.4 s
(11)
Start Clock
Turn off clock
Convert Battery Input
1
Store Battery Input 1
in BAT1 Register
Set /DAV = 0
Power up ADC
Power Down
Reference
Is Data
Averaging
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
Convert Battery Input
2
Store Battery Input 2
in BAT2 Register
Is Data
Averaging
Done
N
Y
Convert Auxiliary
Input 1
Store Auxiliary Input
in AUX1 Register
Is Data
Averaging
Done
N
Y
Convert Auxiliary
Input 2
Store Auxiliary Input
2 in AUX2 Register
Is Data
Averaging
Done
N
Y
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
If measurements of all the battery and auxiliary inputs are required, the port scan mode can be used. This modecauses the TSC2301 to sample and convert both battery inputs and both auxiliary inputs. At the end of this cycle,the battery and auxiliary data registers contain the updated values, and the DAV pin is asserted low, signalingthe host to read the data. Thus, with one write to the TSC2301, the host can cause four different measurementsto be made. Because the battery and auxiliary data registers are consecutive in memory, all four registers can beread in one SPI transaction, as described in Figure 50 .
The flowchart for this process is shown in Figure 69 . The time needed to make a complete port scan is given by:
Port Scan
Figure 69. Port Scan Mode
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OPERATION - D/A CONVERTER
RRNG
VBIAS
DAC
8-Bits
V+
ARNG
AOUT
R1
R2
TSC2301
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
The TSC2301 has an onboard 8-bit DAC, configured as shown in Figure 70 . This configuration yields a currentsink (AOUT) controlled by the value of a resistor connected between the ARNG pin and ground. The D/Aconverter has a control register, which controls whether or not the converter is powered up. The eight-bit data iswritten to the DAC through the DAC data register.
Figure 70. D/A Converter Configuration
This circuit is designed for flexibility in the output voltage at the VBIAS point shown in Figure 70 to accommodatethe widely varying requirements for LCD contrast control bias. V+ can be a higher voltage than the supplyvoltage for the TSC2301. The only restriction is that the voltage on the AOUT pin can never go above theabsolute maximum ratings for the device, and should stay above 1.5 V for linear operation.
The DAC has an output sink range which is limited to approximately 1 mA. This range can be adjusted bychanging the value of RRNG shown in Figure 70 . As this DAC is not designed to be a precision device, theactual value of the output current range can vary as much as ±20%. Furthermore, the current output changesdue to variations in temperature; the DAC has a temperature coefficient of approximately 0.9 uA/ °C.
To set the full-scale current, RRNG can be determined from the graph shown in Figure 71 .
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1
300
200
100
0
10 k 100 k 1 M 10 M 100 M
DAC Fullscale Output Current – A
400
500
RRNG Resistor Value
DAC FULLSCALE OUTPUT CURRENT
vs
RRNG RESISTOR VALUE
600
µ
1000
900
800
700
1100
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Figure 71. DAC Output Current Range vs RRNG Resistor Value
For example, consider an LCD that has a contrast control voltage VBIAS that can range from 2 V to 4 V, thatdraws 400 µA when used, and has an available 5-V supply. This is higher than the TSC2301 supply voltage, butit is within the absolute maximum ratings.
The maximum VBIAS voltage is 4 V, and this occurs when the D/A converter current is 0, so only the 400- µAload current ILOAD is flowing from 5 V to VBIAS. This means 1 V is dropped across R1, so R1 = 1 V/400 µA =2.5 k Ω.
The minimum VBIAS is 2 V, which occurs when the D/A converter current is at its full scale value, IMAX. In thiscase, 5 V - 2 V = 3 V is dropped across R1, so the current through R1 is 3 V/2.5 k Ω= 1.2 mA. This current isIMAX + ILOAD = IMAX + 400 uA, so IMAX must be set to 800 µA. Looking at Figure 73 , this means that RRNGshould be around 1 M Ω.
Since the voltage at the AOUT pin must not go below 1.5 V, this limits the voltage at the bottom of R2 to be1.5-V minimum; this occurs when the D/A converter is providing its maximum current, IMAX. In this case, IMAX+ILOAD flows through R1, and IMAX flows through R2. Thus,
R2 x IMAX + R1(IMAX + ILOAD) = 5 V - 1.5 V = 3.5 V
W R1 = 2.5 k ΩIMAX = 800 µA, ILOAD = 400 µA, thus allowing R2 to be solved as 625 Ω.
In the previous example, when the DAC current is zero, the voltage on the AOUT pin rises above the TSC2301supply voltage. This is not a problem, however, since V+ was within the absolute maximum ratings of theTSC2301, so no special precautions are necessary. Many LCD displays require voltages much higher than theabsolute maximum ratings of the TSC2301. In this case, the addition of an NPN transistor, as shown inFigure 72 , protects the AOUT pin from damage.
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R2
R1
V+
DAC
RRNG
2N3904
AOUT
ARNG
VDD
TSC2301
VBIAS
8–Bits
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Figure 72. DAC Circuit When Using V+ Higher Than V
supply
.
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OPERATION - KEYPAD INTERFACE
Issue Interrupt
KBIRQ
Start Clock
Store Keypad scan
results in KPData
Register
Keypad
Touch
Turn off clock
Reset KBIRQ and Scan
Trigger
Done
Scan and
debounce keys
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
The TSC2301 contains a keypad interface that is suitable for use with matrix keypads up to 4 x 4 keys. A controlregister, the keypad control register, is used to set the scan rate for the keypad and de-bounce times. There isalso a keypad mask register which allows certain keys to be masked from being read, or from causing theTSC2301 to detect a key-press on selected keys. The results of keypad scans are placed in the keypad dataregister.
When a column line (keypad input) is tied to logic high, pressing on all four keys connected to that column issensed. For example, if C1 is tied high, pressing on keys 0, 4, 8, and 12 is detected in the keypad data register.This capability is used to extend the keypad interface beyond 4 x 4 keypads.
When a key-press is detected by the TSC2301, it automatically scans the keypad and de-bounces the key-press.It then drives KBIRQ low. All keys pressed at the time of the scan are then reflected in the keypad data register.This mode is shown in Figure 73 .
Keypad Scan KBRIQ Initiated
Figure 73. Keypad Scan Initiated by Keypress
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AUDIO CODEC
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Audio Analog I/O
The TSC2301 has one pair of stereo inputs, LLINEIN and RLINEIN, and one mono audio input, MICIN. The partalso has one pair of stereo line outputs capable of driving a 10-k Ωload, VOUTL and VOUTR, as well as a stereoheadphone output amplifier capable of driving a 16- Ωload at up to 30 mW/channel, HPL and HPR. Finally, thepart includes a differential mono output capable of driving a 10-k Ωload per side, MONO+ and MONO-.
A special circuit has also been included for inserting a keyclick sound into the analog output signal path based onregister control. This functionality is intended for generating keyclick sounds for user feedback. This function iscontrolled by Reg 04h, Pg 2, and is available when either of the DAC or analog bypass paths are enabled.
The common-mode voltage, VCM, used by the audio section can be powered up independently by the AVPD bit(Bit 14, Reg 05h, Pg 2). Because the audio outputs are biased to this voltage, this voltage is slowly ramped upwhen powered on, and there is an internally programmed delay of approximately 500 ms between powering upthis voltage and unmuting the analog audio signals of the TSC2301, in order to avoid pops and clicks on theoutputs. It is recommended to keep VCM powered up if the 500-ms delay is not tolerable.
Audio Digital I/O
Digital audio data samples can be transmitted between the TSC2301 and the CPU via the I
2
S bus (BCLK,LRCLK, I2SDIN, I2SDOUT). However, all registers, including those pertaining to audio functionality, are onlyaccessible via the SPI bus. The I
2
S bus operates only in slave mode, meaning the BCLK and LRCLK must beprovided as inputs to the part. Four programmable modes for this serial bus are supported and can be setthrough the I2SFM bits (Bits[1:0], Reg 00h, Pg 2) .
PCM Audio Interface
The 4-wire digital audio interface for TSC2301 is comprised of BCLK (pin 24), LRCLK (pin 25), I2SDIN (pin 26),and I2SDOUT (pin 27). For the TSC2301, these formats are selected through the I2SFM bits in Reg 00h, Pg 2.The following figures illustrate audio data input/output formats and timing.
The TSC2301 can accept 32-, 48-, or 64-bit clocks (BCKIN) in one clock of LRCIN. Only 16-bit data formats canbe selected when 32-bit clocks/LRCIN are applied.
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MSB
L–ch R–ch
L–ch R–ch
LSB
LRCIN
BCKIN
FORMAT 0
MSB LSB
DAC: 16–Bit, MSB–First, Right–Justified
ADC: 16–Bit, MSB–First, Left–Justified
116 2 3 14 15 16 1 2 3 14 15 16
MSB LSB
LRCIN
BCKIN
MSB LSB
1 2 3 14 15 16 1 2 3 14 15 16 1
MSB
L–ch R–ch
L–ch R–ch
LSB
LRCIN
BCIN
FORMAT 2
MSB LSB
DAC: 20–Bit, MSB–First, Left–Justified
ADC: 20–Bit, MSB–First, Left–Justified
1 2 3 18 19 20 1 2 3 18 19 20
MSB LSB
LRCIN
BCIN
MSB LSB
1 2 3 18 19 20 1 2 3 18 19 20
MSB
L–ch R–ch
L–ch R–ch
LSB
LRCIN
BCKIN
FORMAT 1
MSB LSB
DAC: 20–Bit, MSB–First, Right–Justified
ADC: 20–Bit, MSB–First, Left–Justified
120 2 3 18 19 20 1 2 3 18 19 20
MSB LSB
LRCIN
BCKIN
MSB LSB
1 2 3 18 19 20 1 2 3 18 19 20 1
1
1
I2SDIN
I2SDOUT
I2SDIN
I2SDOUT
I2SDIN
I2SDOUT
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Figure 74. Audio Data Input/Output Format
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M S B
L –c h R –c h
L –c h R –c h
L S B
F O R M A T 3
M S B L S B
D A C : 2 0 –B it, M S B –F ir s t, I2S
A D C : 2 0 –B it , M S B –F ir s t, I2S
1 2 3 1 8 1 9 2 0 1 2 3 1 8 1 9 2 0
M S B L S B M S B L S B
1 2 3 1 8 1 9 2 0 1 2 3 1 8 1 9 2 0
I2SDIN
BCKIN
LRCIN
BCKIN
LRCIN
I2SDOUT
tBCH
tBCY
tBCL
tLB
tDIH
tDIS
tLRP
tBL
tLDO
tBDO
0.5V DD
0.5VDD
0.5VDD
0.5V DD
I2SDIN
I2SDOUT
BCKIN
LRCIN
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Figure 75. Audio Data Input/Output Format
Figure 76. Audio Data Input/Output Timing
Table 29. Audio Data Input/Output Timing
Parameter Symbol Min Max
BCKIN pulse cycle time t
BCY
300 nsBCKIN pulse width high t
BCH
120 nsBCKIN pulse width low t
BCL
120 nsBCKIN rising edge to LRCIN edge t
BL
40 nsLRCIN edge to BCKIN rising edge t
LB
40 nsLRCIN pulse width t
LRP
t
BCY
nsI2SDIN setup time t
DIS
40 nsI2SDIN hold time t
DIH
40 nsI2SDOUT delay time to BCKIN falling edge t
BDO
40 nsI2SDOUT delay time to LRCIN edge t
LDO
40 nsRising time to all signals t
RISE
20 ns
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Table 29. Audio Data Input/Output Timing (continued)
Parameter Symbol Min Max
Falling time to all signals t
FALL
20 ns
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Audio Data Converters
The TSC2301 includes a stereo 20-bit audio DAC and a stereo 20-bit audio ADC. The DAC and ADC are bothcapable of operating at 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz.The DAC and ADC must operate at the same sampling rate.
When the ADC or DAC is operating, the part requires an audio MCLK input, which should be synchronous to theI
2
S bus clock. The MCLK can be 256/384/512 times the I
2
S LRCLK rate. An internal PLL takes any of thesepossible input clocks and generates a digital clock for use by the internal circuitry of either 44.1 kHz x 512 =22.5792 MHz (when 44.1 kHz submultiple sample-rates are selected) or 48 kHz x 512 = 24.576 MHz (when 48kHz submultiple sample-rates are selected). The user is required to set the MCLK bits (Bits[7:6], Reg 00h, Pg 2)to tell the part the ratio between MCLK and the I
2
S LRCLK rate (there is no specific phase alignment requirementbetween MCLK and BCLK). The user is also required to set the I2SFS bits (Bits[5:2], Reg 00h, Pg 2) to tell thepart what sample rate is in use. When the user is using either 44.1 kHz or 48-kHz sampling rates, and providinga 512 x Fs MCLK, the internal PLL is powered down, as MCLK can be used directly to clock the internal circuitry.This reduces power consumption.
If the user wishes to change sampling rates, the data converters (both DACs and ADCs) must be muted, thenpowered down. The LRCLK and BCLK rates must then be changed. Next the user must write the appropriatesettings to the MCLK, I2SFS, and I2SFM bits, then power up the data converters. Finally, the data converterscan be unmuted.
Due to the wide supply range over which this part must operate, the audio does not operate on an internalreference voltage. The common-mode voltage that the single-ended audio signals are referenced to is set by adivider between the analog supplies and is given by 0.4 x AVDD. The reference voltages used by the audiocodec must be provided as inputs to the part at the Vref+/Vref- pins and are intended to be connected to thesame voltage levels as AVDD and AGND, respectively. Because of this arrangement, the voltages applied toAVDD, AGND, Vref+, and Vref- should be kept as clean and noise-free as possible.
DAC Digital Volume Control
The DAC digital effects processing block implements a digital volume control that can be set through the SPIregisters. The volume level can be varied from 0 dB to -63.5 dB in 0.5-dB steps independently for each channel.The user can mute each channel independently by setting the mute bits in the DAC volume control register (Reg02h, Pg 2). There is a soft-stepping algorithm included in this block, which only changes the actual volume every20 µs, either up or down, until the desired volume is reached. This speed of soft-stepping can be slowed to onceevery 40 µs through the SSRTE bit (Bit 1, Reg 04h, Pg 2).
Because of this soft-stepping, the host does not know whether the DAC has actually been fully muted or not.This may be important if the host wishes to mute the DAC before making a significant change, such as changingsample rates. In order to help with this situation, the part provides a flag back to the host via a read-only SPIregister bit (Bit 0, Reg 04h, Pg 2) that alerts the host when the part has completed the soft-stepping, and theactual volume has reached the desired volume level.
The part also includes functionality to detect when the user switches on or off the de-emphasis or bass-boostfunctions, and to first soft-mute the DAC volume control, then change the operation of the digital effectsprocessing, then soft-unmute the part. This avoids any possible pop/clicks in the audio output due toinstantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC/ADC.The circuit begins operation at power-up with the volume control muted, then soft-steps it up to the desiredvolume level slowly. At power-down, the logic first soft-steps the volume down to a mute level, then powers downthe circuitry.
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N0 2 N1 Z–1 N2 Z–2
32768–2 D1 Z–1–D2 Z–2N3 2 N4 Z–1 N5 Z–2
32768–2 D4 Z–1–D5 Z–2
(13)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Stereo DAC Overview
The stereo DAC consists of a digital block to implement digital interpolation filter, volume control, de-emphasisfilter and programmable digital effects/bass-boost filter for each channel. These are followed by a fifth-ordersingle-bit digital delta-sigma modulator, and switched capacitor analog reconstruction filter. The DAC has beendesigned to provide enhanced performance at low sample rates through increased oversampling and imagefiltering, thereby keeping quantization noise generated within the delta-sigma modulator and signal imagesstrongly suppressed in the full audio band of 20 Hz-20 kHz, even at low sample rates such as 8 kHz. This isrealized by keeping the upsampled rate approximately constant and changing the oversampling ratio as the inputsample rate is reduced. For rates of 8/12/16/24/32/48 kHz, the digital delta-sigma modulator always operates at arate of 6.144 MHz, giving oversampling ratios of 768/512/384/256/192/128, respectively. This ensures thatquantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 kHzat all sample rates. Similarly, for rates of 11.025/22.05/44.1 kHz, the digital delta-sigma modulator alwaysoperates at a rate of 5.6448 MHz, yielding oversampling ratios of 512/256/128, respectively.
Conventional audio DAC designs utilize high-order analog filtering to remove quantization noise that falls withinthe audio band when operating at low sample rates. Here, however, the increased oversampling at low samplerates keeps the noise above 20 kHz, yielding a similar noise floor out to 20 kHz whether the sample rate is 8 kHzor 48 kHz. If the audio bypass path is not in use when the stereo DAC is in use, the user should power down thebypass path, as this improves DAC SNR and reduces power consumption.
In addition, the digital interpolation filter provides enhanced image filtering to reduce signal images caused by theupsampling process that land below 20 kHz. For example, upsampling an 8-kHz signal produces signal imagesat multiples of 8 kHz, i.e., 8 kHz, 16 kHz, 24 kHz, etc. The images at 8 kHz and 16 kHz are below 20 kHz andthus are still audible to the listener, therefore they must be filtered heavily to maintain a good quality output. Theinterpolation filter is designed to maintain at least 65-dB rejection of signal images landing between 0.55 Fs and3.5 Fs, for all sample rates, including any images that land within the audio band (20 Hz-20 kHz). Passbandripple for all sample-rate cases (from 20 Hz to 0.4535 Fs) is +/-0.1-dB maximum.
The analog reconstruction filter design consists of a switched-capacitor filter with one pole and three zeros. Thesingle-bit data operates at 128 x 48 kHz = 6.144 MHz (for selected sample-rates that are submultiples of 48 kHz)or at 128 x 44.1 kHz = 5.6448 MHz (for selected sample-rates that are submultiples of 44.1 kHz). Theinterpolation filter takes data at the selected sample-rate from the effects processing block, then performsupsampling and image filtering, yielding a 6.144-MHz or 5.6448-MHz data stream, which is provided to the digitaldelta-sigma modulator.
Audio DAC SNR performance is 98-dB-A typical over 20 Hz–20 kHz bandwidth in 44.1/48-kHz mode at theline-outputs with a 3.3-V supply level.
DAC Digital De-Emphasis
The DAC digital effects processing block can perform several operations on the audio data before it is passed tothe interpolation filter. One such operation is a digital de-emphasis, which can be enabled or disabled by the uservia the DEEMP bit (Bit 0, Reg 05h, Pg 2). This is only available for sample rates of 32 kHz, 44.1 kHz, and 48kHz. The transfer function consists of a pole with time constant of 50 µs and a zero with time constant of 15 µs.
DAC Programmable Digital Effects Filter
The DAC digital effects processing block also includes a fourth order digital IIR filter with programmablecoefficients (independently programmable per channel). The filter transfer function is given by:
The N and D coefficients are set via SPI registers, and this filter can be enabled or disabled via the BASS bit (Bit1, Reg 05h, Pg 2). This functionality can implement a number of different functions, such as bass-boost (default),treble-boost, mid-boost, or other equalization. This transfer function(s) can be determined by the user and loadedto the TSC2301 at power-up, and the feature can then be switched on or off by the user during normal operation.If a filter with gain over 0 dB is designed and used, and large-scale signals are played at high amplitude throughthe DAC, overloading and undesirable effects can occur.
The default coefficients at reset are given by:
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Default Bass-Boost Transfer Function 48 kHz Mode
1 10 100 1000 10000 100000
Frequency (Hz)
0
–0.5
–1
–1.5
–2
–2.5
–3
–3.5
Gain (dB)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
N0 = N3 = 27618 D1 = D4 = 32130N1 = N4 = -27033 D2 = D5 = -31505N2 = N5 = 26461
which implements the bass-boost transfer function shown in Figure 77 , having a 3-dB attenuation for signalsabove approximately 150 Hz when operating at a 48-kHz sampling rate. All coefficients are represented by 16-bittwos complement integers with values ranging from -32768 to 32767.
Figure 77. Transfer Function of Default Bass-Boost Filter Coefficients at 48-kHz Sampling Rate
Audio ADC
The audio ADC consists of a 4th order multi-bit analog delta-sigma modulator, followed by a digital decimationfilter. The digital output data is then passed to the bus interface for transmission back to the CPU.
The analog modulator is a fully differential switched-capacitor design with multi-bit quantizer and dynamicelement matching to avoid mismatch errors. The modulator operates at an oversampling ratio of 128 for allsample rates. The input to the ADC is filtered by a single-pole analog filter with -3-dB point at approximately 500kHz for antialiasing. This analog filter uses a single off-chip 1 nF cap per ADC (at the AFILT pins) and on-chipresistor.
The digital decimation filter block includes a high-pass IIR filter for the purpose of removing any dc orsub-audio-frequency component from the signal. Since such a low frequency filter can have significant settlingtime, the filter has an adjustable cutoff frequency, in order to allow the host to set a faster settling time initially,then later switch it back to a level that does not affect the audio band. The settings for this high-pass filter are:
HPF -3-dB frequency: 0.000019 Fs (0.912 Hz at Fs = 48 kHz)0.000078 Fs (3.744 Hz at Fs = 48 kHz)0.1 Fs (4.8 kHz at Fs = 48 kHz)
The filter block provides an audio passband ripple of +/-0.03 dB over a passband from 0 Hz to 0.454 samplingfrequency (Fs), and 70-dB minimum stopband attenuation from 0.548 Fs to 64 Fs.
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
The ADC modulator and digital filter operate on a clock that changes directly with Fs. This is in contrast to theDAC, which keeps the modulator running at a high rate of 128 x 44.1 kHz or 128 x 48 kHz even if the incomingdata rate is much lower, such as 8 kHz. Group delay of the ADC path varies with sampling frequency and isgiven by 28.7/Fs.
Audio ADC SNR performance is 88-dB-A typical over 20-Hz - 20-kHz bandwidth in 44.1/48-kHz mode with a3.3-V supply level.
Each audio ADC is preceded by an analog volume control with gain programmable from 20 dB to -40 dB or mutein 0.5-dB steps using Reg 01h, Pg 2. The input to these volume controls are selected as LLINEIN, RLINEIN,MICIN, or a mono mix of LLINEIN and RLINEIN through the INML bits (Bits [13:12], Reg 00h, Pg 2). Anadditional preamp gain is selectable on the MICIN input as 0 dB, 6 dB, or 12 dB using the MICG bits (Bits [9:8],Reg 00h, Pg 2).
Audio Bypass Mode
In audio bypass mode, the L/RLINEIN analog inputs can be routed to mix with the DAC output and play to theline-outputs (VOUTL/R) as well as the headphone outputs (HPL/R) and mono output (MONO+/-). This path has astereo analog volume control associated with it, with range settings from 12.0 dB to -35.5 dB in 0.5-dB steps. Ifthe audio ADCs and DACs are not used while the bypass path is in use, the ADCs and DAC must be powereddown to improve noise performance and reduce power consumption.
This analog volume control has soft-stepping logic associated with it, so that when a volume change is made viathe SPI bus, the logic changes the actual volume incrementally, single-stepping the actual volume up or downonce every 20 µsec until it reaches the desired volume level.
This volume control also has similar algorithms as the ADC/DAC volume controls, in that the volume starts atmute upon power-up, then is slowly single-stepped up to the desired level. At a power-down request, the volumeis slowly single-stepped down to mute before the circuit is actually powered down.
Differential Monophonic Output (MONO+/-)
The differential mono output of the TSC2301 can be used to drive a power amplifier which drives alow-impedance speaker. This block can output either a mono mix of the stereo line outputs, or the analog input tothe left-channel ADC. This is selected through the MONS bit (Bit 2, Reg 04h, Pg 2). The mono mix of the lineoutputs is represented by the equation VOUTL/2 + VOUTR/2. Similarly, the mono mix of the analog line inputs isrepresented by LLINEIN/2 + RLINEIN/2.
Microphone Bias Voltage (MICBIAS)
The TSC2301 provides an output voltage suitable for biasing an electret microphone capsule. This voltage isalways 1 V below the supply voltage of the part. This output can be disabled through the MIBPD bit (Bit 6, Reg05h, Pg 2) to reduce power consumption if not used.
Power Consumption
The TSC2301 provides maximum flexibility to the user for control of power consumption. Towards that end, everysection of the TSC2301 audio codec can be independently powered down. The power down status of thedifferent sections is controlled by Reg 05h in Pg 2. The analog bypass path, headphone amplifier, mono output,stereo DAC, left channel ADC, right channel ADC, microphone bias, crystal oscillator, and oscillator clock buffersections can all be powered down independently. It is recommended that the end-user power down all unusedsections whenever possible in order to minimize power consumption. Below is a table showing powerconsumption in different modes of operation.
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TSC2301 AUDIO CONTROL REGISTERS
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Table 30. Power Consumption by Mode of Operation
Operating Mode Description Register 05h Bit Values Power Consumption
Typ Units
15 14 13 12 11 10 9 8 6 5 4
Stereo Record and Playback
Mono record, line playback, 48 kHz 0 0 1 1 1 0 0 1 1 0 0 45 mWMono record, line playback, 8 kHz 0 0 1 1 1 0 0 1 1 0 0 38 mWStereo record, line playback, 48 kHz 0 0 1 1 1 0 0 0 1 0 0 60 mWStereo record, line playback, 8 kHz 0 0 1 1 1 0 0 0 1 0 0 48 mW
Stereo Playback Only
Line playback only, 48 kHz 0 0 1 1 1 0 1 1 1 0 0 28 mWHeadphone playback only, 48 kHz 0 0 1 0 1 0 1 1 1 0 0 34 mW
Record Only
Stereo line record only, 48 kHz 0 0 1 1 1 1 0 0 1 0 0 34 mWStereo line record only, 8 kHz 0 0 1 1 1 1 0 0 1 0 0 26 mWMono record, 48 kHz 0 0 1 1 1 1 0 1 1 0 0 19 mWMono record only, 8 kHz 0 0 1 1 1 1 0 1 1 0 0 15 mW
Analog Bypass
Line in to line out 0 0 0 1 1 1 1 1 1 0 0 10 mWLine in to headphone out 0 0 0 0 1 1 1 1 1 0 0 13 mW
Power Down
Power down all 1 1 X X X X X X X 0 0 0.5 µWPower down, VCM enabled 1 0 X X X X X X X 0 0 0.8 µW
TSC2301 Audio Control Register (Page 2, Address 00H)
The audio control register of the TSC2301 controls the digital audio interface, the microphone preamp gain, therecord multiplexer settings, and the ADC highpass filter pole. This register determines which ADC high pass filterresponse is selected, as well as which audio inputs are connected to the stereo ADCs. The gain of the MIC input(0 to 12 dB) is also selected. This register is also used to tell the data converters the frequency of MCLK, alongwith the frequency of LRCLK (ADC and DAC sample rates). The format of the audio data is also selected.
The audio control register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
HPF1 HPF0 INML1 INML0 INMR1 INMR0 MICG MICG MCLK MCLK I2SFS I2SFS I2SFS I2SFS I2SFM I2SFM0101032101
Bits [15:14] — HPF1-HPF0
ADC High Pass Filter. These two bits select the pass-band for the high-pass filter or disable the filter. The defaultstate of the filter is enabled, with -3-dB frequency at 0.000019xFs.
Table 31. High-Pass Filter Operation
HPF[1:0]
HPF1 HPF0 Description
0 0 HPF Disabled, signal passes through unaltered0 1 HPF -3-dB frequency = 0.1xFs1 0 HPF -3-dB frequency = 0.000078xFs1 1 HPF -3-dB frequency = 0.000019xFs (default)
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Bits [13:12] — INML1-INML0
Left Audio ADC Input Multiplexer. These two bits select the analog input for the left channel ADC. The input tothe left channel ADC can come from the microphone input, right line input, left line input, or from a mono mix ofthe left and right line inputs. The default input to the left channel ADC is the microphone input.
Table 32. Left Audio ADC Input Selection
INML[1:0]
INML1 INML0 Description
0 0 ADCL input = MIC (default)0 1 ADCL input = LLINEIN1 0 ADCL input = RLINEIN1 1 ADCL input = (RLINEIN+LLINEIN)/2
Bits [11:10] — INMR1-INMR0
Right Audio ADC Input Multiplexer. These two bits select the analog input for the right channel ADC. The input tothe right channel ADC can come from the microphone input, right line input, left line input, or from a mono mix ofthe left and right line inputs. The default input to the right channel ADC is the microphone input.
Table 33. Right Audio ADC Input Selection
INMR[1:0]
INMR1 INMR0 Description
0 0 ADCR input = MIC (default)0 1 ADCR input = LLINEIN1 0 ADCR input = RLINEIN1 1 ADCR input = (RLINEIN+LLINEIN)/2
Bits [9:8] — MICG1-MICG0
Microphone Preamp Gain. These two bits select the gain of the microphone input channel. The gain of themicrophone input channel can be 0 dB, 6 dB, or 12 dB. The default gain of the microphone input channel is 0 dB.
Table 34. Microphone Input Gain Selection
MICG[1:0]
MICG1 MICG0 Description
0 0 MIC gain = 0 dB (default)0 1 MIC gain = 0 dB1 0 MIC gain = 6 dB1 1 MIC gain = 12 dB
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Bits [7:6] — MCLK1-MCLK0
Master Clock Ratio. These two bits select the ratio of the audio master clock frequency to the audio samplingfrequency. The ratio can be 256 Fs, 384 Fs, or 512 Fs. The default master clock frequency is 256 Fs.
Table 35. Master Clock Ratio Selection
MCLK[1:0]
MCLK1 MCLK0 Description
0 0 Master clock (MCLK) = 256 x Fs (default)0 1 Master clock (MCLK) = 384 x Fs1 0 Master clock (MCLK) = 512 x Fs1 1 Master clock (MCLK) = 256 x Fs
Bits [5:2] — I2SFS3-I2SFS0
I
2
S Sample Rate. These bits tell the internal PLL what the audio sampling rate is so that it provides the properclock rate to the data converters and the digital filters. The default sample rate is 48 kHz. See Table 36 for acomplete listing of available sampling rates. All combinations of I2SFS[3:0] not in Table 36 are not valid.
Table 36. I
2
S Sample Rate Select
I2SFS3 I2SFS2 I2SFS1 I2SFS0 Function
0 0 0 0 Fs = 48 kHz (default)0 0 0 1 Fs = 44.1 kHz0 0 1 0 Fs = 32 kHz0 0 1 1 Fs = 24 kHz0 1 0 0 Fs = 22.05 kHz0 1 0 1 Fs = 16 kHz0 1 1 0 Fs = 12 kHz0 1 1 1 Fs = 11.05 kHz1 0 0 0 Fs = 8 kHz
Bits [1:0] — I2SFM1-I2SFM0
I
2
S Format. These two bits select the I
2
S interface format. Both 16-bit and 20-bit data formats are supported. Thedefault format is 20-bit I
2
S.
Table 37. I
2
S Format Selection
I2SFM [1:0]
I2SFM1 I2SFM0 Description
0 0 DAC: 16-bit, MSB-first, right justified ADC: 16-bit, MSB-first, left justified0 1 DAC: 20-bit, MSB-first, right justified ADC: 20-bit, MSB-first, left justified1 0 DAC: 20-bit, MSB-first, left justified ADC: 20-bit, MSB-first, left justified1 1 DAC: 20-bit, MSB-first, I
2
S (default) ADC: 20-bit, MSB-first, I
2
S (default)
ADC VOLUME CONTROL REGISTER (Page 2, Address 01h)
The ADC volume control register controls the independent programmable gain amplifiers (PGA's) on the left andright channel inputs to the audio ADCs of the TSC2301. The gain of these PGAs can be adjusted from
-40 dB to 20 dB in 0.5-dB steps. The ADC inputs can also be hard-muted, or internally shorted to VCM so that noinput signal is seen.
The ADC volume control register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
ADMU ADVL ADVL5 ADVL4 ADVL3 ADVL ADVL ADVL ADMU ADVR6 ADVR5 ADVR4 ADVR3 ADVR2 ADVR ADVRL 6 2 1 0 R 1 0
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Bit 15 — ADMUL
Left ADC Mute. This bit is used to mute the input to the left channel ADC volume control. The user can set thisbit to mute the ADC while retaining the previous gain setting in ADVL[6:0], so that the PGA returns to theprevious gain setting when ADMUL is cleared. When the ADMUL bit is set, the left ADC PGA soft-steps down toits lowest level, then mutes. This procedure is used to reduce any audible artifacts ( pops or clicks) during themute operation. This soft-stepping process is reversed when the ADMUL bit is cleared (unmute).
Table 38. Left ADC Mute
ADMUL Description
0 Left channel ADC is active.1 Left channel ADC is mute. (default)
Bits [14:8] — ADVL6- ADVL0
Left ADC Volume Control. These 7 bits control the gain setting of the left channel ADC volume control. Thisvolume control can be programmed from -40 dB to 20 dB in 0.5-dB steps. Full volume (+20 dB) corresponds to asetting of 7Fh. Unity gain (0 dB) corresponds to 57h. Full attenuation (-40 dB) corresponds to 07h. Any valuelower than 07h engages the mute function described above. Volume control changes are always soft-stepped, asdescribed above. The default volume setting is 0 dB.
ADVL[6:0] = 1010111 (087d) = 0 dB (default)
ADVL[6:0] = 1111111 (127d) = +20 dB (Max)
ADVL[6:0] = 0000111 (007d) = -40 dB (Min)
ADVL[6:0] = 0d-6d = mute
Bit 7 — ADMUR
Right ADC Mute. This bit is used to mute the input to the right channel ADC. The user can set this bit to mute theADC while retaining the previous gain setting in ADVR[6:0], so that the PGA returns to the previous gain settingwhen ADMUR is cleared. When the ADMUR bit is set, the right ADC PGA soft-steps down to its lowest level,then mutes. This procedure is used to reduce any audible artifacts ( pops or clicks) during the mute operation.This soft-stepping process is reversed when the ADMUR bit is cleared (unmute).
Table 39. Right ADC Mute
ADMUR Description
0 Right channel ADC is active.1 Right channel ADC is mute. (default)
Bits [6:0] — ADVR6- ADVR0
Right ADC Volume Control. These 7 bits control the gain setting of the right channel ADC volume control PGA.This volume control can be programmed from -40 dB to 20 dB in 0.5-dB steps. Full volume (20 dB) correspondsto a setting of 7Fh. Unity gain (0 dB) corresponds to 57h. Full attenuation (-40 dB) corresponds to 07h. Any valuelower than 07h engages the mute function described above. Volume control changes are always soft-stepped, asdescribed above. The default volume setting is 0 dB.
ADVR[6:0] = 1010111 (087d) = 0 dB (default)
ADVR[6:0] = 1111111 (127d) = +20 dB (Max)
ADVR[6:0] = 0000111 (007d) = -40 dB (Min)
ADVR[6:0] = 0d-6d = mute
DAC VOLUME CONTROL REGISTER (Page 02, Address 02h)
The DAC volume control register controls the independent digital gain controls on the left and right channel audioDAC's of the TSC2301. The gain of the DACs can be adjusted from -63.5 dB to 0 dB in 0.5-dB steps. The DACinputs can also be muted, so that all zeroes are sent to the DAC interpolation filters.
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The DAC volume control register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
DAMU DAVL DAVL5 DAVL4 DAVL3 DAVL DAVL DAVL DAMU DAVR6 DAVR5 DAVR4 DAVR3 DAVR2 DAVR DAVRL 6 2 1 0 R 1 0
Bit 15 — DAMUL
Left DAC Mute. This bit is used to mute the input to the left channel DAC. The user can set this bit to mute theDAC while retaining the previous gain setting in DAVL[6:0], so that the gain control returns to the previous gainsetting when DAMUL is cleared. When the DAMUL bit is set, the left DAC digital gain control soft-steps down toits lowest level, then all zeroes are sent to the interpolation filter of this DAC. This procedure is used to reduceany audible artifacts ( pops or clicks) of the mute procedure. This soft-stepping process is reversed when theDAMUL bit is cleared (unmute).
Table 40. Left DAC Mute
DAMUL Description
0 Left channel DAC is active.1 Left channel DAC is mute. (default)
Bits [14:8] — DAVL6- DAVL0
Left DAC Volume Control. These 7 bits control the gain setting of the left channel DAC volume control PGA. Thisvolume control can be programmed from -63.5 dB to 0dB in 0.5-dB steps. Full volume (0dB) corresponds to asetting of 7Fh. Full attenuation (-63.5 dB) corresponds to 00h. The default volume setting is 0 dB.
DAVL[6:0] = 1111111 (127d) = 0 dB (default)
DAVL[6:0] = 0000000 (000d) = -63.5 dB (Min)
1LSB = 0.5 dB
Bit 7 — DAMUR
Right DAC Mute. This bit is used to mute the input to the right channel DAC. The user can set this bit to mute theDAC while retaining the previous gain setting in DAVR[6:0], so that the gain control returns to the previous gainsetting when DAMUR is cleared. When the DAMUR bit is set, the left DAC digital gain control soft-steps down toits lowest level, then all zeroes are sent to the interpolation filter of this DAC. This procedure is used to reduceany audible artifacts ( pops or clicks) of the mute procedure. This soft-stepping process is reversed when theDAMUR bit is cleared (unmute).
Table 41. Right DAC Mute
DAMUR Description
0 Right channel DAC is active.1 Right channel DAC is mute. (default)
Bits [6:0] — DAVR6- DAVR0
Right DAC Volume Control. These 7 bits control the gain setting of the right channel DAC volume control. Thisvolume control can be programmed from -63.5 dB to 0 dB in 0.5-dB steps. Full volume (0 dB) corresponds to asetting of 7Fh. Full attenuation (-63.5 dB) corresponds to 00h. The default volume setting is 0 dB.
DAVR[6:0] = 1111111 (127d) = 0 dB (default)
DAVR[6:0] = 0000000 (000d) = -63.5 dB (Min)
1LSB = 0.5 dB
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ANALOG AUDIO BYPASS PATH VOLUME CONTROL REGISTER (Page 02, Address 03h)
The bypass path volume control register controls the independent programmable gain amplifiers (PGA's) on theleft and right channel analog audio bypass paths of the TSC2301. These bypass paths direct the line inputsdirectly to the line and headphone outputs entirely in the analog domain, with no A/D or D/A conversion. Thisfeature can be used for playback of an external analog source, such as an FM stereo tuner through theTSC2301's headphone amplifier. The gain of these PGA's can be adjusted from -35.5 dB to 12 dB in 0.5 dBsteps. The bypass paths can also be muted, so that no signal is transmitted.
The bypass path volume control register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
BPMU BPVL BPVL5 BPVL4 BPVL3 BPVL BPVL BPVL BPMU BPVR6 BPVR5 BPVR4 BPVR3 BPVR2 BPVR BPVRL 6 2 1 0 R 1 0
Bit 15 — BPMUL
Left Channel Audio Bypass Mute. This bit is used to mute the bypass path from the left channel line input(LLINEIN) to the left channel line and headphone outputs (VOUTL and HPL). The user can set this bit to mutethe bypass path while retaining the previous gain setting in BPVL[6:0], so that the PGA returns to the previousgain setting when BPMUL is cleared. When the BPMUL bit is set, the PGA soft-steps down to its lowest level,then the bypass path is muted. This procedure is used to reduce any audible artifacts ( pops or clicks) during themute operation. This soft-stepping process is reversed when the BPMUL bit is cleared (unmute).
Table 42. Left Channel Audio Bypass Mute
BPMUL Description
0 Left channel audio bypass path is active.1 Left channel audio bypass path is mute. (default)
Bits [14:8] — BPVL6- BPVL0
Left Channel Audio Bypass Path Volume Control. These 7 bits control the gain setting of the left channel bypasspath volume control PGA. This volume control can be programmed from -35.5 dB to 12 dB in 0.5 dB steps. Fullvolume (+12 dB) corresponds to a setting of 7Fh. Unity gain (0 dB) corresponds to 67h. Full attenuation (-35.5dB) corresponds to 20h. Any value lower than 20h engages the mute function described above. The defaultvolume setting is 0 dB.
BPVL[6:0] = 1100111 (103d) = 0 dB (default)
BPVL[6:0] = 1111111 (127d) = 12 dB (Max)
BPVL[6:0] = 0100000 (032d) = -35.5 dB (Min)
BPVL[6:0] = 0d-31d = mute
Bit 7 — BPMUR
Right Channel Audio Bypass Mute. This bit is used to mute the bypass path from the right channel line input(RLINEIN) to the right channel line and headphone outputs (VOUTR and HPR). The user can set this bit to mutethe bypass path while retaining the previous gain setting in BPVR[6:0], so that the PGA returns to the previousgain setting when BPMUR is cleared. When the BPMUR bit is set, the PGA soft-steps down to its lowest level,then the bypass path is muted. This procedure is used to reduce any audible artifacts ( pops or clicks) during themute operation. This soft-stepping process is reversed when the BPMUR bit is cleared (unmute).
Table 43. Right Channel Audio Bypass Mute
BPMUR Description
0 Right channel audio bypass path is active.1 Right channel audio bypass path is mute. (default)
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Bits [6:0] — BPVR6- BPVR0
Right Channel Audio Bypass Path Volume Control. These 7 bits control the gain setting of the right channelbypass path volume control PGA. This volume control can be programmed from -35.5 dB to +12 dB in 0.5-dBsteps. Full volume (+12 dB) corresponds to a setting of 7Fh. Unity gain (0 dB) corresponds to 67h. Fullattenuation (-35.5 dB) corresponds to 20h. Any value lower than 20h engages the mute function describedabove. The default volume setting is 0 dB.
BPVR[6:0] = 1100111 (103d) = 0 dB (default)
BPVR[6:0] = 1111111 (127d) = +12 dB (Max)
BPVR[6:0] = 0100000 (032d) = -35.5 dB (Min)
BPVR[6:0] = 0d-31d = mute
KEYCLICK CONTROL REGISTER (Page 2, Address 04H)
The Keyclick Control Register of the TSC2301 controls the setup of the internal keyclick sound generator. Thisregister is used to initiate and set the frequency, amplitude, and duration of the internally generated keyclicksound. This register also controls the input to the differential mono output, and the soft-stepping function of theTSC2301 volume controls.
The keyclick control register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
KEYST KCAM KCA KCAM RESV KCFR KCFR KCFR KCLN3 KCLN2 KCLN1 KCLN0 RESV MONS SSRT SSTE2 M1 0 2 1 0 E P
Bit 15 — KEYST
Keyclick Start. This bit initiates a keyclick sound.
Table 44. Keyclick Start
KEYST Description
0 No keyclick sound (default)1 Initiate a keyclick sound
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Bits [14:12] — KCAM2-KCAM0
Keyclick Amplitude. These bits set the amplitude of the keyclick sound with eight amplitude levels provided.
KCAM[2:0] = 100 = Medium amplitude (default)
KCAM[2:0] = 111 = Maximum amplitude
KCAM[2:0] = 000 = Minimum amplitude
Bit 11 — RESERVED
This bit is reserved, and should be written to 0. If read, it reads back as 0.
Bits [10:8] — KCFR2-KCFR0
Keyclick Frequency. These bits set the frequency of the keyclick sound (frequencies are approximate).
Table 45. Keyclick Frequency
KCFR2 KCFR1 KCFR0 Keyclick Tone Frequency
0 0 0 62.5 Hz0 0 1 125 Hz0 1 0 250 Hz0 1 1 500 Hz1 0 0 1 k Hz (default)1 0 1 2 k Hz1 1 0 4 k Hz1 1 1 8 k Hz
Bits [7:4] — KCLN3-KCLN0
Keyclick Length. These bits set the approximate duration of the keyclick sound, 16 settings for duration areprovided. The formula for the number of periods heard is:
KCLN[3:0] = 0000 = 2 periods of the keyclick sound (min)
KCLN[3:0] = 0001 = 4 periods of the keyclick sound (default)
KCLN[3:0] = 0010 = 6 periods of the keyclick sound
KCLN[3:0] = 0011 = 8 periods of the keyclick sound
KCLN[3:0] = 1111 = 32 periods of the keyclick sound (max)
Bit 3 — RESERVED
This bit is reserved, and should be written as 0. If read, it is read back as 0.
Bit 2 — MONS
Mono Select. This bit determines the position of the mono multiplexer. This multiplexer allows either the leftchannel ADC Input or the mono mix of the stereo line outputs to be played out the differential mono output(MONO+/-).
Table 46. Mono Select
MONS Description
0 Mono output comes from left ADC input (default).1 Mono output comes from mono mix of line outputs.
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Bit 1 — SSRTE
Volume Soft-stepping Rate Select. This bit selects the speed of the soft-stepping function of the TSC2301volume controls. At normal speed, the actual volume is updated approximately once every 20 µs. At half speed,the actual volume is updated approximately once every 40 µs.
Table 47. Volume Soft-Stepping Rate Select
SSRTE Description
0 Normal step rate used (default).1 Half step rate used.
Bit 0 — SSTEP
Soft-step Flag. This read-only bit indicates that the TSC2301 volume control soft-stepping is completed.
Table 48. Soft-Step Flag
SSTEP Description
0 Soft-stepping is not complete.1 Soft-stepping is complete (default).
AUDIO POWER CONTROL REGISTER (Page 2, Address 05H)
The audio power / miscellaneous control register of the TSC2301 controls the powering down of various audioblocks of the TSC2301. The default state of the TSC2301 has all audio blocks powered down. Before using anyof the audio blocks, they must be powered up by writing to this register. This register also controls the crystaloscillator clock and buffer, the bass-boost filter, and the de-emphasis filter.
The audio power / miscellaneous control register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
APD AVPD ABPD HAPD MOPD DAPD ADPD ADPD PDSTS MIBPD OSC BCKC SMPD OTSY BASS DEEML R C N P
For bits 15 through 8 of this register, writing a 1 to a selected bit powers down the affected section, writing a 0powers up the section.
Bit 15 — APD
Audio Power Down. This bit powers down the entire audio section if set, regardless of the settings of the otherbits in this register. When this bit is cleared, the individual sections of the audio codec still need to be poweredup individually. The settings of the other bits in the register are retained when this bit is set and cleared. Thedefault is 1 (powered down).
Bit 14 — AVPD
Audio VCM Power Down. If this is set to 1, the VCM powers up whenever it is needed (such as when the audioADC, DAC, or bypass path is enabled) and powers down when no longer needed. If this bit is set to 0, after anaudio component is powered up and causes VCM to power up, it no longer powers down, even if all audiocomponents are powered down. This is intended to avoid the 500 µs delay needed for VCM to power up slowly.The default is 1 (powered down).
Bit 13 — ABPD
Audio Bypass Path Power Down. This is used to power up (set to 0) or power down (set to 1) the audio bypasspath. The default is 1 (powered down).
Bits 12 — HAPD
Headphone Amplifier Power Down. This is used to power up (set to 0) or power down (set to 1) the headphoneamplifier. The default is 1 (powered down).
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Bit 11 — MOPD
Mono Driver Power Down. This is used to power up (set to 0) or power down (set to 1) the mono output driver. Ifonly playback of the line or Mic inputs through the mono output is needed, the user need only power up themono section, and not the DAC or ADCs. The line inputs, Mic preamp, left channel ADC multiplexer and leftchannel volume control all power up if the mono output is powered up. The default is 1 (powered down).
Bit 10 — DAPD
DAC Power Down. This is used to power up (set to 0) or power down (set to 1) the entire stereo DAC. Thedefault is 1 (powered down).
Bit 9 — ADPDL
Left Channel ADC Power Down. This is used to power up (set to 0) or power down (set to 1) the entire leftchannel ADC. The line inputs, Mic preamp, left channel ADC multiplexer and left channel volume control allautomatically power up when the left channel ADC is powered up. The default is 1 (powered down).
Bit 8 — ADPDR
Right Channel ADC Power Down. This is used to power up (set to 0) or power down (set to 1) the entire rightchannel ADC. The line inputs, Mic preamp, right channel ADC multiplexer and right channel volume control allautomatically power up when the right channel ADC is powered up. The default is 1 (powered down).
Bit 7 — PDSTS
Power Up/Down Done. This read-only bit indicates that all power-up or power-down processes requested arecompleted.
Table 49. Power Up/Down Flag
PDSTS Description
0 Power up/down is not complete.1 Power up/down is complete (default).
Bit 6 — MIBPD
Microphone Bias Power Down. This is used to power up (set to 0) or power down (set to 1) the microphone biasoutput.
Table 50. Microphone Bias Power Down
OSCC Description
0 Microphone bias is on.1 Microphone bias is off (default).
Bit 5 — OSCC
Crystal Oscillator Control. This bit turns ON/OFF the crystal Oscillator.
Table 51. Crystal Oscillator Control
OSCC Description
0 Crystal oscillator is off (default).1 Crystal oscillator is on.
Bit 4 — BCKC
Oscillator Clock Buffer Control. This bit turns ON/OFF the output clock buffer.
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Table 52. Oscillator Clock Buffer Control
BCKC Description
0 The output clock buffer is off (default).1 The output clock buffer is on.
Bit 3 — SMPD
Synchronization Monitor Power Down. This bit turns ON/OFF the I
2
S bus sync monitor.
Table 53. Synchronization Monitor Power Down
SMPD Description
0 The I
2
S bus sync monitor is on (default).1 The I
2
S bus sync monitor is off.
Bit 2 — OTSYN
I
2
S Out Of Sync. This read-only sticky bit reflects the sync status of the I
2
S bus. It always resets to zero afterbeing read.
Table 54. I
2
S Out of Sync
OTSYN Description
0 The I
2
S bus is in sync (default).1 The I
2
S bus is out of sync.
Bit 1 — BASS
Digital-effects filter control. This bit turns ON/OFF the digital-effects filter. If the digital-effects filter is off, thesignal passes through with no filtering performed.
Table 55. Digital-Effects Filter Control
BASS Description
0 The digital-effects filter is off (default).1 The digital-effects filter is on.
Bit 0 — DEEMP
De-emphasis control. This bit turns ON/OFF the de-emphasis function.
Table 56. De-Emphasis Control
DEEMP Description
0 De-emphasis is off (default).1 De-emphasis is on.
GPIO CONTROL REGISTER (Page 02, Address 06h)
The GPIO control register controls the GPIO pins of the TSC2301. The direction of each GPIO pin can be setindependently. For GPIOs configured as output pins, the data to be driven is written to this register. For GPIO'sconfigured as inputs, the input data can be read from this register. This register also contains a bit, SDAVB whichmirrors the state of the DAVB output line.
The GPIO Control Register is formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
RESV RESV IO5 IO 4 IO 3 IO 2 IO 1 IO 0 RESV RESV GPIO5 GPIO4 GPIO3 GPIO2 GPIO GPIO1 0
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Bits 15,14 — RESERVED
These bits are reserved and should be written to 0. If read, they read back as 0.
Bits [13:8] — IO5- IO0
GPIO Directional Control. These 6 bits control the direction of the TSC2301s six GPIO pins. When one of thesebits is set to one, the corresponding GPIO pin is configured as an output. When one of these bits is set to zero,the corresponding GPIO pin is configured as an input. The default setting of these bits is zero (all inputs).
Bits 7,6 — RESERVED
These bits are reserved, and should be written to 0. If read, they read back as 0.
Bits [5:0] — GPIO5- GPIO0
GPIO Data. These bits control the data on the GPIO pins. When a GPIO pin is configured as an output, the datawritten to one of these bits is driven on the corresponding GPIO pin. When a GPIO pin is configured as an input,the data input on the GPIO pin is returned to the corresponding register bit, and can be read by the hostprocessor.
DAC BASS-BOOST FILTER COEFFICIENT REGISTERS (Page 02, Addresses 07h-1Ah)
The DAC bass-boost coefficient registers implement the transfer function described. The coefficients arerepresented by 16-bit twos complement integers with values ranging from -32768 to 32767.
The DAC bass-boost coefficient registers are formatted as follows:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 57. DAC Bass-Boost Coefficient Registers
Address DAC Channel Coefficient Default
07h Left N0 6BE208h Left N1 966709h Left N2 675D0Ah Left N3 6BE20Bh Left N4 96670Ch Left N5 675D0Dh Left D1 7D820Eh Left D2 84EF0Fh Left D4 7D8210h Left D5 84EF11h Right N0 6BE212h Right N1 966713h Right N2 675D14h Right N3 6BE215h Right N4 966716h Right N5 675D17h Right D1 7D8218h Right D2 84EF19h Right D4 7D821Ah Right D5 84EF
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AUDIO CLOCK CONFIGURATION REGISTER (Page 02, Address 1Bh)
This register allows the user to use the output of the crystal oscillator as MCLK, and receive the PLL output onthe PENIRQ pin.Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MSB LSB
X X X X X X X X X X X X PLPN COMK X X
Bits [15:4] — RESERVED
These bits are reserved, and should be written to 040h. If read, they read back as 040h.
Bits 3 — PLPN
Output PLL on the PENIRQ pin. This bit allows the user to receive the output of the audio codec internal PLL.This bit is provided so the host processor can use the output of the PLL, to generate its I
2
S signals in sync withan external MCLK or crystal oscillator. Writing a 1 to this bit connects the output of the PLL to the PENIRQ pin.Otherwise, the PENIRQ pin operates as normal. The user must take care in using this function, as PENIRQsignals are overridden.
Table 58. Output PLL on PENIRQ Pin
DEEMP Description
0 PENIRQ operates as normal (default).1 Output PLL on PENIRQ.
Bits 2 — COMK
Crystal Oscillator as MCLK. This bit allows the user to use the output of the internal crystal oscillator as theMCLK for the audio codec. In this case, the MLCK pin must be grounded. In this case, the output of the crystaloscillator replaces MCLK in all functions.
Table 59. Crystal Oscillator as MCLK
DEEMP Description
0 Crystal oscillator and MCLK operates as normal (default).1 Use crystal oscillator output as MCLK.
Bits [1:0] — RESERVED
These bits are reserved, and must be written to 0. If read, they read back as 0.
LAYOUT
The following layout suggestions provide optimum performance from the TSC2301. However, many portableapplications have conflicting requirements concerning power, cost, size, and weight. In general, most portabledevices have fairly clean power and grounds because most of the internal components are very low power. Thissituation means less bypassing for the converter power and less concern regarding grounding. Still, eachsituation is unique and the following suggestions should be reviewed carefully.
For optimum performance, care must be taken with the physical layout of the TSC2301 circuitry. The basic SARarchitecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, anddigital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any singleconversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easilyaffect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, andhigh power devices. The degree of error in the digital output depends on the reference voltage, layout, and theexact timing of the external event. The error can change if the external event changes in time with respect to theinternal conversion clock. The touch screen circuitry, as well as the audio headphone amplifiers, uses theHPVDD/HPGND supplies for its power, and any noise on this supply may adversely affect performance in theseblocks.
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As described earlier, the audio common-mode voltage VCM is derived directly through an internal resistor dividerbetween AVDD and AGND. Therefore, noise that couples onto AVDD/AGND is translated onto VCM and canadversely impact audio performance. The reference pins for the audio data converters, VREF+/VREF-, shouldalso be kept as clean and noise-free as possible, since noise here affects audio DAC/ADC quality. Decouplingcapacitors are recommended between VREF+ and VREF-, in addition to a series resistance between VREF+and the source of the voltage (such as connecting to the source providing AVDD).
With this in mind, power to the TSC2301 must be clean and well bypassed. A 0.1- µF ceramic bypass capacitorshould be placed as close to the device as possible on each supply pin to its respective ground pin. A 1 -µF to10- µF capacitor may also be needed if the impedance of the connection between a supply and the power supplyis high.
A bypass capacitor on the SAR Vref pin may not be absolutely necessary because this reference is buffered byan internal op amp, but a 0.1uF bypass capacitor may reduce noise on this reference. If an external referencevoltage originates from an op amp, make sure that it can drive any bypass capacitor that is used withoutoscillation.
The TSC2301 SAR converter architecture offers no inherent rejection of noise or voltage variation in regards tousing an external reference input. This is of particular concern when the reference input is tied to the powersupply. Any noise and ripple from the supply appears directly in the digital results. While high frequency noisecan be filtered out, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove.
The HPGND pin must be connected to a clean ground point. In many cases, this is the analog ground for theSAR converter. Avoid connections which are too near the grounding point of a microcontroller or digital signalprocessor. If needed, run a ground trace directly from the converter to the power supply entry or batteryconnection point. The ideal layout includes an analog ground plane dedicated to the converter and associatedanalog circuitry.
In the specific case of use with a resistive touch screen, care must be taken with the connection between theconverter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnectionshould be as short and robust as possible. Loose connections can be a source of error when the contactresistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of error in touch screen applications (e.g., applications thatrequire a back-lit LCD panel). This EMI noise can be coupled through the LCD panel to the touch screen andcause flickering of the converted data. Several things can be done to reduce this error, such as utilizing a touchscreen with a bottom-side metal layer connected to ground. This couples the majority of noise to ground.Additionally, filtering capacitors, from Y+, Y-, X+, and X- to ground, can also help. Note, however, that the use ofthese capacitors increases screen settling time and requires longer panel voltage stabilization times, as well asincreased precharge and sense times for the touch screen control circuitry of the TSC2301.
87
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TSC2301IPAG ACTIVE TQFP PAG 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TSC2301IPAGG4 ACTIVE TQFP PAG 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TSC2301IPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TSC2301IPAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TSC2301IZQZ ACTIVE BGA
MICROSTAR
JUNIOR
ZQZ 120 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
TSC2301IZQZR ACTIVE BGA
MICROSTAR
JUNIOR
ZQZ 120 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TSC2301IPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
TSC2301IZQZR BGA MI
CROSTA
R JUNI
OR
ZQZ 120 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TSC2301IPAGR TQFP PAG 64 1500 346.0 346.0 41.0
TSC2301IZQZR BGA MICROSTAR
JUNIOR ZQZ 120 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2011
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
4040282/C 11/96
Gage Plane
33
0,17
0,27
16
48
1
7,50 TYP
49
64
SQ
9,80
1,05
0,95
11,80
12,20
1,20 MAX
10,20 SQ
17
32
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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