128K x 8 Static RAM
CY62128V Family
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 27, 200 1
1*CY6212 8V Fam i ly
Features
• Low voltage range:
—2.7V–3.6V (CY621 28V)
—2.3V–2.7V (CY621 28V2 5)
—1.6V–2.0V (CY621 28V1 8)
• Low active power and standby power
• Easy memory ex pans ion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY621 28V fam ily is composed of thre e high-perf ormance
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE1), an active HIGH Chip Enable (CE2), an active
LOW Output Enable (OE) and three-state drivers. These de-
vices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Writing to the device is accomplished by taking Chip Enable
one (CE1) and Write Enable (WE) inputs LOW and the Chip
Enab le two (CE2) inp ut HIGH. Data on the ei ght I/O pins (I/ O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
Read ing f rom th e device is acc ompli shed by t aking Chip E n-
able one (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE2) HIGH. Under
these conditions, the contents of the memor y location speci-
fied by the address pins will appear on the I/O pins.
The eight inp ut/o utp ut pin s (I/O0 thro ug h I/ O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LO W , CE2 HIGH, and WE LOW).
14
15
Logic Block Diagram Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
CE
2
I/O1
I/O2
I/O3
512x256x8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11
A13
A12
A
A10
CE
1
A
A16
A9
62128V-1
62128V-2
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOIC
12
13
29
32
31
30
16
15 17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
Reverse TSOP I
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
(not to scale)
Top View
62128V-3 62128V-4
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
STSOP
Top View
(not to scal e)
30
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
1
A
11
A
5
9
10
32
1
2
3
4
5
6
7
8
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
26
25
26
27
CY62128V Fami ly
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)...........................................–0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z S tate[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +7 0°C 1.6V to 3.6V
Industrial –40°C to +85°C 1.6V to 3.6V
Product Portfolio
VCC Range
Power Dissipation (Comme rcial)
Operating (ICC)Standby (ISB2)
Product Min. Typ.[2] Max. Speed Typ.[2] Maximum Typ.[2] Maximum
CY62128V 2.7V 3.0V 3.6V 55, 70 ns 20 mA 40 mA 0.4 µA100 µA (XL = 10 µA)
CY62128V25 2.3V 2.5V 2.7V 100 ns 15 mA 20 mA 0.3 µA50 µA (LL = 12 µA)
CY62128V18 1.6V 1.8V 2.0V 200 ns 10 mA 15 mA 0.3 µA30 µA (LL = 10 µA)
Electrical Characteristics Ove r the Operating Range
CY62128V-55/70
Parameter Description Test Conditions Min. Typ.[2] Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage 2 VCC
+0.5V V
VIL Input LOW Voltage –0.5 0.8 V
IIX Input Load Curr ent GND < VI < VCC –1 ±1 +1 µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 ±1 +1 µA
ICC VCC Operat ing Supply
Current VCC = Max. ,
IOUT = 0 mA,
f = fMAX = 1/tRC
Com’l,
70 ns L20 40 mA
LL, XL 20 40
Ind’l,
55 ns LL 23 50
Ind’l,
70 ns L20 40
LL 20 40
ISB1 Automatic CE
Power-Down Current—
TTL Inputs
Max. V CC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
Com’l,
70 ns L15 300 µA
LL, XL 15 300
Coml,
55 ns LL 17 350
Ind’l L15 300
LL 15 300
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C.
CY62128V Family
3
ISB2 Automatic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE > VCC – 0.3V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
Com’l L0.4 100 µA
LL 15 µA
XL 10 µA
Ind’l L100 µA
LL 30 µA
Electrical Characteristics Over the Operating Range (continued)
CY62128V-55/70
Parameter Description Test Conditions Min. Typ.[2] Max. Unit
Electrical Characteristics Ove r the Operating Range
CY62128V25-100 CY62128V18-200
Parameter Description Test Conditions Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –0.1 mA 2.4 0.8*
VCC V
VOL Output LOW Voltage VCC = Min., IOL = 0.1 mA 0.4 0.2 V
VIH Input HIGH Voltage 2 VCC
+0.5 0.7*
VCC VCC
+0.3 V
VIL Input LOW Voltage –0.5 0.8 –0.5 0.3*
VCC V
IIX Input Load Curr ent GND < VI < VCC –1 ±1 +1 –1 ±0.1 +1 µA
IOZ Output Leakage Current GND < VO < VCC, Output
Disabled –1 ±1 +1 –1 ±0.1 +1 µA
ICC VCC Operat ing Supply
Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
L15 20 10 15 mA
LL
ISB1 Automatic CE
Power-Down Current—
TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
L15 300 5100 µA
LL
ISB2 Automatic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE > VCC – 0.3V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
L0.4 50 0.4 30 µA
LL 12 10 µA
Indust’l Temp Range LL 24 20 µA
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25 °C, f = 1 MHz,
VCC = 3.0V 6pF
COUT Output Capacitance 8pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
CY62128V Family
4
AC Test Loads and Waveforms
1.8V
VCC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
<5ns <5ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
62128V–5 62128V–6
RTH
R1
Parameters 3.3V 2.5V 1.8V Unit
R1 1213 15909 10800 Ohms
R2 1378 4487 4154 Ohms
RTH 645 3500 3000 Ohms
VTH 1.75V 0.55V 0.50V Volts
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions[4] Min. Typ.[2] Max. Unit
VDR VCC f or Data Retention 1.6 V
ICCDR Data Retention Current Com’l L VCC = 2V
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
No input may exceed
VCC+0.3V
0.4 10 µA
LL,
XL 10 µA
Ind’l L20 µA
LL 20 µA
tCDR[3] Chip Deselect to Data Retention Time 0ns
tROperation Recovery Time tRC ns
Data Retention Waveform
Note:
4. No input may exceed VCC+0.3V.
C62128V–7
1.8V1.8V
tCDR
VDR >1.6 V
DATA RETENTION MODE
tR
CE
VCC
CY62128V Family
5
Data Retention Current Graph (for “L” version only)
Switching Characteristics Over the Operating Range[5]
62128V-55 62128V-70 62128V25-100 62128V18-200
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 55 70 100 200 ns
tAA Address to Data Valid 55 70 100 200 ns
tOHA Data Hold from Address Change 510 10 10 ns
tACE CE LOW to Data Valid 55 70 100 200 ns
tDOE OE LO W to Data Valid 20 35 75 125 ns
tLZOE OE LOW to Low Z[6] 10 10 10 10 ns
tHZOE OE HIGH to High Z[6, 7] 20 25 50 75 ns
tLZCE CE LOW to Low Z[6] 10 10 10 10 ns
tHZCE CE HIGH to High Z[6, 7] 20 25 50 75 ns
tPU CE LOW to Power-Up 0 0 0 0 ns
tPD CE HIGH to Power-Down 55 70 100 200 ns
WRITE CYCLE[8, 9]
tWC Write Cycl e Time 55 70 100 200 ns
tSCE CE LOW to Write End 45 60 100 190 ns
tAW Address Set-Up to Write End 45 60 100 190 ns
tHA Address Hold from Write End 0 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 0 ns
tPWE WE Pulse Width 45 55 90 125 ns
tSD Data Set-Up to Write End 25 30 60 100 ns
tHD Data Hold from Write End 0 0 0 0 ns
tHZWE WE LOW to H igh Z[6, 7 ] 20 25 50 100 ns
tLZWE WE HIGH to Low Z[6] 5 5 10 15 ns
5. Test conditions assume signal transition time of 5 ns or less timing ref erence levels of 1.5V, input pulse lev els of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacita nce.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is le ss th an t LZOE, and tHZWE is le ss than tLZWE f or an y given de vic e.
7. tHZOE, tHZCE, and tHZWE are specifi ed with CL = 5 pF as in part (b) of A C Test Loads . Transition is measur ed ±200 mV from steady-s tate v oltage .
8. The internal write time of the memory is defined by the overlap of CE 1 LOW, CE2 HIGH, and W E LOW. CE1 and WE signal s mus t be LO W and C E2 HIGH to initiate a
write and either signal c an terminate a write by going H IGH. The data i nput set-up and hold timing should be re ferenc ed to the rising edge of the signal that t erminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LO W ) is th e sum of tHZWE and tSD.
SUPPLY VOLTAGE (V)
DATA RETEN TIO N
CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
T=25°C
1.6
2.6
3.6
(µA)
40
30
20
10
0
50
60
70
80
A
CY62128V Family
6
Switching Waveforms
Read Cycle No. 2 (OE Controlled)[11, 12]
Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14]
Notes:
10. Device is continuously selected. OE, CE = VIL, CE2=VIH.
11. WE is HIGH for read cyc le.
12. Address valid prior to or coincident with CE1 transi tion LOW and CE2 tra nsition HIGH .
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE 2 goes LOW sim ultaneo usly with WE HIGH, the o utput remains i n a h igh-imped ance stat e.
Read Cycle No. 1
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
62128V–8
[10, 11]
62128V-9
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
62128V-10
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
CY62128V Family
7
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
Switching Waveforms (continued)
62128V-11
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZOE
DATAIN VALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
NOTE 15
Truth Table
CE1CE2OE WE I/O0–I/O7Mode Power
H X X X High Z Power-Down Standby (I SB)
X L X X High Z Power-Down Standb y (I SB)
L H L H Data Out Read Active (ICC)
L H X L Data In Write Active (ICC)
L H H H High Z Selected, Outputs Disabled Active (ICC)
Note:
15. During this period, the I/Os are in output state and input signals should not be applied.
CY62128V Family
8
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
55 CY62128VLL-55ZAI ZA32 32-Lead STSOP Type 1 Industrial
70 CY62128VL-70SC S34 32-Lead 450-Mil SOIC Commercial
CY62128VLL-70SC
CY62128VL-70ZC Z32 32-Lead TSOP Type 1
CY62128VLL-70ZC
CY62128VL-70ZAC ZA32 32-Lead STSOP Type 1
CY62128VLL-70ZAC
CY62128VLL-70ZRC ZR32 32-Lead Reverse TSOP Type 1
CY62128VLL-70SI S34 32-Lead 450-Mil SOIC Industrial
CY62128VL-70ZI Z32 32-Lead TSOP Type 1
CY62128VLL-70ZI
CY62128VL-70ZAI ZA32 32-Lead STSOP Type 1
CY62128VLL-70ZAI
CY62128VLL-70ZRI ZR32 32-Lead Reverse TSOP Type 1
200 CY62128V18L-200ZC Z32 32-Lead TSOP Type 1 Commercial
CY62128V18L-200ZAI ZA32 32-Lead STSOP Type 1 Industrial
CY62128V18LL-200ZAI
Document #: 38-00547-*C
CY62128V Family
9
P ackage Diagrams
32-Lead (450 MIL) Molded SOIC S34
51-85081-A
CY62128V Family
10
P ackage Diagrams
51-85056-C
32-Lead Thin Small Outline Package Z32
CY62128V Family
11
P ackage Diagrams
32-Lead Shrunk Thin Small Outline Package ZA32
51-85094-C
CY62128V Family
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other than circ uitry embodi ed in a Cypress S emiconductor p roduct. Nor does it conv ey or imply an y license under pa tent or other rights. Cypress S emiconductor doe s not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
P ackage Diagrams
51-85089-B
32-Lead Reverse Thin Small Outline Package ZR32