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FEATURES APPLICATIONS
DESCRIPTION
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
11.3-GBPS DIFFERENTIAL VCSEL DRIVER
•10-Gigabit Ethernet Optical Transmitters•Up to 11.3-Gbps Operation
•8×and 10 ×Fibre Channel Optical•Two-Wire Digital Interface
Transmitters•Digitally Selectable Modulation Current up to
•SONET OC-192/SDH STM-64 Optical40 mA
Transmitters•Digitally Selectable Bias Current up to 20 mA
•XFP and SFP+ Transceiver Modules•Automatic Power Control (APC) Loop
•XENPAK, XPAK, X2, and 300-Pin MSA•Supports Transceiver Management System
Transponder Modules(TMS)
•Programmable Input Equalizer•Includes Laser Safety Features•Analog Temperature Sensor Output•Single 3.3-V Supply•Operating Temperature –40 °C to 85 °C•Surface-Mount, Small-Footprint, 4-mm ×4-mm, 20-Pin QFN Package
The ONET1191V is a high-speed, 3.3-V laser driver designed to directly modulate VCSELs at data rates up to11.3 Gbps.
The device provides a two-wire serial interface which allows digital control of the modulation and bias currents,eliminating the need for external components. An optional input equalizer can be used for equalization of up to300 mm (12 inches) of microstrip or stripline transmission line on FR4 printed-circuit boards.
The ONET1191V includes an integrated automatic power control (APC) loop as well as circuitry to support lasersafety and transceiver management systems.
The VCSEL driver is characterized for operation from –40 °C to 85 °C ambient temperatures and is available in asmall-footprint, 4-mm ×4-mm, 20-pin QFN package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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BLOCK DIAGRAM
DIN+
DIN–
GND
MOD+
MOD–
Power-OnReset
GND VCC
RESET
Equalizer
EQENB
EQENB
EQADJ
EQADJ RESET
MODC IMOD
MODR
ENA
MODC MODR ENA
FLT
VCC
SCK
SDA
DIS
SCK
SDA
DIS
FLT
BIAS
MONB
MONP
BIAS
MONB
MONP
PD
COMP
PD
COMP
Analog
Reference
RZTC
BGV
TS
RZTC
BGV
TS
2-WireInterfaceandControlLogicClock
FAULT
PDP
BIASC
OLE
ENA
2
2
100 W
8
8
8
55 W55 W
8
FAULTPDP
BIASCOLE
ENA
B0072-02
BiasCurrent
Generator
and
AutomaticPower
Control Loop(APC)
Modulation
Current
Generator
High-Speed
Current
Modulator
Limiting
GainStage
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
A simplified block diagram of the ONET1191V is shown in Figure 1 .
The VCSEL driver consists of an equalizer, a high-speed current modulator, a modulation current generator,power-on reset circuitry, a two-wire interface and control logic block, a bias current generator and automaticpower control loop, and an analog reference block.
Figure 1. Simplified Block Diagram of the ONET1191V
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EQUALIZER
HIGH-SPEED CURRENT MODULATOR
MODULATION CURRENT GENERATOR
TWO-WIRE INTERFACE AND CONTROL LOGIC
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
The data signal can be applied to an input equalizer by means of the input signal pins DIN+/DIN–, which provideon-chip differential 100- Ωline termination. The equalizer is enabled by setting EQENB = 0 (bit 1 of register 0).Equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line on FR4 printed circuit boardscan be achieved. The amount of equalization is digitally controlled by the two-wire interface and control logicblock and depends on the register settings EQADJ[0..7] (register 3). The equalizer can also be turned off andbypassed by setting EQENB = 1. For details about the equalizer settings, see Table 6 .
The output of the equalizer is applied to the high-speed current modulator. The limiting gain stage ensuressufficient drive amplitude and edge speed for driving the current modulator differential pair.
The modulation current is sunk from the common-emitter node of the named differential pair by means of amodulation current generator, which is digitally controlled by the two-wire interface and control logic block.
The collector nodes of the differential pair are connected to the output pins MOD+/MOD–, which include on-chip2×55- Ωback-termination to VCC. The 55- Ωback-termination helps to suppress signal distortion caused bydouble reflections for VCSEL diodes with impedances from 50 Ωthrough 75 Ω.
The modulation current generator provides the current for the current modulator described previously. The circuitis digitally controlled by the two-wire interface and control logic block.
An 8-bit-wide control bus, MODC, is used to set the desired modulation current. Furthermore, two modulationcurrent ranges are selected by means of the MODR signal. The ENA signal enables or disables the modulationcurrent generator.
The modulation current can be disabled by setting the DIS input pin to a high level. The modulation current isalso disabled in a fault condition if the fault detection enable register flag FLTEN is set.
For more information about the register functionality, see the register mapping description in Table 6 .
The ONET1191V uses a two-wire serial interface for digital control. A simplified block diagram of this interface isshown in Figure 2 . The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serialclock from a microcontroller, for example. Both inputs include 100-k Ωpullup resistors to VCC. For driving theseinputs, an open-drain output is recommended.
A write cycle consists of a START command, three address bits with MSB first, 8 data bits with MSB first, and aSTOP command. In idle mode, both the SDA and SCK lines are at a high level.
A START command is initiated by the falling edge of SDA with SCK at a high level, transitioning to a low level.
Bits are clocked into an 11-bit-wide shift register during the high level of the serial clock, SCK.
A STOP command is detected on the rising edge of SDA after SCK has changed from a low to a high level.
At the time of detection of a STOP command, the eight data bits from the shift register are copied to a selected8-bit register. Register selection occurs according to the three address bits in the shift register, which aredecoded to eight independent select signals using an 3-to-8 decoder block.
In the ONET1191V, addresses 0 (000b) through 3 (011b) are used.
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111
110
101
100
011
010
001
000
Start
Stop
SDA
SCK
8
8
8
11-BitShiftRegister
8BitsData 3Bits Addr
3
B0068-03
8
8
8-BitRegister
ControlFunctions(7Bits)
Unused(1Bit)
8-BitRegister
ModulationCurrent(8Bits)
8-BitRegister
BiasCurrent(8Bits)
8-BitRegister
EqualizerSetting(8Bits)
Start/Stop
Detector
Logic
3-to-8Decoder
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
Figure 2. Simplified Two-Wire Interface Block Diagram
The timing definition for the serial data signal SDA and the serial clock signal SCK is shown in Figure 3 . Thecorresponding timing requirements are listed in Table 1 .
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START STOP1 0 1 0 1 1
SDA
SCK
DTAR
DTAF
STRTHLD
CLKR
CLKF
CLKHI
DTAHI
DTASTP
DTAWT
DTAHLD
STOPSTP
T0077-01
REGISTER MAPPING
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
Figure 3. Two-Wire Interface Timing Diagram
Table 1. Two-Wire Interface Timing
PARAMETER DESCRIPTION MIN MAX UNIT
STRT
HLD
START hold time Time required from data falling edge to clock falling edge at START 10 nsCLK
R
, DTA
R
Clock and data rise time Clock and data rise time 10 nsCLK
F
, DTA
F
Clock and data fall time Clock and data fall time 10 nsCLK
HI
Clock high time Minimum clock high period 50 nsDTA
HI
Data high time Minimum data high period 100 nsDTA
STP
Data setup time Minimum time from data rising edge to clock rising edge 10 nsDTA
WT
Data wait time Minimum time from data falling edge to data rising edge 50 nsDTA
HLD
Data hold time Minimum time from clock falling edge to data falling edge 10 nsSTOP
STP
STOP setup time Minimum time from clock rising edge to data rising edge at STOP 10 ns
The register mapping for the register addresses 0 (000b) through 3 (011b) are shown in Table 2 throughTable 5 .Table 6 describes the circuit functionality based on the register settings.
Table 2. Register 0 (000b) Mapping
address 0 (000b)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ENA PDP PDR OLE FLTEN MODR EQENB –
Table 3. Register 1 (001b) Mapping
address 1 (001b)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
MODC7 MODC6 MODC5 MODC4 MODC3 MODC2 MODC1 MODC0
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ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
Table 4. Register 2 (010b) Mapping
address 2 (010b)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
BIASC7 BIASC6 BIASC5 BIASC4 BIASC3 BIASC2 BIASC1 BIASC0
Table 5. Register 3 (011b) Mapping
address 3 (011b)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
EQADJ7 EQADJ6 EQADJ5 EQADJ4 EQADJ3 EQADJ2 EQADJ1 EQADJ0
Table 6. Register Functionality
SYMBOL REGISTER FUNCTION
ENA Enable Enables chip when set to 1. Can be toggled low to reset a fault condition.PDP Photodiode polarity Photodiode polarity bit:1 = photodiode cathode connected to V
CC0 = photodiode anode connected to GNDPDR Photodiode current range Photodiode current range bit:With coupling ratio CR between VCSEL bias current and photodiode current = 301 = 12 µA–640 µA with 2.5 µA resolution0 = 2.5 µA–12 8 µA with 0.5 µA resolutionOLE Open loop enable Open-loop enable bit:1 = open-loop bias current control0 = closed-loop bias current controlFLTEN Fault detection enable Fault detection enable bit:1 = fault detection on0 = fault detection offMODR Modulation tail current range Laser modulation tail current range:1 = 0 mA–40 mA0 = 0 mA–20 mAEQENB Equalizer enable Equalizer enable bit1 = equalizer disabled0 = equalizer enabledMODC7 Modulation current bit 7 (MSB) Modulation current setting:MODC6 Modulation current bit 6MODC5 Modulation current bit 5 MODR = 1:MODC4 Modulation current bit 4 Modulation current up to 40 mA in 156- µA stepsMODC3 Modulation current bit 3MODC2 Modulation current bit 2 MODR = 0:MODC1 Modulation current bit 1 Modulation current up to 20 mA in 78- µA stepsMODC0 Modulation current bit 0 (LSB)BIASC7 Bias current bit 7 (MSB) Closed loop (APC):
BIASC6 Bias current bit 6 Coupling ratio CR = I
BIAS-VCSEL
/I
PD
BIASC5 Bias current bit 5 PDR = 0, BIASC = 0..255, I
BIAS-VCSEL
≤20 mA:BIASC4 Bias current bit 4 I
BIAS-VCSEL
= 0.5 µA×CR ×BIASCBIASC3 Bias current bit 3 PDR = 1, BIASC = 0..255, I
BIAS-VCSEL
≤20 mA:BIASC2 Bias current bit 2 I
BIAS-VCSEL
= 2.5 µA×CR ×BIASCBIASC1 Bias current bit 1BIASC0 Bias current bit 0 (LSB) Open loop: I
BIAS-VCSEL
= 75 µA×BIASCEQADJ7 Equalizer adjustment bit 7 (MSB) Equalizer adjustment setting
EQADJ6 Equalizer adjustment bit 6EQADJ5 Equalizer adjustment bit 5 EQENB = 1EQADJ4 Equalizer adjustment bit 4 Equalizer is turned off and bypassedEQADJ3 Equalizer adjustment bit 3
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BIAS CURRENT GENERATION AND APC LOOP
ANALOG REFERENCE
POWER-ON RESET AND REGISTER LOADING SEQUENCE
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
Table 6. Register Functionality (continued)
SYMBOL REGISTER FUNCTION
EQADJ2 Equalizer adjustment bit 2 EQENB = 0EQADJ1 Equalizer adjustment bit 1 Maximum equalization for 0000 0000EQADJ0 Equalizer adjustment bit 0 (LSB) Minimum equalization for 1111 1111
The bias current generation and APC loop are controlled by means of the two-wire interface. In open-loopoperation, selected by setting OLE = 1 (bit 4 of register 0), the bias current is set directly by the 8-bit-widecontrol word BIASC[0..7] (register 2). In automatic power control mode, selected by setting OLE = 0, the biascurrent depends on the register settings BIASC[0..7] and the coupling ratio (CR) between the VCSEL biascurrent and the photodiode current. CR = I
BIAS-VCSEL
/I
PD
.
Two photodiode current ranges can be selected by means of the PDR register (bit 5 of register 0). Thephotodiode range should be chosen to keep the laser bias control DAC close to the center of its range. Thiskeeps the laser bias current setpoint resolution high and the loop settling time constant within specification.
For details regarding the bias current setting in open- as well as in closed-loop mode, see Table 6 .
In closed-loop mode, the photodiode polarity bit, PDP, must be set for common-anode or common-cathodeconfiguration to ensure proper operation. In open-loop mode, if a photodiode is present, the photodiode polaritybit must be set to the opposite setting.
The ONET1191V VCSEL driver is supplied by a single 3.3-V ±10% supply voltage connected to the VCC pins.This voltage is referred to ground (GND).
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from whichall other internally required voltages and bias currents are derived.
An external zero-temperature-coefficient resistor must be connected from the RZTC pin of the device to ground(GND). This resistor is used to generate a precise, zero-TC current, which is required as a reference current forthe on-chip DACs.
In order to minimize the module component count, the ONET1191V provides an on-chip temperature sensor.The output voltage of the temperature sensor is available at the TS pin.
The voltage is V
TS
= (8.2 mV/ °C×TEMP) + 1140 mV, with TEMP given in °C.
Note that the voltage at TS is not buffered. As a result, TS can only drive capacitive loads.
The ONET1191V has power-on-reset circuitry, which ensures that all registers are reset to zero during startup.After the power-on to initialize time (t
INIT1
), the internal registers are ready to be loaded. It is important that theregisters are loaded in the following order:1. Bias current register (register 2, 010b)2. Modulation current register (register 1, 001b)3. Control register (register 0, 000b)4. Loading of equalizer register (register 3, 011b) is not required.
The part is ready to transmit data after the initialize to transmit time t
INIT2
, assuming that the control registerenable bit ENA is set to 1 and the disable pin DIS is low.
The ONET1191V can be disabled using either the ENA control register bit or the disable pin DIS. In both cases,the internal registers are not reset. After the disable pin DIS is set low and/or the enable bit ENA is set backto 1, the part returns to its prior output settings.
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LASER SAFETY FEATURES AND FAULT RECOVERY PROCEDURE
PACKAGE
DIS
GND
RZTC
DIN+
TS
DIN–
SCK
GND
SDA
FLT
PD
VCC
COMP
MOD+
MONP
MOD–
MONB
VCC
BGV
BIAS
RGP PACKAGE
(TOP VIEW)
1
2
3
4
5
15
14
EP 13
12
11
P0031-04
6789
10
161920 18 17
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
The ONET1191V provides built-in laser safety features. The following fault conditions are detected:•Voltage at MONB exceeds the voltage at RZTC (1.15V).•Photodiode current exceeds 150% of its set value.•Bias control DAC drops in value by more than 50% in one step.
If one or more fault conditions occur and the fault enable bit FLTEN is set to 1, the ONET1191V responds by:•Setting the VCSEL bias current to zero•Setting the modulation current to zero•Asserting and latching the FLT pin
Fault recovery is performed by the following procedure:1. The disable pin DIS and/or the enable control bit ENA are toggled for at least the fault latch reset timet
RESET
.2. The FLT pin deasserts while the disable pin DIS is asserted or the enable bit ENA is deasserted.3. If the fault condition is no longer present, the part returns to normal operation with its prior output settingsafter the disable negate time t
ON
.4. If the fault condition is still present, FLT reasserts once DIS is set to a low level, and the part does not returnto normal operation.
The ONET1191V is packaged in a small-footprint, 4-mm ×4-mm, 20-pin QFN package with a lead pitch of0,5 mm. The pinout is shown in Figure 4 .
Figure 4. Pinout of ONET1191V in a 4-mm ×4-mm, 20-Pin QFN Package
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ABSOLUTE MAXIMUM RATINGS
(1)
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
Buffered bandgap voltage with open emitter output. This is a replica of the bandgap voltage atBGV 11 Anolog-out
RZTC. For best matching, use the same 28.7-k Ωresistor to GND as used at RZTC.Sinks average bias current for VCSEL in both APC and open-loop modes. Connect to laser cathodeBIAS 16 Analog
through an inductor. BLM15HG102SN1D recommended.Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01- µF capacitor toCOMP 14 Analog
ground.DIN+ 7 Analog-in Noninverted data input. On-chip differentially 100- Ωterminated to DIN–. Must be ac-coupled.DIN– 8 Analog-in Inverted data input. On-chip differentially 100- Ωterminated to DIN+. Must be ac-coupled.DIS 1 Digital-in Disables both bias and modulation currents when set to high state. Toggle to reset a fault condition.FLT 10 Digital-out Fault detection flag.GND 6, 9, EP Supply Circuit ground. Exposed die pad (EP) must be grounded.MOD+ 19 CML-out Noninverted modulation current output. On-chip, 55- Ωback-terminated to VCC.MOD– 18 CML-out Inverted modulation current output. On-chip, 55- Ωback-terminated to VCC.Bias current monitor. Sources a 3.3% replica of the bias current. Connect an external resistor toMONB 12 Analog-out ground (GND). If the voltage at this pin exceeds 1.15 V, a fault is triggered. Typically, choose aresistor to give MONB voltage of 0.8 V at the maximum desired bias current.Photodiode current monitor. Sources a 50% replica of the photodiode current when PDR = 1 and aMONP 13 Analog-out
250% replica when PDR = 0. Connect an external resistor (5 k Ωtypical) to ground (GND).Photodiode input. Pin can source or sink current dependent on PDP register setting. PDP = 0:PD 15 Analog
source; PDP = 1: sink. Pin supplies >1.5-V reverse bias.Connect external zero-TC, 28.7-k Ωresistor to ground (GND). Used to generate a defined zero-TCRZTC 2 Analog
reference current for internal DACs.SCK 4 Digital-in Two-wire interface serial clock. Includes a 100-k Ωpullup resistor to VCC.SDA 5 Digital-in Two-wire interface serial data input. Includes a 100-k Ωpullup resistor to VCC.TS 3 Analog-out Temperature sensor output. Not buffered, capacitive load only.VCC 17, 20 Supply 3.3-V ±10% supply voltage
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
V
CC
Supply voltage
(2)
–0.3 to 4 VV
DIS
, V
RZTC
, V
TS
, V
SCK
, V
SDA
, Voltage at DIS, RZTC, TS, SCK, SDA, DIN+, DIN–, FLT, BGV, MONB, –0.3 to 4 VV
DIN+
, V
DIN–
, V
FLT
, V
BGV
, V
MONB
, MONP, CAPC, PD, BIAS, MOD+, MOD–
(2)
V
MONP
, V
CAPC
, V
PD
, V
BIAS
, V
MOD+
,V
MOD–
ESD ESD rating at all pins 2 kV (HBM)T
J,max
Maximum junction temperature 125 °CT
stg
Storage temperature range –65 to 85 °CT
A
Characterized free-air operating temperature range –40 to 85 °CT
LEAD
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.
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RECOMMENDED OPERATING CONDITIONS
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
MIN NOM MAX UNIT
V
CC
Supply voltage 2.9 3.3 3.6 VV
IH
Digital input high voltage DIS, SCK, SDA 2 VV
IL
Digital input low voltage DIS, SCK, SDA 0.8 VBias output headroom voltage V
BIAS
– GND 300 mVControl bit PDR = 1, step size = 2.5 µA 12 640Photodiode current range µAControl bit PDR = 0 step size = 0.5 µA 2.5 128R
RZTC
Zero-TC resistor value
(1)
1.15-V bandgap bias across resistor 28.4 28.7 29 k ΩControl bit EQENA = 1 200 1200V
IN
Differential input voltage swing mVp-pControl bit EQENA = 0 500 1200t
R-IN
Input rise time 20%–80% 30 55 pst
F-IN
Input fall time 20%–80% 30 55 psT
A
Operating free-air temperature –40 85 °C
(1) Changing the value alters the DAC ranges.
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DC ELECTRICAL CHARACTERISTICS
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
Over recommended operating conditions; all values are for open-loop operation, I
MODC
= 12 mA, I
BIASC
= 6 mA, andR
RZTC
= 28.7 k Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
Supply voltage 2.9 3.3 3.6 VI
MODC
= 24mA, I
BIASC
= 6 mA, including I
MODC
and I
BIASC
,
62 71EQENB = 1I
MODC
= 24mA, I
BIASC
= 6mA, including I
MODC
and I
BIASC
,I
VCC
Supply current 70 mAEQENB = 0Disabled, DIS = high and/or control bit ENA = low,
35 42EQENB = 1R
IN
Data input resistance Differential between DIN+/DIN– 85 100 125 ΩR
OUT
Data output resistance Single-ended to V
CC
45 55 65 ΩSCK, SDA, 100-k Ωpullup to V
CC
(1)
–50 10 µADigital input current
DIS
(1)
–10 10 µAV
OH
Digital output high voltage FLT, I
SOURCE
= 500 µA 2.4 VV
OL
Digital output low voltage FLT, I
SINK
= 500 µA 0.4 VI
BIAS-DIS
Bias current during disable 100 µAI
BIAS-MIN
Minimum bias current See
(2)
0.2 mAI
BIAS-MAX
Maximum bias current DAC set to maximum, open- and closed-loop 14 20 mAPhotodiode reverse biasV
PD
APC active, I
PD
= max 1.5 2.3 Vvoltage
Photodiode fault current
150%level, percent of target I
PD
(1)
Temperature sensor voltage –40 °C to 120 °C junction temperature, capacitive loadV
TS
0.5 2.5 Vrange only, with midscale calibration.
(1)
Temperature sensor
With midscale calibration
(1)
±3°Caccuracy
Temperature sensor driveI
TS
Source or sink
(1)
–1 1 µAcurrent
I
MONP
/I
PD
with control bit PDR = 1 40% 50% 60%Photodiode current monitorratio
I
MONP
/I
PD
with control bit PDR = 0 200% 265% 300%Bias current monitor ratio I
MONB
/I
BIAS
(nominal 1/30 = 3.3%). 1.2-k Ωsense resistor 2.7% 3.3% 4%V
CC-RST
V
CC
reset threshold voltage V
CC
voltage level which triggers power-on reset
(1)
2.4 2.5 2.8 VV
CC
reset threshold voltageV
CC-RSTHYS
100
(1)
mVhysteresisV
MONB-FLT
Fault voltage at MONB Fault occurs if voltage at MONB exceeds value 1.05 1.15 1.25 V
(1) Assured by simulation over process, supply, and temperature variation(2) The bias current can be set below the specified minimum according to the corresponding register setting described in the registermapping section. However, in closed-loop operation, settings below the specified value may trigger a fault.
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AC ELECTRICAL CHARACTERISTICS
TYPICAL CHARACTERISTICS
TA − Free-Air Temperature − °C
0
2
4
6
8
−40 −20 0 20 40 60 80 100
Deterministic Jitter − psPP
G002
Modulation Current − mA
0
2
4
6
8
5 10 15 20
Deterministic Jitter − psPP
G001
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
Over recommended operating conditions with 50- Ωoutput load, open-loop operation, I
MODC
= 12 mA, I
BIASC
= 6 mA, andR
RZTC
= 28.7 k Ω, unless otherwise noted. Typical operating condition is at V
CC
= 3.3 V and T
A
= 25 °C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
r-OUT
Output rise time 20%–80%, t
r-IN
< 40 ps, 50- Ωload 20 30 pst
f-OUT
Output fall time 20%–80%, t
f-IN
< 40 ps, 50- Ωload 25 30 psControl bit MODR = 1, 50- Ωload 36 45I
MOD-MAX
Maximum modulation current mAControl bit MODR = 0, 50- Ωload 18 27Control bit MODR = 1, 50- Ωload 175I
MOD-STEP
Modulation current step size µAControl bit MODR = 0, 50- Ωload 100Control bit EQENB = 1, K28.5 pattern at 11.3 Gbps 4 12DJ Deterministic output jitter ps
p-pControl bit EQENB = 0, K28.5 pattern at 11.3 Gbps, 10 20maximum equalization with 300-mm FR4 traceRJ Random output jitter 50- Ωload 0.5 0.8 ps
RMS
τ
APC
APC time constant C
APC
= 0.01 µF, I
PD
= 100 µA, PD coupling ratio CR = 40
(1)
200 µst
OFF
Transmitter disable time Rising edge of DIS to I
BIAS
≤0.1 ×I
BIAS-NOMINAL
(1)
1 5 µst
ON
Disable negate time Falling edge of DIS to I
BIAS
≥0.9 ×I
BIAS-NOMINAL
(1)
1 mst
INIT1
Power-on to initialize Power-on to registers ready to be loaded 1 10 msRegister load STOP command to part ready to transmit validt
INIT2
Initialize to transmit 2 msdata
(1)
t
RESET
DIS pulse duration Time DIS must held high to reset part
(1)
100 nst
FAULT
Fault assert time Time from fault condition to FLT high
(1)
50 µs
(1) Assured by simulation over process, supply, and temperature variation
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25 °C, I
BIASC
= 6 mA, I
MODC
= 12 mA, MODR = 0 (unless otherwise noted).
DETERMINISTIC JITTER DETERMINISTIC JITTERvs vsMODULATION CURRENT TEMPERATURE
Figure 5. Figure 6.
12
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TA − Free-Air Temperature − °C
0.0
0.1
0.2
0.3
0.4
0.5
−40 −20 0 20 40 60 80 100
Random Jitter − psrms
G004
Modulation Current − mA
0.0
0.1
0.2
0.3
0.4
0.5
5 10 15 20 25 30
Random Jitter − psrms
G003
Modulation Current − mA
0
5
10
15
20
25
30
35
5 10 15 20 25 30
tt − Transition Time − ps
G005
Fall Time
Rise Time
Bias Current Register Setting − mA
0
2
4
6
8
10
12
14
0 2 4 6 8 10 12 14 16
Open-Loop Bias Current − mA
G006
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
TYPICAL CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3 V, T
A
= 25 °C, I
BIASC
= 6 mA, I
MODC
= 12 mA, MODR = 0 (unless otherwise noted).
RANDOM JITTER RANDOM JITTERvs vsMODULATION CURRENT TEMPERATURE
Figure 7. Figure 8.
RISE TIME AND FALL TIME BIAS CURRENT IN OPEN-LOOP MODEvs vsMODULATION CURRENT BIASC REGISTER SETTING
Figure 9. Figure 10.
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Bias Current − mA
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0 2 4 6 8 10 12 14
IMONB − Bias-Monitor Current − mA
G016
Modulation Current Register Setting − mA
0
5
10
15
20
25
30
35
40
45
50
5 10 15 20 25 30 35 40
Modulation Current − mA
G007
TA − Free-Air Temperature − °C
50
55
60
65
70
75
80
−40 −20 0 20 40 60 80 100
Supply Current − mA
G008
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
TYPICAL CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3 V, T
A
= 25 °C, I
BIASC
= 6 mA, I
MODC
= 12 mA, MODR = 0 (unless otherwise noted).
BIAS-MONITOR CURRENT I
MONB
MODULATION CURRENTvs vsBIAS CURRENT MODC REGISTER SETTING, MODR = 1
Figure 11. Figure 12.
SUPPLY CURRENT
vsTEMPERATURE EYE DIAGRAM AT 11.3 GBPS
Figure 13. Figure 14.
14
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ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
TYPICAL CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3 V, T
A
= 25 °C, I
BIASC
= 6 mA, I
MODC
= 12 mA, MODR = 0 (unless otherwise noted).
EYE DIAGRAM AT 11.3 GBPS EYE DIAGRAM AT 11.3 GBPS
Figure 15. Figure 16.
EYE DIAGRAM AT 11.3 GBPSEYE DIAGRAM AT 8.5 GBPS 12" OF FR4 AT INPUTS
Figure 17. Figure 18.
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−40
−35
−30
−25
−20
−15
−10
−5
0
SDD11 − Differential Input Return Gain − dB
f − Frequency − MHz G014
10 100k100 1k 10k
−35
−30
−25
−20
−15
−10
−5
0
SDD22 − Differential Input Return Gain − dB
f − Frequency − MHz G015
10 100k100 1k 10k
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
TYPICAL CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3 V, T
A
= 25 °C, I
BIASC
= 6 mA, I
MODC
= 12 mA, MODR = 0 (unless otherwise noted).
DIFFERENTIAL S
11
DIFFERENTIAL S
22
Figure 19. Figure 20.
16
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APPLICATION INFORMATION
DIN+
DIN–
BGV
DIS
MONB
SDA
TS–
MONP
S0212-01
FLT
SDK
MONP
DIN+
DIN–
MONB
MOD–
MOD+
BIAS
DIS
TS
SCK
SDA
GND VCC
VCC
FLT
RZTC
PD
COMP
GND
BGV
VCSEL
VCC
ONET1191V
20-PinQFN
C1
0.01 Fm
C7
0.01 Fm
C6
0.1 Fm
C4
0.01 Fm
C3
0.01 Fm
C5
0.01 Fm
R
1.2k
MONB
W
R
28.7k
ZTC
W
100 DiffW100 DiffW
R
5k
MONP
W
C2
0.01 Fm
L5
BLM15HG102SN1
L4
BLM15HG102SN1
L1
BLM15HG102SN1
L3
100nH
L2
100nH
Monitor
Photodiode
NdB
Pad
NdB
Pad
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
Figure 21 shows a typical application circuit using the ONET1191V with a common-cathode VCSEL, biased toV
CC
, and driven differentially. The VCSEL driver is controlled via the two-wire interface SDA/SCK by amicroprocessor. In a typical application, the FLT, MONP, MONB, and TS outputs are also connected to themicrocontroller for transceiver management purposes. The monitor photodiode anode is grounded and thephotodiode polarity bit, PDP, must be set to 0.
The component values in Figure 21 are typical examples and may be varied according to the intendedapplication. For best performance, it is recommended to use differential drive. Single-ended VCSEL drive can beimplemented by terminating the unused driver output in a resistance that matches the VCSEL series resistance;however, the available VCSEL modulation current is halved.
Figure 21. Typical Application Circuit With a Common Cathode VCSEL
In the recommended application circuit, the purpose of the attenuator pads is to improve the signal integritybetween the VCSEL driver and the VCSEL. Because the VCSEL impedance is reactive, the pads attenuatereflections and provide a better matching impedance for the modulation current outputs. The disadvantage ofusing the attenuator pads is that the efficiency is reduced. That is, not all of the modulation current at the outputsof the VCSEL driver is available to drive the VCSEL. Table 7 lists the available modulation current at theVCSEL, I
MOD
, depending on the modulation tail current register setting, I
MODC
, the attenuator value, and theVCSEL series resistance. If care is taken in matching the output impedance of the ONET1191V to theimpedance of the VCSEL, and if controlled-impedance transmission lines are used, attenuator pads may not benecessary.
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LAYOUT GUIDELINES
ONET1191V
SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006
Table 7. I
MOD
vs I
MODC
for a Given Attenuator Pad and VCSEL
I
MODC
(mA): 50- ΩPAD VCSEL SERIES I
MOD
(mA): MODULATIONREGISTER SETTING ATTENUATION (dB) RESISTANCE ( Ω) CURRENT AT THE VCSEL
40 3 100 14.7640 6 100 10.5230 3 100 11.0730 6 100 7.8920 3 100 7.3820 6 100 5.2640 3 60 18.3340 6 60 13.1230 3 60 13.7530 6 60 9.8420 3 60 9.1720 6 60 6.56
For optimum performance, use 50- Ωtransmission lines (100- Ωdifferential) for connecting the signal source tothe DIN+ and DIN– pins and for connecting the modulation current outputs, MOD+ and MOD–, to the VCSEL.The length of the transmission lines should be kept as short as possible to reduce loss and pattern-dependentjitter.
18
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ONET1191VRGPR ACTIVE QFN RGP 20 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ONET1191VRGPRG4 ACTIVE QFN RGP 20 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ONET1191VRGPT ACTIVE QFN RGP 20 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ONET1191VRGPTG4 ACTIVE QFN RGP 20 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 20-Sep-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ONET1191VRGPR QFN RGP 20 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
ONET1191VRGPT QFN RGP 20 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ONET1191VRGPR QFN RGP 20 3000 338.1 338.1 20.6
ONET1191VRGPT QFN RGP 20 250 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
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