© Semiconductor Components Industries, LLC, 2012
January, 2012 − Rev. 3
1Publication Order Number:
EVBUM2055/D
ECLLQFP32EVB
Evaluation Board User's
Manual for High Frequency
LQFP32
INTRODUCTION
ON Semiconductor has developed an evaluation board
for the devices in 32−lead LQFP package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 32−lead LQFP device
samples. The board provides a high bandwidth 50 W
controlled impedance environment. Figures 1 and 2 show
the top and bottom view of the evaluation board, which can
be configured in several different ways, depending on
device under test (see Table 1. Configuration List).
This evaluation board manual contains:
•Information on 32−lead LQFP Evaluation Board
•Assembly Instructions
•Appropriate Lab Setup
•Bill of Materials
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Board Lay−Up
The 32−lead LQFP evaluation board is implemented in
four layers with split (dual) power supplies (see Figure 3.
Evaluation Board Lay−Up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the
50 W internal impedance in the oscilloscope as a termination
for ECL devices. The first layer or primary trace layer is
0.008″ thick Rogers RO4003 material, which is designed to
have equal electrical length on all signal traces from the
device under the test (DUT) to the sense output. The second
layer is the 1.0 oz copper ground. The FR4 dielectric
material is placed between second and third layer and
between third and fourth layer. The third layer is the power
plane (VCC and VEE) and a portion of this layer is a ground
plane. The fourth layer is the secondary trace layer.
Figure 1. Top View of the 32−lead LQFP Evaluation Board
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EVAL BOARD USER’S MANUAL
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Figure 2. Bottom View of the 32−lead LQFP Evaluation Board
Bottom View
Enlarged Bottom View
Figure 3. Evaluation Board Lay−up
LAY−UP DETAIL
4 LAYER
LAYER 1 (TOP SIDE) 1 OZ
ROGERS 4003 0.008 in
LAYER 2 (GROUND PLANE P1) 1 OZ
FR−4 0.020 in
LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ
FR−4 0.025 in
LAYER 4 (BOTTOM SIDE) 1 OZ
SILKSCREEN (TOP SIDE)
0.062 $ 0.007
Board Layout
The 32−lead LQFP evaluation board was designed to be
versatile and accommodate several different configurations.
The input, output, and power pin layout of the evaluation
board is shown in Figures 4 and 5. The evaluation board has
at least thirteen possible configurable options. Table 1, list
the devices and the relevant configuration that utilizes this
PCB board. Lists of components and simple schematics are
located in Figures 6 through 18. Place SMA connectors on
J1 through J32, 50 W chip resistors between ground pad and
Pin 1 pad through Pin 32 pad, and chip capacitors C1 through
C5 according to configuration figures. (C4 and C5 are 0.01
mF and C1, C2, and C3 are 0.1ĂmF); (See Figure 5).
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Figure 4. Evaluation Board Layout
Top View
Bottom View
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Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 24
Pin 23
Pin 22
Pin 21
Pin 20
Pin 19
Pin 18
Pin 17
Figure 5. Enlarged Bottom View of the Evaluation Board
Ground
VEE
VCC
C5
C4
Pin 16
Pin 15
Pin 14
Pin 13
Pin 12
Pin 11
Pin 10
Pin 9
Pin 25
Pin 26
Pin 27
Pin 28
Pin 29
Pin 30
Pin 31
Pin 32
Table 1. Configuration List
Configuration Comments Device
1See Figure 6 LVE164
2See Figure 7 EP016 / EP016A
3See Figure 8 EP101 / EP105
4See Figure 9 EP116
5See Figure 10 EP131
6See Figure 11 EP142
7See Figure 12 EP195 / EP196
8See Figure 13 EP445
9See Figure 14 EP446
10 See Figure 15 EP451
11 See Figure 16 EP809
12 See Figure 17 LVEP111 / LVEP210
13 See Figure 18 LVEP210S
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Evaluation Board Assembly Instructions
The 32−lead LQFP evaluation board is designed for
characterizing devices in a 50 W laboratory environment
using high bandwidth equipment. Each signal trace on the
board has a via, which has an option of placing a termination
resistor depending on the input/output configuration (see
Table 1, Configuration List). Table 17 contains the Bill of
Materials for this evaluation board.
Solder the Device on the Evaluation Board
The soldering can be accomplished by hand soldering or
soldering re−flow techniques. Make sure pin 1 of the device
is located next to the white dotted mark and all the pins are
aligned to the footprint pads. Solder the 32−lead LQFP
device to the evaluation board.
Connecting Power and Ground Planes
For standard ECL lab setup and test, a split (dual) power
supply is required enabling the 50 W internal impedance in
the oscilloscope to be used as a termination of the ECL
signals (VTT = VCC – 2.0 V, in split power supply setup, VTT
is the system ground, VCC is 2.0 V, and VEE is –3.0 V or
–1.3 V; see Table 2, Power Supply Levels).
Table 2. Power Supply Levels
Power Supply VCC VEE GND
5.0 V 2.0 V −3.0 V 0.0 V
3.3 V 2.0 V −1.3 V 0.0 V
2.5 V 2.0 V −0.5 V 0.0 V
Connect three banana jack sockets to VCC, VEE, and GND
labeled holes. Wire bond the appropriate device pin pad on
the bottom side of the board to VCC and VEE power stripes.
(Device specific, please see configuration for each desired
device. See Figure 5)
It is recommended to solder 0.01 mF capacitors to C4 and
C5 to reduce the unwanted noise from the power supplies.
C1, C2, and C3 pads are provided for 0.1 mF capacitor to
further diminish the noise from the power supplies. Adding
capacitors can improve edge rates, reduce overshoot and
undershoot.
Termination
All ECL outputs need to be terminated to VTT (VTT = VCC
–2.0 V = GND) via a 50 W resistor. 0402 chip resistor pads
are provided on the bottom side of the evaluation board to
terminate the ECL driver (More information on termination
is provided in AN8020). Solder the chip resistors to the
bottom side of the board between the appropriate input of the
device pin pads and the ground pads. For ease of assembly,
it is advised to place and solder termination resistors on its
vertical (side) position, instead of its original or flat position.
Installing the SMA Connectors
Each configuration indicates the number of SMA
connectors needed to populate an evaluation board for a
given configuration. Each input and output requires one
SMA connector. Attach all the required SMA connectors
onto the board and solder the connectors to the board on J1
through J32. Please note that alignment of the signal
connector pin of the SMA can influence the lab results. The
reflection and launch of the signals are largely influenced by
imperfect alignment and soldering of the SMA connector.
Validating the Assembled Board
After assembling the evaluation board, it is recommended
to perform continuity checks on all soldered areas before
commencing with the evaluation process. Time Domain
Reflectometry (TDR) is another highly recommended
validation test.
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CONFIGURATIONS
J2
J3
J4
J5
J6
J10
J11
J12
J31 J30 J29 J28 J27 J26
J13
J15
J19
J20
J21
J22
J23
Figure 6. Configuration 1
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
LVE164
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
LVE164
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
N
N
N
J28
J27
J26
J25
J24
J23
J22
31
Y
Y
N
30
Y
Y
N
29
Y
Y
N
28
Y
Y
N
27
Y
Y
N
26
Y
Y
N
25
N
N
N
24
N
N
N
23
Y
Y
N
22
Y
Y
N
21
J21
J20
J19
J18
Y
Y
N
J17
J16
J15
J14
J13
J12
J11
20
Y
Y
N
19
Y
Y
N
18
N
N
Y
17
N
N
N
16
N
N
N
15
Y
Y
N
14
N
N
Y
13
Y
N
N
12
Y
N
N
11
Y
Y
N
10
J10
J9
J8
J7
Y
Y
N
J6
J5
J4
J3
J2
J1
9
Y
Y
N
8
N
N
N
7
N
N
Y
6
Y
Y
N
5
Y
Y
N
4
Y
Y
N
3
Y
Y
N
2
Y
Y
N
1
N
N
N
Table 3. Configuration 1 (Device LVE164)
J9
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J2
J3
J4
J5
J6
J7
J10
J11
J12
J31 J30 J29 J27 J26
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
Figure 7. Configuration 2
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
EP016 / EP016A
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
EP016 / EP016A
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
N
N
Y
J28
J27
J26
J25
J24
J23
J22
31
Y
N
N
30
Y
N
N
29
Y
N
N
28
N
N
Y
27
Y
Y
N
26
Y
Y
N
25
Y
Y
N
24
Y
N
N
23
Y
Y
N
22
Y
Y
N
21
J21
J20
J19
J18
Y
Y
N
J17
J16
J15
J14
J13
J12
J11
20
Y
Y
N
19
Y
Y
N
18
Y
Y
N
17
Y
Y
N
16
Y
Y
N
15
Y
Y
N
14
Y
Y
N
13
N
N
Y
12
Y
N
N
11
Y
N
N
10
J10
J9
J8
J7
Y
N
N
J6
J5
J4
J3
J2
J1
9
N
N
Y
8
N
N
Y
7
Y
Y
N
6
Y
N
N
5
Y
N
N
4
Y
N
N
3
Y
N
N
2
Y
N
N
1
N
N
Y
Table 4. Configuration 2 (Device EP016 and EP016A)
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J2
J3
J4
J5
J6
J7
J11
J12
J30 J29 J27 J26
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
Figure 8. Configuration 3
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
EP101 / EP105
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
EP101 / EP105
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
N
N
Y
J28
J27
J26
J25
J24
J23
J22
31
N
N
Y
30
Y
N
N
29
Y
N
N
28
N
N
Y
27
Y
Y
N
26
Y
Y
N
25
Y
Y
N
24
Y
Y
N
23
Y
Y
N
22
Y
Y
N
21
J21
J20
J19
J18
Y
Y
N
J17
J16
J15
J14
J13
J12
J11
20
Y
Y
N
19
Y
Y
N
18
Y
Y
N
17
Y
Y
N
16
Y
Y
N
15
Y
Y
N
14
Y
Y
N
13
N
N
Y
12
Y
Y
N
11
Y
Y
N
10
J10
J9
J8
J7
N
N
Y
J6
J5
J4
J3
J2
J1
9
N
N
N
8
N
N
Y
7
Y
N
N
6
Y
N
N
5
Y
N
N
4
Y
N
N
3
Y
N
N
2
Y
N
N
1
N
N
Y
Table 5. Configuration 3 (Device EP101 and EP105)
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J2
J3
J4
J5
J6
J7
J10
J11
J31 J30 J29 J27 J26
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
Figure 9. Configuration 4
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
EP116
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
EP116
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
Y
Y
N
J28
J27
J26
J25
J24
J23
J22
31
Y
Y
N
30
Y
Y
N
29
Y
Y
N
28
N
N
Y
27
Y
Y
N
26
Y
Y
N
25
Y
Y
N
24
Y
Y
N
23
Y
Y
N
22
Y
Y
N
21
J21
J20
J19
J18
Y
N
N
J17
J16
J15
J14
J13
J12
J11
20
Y
N
N
19
Y
N
N
18
Y
N
N
17
N
N
Y
16
N
N
Y
15
Y
N
N
14
Y
N
N
13
N
N
Y
12
N
N
Y
11
Y
N
N
10
J10
J9
J8
J7
Y
N
N
J6
J5
J4
J3
J2
J1
9
N
N
Y
8
N
N
Y
7
Y
N
N
6
Y
N
N
5
Y
N
N
4
Y
N
N
3
Y
N
N
2
Y
Y
N
1
Y
Y
N
Table 6. Configuration 4 (Device EP116)
J1
J32
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J2
J3
J4
J5
J6
J7
J10
J11
J12
J31 J30 J29 J27 J26
J14
J15
J17
J18
J19
J20
J21
J22
J23
J24
Figure 10. Configuration 5
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
EP131
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
EP131
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
Y
Y
N
J28
J27
J26
J25
J24
J23
J22
31
Y
Y
N
30
Y
Y
N
29
Y
Y
N
28
N
N
Y
27
Y
Y
N
26
Y
Y
N
25
N
N
Y
24
Y
N
N
23
Y
N
N
22
Y
N
N
21
J21
J20
J19
J18
Y
N
N
J17
J16
J15
J14
J13
J12
J11
20
Y
N
N
19
Y
N
N
18
Y
N
N
17
Y
N
N
16
N
N
Y
15
Y
Y
N
14
Y
Y
N
13
N
N
Y
12
Y
Y
N
11
Y
Y
N
10
J10
J9
J8
J7
Y
Y
N
J6
J5
J4
J3
J2
J1
9
N
N
Y
8
Y
Y
N
7
Y
Y
N
6
Y
Y
N
5
Y
Y
N
4
Y
Y
N
3
Y
Y
N
2
Y
Y
N
1
Y
Y
N
Table 7. Configuration 5 (Device EP131)
J32
J1
J8
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J2
J3
J4
J5
J6
J7
J10
J11
J12
J31 J30 J29 J27 J26
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
Figure 11. Configuration 6
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
EP142
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
EP142
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
N
N
Y
J28
J27
J26
J25
J24
J23
J22
31
Y
Y
N
30
Y
Y
N
29
Y
Y
N
28
N
N
Y
27
Y
Y
N
26
Y
Y
N
25
Y
Y
N
24
Y
Y
N
23
Y
Y
N
22
Y
N
N
21
J21
J20
J19
J18
Y
N
N
J17
J16
J15
J14
J13
J12
J11
20
Y
N
N
19
Y
N
N
18
Y
N
N
17
N
N
Y
16
N
N
Y
15
N
N
Y
14
N
N
Y
13
N
N
Y
12
Y
N
N
11
Y
N
N
10
J10
J9
J8
J7
Y
N
N
J6
J5
J4
J3
J2
J1
9
Y
Y
N
8
Y
Y
N
7
Y
Y
N
6
Y
Y
N
5
Y
Y
N
4
Y
Y
N
3
Y
Y
N
2
Y
Y
N
1
Y
Y
N
Table 8. Configuration 6 (Device EP142)
J8
J9
J1
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J2
J3
J4
J5
J7
J10
J11
J12
J31 J30 J29 J27 J26
J14
J15
J16
J17
J20
J21
J23
J25
Figure 12. Configuration 7
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
EP195 / EP196
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
EP195 / EP196
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
Y
Y
N
J28
J27
J26
J25
J24
J23
J22
31
Y
Y
N
30
Y
Y
N
29
Y
Y
N
28
N
N
Y
27
Y
Y
N
26
Y
Y
N
25
Y
Y
N
24
N
N
Y
23
Y
Y
N
22
N
N
Y
21
J21
J20
J19
J18
Y
N
N
J17
J16
J15
J14
J13
J12
J11
20
Y
N
N
19
N
N
Y
18
N
N
Y
17
*
N
N
16
Y
Y
N
15
Y
Y
N
14
N
N
Y
13
Y
Y
N
12
Y
Y
N
11
Y
Y
N
10
J10
J9
J8
J7
Y
Y
N
J6
J5
J4
J3
J2
J1
9
N
N
Y
8
Y
N
N
7
Y
N
N
6
Y
N
N
5
Y
Y
N
4
Y
Y
N
3
Y
Y
N
2
Y
Y
N
1
Y
Y
N
Table 9. Configuration 7 (Device EP195 and EP196)
J32
J1
J8
Only for EP196
* Only for EP196
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J2
J3
J4
J5
J6
J7
J10
J11
J31 J30 J29 J27 J26
J14
J15
J18
J19
J21
J22
J23
J25
Figure 13. Configuration 8
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
EP445
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
EP445
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
N
N
Y
J28
J27
J26
J25
J24
J23
J22
31
Y
Y
N
30
Y
Y
N
29
Y
N
N
28
N
N
Y
27
Y
Y
N
26
Y
Y
N
25
Y
Y
N
24
N
N
Y
23
Y
Y
N
22
Y
Y
N
21
J21
J20
J19
J18
Y
N
N
J17
J16
J15
J14
J13
J12
J11
20
N
N
Y
19
Y
N
N
18
Y
N
N
17
N
N
Y
16
N
N
Y
15
Y
N
N
14
Y
N
N
13
N
N
Y
12
N
N
Y
11
Y
N
N
10
J10
J9
J8
J7
Y
N
N
J6
J5
J4
J3
J2
J1
9
Y
N
N
8
Y
N
N
7
Y
Y
N
6
Y
N
N
5
Y
Y
N
4
Y
Y
N
3
Y
Y
N
2
Y
Y
N
1
Y
Y
N
Table 10. Configuration 8 (Device EP445)
J9
J1
ECLLQFP32EVB
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J2
J3
J4
J5
J6
J7
J11
J12
J31 J30 J29 J27 J26
J14
J15
J17
J18
J19
J20
J21
J22
J23
J24
Figure 14. Configuration 9
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
EP446
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
EP446
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
N
N
Y
J28
J27
J26
J25
J24
J23
J22
31
Y
N
N
30
Y
Y
N
29
Y
Y
N
28
N
N
Y
27
Y
N
N
26
Y
N
N
25
N
N
Y
24
Y
Y
N
23
Y
Y
N
22
Y
Y
N
21
J21
J20
J19
J18
Y
Y
N
J17
J16
J15
J14
J13
J12
J11
20
Y
Y
N
19
Y
Y
N
18
Y
Y
N
17
Y
Y
N
16
N
N
Y
15
Y
N
N
14
Y
N
N
13
N
N
Y
12
Y
N
N
11
Y
N
N
10
J10
J9
J8
J7
N
N
Y
J6
J5
J4
J3
J2
J1
9
N
N
Y
8
N
N
Y
7
Y
Y
N
6
Y
Y
N
5
Y
N
N
4
Y
Y
N
3
Y
Y
N
2
Y
Y
N
1
N
N
Y
Table 11. Configuration 9 (Device EP446)
ECLLQFP32EVB
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15
J2
J3
J4
J5
J8
J7
J10
J11
J12
J31 J30 J29 J27 J26
J14
J15
J17
J18
J20
J21
J22
J23
J24
J25
Figure 15. Configuration 10
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
EP451
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
EP451
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
Y
Y
N
J28
J27
J26
J25
J24
J23
J22
31
Y
Y
N
30
Y
Y
N
29
Y
Y
N
28
N
N
Y
27
Y
Y
N
26
Y
Y
N
25
Y
Y
N
24
Y
Y
N
23
Y
Y
N
22
Y
Y
N
21
J21
J20
J19
J18
Y
N
N
J17
J16
J15
J14
J13
J12
J11
20
Y
N
N
19
N
N
Y
18
Y
N
N
17
Y
N
N
16
N
N
Y
15
Y
N
N
14
Y
N
N
13
N
N
Y
12
Y
N
N
11
Y
N
N
10
J10
J9
J8
J7
Y
N
N
J6
J5
J4
J3
J2
J1
9
Y
N
N
8
Y
N
N
7
Y
N
N
6
N
N
Y
5
Y
Y
N
4
Y
Y
N
3
Y
Y
N
2
Y
Y
N
1
Y
Y
N
Table 12. Configuration 10 (Device EP451)
J9
J1
J32
ECLLQFP32EVB
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16
J2
J3
J4
J5
J6
J8
J10
J11
J12
J31 J30 J29 J28 J27 J26
J14
J15
J18
J19
J20
J21
J22
J23
Figure 16. Configuration 11
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
EP809
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE = VCCO
VCC
EXPANDED BOTTOM VIEW
EP809
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
N
N
Y
J28
J27
J26
J25
J24
J23
J22
31
Y
N
N
30
Y
N
N
29
Y
N
N
28
Y
N
N
27
Y
N
N
26
Y
N
N
25
N
N
Y
24
N
N
Y
23
Y
N
N
22
Y
N
N
21
J21
J20
J19
J18
Y
N
N
J17
J16
J15
J14
J13
J12
J11
20
Y
N
N
19
Y
N
N
18
Y
N
N
17
N
N
Y
16
N
N
Y
15
Y
N
N
14
Y
N
N
13
Y
N
N
12
Y
N
N
11
Y
N
N
10
J10
J9
J8
J7
Y
N
N
J6
J5
J4
J3
J2
J1
9
N
N
Y
8
Y
Y
N
7
N
N
Y
6
Y
Y
N
5
Y
Y
N
4
Y
Y
N
3
Y
Y
N
2
Y
Y
N
1
N
N
Y
Table 13. Configuration 11 (Device EP809)
J13
ECLLQFP32EVB
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J2
J3
J4
J6
J7
J10
J11
J12
J31 J30 J29 J28 J27 J26
J14
J15
J17
J18
J19
J20
J21
J22
J23
J24
Figure 17. Configuration 12
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
LVEP111 / LVEP210
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
LVEP111 / LVEP210
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
N
N
Y
J28
J27
J26
J25
J24
J23
J22
31
Y
N
N
30
Y
N
N
29
Y
N
N
28
Y
N
N
27
Y
N
N
26
Y
N
N
25
N
N
Y
24
Y
N
N
23
Y
N
N
22
Y
N
N
21
J21
J20
J19
J18
Y
N
N
J17
J16
J15
J14
J13
J12
J11
20
Y
N
N
19
Y
N
N
18
Y
N
N
17
Y
N
N
16
N
N
Y
15
Y
N
N
14
Y
N
N
13
Y
N
N
12
Y
N
N
11
Y
N
N
10
J10
J9
J8
J7
Y
N
N
J6
J5
J4
J3
J2
J1
9
N
N
Y
8
N
N
Y
7
Y
Y
N
6
Y
Y
N
5
Y
N
N
4
Y
Y
N
3
Y
Y
N
2
Y
Y
N
1
N
N
Y
Table 14. Configuration 12 (Device LVEP111 and LVEP210)
J13
* Pin 2 is No Connect for LVEP210
ECLLQFP32EVB
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18
J2
J3
J4
J6
J7
J10
J11
J12
J31 J30 J29 J28 J27 J26
J14
J15
J17
J18
J19
J20
J21
J22
J23
J24
Figure 18. Configuration 13
0402 CHIP
RESISTOR
50 W
PIN 1
WIRE
NORMAL TOP VIEW
LVEP210S
0805 CHIP
CAPACITOR
0.01 mF
SMA CONNECTORS
BANANA
JACK PLUG 0603 CHIP
CAPACITOR
0.1 mF
VEE
VCC
EXPANDED BOTTOM VIEW
LVEP210S
32
Power
Resistor
Connector
Pin #
Device
J32
J31
J30
J29
N
N
Y
J28
J27
J26
J25
J24
J23
J22
31
Y
N
N
30
Y
N
N
29
Y
N
N
28
Y
N
N
27
Y
N
N
26
Y
N
N
25
N
N
Y
24
Y
N
N
23
Y
N
N
22
Y
N
N
21
J21
J20
J19
J18
Y
N
N
J17
J16
J15
J14
J13
J12
J11
20
Y
N
N
19
Y
N
N
18
Y
N
N
17
Y
N
N
16
N
N
Y
15
Y
N
N
14
Y
N
N
13
Y
N
N
12
Y
N
N
11
Y
N
N
10
J10
J9
J8
J7
Y
N
N
J6
J5
J4
J3
J2
J1
9
N
N
Y
8
N
N
Y
7
Y
Y
N
6
Y
Y
N
5
Y
Y
N
4
Y
Y
N
3
Y
Y
N
2
Y
Y
N
1
N
N
Y
Table 15. Configuration 13 (Device LVEP210S)
J13
ECLLQFP32EVB
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19
LAB SETUP
Figure 19. Example of Standard Lab Setup (Configuration 12)
D
U
T
Differential
Signal
Generator
Test Measuring
Equipment
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Trigger
Trigger
Out1
Out1 J4
J3
J31
J30
J29
J28
J27
J26
J24
J23
VCC GND VEE
Power Supply
1. Connect appropriate power supplies to VCC, VEE,
and GND.
For standard ECL lab setup and test, a split (dual)
power supply is required enabling the 50 W
internal impedance in the oscilloscope to be used
as a termination of the ECL signals (VTT = VCC
– 2.0 V, in split power supply setup, VTT is the
system ground, VCC is 2.0 V, and VEE is –3.0 V or
–1.3 V; see Table 16).
2. Connect a signal generator to the input SMA
connectors. Setup input signal according to the
device data sheet.
3. Connect a test measurement device on the device
output SMA connectors.
NOTE: The test measurement device must contain 50 W
termination.
Table 16. Power Supply Levels
Power Supply VCC VEE GND
5.0 V 2.0 V −3.0 V 0.0 V
3.3 V 2.0 V −1.3 V 0.0 V
2.5 V 2.0 V −0.5 V 0.0 V
Table 17. Bill of Materials
Components Manufacturer Description Part Number Web Site
SMA Connector Johnson
Components*
SMA Connector, Side Launch,
Gold Plated
142−0701−851 http://www.johnsoncomponents.com
Banana Jack Keystone* Standard Jack 6096 http://www.keyelco.com
Miniature Jack 6090
Chip Capacitor Johanson
Dielectric*
0603/0805/1205 0.01 mF
Chip Capacitor
−http://www.johansondielectrics.com
0603/0805/1205 0.1 mF
Chip Capacitor
−
Chip Resistor Panasonic* 0402 50 W ±1% Precision Think
Film Chip Resistor
ERJ−2RKF49R9X http://www.panasonic.com
Evaluation Board ON Semiconductor LQFP32 Evaluation Board ECLLQFP32EVB http://www.onsemi.com
Device Samples ON Semiconductor LQFP32 Package Device Various http://www.onsemi.com
*Components are available through most distributors, i.e. www.newark.com, www.digikey.com.
ECLLQFP32EVB
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20
Figure 20. Gerber Files
Top View
Second Layer (Ground Plane)
ECLLQFP32EVB
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21
Figure 21. Gerber Files
Third Layer (Power and Ground Plane)
(Left side − VCC, Right side − VEE, Middle Box − Ground)
Bottom Layer
ECLLQFP32EVB
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