LTC3388-1/LTC3388-3 20V High Efficiency Nanopower Step-Down Regulator DESCRIPTION FEATURES 720nA Input IQ in Regulation (No Load), VIN = 4V nn 820nA Input I in Regulation (No Load), V = 20V Q IN nn 400nA Input I in UVLO Q nn 2.7V to 20V Input Operating Range nn Up to 50mA of Output Current nn Pin Selectable Output Voltages: nn 1.2V, 1.5V, 1.8V, 2.5V (LTC3388-1) nn 2.8V, 3.0V, 3.3V, 5.0V (LTC3388-3) nn High Efficiency Hysteretic Synchronous DC/DC Conversion nn Standby Mode Disables Buck Switching nn Available in 10-Lead MSE and 3mm x 3mm DFN Packages nn APPLICATIONS The LTC(R)3388-1/LTC3388-3 are high efficiency step-down DC/DC converters with internal high side and synchronous power switches that draw only 720nA typical DC supply current at no load while maintaining output voltage regulation. Capable of supplying 50mA of load current, the LTC3388-1/ LTC3388-3 also incorporate an accurate undervoltage lockout (UVLO) feature to disable the converter and maintain a low quiescent current state when the input voltage falls below 2.3V. In regulation, the LTC3388-1/LTC3388-3 enter a sleep state in which both input and output quiescent currents are minimal. The buck converter turns on and off as needed to maintain regulation. An additional standby mode disables buck switching while the output is in regulation for short duration loads requiring low ripple. Output voltages of 1.2V, 1.5V, 1.8V, 2.5V (LTC3388-1) and 2.8V, 3.0V, 3.3V, 5.0V (LTC3388-3) are pin selectable. The LTC3388-1/LTC3388-3 can operate with VIN up to 20V while the no load quiescent current remains below 1A. Keep Alive Power for Portable Products Industrial Control Supplies nn Distributed Power Systems nn Battery-Operated Devices nn nn L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Efficiency vs Load Current 50mA Step-Down Converter 100 1F 6V 2.2F 25V VIN CAP LTC3388-1/ LTC3388-3 EN PGOOD STBY D0, D1 VOUT 47F 6V 2 GND OUTPUT VOLTAGE SELECT VOUT = 1.8V, L = 100H 80 100H SW VOUT VIN2 4.7F 6V 90 EFFICIENCY (%) 2.7V TO 20V 338813 TA01a 70 60 50 40 30 20 VIN = 3.0V VIN = 10V VIN = 20V 10 0 1 10 100 1m LOAD CURRENT (A) 10m 338813 TA01b 338813fa For more information www.linear.com/LTC3388 1 LTC3388-1/LTC3388-3 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN.............................................................. -0.3V to 22V D0, D1...............-0.3V to [Lesser of (VIN2 + 0.3V) or 6V] CAP....................... [Higher of -0.3V or (VIN - 6V)] to VIN VIN2, VOUT...........-0.3V to [Lesser of (VIN + 0.3V) or 6V] EN, STBY...................................................... -0.3V to 6V PGOOD.......................................................... -0.3V to 6V ISW........................................................................210mA Operating Junction Temperature Range (Notes 2, 3)............................................. -40C to 125C Storage Temperature Range................... -65C to 125C Lead Temperature (Soldering, 10 sec) MSE Only............................................................... 300C PIN CONFIGURATION TOP VIEW EN 1 STBY 2 CAP 3 VIN 4 SW 5 TOP VIEW 10 PGOOD 11 GND EN STBY CAP VIN SW 9 D0 8 D1 7 VIN2 6 VOUT 1 2 3 4 5 11 GND 10 9 8 7 6 PGOOD D0 D1 VIN2 VOUT MSE PACKAGE 10-LEAD PLASTIC MSOP DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W, JC = 7.5C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125C, JA = 45C/W, JC = 10C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3388EDD-1#PBF LTC3388EDD-1#TRPBF LFWN 10-Lead (3mm x 3mm) Plastic DFN -40C to 125C LTC3388IDD-1#PBF LTC3388IDD-1#TRPBF LFWN 10-Lead (3mm x 3mm) Plastic DFN -40C to 125C LTC3388EMSE-1#PBF LTC3388EMSE-1#TRPBF LTFWM 10-Lead Plastic MSOP -40C to 125C LTC3388IMSE-1#PBF LTC3388IMSE-1#TRPBF LTFWM 10-Lead Plastic MSOP -40C to 125C LTC3388EDD-3#PBF LTC3388EDD-3#TRPBF LFWQ 10-Lead (3mm x 3mm) Plastic DFN -40C to 125C LTC3388IDD-3#PBF LTC3388IDD-3#TRPBF LFWQ 10-Lead (3mm x 3mm) Plastic DFN -40C to 125C LTC3388EMSE-3#PBF LTC3388EMSE-3#TRPBF LTFWP 10-Lead Plastic MSOP -40C to 125C LTC3388IMSE-3#PBF LTC3388IMSE-3#TRPBF LTFWP 10-Lead Plastic MSOP -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 338813fa For more information www.linear.com/LTC3388 LTC3388-1/LTC3388-3 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are for TA = 25C (Note 2). Unless otherwise noted, VIN = 5.5V. SYMBOL PARAMETER VIN Input Voltage Range CONDITIONS IQ VIN Quiescent Current When Enabled UVLO Sleep Sleep Active VIN = 2V VIN = 4V VIN = 20V ISW = 0A (Note 4) IQ,STBY VIN Quiescent Current Enabled, in Standby Sleeping Not Sleeping IQ,SD MIN TYP UNITS V 400 720 820 150 600 1100 1200 250 nA nA nA A VIN = 4V VIN = 4V 720 2000 1100 3000 nA nA VIN Quiescent Current When Disabled VIN = 4V VIN = 20V 520 620 800 900 nA nA VUVLO VIN Undervoltage Lockout Threshold VIN Rising VIN Falling VOUT Regulated Output Voltage (LTC3388-1) 1.2V Output Selected; D1 = 0, D0 = 0 Sleep Threshold Wake-Up Threshold 1.5V Output Selected; D1 = 0, D0 = 1 Sleep Threshold Wake-Up Threshold 1.8V Output Selected; D1 = 1, D0 = 0 Sleep Threshold Wake-Up Threshold 2.5V Output Selected; D1 = 1, D0 = 1 Sleep Threshold Wake-Up Threshold VOUT Regulated Output Voltage (LTC3388-3) 2.8V Output Selected; D1 = 0, D0 = 0 Sleep Threshold Wake-Up Threshold 3.0V Output Selected; D1 = 0, D0 = 1 Sleep Threshold Wake-Up Threshold 3.3V Output Selected; D1 = 1, D0 = 0 Sleep Threshold Wake-Up Threshold 5.0V Output Selected; D1 = 1, D0 = 1 Sleep Threshold Wake-Up Threshold 2.7 MAX 20 l l l 2.15 2.5 2.3 2.65 V V l l 1.140 1.208 1.192 1.260 V V l l 1.440 1.508 1.492 1.560 V V l l 1.737 1.808 1.792 1.863 V V l l 2.400 2.508 2.492 2.600 V V l l 2.688 2.816 2.784 2.912 V V l l 2.895 3.016 2.984 3.105 V V l l 3.201 3.316 3.284 3.399 V V l l 4.820 5.016 4.984 5.180 V V 83 92 PGOOD Threshold As a Percentage of the Selected VOUT VOL, PGOOD PGOOD Output Low Voltage 100A Into Pin IVOUT Output Quiescent Current LTC3388-1: VOUT = 2.5V LTC3388-3: VOUT = 5.0V IPEAK PMOS Switch Peak Current l 100 IOUT Available Output Current l 50 RP, BUCK PMOS Switch On-Resistance RN, BUCK 60 120 150 NMOS Switch On-Resistance 1.3 l 100 V nA nA 210 mA mA 1.1 Maximum Duty Cycle % 0.2 l % 338813fa For more information www.linear.com/LTC3388 3 LTC3388-1/LTC3388-3 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are for TA = 25C (Note 2). Unless otherwise noted, VIN = 5.5V. SYMBOL PARAMETER VIH D0/D1/EN/STBY Input High Voltage CONDITIONS l VIL(D0, D1) D0/D1 Input Low Voltage l 0.4 V l 150 mV 10 nA VIL(EN,STBY) EN/STBY Input Low Voltage IIH D0/D1/EN/STBY Input High Current IIL D0/D1/EN/STBY Input Low Current MIN TYP MAX UNITS 1.2 V 10 nA Additional IQ at VIN with EN at VIH(MIN) VEN = 1.2V, VIN = 4V 40 nA Additional IQ at VIN with STBY at VIH(MIN) VSTBY = 1.2V, VIN = 4V 40 nA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3388-1/LTC3388-3 are tested under pulsed load conditions such that TJ TA. The LTC3388E-1/LTC3388E-3 are guaranteed to meet specifications from 0C to 85C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3388I-1/LTC3388I-3 are guaranteed over the -40C to 125C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: The junction temperature (TJ, in C) is calculated from the ambient temperature (TA, in C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD * JA), where JA (in C/W) is the package thermal impedance. Note 4: Dynamic supply current is higher due to gate charge being delivered at the switching frequency. TYPICAL PERFORMANCE CHARACTERISTICS Input IQ vs VIN, UVLO 1600 125C 700 INPUT IQ (nA) INPUT IQ (nA) 25C -40C 300 4 85C 1000 25C 800 -40C 0 0.5 1 1.5 VIN (V) 2 2.5 338813 G01 200 125C 800 85C 600 25C -40C 400 200 400 100 Input IQ vs VIN , EN Low 1000 600 200 0 125C 1200 85C 400 D1 = D0 = 0 1200 1400 600 500 Input IQ vs VIN, No Load INPUT IQ (nA) 800 2 4 6 8 10 12 VIN (V) 14 16 18 20 338813 G02 0 0 2 4 6 8 10 12 14 16 18 20 VIN (V) 338813 G03 338813fa For more information www.linear.com/LTC3388 LTC3388-1/LTC3388-3 TYPICAL PERFORMANCE CHARACTERISTICS UVLO vs Temperature 180 2.8 RP,BUCK /RN,BUCK vs Temperature IPEAK vs Temperature 2.0 170 1.8 160 1.6 2.6 IPEAK (mA) VUVLO (V) 2.4 UVLO FALLING RDS(ON) () NMOS UVLO RISING 150 1.4 140 1.2 130 1.0 PMOS 2.2 2.0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 120 -50 125 -25 0 25 50 75 TEMPERATURE (C) 100 338813 G06 1.2V Output vs Temperature (LTC3388-1) Operating Waveforms 1.5V Output vs Temperature (LTC3388-1) 1.24 VOUT 50mV/DIV AC-COUPLED 1.54 SLEEP THRESHOLD 1.22 1.50 VOUT (V) VOUT (V) 1.16 1.14 1.12 5s/DIV VIN = 5.5V, VOUT = 1.8V ILOAD = 20mA L = 22H, COUT = 47F 338813 G07 1.44 1.42 PGOOD FALLING 1.38 1.08 1.06 -50 1.46 1.40 PGOOD FALLING 1.10 WAKE-UP THRESHOLD 1.48 WAKE-UP THRESHOLD 1.18 INDUCTOR CURRENT 100mA/DIV SLEEP THRESHOLD 1.52 1.20 VSW 2V/DIV 0V 5 25 45 65 85 105 125 TEMPERATURE (C) 338813 G05 338813 G04 0mA 0.8 -55 -35 -15 125 1.36 -25 0 25 50 75 TEMPERATURE (C) 100 1.34 -50 125 -25 0 25 50 75 TEMPERATURE (C) 100 338813 G08 1.8V Output vs Temperature (LTC3388-1) 2.55 SLEEP THRESHOLD 2.85 WAKE-UP THRESHOLD 1.70 2.40 2.35 PGOOD FALLING -25 0 25 50 75 TEMPERATURE (C) 100 125 338813 G10 2.25 -50 WAKE-UP THRESHOLD 2.75 2.70 2.65 PGOOD FALLING 2.60 PGOOD FALLING 2.30 SLEEP THRESHOLD 2.80 VOUT (V) 1.75 1.60 -50 2.90 2.45 VOUT (V) VOUT (V) WAKE-UP THRESHOLD 2.8V Output vs Temperature (LTC3388-3) SLEEP THRESHOLD 2.50 1.80 1.65 338813 G09 2.5V Output vs Temperature (LTC3388-1) 1.85 125 2.55 -25 0 25 50 75 TEMPERATURE (C) 100 125 338813 G11 2.50 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 338813 G12 338813fa For more information www.linear.com/LTC3388 5 LTC3388-1/LTC3388-3 TYPICAL PERFORMANCE CHARACTERISTICS 3.0V Output vs Temperature (LTC3388-3) 3.3V Output vs Temperature (LTC3388-3) 3.10 3.40 3.05 WAKE-UP THRESHOLD 5.0 WAKE-UP THRESHOLD WAKE-UP THRESHOLD 3.25 2.90 2.85 4.9 VOUT (V) 2.95 3.20 3.15 3.10 2.80 4.7 -25 0 25 50 75 TEMPERATURE (C) 100 2.95 -50 125 -25 0 25 50 75 TEMPERATURE (C) 338813 G13 4.5 -50 125 3.36 1.56 VOUT (V) 3.30 1.48 1.46 3.26 1.46 100 1m LOAD CURRENT (A) 3.24 10m 1 10 100 1m LOAD CURRENT (A) 338813 G16 1.44 10m IVOUT vs Temperature (LTC33881) 70 3.32 60 IVOUT (nA) 3.34 160 VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 140 50 80 3.26 30 60 6 6 8 10 12 14 VIN (V) 16 18 20 338813 G19 10 20 -50 12 14 VIN (V) 16 18 20 338813 G18 VOUT = 5.0V VOUT = 3.3V VOUT = 3.0V VOUT = 2.8V 100 40 4 8 120 3.28 3.24 6 IVOUT vs Temperature (LTC33883) IVOUT (nA) 80 L = 22H, ILOAD = 30mA, D1 = 0, D0 = 1 3.30 4 338813 G17 VOUT Line Regulation (LTC3388-3) 3.36 L = 22H, ILOAD = 30mA, D1 = 0, D0 = 1 1.50 3.28 10 125 1.52 1.48 1 100 1.54 3.32 VOUT (V) 1.52 1.44 0 25 50 75 TEMPERATURE (C) VOUT Line Regulation (LTC3388-1) VIN = 5.5V, L = 22H, COUT = 100F, D1 = 1, D0 = 0 3.34 1.50 -25 338813 G15 VOUT Load Regulation (LTC3388-3) VIN = 5.5V, L = 22H, COUT = 100F, D1 = 0, D0 = 1 1.54 100 338813 G14 VOUT Load Regulation (LTC3388-1) 1.56 PGOOD FALLING 4.6 3.00 2.70 -50 4.8 PGOOD FALLING 3.05 PGOOD FALLING 2.75 VOUT (V) SLEEP THRESHOLD SLEEP THRESHOLD 3.30 VOUT (V) VOUT (V) 5.1 3.35 SLEEP THRESHOLD 3.00 VOUT (V) 5.0V Output vs Temperature (LTC3388-3) -25 0 25 50 75 TEMPERATURE (C) 100 125 338813 G20 40 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 338813 G21 338813fa For more information www.linear.com/LTC3388 LTC3388-1/LTC3388-3 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs ILOAD, L = 22H (LTC3388-1) 100 100 VIN = 3.0V 90 80 80 70 70 60 50 40 30 VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 20 10 0 1 10 VIN = 3.0V 90 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs ILOAD, L = 100H (LTC3388-1) 100 1m LOAD CURRENT (A) 60 50 40 30 VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 20 10 0 10m 1 10 338813 G22 100 90 85 80 75 70 90 85 80 75 2 4 6 8 10 12 VIN (V) 14 16 18 70 20 90 90 80 80 EFFICIENCY (%) EFFICIENCY (%) 100 70 60 ILOAD = 50mA ILOAD = 100A ILOAD = 50A ILOAD = 30A ILOAD = 10A 40 2 4 6 8 10 12 VIN (V) 4 6 8 18 16 18 20 338813 G25 60 ILOAD = 50mA ILOAD = 100A ILOAD = 50A ILOAD = 30A ILOAD = 10A 40 16 14 70 50 14 10 12 VIN (V) Efficiency vs VIN for VOUT = 1.8V, L = 100H (LTC3388-1) 100 50 2 338813 G24 Efficiency vs VIN for VOUT = 1.8V, L = 22H (LTC3388-1) 30 VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 95 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs VIN for ILOAD = 50mA, L = 100H (LTC3388-1) VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 95 10m 338813 G23 Efficiency vs VIN for ILOAD = 50mA, L = 22H (LTC3388-1) 100 100 1m LOAD CURRENT (A) 20 30 2 4 6 338813 G26 8 10 12 VIN (V) 14 16 18 20 338813 G27 338813fa For more information www.linear.com/LTC3388 7 LTC3388-1/LTC3388-3 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs ILOAD, L = 22H (LTC3388-3) 100 80 80 70 70 60 50 40 30 VOUT = 5.0V VOUT = 3.3V VOUT = 3.0V VOUT = 2.8V 20 10 0 1 10 100 1m LOAD CURRENT (A) 60 50 40 30 10 0 10m 100 1m LOAD CURRENT (A) 10m Efficiency vs VIN for ILOAD = 50mA, L = 22H (LTC3388-3) Efficiency vs VIN for ILOAD = 50mA, L = 100H (LTC3388-3) 95 90 90 EFFICIENCY (%) 95 85 80 VOUT = 5.0V VOUT = 3.3V VOUT = 3.0V VOUT = 2.8V 4 6 8 10 85 80 12 14 VIN (V) 16 18 70 20 90 80 80 EFFICIENCY (%) 90 70 60 ILOAD = 50mA ILOAD = 100A ILOAD = 50A ILOAD = 30A ILOAD = 10A 4 6 8 10 12 14 VIN (V) 6 8 10 18 20 338813 G31 60 ILOAD = 50mA ILOAD = 100A ILOAD = 50A ILOAD = 30A ILOAD = 10A 40 18 16 70 50 16 12 14 VIN (V) Efficiency vs VIN for VOUT = 3.3V, L = 100H (LTC3388-3) 100 40 4 338813 G30 100 50 VOUT = 5.0V VOUT = 3.3V VOUT = 3.0V VOUT = 2.8V 75 Efficiency vs VIN for VOUT = 3.3V, L = 22H (LTC3388-3) EFFICIENCY (%) 10 338813 G29 75 8 1 338813 G28 100 30 VOUT = 5.0V VOUT = 3.3V VOUT = 3.0V VOUT = 2.8V 20 100 70 VIN = 6.0V 90 EFFICIENCY (%) EFFICIENCY (%) 100 VIN = 6.0V 90 EFFICIENCY (%) Efficiency vs ILOAD, L = 100H (LTC3388-3) 20 30 4 6 338813 G32 8 10 12 14 VIN (V) 16 18 20 338813 G33 338813fa For more information www.linear.com/LTC3388 LTC3388-1/LTC3388-3 PIN FUNCTIONS EN (Pin 1): Enable Input. Logic level input referenced to VIN2. A logic high on EN will enable the buck converter. Driving EN to VIN2 will result in no additional quiescent current on VIN. However, if EN is driven near VIH or VIL 40nA of additional quiescent current can appear on VIN. STBY (Pin 2): Standby Input. Logic level input referenced to VIN2. A logic high on STBY will place the part in standby mode. Driving STBY to VIN2 will result in no additional quiescent current on VIN. However, if STBY is driven near VIH or VIL 40nA of additional quiescent current can appear on VIN. CAP (Pin 3): Internal rail referenced to VIN to serve as gate drive for buck PMOS switch. A 1F capacitor should be connected between CAP and VIN. This pin is not intended for use as an external system rail. VIN (Pin 4): Input Voltage. A 2.2F or larger capacitor should be connected from VIN to GND. SW (Pin 5): Switch Pin for the Buck Switching Regulator. A 22H or larger inductor should be connected from SW to VOUT. VOUT (Pin 6): Sense pin used to monitor the output voltage and adjust it through internal feedback. VIN2 (Pin 7): Internal low voltage rail to serve as gate drive for buck NMOS switch. Also serves as a logic high rail for output voltage select bits D0 and D1. A 4.7F capacitor should be connected from VIN2 to GND. This pin is not intended for use as an external system rail. D1 (Pin 8): Output Voltage Select Bit. D1 should be tied high to VIN2 or low to GND to select desired VOUT (see Table 1). D0 (Pin 9): Output Voltage Select Bit. D0 should be tied high to VIN2 or low to GND to select desired VOUT (see Table 1). PGOOD (Pin 10): Power Good Open-Drain NMOS Output. The PGOOD pin is Hi-Z when VOUT is above 92% of the target value. GND (Exposed Pad Pin 11): Ground. The exposed pad should be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the LTC3388-1/LTC3388-3. 338813fa For more information www.linear.com/LTC3388 9 LTC3388-1/LTC3388-3 BLOCK DIAGRAM VIN 4 INTERNAL RAIL GENERATION VIN2 40nA UVLO 3 CAP 5 SW 7 VIN2 EN 1 VIN2 BUCK CONTROL 40nA 11 GND STBY 2 8, 9 D1, D0 SLEEP 6 BANDGAP REFERENCE VOUT 10 PGOOD 2 REF - PGOOD + 338813 BD 10 338813fa For more information www.linear.com/LTC3388 LTC3388-1/LTC3388-3 OPERATION The LTC3388-1/LTC3388-3 is an ultralow quiescent current power supply designed to maintain a regulated output voltage by means of a nanopower high efficiency synchronous buck regulator. Undervoltage Lockout (UVLO) When the voltage on VIN rises above the UVLO rising threshold the buck converter is enabled and charge is transferred from the input capacitor to the output capacitor. If VIN falls below the UVLO falling threshold the part will re-enter UVLO. In UVLO the quiescent current is approximately 400nA and the buck converter is disabled. Internal Rail Generation Two internal rails, CAP and VIN2, are generated from VIN and are used to drive the high side PMOS and low side NMOS of the buck converter, respectively. Additionally the VIN2 rail serves as logic high for EN, STBY, and output voltage select bits D0 and D1. The VIN2 rail is regulated at 4.6V above GND while the CAP rail is regulated at 4.8V below VIN. The VIN2 and CAP rails are not intended to be used as external rails. Bypass capacitors are connected to the CAP and VIN2 pins to serve as energy reservoirs for driving the buck switches. When VIN is below 4.6V, VIN2 is equal to VIN. CAP is at GND until VIN rises above 4.8V. Figure 1 shows the ideal VIN, VIN2 and CAP relationship. 18 16 VOLTAGE (V) 14 VIN 12 10 8 6 VIN2 4 2 0 CAP 0 5 10 VIN (V) 15 338813 F01 Figure 1. Ideal VIN, VIN2 and CAP Relationship Buck Operation The buck regulator uses a hysteretic voltage algorithm to control the output through internal feedback from the VOUT sense pin. The buck converter charges an output capacitor through an inductor to a value slightly higher than the regulation point. It does this by ramping the inductor current up to 150mA through an internal PMOS switch and then ramping it down to 0mA through an internal NMOS switch. This efficiently delivers energy to the output capacitor. The ramp rate is determined by VIN, VOUT, and the inductor value. When the buck brings the output voltage into regulation the converter enters a low quiescent current sleep state that monitors the output voltage with a sleep comparator. During this operating mode load current is provided by the buck output capacitor. When the output voltage falls below the regulation point the buck regulator wakes up and the cycle repeats. This hysteretic method of providing a regulated output reduces losses associated with FET switching and maintains an output at light loads. The buck delivers a minimum of 50mA of average load current when it is switching. When the sleep comparator signals that the output has reached the sleep threshold the buck converter may be in the middle of a cycle with current still flowing through the inductor. Normally both synchronous switches would turn off and the current in the inductor would freewheel to zero through the NMOS body diode. The LTC3388-1/ LTC3388-3 keeps the NMOS switch on during this time to prevent the conduction loss that would occur in the diode if the NMOS were off. If the PMOS is on when the sleep comparator trips, the NMOS will turn on immediately in order to ramp down the current. If the NMOS is on it will be kept on until the current reaches zero. Though the quiescent current when the buck is switching is much greater than the sleep quiescent current, it is still a small percentage of the average inductor current which results in high efficiency over most load conditions. The buck operates only when the output voltage discharges to the sleep falling threshold. Thus, the buck operating quiescent current is averaged with the low sleep quiescent current. This allows the converter to remain very efficient at loads as low as 10A. 338813fa For more information www.linear.com/LTC3388 11 LTC3388-1/LTC3388-3 OPERATION Four selectable voltages are available by tying the output select bits, D0 and D1, to GND or VIN2. Table 1 shows the four D0/D1 codes and their corresponding output voltages as well as the difference in output voltages between the LTC3388-1 and LTC3388-3. Table 1. LTC3388-1/LTC3388-3 Output Voltage Selection D1 D0 VOUT VOUT Quiescent Current (I VOUT) 0 0 1.2V/2.8V 28nA/66nA 0 1 1.5V/3.0V 36nA/72nA 1 0 1.8V/3.3V 43nA/78nA 1 1 2.5V/5.0V 60nA/120nA The internal feedback network draws a small amount of current from VOUT as listed in Table 1. Dropout Operation When the input supply voltage decreases towards the output voltage, the rate of change of inductor current decreases, reducing the switching frequency of the current bursts. Further reduction in input supply voltage will eventually cause the PMOS to be turned on 100%, i.e., DC. The output voltage will then be determined by the input voltage minus the voltage drop across the PMOS and the inductor. Power Good Comparator A power good comparator causes the PGOOD pin to go Hi-Z the first time the converter reaches the sleep threshold of the programmed VOUT, signaling that the 3.5 output is in regulation. The PGOOD pin will remain Hi-Z until VOUT falls to 92% of the desired regulation voltage. Additionally, if PGOOD is high and VIN falls below the UVLO falling threshold, PGOOD will remain high until VOUT falls to 92% of the desired regulation point. This allows output energy to be used even if the input is lost. Figure 2 shows the behavior for VOUT = 1.8V and a 10A load. At t = 2s VIN becomes high impedance and is discharged by the quiescent current of the LTC3388-1 and through servicing VOUT. VIN crosses UVLO falling but PGOOD remains high until VOUT decreases to 92% of the desired regulation point. This scenario is likely for cases in which the selected output voltage is below the UVLO falling threshold. If the input becomes high impedance and begins to fall it will be supported by the output through the body diode of the PMOS switch. For a high enough output voltage the part will not necessarily enter UVLO while VOUT remains PGOOD. This is always true for the output voltages available on the LTC3388-3. The D0/D1 inputs can be switched while in regulation as shown in Figure 3. If VOUT is programmed to a voltage with a PGOOD falling threshold above the old VOUT, PGOOD will transition low until the new regulation point is reached. When VOUT is programmed to a lower voltage, PGOOD will remain high through the transition. The PGOOD pin is designed to drive a microprocessor or other chip I/O and is not intended to drive higher current loads such as an LED. 6 CIN = 22F, COUT = 100F, ILOAD = 10A 3.0 VIN VOUT VOLTAGE (V) VOLTAGE (V) 5 VIN = UVLO FALLING 2.5 2.0 1.5 VOUT 1.0 VOUT 3 2 PGOOD = LOGIC 1 PGOOD 0 2 4 6 TIME (sec) 8 10 0 0 2 4 6 8 10 12 14 16 18 20 TIME (ms) 338813 F03 338813 F02 Figure 2. PGOOD Operation During Transition to UVLO 12 D1=D0=0 4 1 0.5 0 COUT = 100F, ILOAD = 50mA D1=D0=0 D1=D0=1 Figure 3. PGOOD Operation During D0/D1 Transition 338813fa For more information www.linear.com/LTC3388 LTC3388-1/LTC3388-3 OPERATION Enable and Standby Modes Two logic pins, EN and STBY, determine the operating mode of the LTC3388-1/LTC3388-3. When EN is high and STBY is low the synchronous buck converter is enabled and will regulate the output if the input voltage is above the programmed output voltage and above the UVLO threshold. If EN is low the buck converter circuitry is powered down to save quiescent current. The internal rail generation circuits are kept alive and the voltages at VIN2 and CAP are maintained. When low, EN also shuts down the PGOOD circuitry and pulls the PGOOD pin low. If EN is high and the input falls below the UVLO threshold, the buck converter is shut down. While enabled, the LTC3388-1/LTC3388-3 can be placed in standby mode by bringing STBY high. In standby mode the buck converter is disabled, eliminating the quiescent current used to run the buck circuitry. The PGOOD and sleep comparators are kept alive to maintain the state of the PGOOD pin. The sleep comparator has lower quiescent current than the PGOOD comparator and when the LTC3388-1/LTC3388-3 is in sleep mode the PGOOD comparator is shut down and PGOOD is held high. The same occurs in standby mode. If the LTC3388-1/LTC3388-3 was in sleep before entering standby it will stay in sleep in standby, saving the quiescent current of the PGOOD comparator. If VOUT falls below the sleep falling threshold the PGOOD comparator will be enabled. If VOUT falls below the PGOOD falling threshold the PGOOD pin will be pulled low. If STBY is driven high with EN low it will be ignored and the LTC3388-1/LTC3388-3 will remain shut down. If EN and STBY are driven high but near VIH or low but near VIL, additional quiescent current may appear on VIN. This additional quiescent current is typically 40nA and depends on VIN and temperature. Driving EN or STBY to 0V or VIN2 will prevent additional quiescent current on VIN. Figure 4 shows VOUT during a transition into and out of standby. While in standby, the buck is off and VOUT is quiet. VOUT 50mV/DIV AC-COUPLED STANDBY 5V/DIV 0V 500s/DIV VIN = 5.5V, L = 22H, COUT = 100F STANDBY TRANSIENT 338813 F04 Figure 4. LTC3388-3 Standby Transient, VOUT = 3.3V, ILOAD = 5mA 338813fa For more information www.linear.com/LTC3388 13 LTC3388-1/LTC3388-3 APPLICATIONS INFORMATION Introduction The basic LTC3388-1/LTC3388-3 application circuit is shown on the front page. External components are selected based on the performance requirements of the application. Input Capacitor Selection The input capacitor at VIN should be selected to adequately bypass the LTC3388-1/LTC3388-3 and filter the switching current presented by the buck regulator. The VIN capacitor should be rated to withstand the highest voltage ever present at VIN. It should be placed as close as possible to the LTC3388-1/LTC3388-3 to force the high frequency switching current into a tight local loop to minimize EMI. A 2.2F ceramic X7R or X5R capacitor should be adequate for bypassing. High ripple current, high voltage rating, and low ESR make ceramic capacitors ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. A sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. For such applications with inductive source impedance, such as a long wire, a series RC network may be required in parallel with CIN to dampen the ringing of the input supply. Figure 5 shows this circuit and the typical values required to dampen the ringing. The RC resistor may be replaced by a single electrolytic capacitor that has an ESR equivalent to the needed series resistance of the network. See Application Note 88 for a complete discussion of this phenomenon. Output Capacitor Selection The duration for which the regulator sleeps depends on the load current and the size of the output capacitor. The sleep time decreases as the load current increases and/or as the output capacitor decreases. The DC sleep hysteresis window, VHYST, is 8mV and 16mV around the programmed output voltage on the LTC3388-1 and LTC3388-3 respectively. Ideally this means that the sleep time is determined by the following equation: V tSLEEP = COUT HYST ILOAD This is true for output capacitors on the order of 100F or larger, but as the output capacitor decreases towards 10F delays in the internal sleep comparator along with the load current may result in the VOUT voltage slewing past the 8mV/16mV thresholds. This will lengthen the sleep time and increase VOUT ripple. A capacitor less than 10F is not recommended as VOUT ripple could increase to an undesirable level. LTC3388-1/ LTC3388-3 LIN VIN R= LIN CIN 4 * CIN 338813 F05 CIN Figure 5. Series RC to Reduce VIN Ringing 14 338813fa For more information www.linear.com/LTC3388 LTC3388-1/LTC3388-3 APPLICATIONS INFORMATION If transient load currents above 50mA are required then a larger capacitor can be used at the output. This capacitor will be continuously discharged during a load condition and the capacitor can be sized for an acceptable drop in VOUT: COUT = (ILOAD - IBUCK ) a DC current rating greater than 200mA. The DCR of the inductor can have an impact on efficiency as it is a source of loss. Trade-offs between price, size, and DCR should be evaluated. Table 2 lists several inductors that work well with the LTC3388-1/LTC3388-3. tLOAD VOUT + - VOUT - Table 2. Recommended Inductors for LTC3388-1/LTC3388-3 Here VOUT+ is the value of VOUT when PGOOD goes high and VOUT- is the desired lower limit of VOUT. IBUCK is the average current being delivered from the buck converter, typically IPEAK /2. A standard surface mount ceramic capacitor can be used for COUT, though some applications may be better suited to a low leakage aluminum electrolytic capacitor or a supercapacitor. These capacitors can be obtained from manufacturers such as Vishay, Illinois Capacitor, AVX, or CAP-XX. EN SIZE in mm (L x W x H) MANUFACTURER CDRH2D18/LDNP 22 300 0.320 3.2 x 3.2 x 2.0 Sumida A997AS-220M 22 390 0.440 4.0 x 4.0 x 1.8 Toko LPS5030-223MLC 22 700 0.190 4.9 x 4.9 x 3.0 Coilcraft LPS4012-473MLC 47 350 1.400 4.0 x 4.0 x 1.2 Coilcraft SLF7045T 100 500 0.250 7.0 x 7.0 x 4.5 TDK LTC3388-1 STBY PGOOD VIN 2.7V TO 5.5V MAX DCR () A 1F capacitor should be connected between VIN and CAP and a 4.7F capacitor should be connected between VIN2 and GND. These capacitors hold up the internal rails during buck switching and compensate the internal rail generation circuits. In applications where the input source is limited to less than 6V, the CAP pin can be tied to GND and the VIN2 pin can be tied to VIN as shown in Figure 6. This circuit does not require the capacitors on VIN2 and CAP, saving components and allowing a lower voltage rating for the single VIN capacitor. The buck is optimized to work with an inductor of at least 22H. This value represents a suitable trade-off between size and efficiency for typical applications. A larger inductor will benefit high voltage applications by increasing the on-time of the PMOS switch and improving efficiency by reducing gate charge loss. Choose an inductor with EN MAX IDC (mA) VIN2 and CAP Capacitors Inductor STBY INDUCTOR TYPE L (H) VIN2 2.2F 6V SW CAP 22H VOUT 1.2V VOUT D1 D0 PGOOD 10F 6V GND 338813 F06 Figure 6. Smallest Solution Size 1.2V Low Input Voltage Power Supply 338813fa For more information www.linear.com/LTC3388 15 LTC3388-1/LTC3388-3 APPLICATIONS INFORMATION Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (1 + 2 + 3 + ...) where 1, 2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses: 1) DC VIN operating current while active and in sleep, 2) MOSFET gate charge loss, and 3) I2R losses. The VIN operating current dominates the efficiency loss at very low load currents whereas the gate charge and I2R loss dominates the efficiency loss at medium to high load currents. 1. The DC VIN current is the average of the quiescent supply currents, given in the electrical characteristics, in the active and sleep modes. This can be estimated with the following equation: I ILOAD LOAD IVIN(AVG) = IQ(ACTIVE) + 1- I IBUCK Q(SLEEP) IBUCK where IBUCK is the average current being delivered from the buck converter, typically IPEAK/2. For very light loads IQ(SLEEP) will dominate this loss term which is why the extremely low quiescent current in sleep of the LTC3388-1/LTC3388-3 is critical. 2. Internal MOSFET gate charge currents result from switching the gate capacitance of the internal power 16 MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. Of course, this switching current only appears when the buck is on and is important at high load currents. Gate charge loss can be reduced by increasing the inductor, thereby reducing the switching frequency when the buck is active. 3. I2R losses are calculated from the resistances of the internal switches, RSW, and the external inductor DCR. When switching, the average output current flowing through the inductor is "chopped" between the high side PMOS switch and the low side NMOS switch. Thus, the series resistance looking back into the switch pin is a function of the top and bottom switch on-resistance and the duty cycle (DC = VOUT/VIN) as follows: RSW = (RP,BUCK)DC + (RN,BUCK)(1 - DC) The on-resistance for both the top and bottom MOSFETs can be obtained from the curves in the Typical Performance Characteristics section. Thus, to obtain the I2R losses, simply add RSW to the DCR and multiply the result by the square of the average output current: I2R Loss = IO2(RSW + DCR) This loss term only occurs when the buck is operating and must be multiplied by the percentage of time the buck is operating versus sleeping or ILOAD/IBUCK to see its overall effect. Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% of the total power loss. 338813fa For more information www.linear.com/LTC3388 LTC3388-1/LTC3388-3 APPLICATIONS INFORMATION Interfacing with a Microprocessor will cease and the output capacitor will support the load of the microprocessor and other circuitry. While in standby the output voltage will decrease as it's loaded. The output capacitor should be sized to minimize the decline. The PGOOD, STBY, and EN pins can be useful when powering a microprocessor from the LTC3388-1/LTC3388-3. The PGOOD signal can be used to enable a sleeping microprocessor or other circuitry when VOUT reaches regulation, as shown in Figure 7. While active, a microprocessor may draw a small load when operating sensors, and then draw a large load to transmit data. Figure 7 shows the LTC3388-1/ LTC3388-3 responding smoothly to such a load step. The EN pin can be used to activate the LTC3388-1/LTC3388-3. For instance, in Figure 8 the LTC3388-1 is enabled by the PGOOD output of the LTC3588-1, a piezoelectric energy harvesting power supply, to create a 1.2V rail. The quiescent current that the LTC3388-1 draws will appear at the input of the LTC3588-1, reduced by the conversion ratio of the LTC3588-1 buck converter. Because the LTC3388-1 is driven by a 3.3V supply no capacitors are needed for the internal VIN2 and CAP rails. The microprocessor or other circuitry may require a quiet supply for performing some functions. The STBY pin allows the microprocessor to place the LTC3388-1/LTC3388-3 into standby mode where the buck converter is inactive. Any ripple in the output voltage of the LTC3388-1/LTC3388-3 2.7V TO 4.2V + STBY VIN EN PGOOD LTC3388-1 D1 SW VIN2 Li-ION 10F 6V VOUT CAP D0 GND STBY EN 22H 1M 1.8V TX MICROPROCESSOR CORE VOUT 20mV/DIV AC-COUPLED GND 47F 6V LOAD CURRENT 25mA/DIV 0mA 338813 F07a 250s/DIV VIN = 5.5V L = 22H, COUT = 100F LOAD STEP BETWEEN 5mA AND 50mA 338813 F07b Figure 7. 1.8V Step-Down Converter Powering a Microprocessor with a Wireless Transmitter and 45mA Load Step Response 338813fa For more information www.linear.com/LTC3388 17 LTC3388-1/LTC3388-3 APPLICATIONS INFORMATION MIDE V21BL 1F 6V 10F 25V 4.7F 6V PZ1 PZ2 VIN PGOOD LTC3588-1 CAP SW VIN2 VOUT D1 D0 GND PGOOD VIN2 LTC3388-1 EN 47H 1M 3.3V 10F 6V 22H 1.2V SW VIN VOUT CAP D1 D0 GND 47F 6V STBY 338813 F07 Figure 8. Piezoelectric Energy Harvester and 1.2V Secondary Rail 18 338813fa For more information www.linear.com/LTC3388 LTC3388-1/LTC3388-3 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD Package 10-Lead Plastic DFN (3mm x 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 0.05 3.55 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 0.10 (4 SIDES) R = 0.125 TYP 6 0.40 0.10 10 1.65 0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 5 0.75 0.05 0.00 - 0.05 1 (DD) DFN REV C 0310 0.25 0.05 0.50 BSC 2.38 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 338813fa For more information www.linear.com/LTC3388 19 LTC3388-1/LTC3388-3 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSE Package 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev D) BOTTOM VIEW OF EXPOSED PAD OPTION 1.88 0.102 (.074 .004) 5.23 (.206) MIN 0.889 0.127 (.035 .005) 1.68 0.102 (.066 .004) 1 0.05 REF 10 3.00 0.102 (.118 .004) (NOTE 3) DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 10 9 8 7 6 DETAIL "A" 0 - 6 TYP 1 2 3 4 5 GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 - 0.27 (.007 - .011) TYP 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 20 0.497 0.076 (.0196 .003) REF 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) 0.254 (.010) 0.29 REF 1.68 (.066) 3.20 - 3.45 (.126 - .136) 0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 1.88 (.074) 0.1016 0.0508 (.004 .002) MSOP (MSE) 0210 REV D 338813fa For more information www.linear.com/LTC3388 LTC3388-1/LTC3388-3 REVISION HISTORY REV DATE DESCRIPTION A 08/15 Modified COUT Equation PAGE NUMBER 15 338813fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection its circuits as described herein will not infringe on existing patent rights. Forof more information www.linear.com/LTC3388 21 LTC3388-1/LTC3388-3 TYPICAL APPLICATION Piezoelectric Energy Harvester with Dual, 3.3V Outputs 1F 6V 10F 25V 4.7F 6V PZ1 PZ2 VIN PGOOD LTC3588-1 22H CAP SW VIN2 VOUT 3.3V D1 D0 1F 6V 47F 6V 2.2F 10V GND VIN PGOOD CAP LTC3388-3 * SW VIN2 VOUT EN 4.7F 6V 22H 47F 6V D1 D0 GND STBY -3.3V * EXPOSED PAD MUST BE ELECTRICALLY ISOLATED FROM SYSTEM GROUND AND CONNECTED TO THE -3.3V RAIL. 338813 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1389 Nanopower Precision Shunt Voltage Reference 800nA Operating Current, 1.25V/2.5V/4.096V LTC1540 Nanopower Comparator with Reference 0.3A IQ, Drives 0.01F, Adjustable Hysteresis, 2V to 11V Input Range LT3009 3A IQ, 20mA Low Dropout Linear Regulator Low 3A IQ, 1.6V to 20V Range, 20mA Output Current LTC3588-1 Piezoelectric Energy Harvesting Power Supply <1A IQ in Regulation, 2.7V to 20V Input Range, Integrated Bridge Rectifier LTC3588-2 Piezoelectric Energy Harvesting Power Supply <1A IQ in Regulation, UVLO Rising = 16V, UVLO Falling = 14V, VOUT = 3.45V, 4.1V, 4.5V, 5.0V LT3652 Power Tracking 2A Battery Charger for Solar Power MPPT for Solar, 4.95V to 32V, Up to 2A Charge Current LT3970 40V, 350mA Step-Down Regulator with 2.5A IQ Integrated Boost and Catch Diodes, 4.2V to 40V Operating Range LT3971 38V, 1.2A, 2MHz Step-Down Regulator with 2.8A IQ 4.3V to 38V Operating Range, Low Ripple Burst Mode(R) Operation LT3991 55V, 1.2A 2MHz Step-Down Regulator with 2.8A IQ 4.3V to 55V Operating Range, Low Ripple Burst Mode Operation LTC3631 45V, 100mA, Synchronous Step-Down Regulator with 12A IQ 4.5V to 45V Operating Range, Overvoltage Lockout Up to 60V LTC3642 45V, 50mA, Synchronous Step-Down Regulator with 12A IQ 4.5V to 45V Operating Range, Overvoltage Lockout Up to 60V 22 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC3388 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC3388 338813fa LT 0815 REV A * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2010