LTC3388-1/LTC3388-3
1
338813fa
For more information www.linear.com/LTC3388
TYPICAL APPLICATION
FEATURES DESCRIPTION
20V High Efficiency
Nanopower
Step-Down Regulator
The LT C
®
3388-1/LTC3388-3 are high efficiency step-down
DC/DC converters with internal high side and synchronous
power switches that draw only 720nA typical DC supplycur-
rent at no load while maintaining output voltage regulation.
Capable of supplying 50mA of load current, the LTC3388-1/
LTC3388-3 also incorporate an accurate undervoltage
lockout (UVLO) feature to disable the converter and main-
tain a low quiescent current state when the input voltage
falls below 2.3V. In regulation, the LTC3388-1/LTC3388-3
enter a sleep state in which both input and output quies-
cent currents are minimal. The buck converter turns on
and off as needed to maintain regulation. An additional
standby mode disables buck switching while the output is
in regulation for short duration loads requiring low ripple.
Output voltages of 1.2V, 1.5V, 1.8V, 2.5V (LTC3388-1)
and 2.8V, 3.0V, 3.3V, 5.0V (LTC3388-3) are pin selectable.
The LTC3388-1/LTC3388-3 can operate with VIN up to 20V
while the no load quiescent current remains below 1µA.
L, LT , LT C , LT M, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
50mA Step-Down Converter
APPLICATIONS
n 720nA Input IQ in Regulation (No Load), VIN = 4V
n 820nA Input IQ in Regulation (No Load), VIN = 20V
n 400nA Input IQ in UVLO
n 2.7V to 20V Input Operating Range
n Up to 50mA of Output Current
n Pin Selectable Output Voltages:
n 1.2V, 1.5V, 1.8V, 2.5V (LTC3388-1)
n 2.8V, 3.0V, 3.3V, 5.0V (LTC3388-3)
n High Efficiency Hysteretic Synchronous
DC/DC Conversion
n Standby Mode Disables Buck Switching
n Available in 10-Lead MSE and 3mm × 3mm
DFN Packages
n Keep Alive Power for Portable Products
n Industrial Control Supplies
n Distributed Power Systems
n Battery-Operated Devices
338813 TA01a
VIN
CAP
VIN2
EN
STBY
SW
VOUT
PGOOD
D0, D1
LTC3388-1/
LTC3388-3
GND
1µF
6V
4.7µF
6V
2.2µF
25V
2.7V TO 20V
47µF
6V
OUTPUT
VOLTAGE
SELECT
VOUT
100µH
2
Efficiency vs Load Current
LOAD CURRENT (A)
EFFICIENCY (%)
100
40
50
30
20
80
90
70
60
10
0
338813 TA01b
100µ 1m 10m1µ 10µ
VOUT = 1.8V, L = 100µH
VIN = 3.0V
VIN = 10V
VIN = 20V
LTC3388-1/LTC3388-3
2
338813fa
For more information www.linear.com/LTC3388
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN ............................................................. –0.3V to 22V
D0, D1 ..............–0.3V to [Lesser of (VIN2 + 0.3V) or 6V]
CAP ...................... [Higher of –0.3V or (VIN – 6V)] to VIN
VIN2, VOUT ..........–0.3V to [Lesser of (VIN + 0.3V) or 6V]
EN, STBY ..................................................... –0.3V to 6V
PGOOD ......................................................... –0.3V to 6V
(Note 1)
TOP VIEW
11
GND
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1PGOOD
D0
D1
VIN2
VOUT
EN
STBY
CAP
VIN
SW
TJMAX = 125°C, θJA = 43°C/W, θJC = 7.5°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
EN
STBY
CAP
VIN
SW
10
9
8
7
6
PGOOD
D0
D1
VIN2
VOUT
TOP VIEW
MSE PACKAGE
10-LEAD PLASTIC MSOP
11
GND
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3388EDD-1#PBF LTC3388EDD-1#TRPBF LFWN 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3388IDD-1#PBF LTC3388IDD-1#TRPBF LFWN 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3388EMSE-1#PBF LTC3388EMSE-1#TRPBF LTFWM 10-Lead Plastic MSOP –40°C to 125°C
LTC3388IMSE-1#PBF LTC3388IMSE-1#TRPBF LTFWM 10-Lead Plastic MSOP –40°C to 125°C
LTC3388EDD-3#PBF LTC3388EDD-3#TRPBF LFWQ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3388IDD-3#PBF LTC3388IDD-3#TRPBF LFWQ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3388EMSE-3#PBF LTC3388EMSE-3#TRPBF LTFWP 10-Lead Plastic MSOP –40°C to 125°C
LTC3388IMSE-3#PBF LTC3388IMSE-3#TRPBF LTFWP 10-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ISW .......................................................................210mA
Operating Junction Temperature Range
(Notes 2, 3) ............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
MSE Only .............................................................. 300°C
LTC3388-1/LTC3388-3
3
338813fa
For more information www.linear.com/LTC3388
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are for TA = 25°C (Note 2). Unless otherwise noted, VIN = 5.5V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Voltage Range l2.7 20 V
IQVIN Quiescent Current When Enabled
UVLO
Sleep
Sleep
Active
VIN = 2V
VIN = 4V
VIN = 20V
ISW = 0A (Note 4)
400
720
820
150
600
1100
1200
250
nA
nA
nA
µA
IQ,STBY VIN Quiescent Current Enabled, in Standby
Sleeping
Not Sleeping
VIN = 4V
VIN = 4V
720
2000
1100
3000
nA
nA
IQ,SD VIN Quiescent Current When Disabled VIN = 4V
VIN = 20V
520
620
800
900
nA
nA
VUVLO VIN Undervoltage Lockout Threshold VIN Rising
VIN Falling
l
l
2.15
2.5
2.3
2.65 V
V
VOUT Regulated Output Voltage (LTC3388-1) 1.2V Output Selected; D1 = 0, D0 = 0
Sleep Threshold
Wake-Up Threshold
1.5V Output Selected; D1 = 0, D0 = 1
Sleep Threshold
Wake-Up Threshold
1.8V Output Selected; D1 = 1, D0 = 0
Sleep Threshold
Wake-Up Threshold
2.5V Output Selected; D1 = 1, D0 = 1
Sleep Threshold
Wake-Up Threshold
l
l
l
l
l
l
l
l
1.140
1.440
1.737
2.400
1.208
1.192
1.508
1.492
1.808
1.792
2.508
2.492
1.260
1.560
1.863
2.600
V
V
V
V
V
V
V
V
VOUT Regulated Output Voltage (LTC3388-3) 2.8V Output Selected; D1 = 0, D0 = 0
Sleep Threshold
Wake-Up Threshold
3.0V Output Selected; D1 = 0, D0 = 1
Sleep Threshold
Wake-Up Threshold
3.3V Output Selected; D1 = 1, D0 = 0
Sleep Threshold
Wake-Up Threshold
5.0V Output Selected; D1 = 1, D0 = 1
Sleep Threshold
Wake-Up Threshold
l
l
l
l
l
l
l
l
2.688
2.895
3.201
4.820
2.816
2.784
3.016
2.984
3.316
3.284
5.016
4.984
2.912
3.105
3.399
5.180
V
V
V
V
V
V
V
V
PGOOD Threshold As a Percentage of the Selected VOUT 83 92 %
VOL, PGOOD PGOOD Output Low Voltage 100µA Into Pin l0.2 V
IVOUT Output Quiescent Current LTC3388-1: VOUT = 2.5V
LTC3388-3: VOUT = 5.0V
60
120
nA
nA
IPEAK PMOS Switch Peak Current l100 150 210 mA
IOUT Available Output Current l50 mA
RP, BUCK PMOS Switch On-Resistance 1.1 Ω
RN, BUCK NMOS Switch On-Resistance 1.3 Ω
Maximum Duty Cycle l100 %
LTC3388-1/LTC3388-3
4
338813fa
For more information www.linear.com/LTC3388
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are for TA = 25°C (Note 2). Unless otherwise noted, VIN = 5.5V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH D0/D1/EN/STBY Input High Voltage l1.2 V
VIL(D0, D1) D0/D1 Input Low Voltage l0.4 V
VIL(EN,STBY) EN/STBY Input Low Voltage l150 mV
IIH D0/D1/EN/STBY Input High Current 10 nA
IIL D0/D1/EN/STBY Input Low Current 10 nA
Additional IQ at VIN with EN at VIH(MIN) VEN = 1.2V, VIN = 4V 40 nA
Additional IQ at VIN with STBY at VIH(MIN) VSTBY = 1.2V, VIN = 4V 40 nA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3388-1/LTC3388-3 are tested under pulsed load
conditions such that TJ ≈ TA. The LTC3388E-1/LTC3388E-3 are
guaranteed to meet specifications from 0°C to 85°C junction temperature.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LTC3388I-1/LTC3388I-3 are guaranteed
over the –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according
to the formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package
thermal impedance.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Input IQ vs VIN, UVLO Input IQ vs VIN, No Load Input IQ vs VIN, EN Low
TYPICAL PERFORMANCE CHARACTERISTICS
VIN (V)
INPUT I
Q
(nA)
800
400
500
600
700
300
200
100
0
338813 G01
1 1.5 2 2.50 0.5
–40°C
85°C
25°C
125°C
VIN (V)
INPUT IQ (nA)
1600
1000
1200
1400
800
600
400
200
338813 G02
6 8 10 202 4 16 1812 14
85°C
25°C
–40°C
125°C
D1 = D0 = 0
VIN (V)
INPUT I
Q
(nA)
1200
800
1000
600
0
200
400
338813 G03
6 8 10 200 2 4 16 1812 14
85°C
25°C
125°C
–40°C
LTC3388-1/LTC3388-3
5
338813fa
For more information www.linear.com/LTC3388
TYPICAL PERFORMANCE CHARACTERISTICS
UVLO vs Temperature IPEAK vs Temperature
RP,BUCK /RN,BUCK
vs Temperature
Operating Waveforms
1.2V Output vs Temperature
(LTC3388-1)
1.5V Output vs Temperature
(LTC3388-1)
1.8V Output vs Temperature
(LTC3388-1)
2.5V Output vs Temperature
(LTC3388-1)
2.8V Output vs Temperature
(LTC3388-3)
TEMPERATURE (°C)
V
UVLO
(V)
2.8
2.6
2.4
2.2
2.0
338813 G04
50 75 100 125–50 250–25
UVLO RISING
UVLO FALLING
TEMPERATURE (°C)
I
PEAK
(mA)
180
160
170
140
150
130
120
338813 G05
50 75 100 125–50 250–25
TEMPERATURE (°C)
RDS(ON) (Ω)
2.0
1.6
1.8
1.2
1.4
1.0
0.8
338813 G06
45 65 85 105 125–55 25–15 5–35
NMOS
PMOS
5µs/DIV
0V
VOUT
50mV/DIV
AC-COUPLED
VSW
2V/DIV
VIN = 5.5V, VOUT = 1.8V
ILOAD = 20mA
L = 22µH, COUT = 47µF
INDUCTOR
CURRENT
100mA/DIV
0mA 338813 G07
TEMPERATURE (°C)
VOUT (V)
1.24
1.16
1.14
1.18
1.20
1.22
1.10
1.12
1.08
1.06
338813 G08
50 75 100 125–50 250–25
PGOOD FALLING
WAKE-UP THRESHOLD
SLEEP THRESHOLD
TEMPERATURE (°C)
V
OUT
(V)
1.54
1.46
1.50
1.52
1.42
1.38
1.44
1.48
1.40
1.36
1.34
338813 G09
50 75 100 125–50 250–25
PGOOD FALLING
WAKE-UP THRESHOLD
SLEEP THRESHOLD
TEMPERATURE (°C)
V
OUT
(V)
1.85
1.65
1.75
1.80
1.70
1.60
338813 G10
50 75 100 125–50 250–25
PGOOD FALLING
WAKE-UP THRESHOLD
SLEEP THRESHOLD
TEMPERATURE (°C)
V
OUT
(V)
2.55
2.30
2.35
2.45
2.50
2.40
2.25
338813 G11
50 75 100 125–50 250–25
PGOOD FALLING
WAKE-UP THRESHOLD
SLEEP THRESHOLD
TEMPERATURE (°C)
VOUT (V)
2.90
2.55
2.60
2.70
2.75
2.80
2.85
2.65
2.50
338813 G12
50 75 100 125–50 250–25
PGOOD FALLING
WAKE-UP THRESHOLD
SLEEP THRESHOLD
LTC3388-1/LTC3388-3
6
338813fa
For more information www.linear.com/LTC3388
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT Line Regulation
(LTC3388-3)
IVOUT vs Temperature (LTC3388-
1)
IVOUT vs Temperature (LTC3388-
3)
3.0V Output vs Temperature
(LTC3388-3)
3.3V Output vs Temperature
(LTC3388-3)
5.0V Output vs Temperature
(LTC3388-3)
VOUT Load Regulation
(LTC3388-1)
VOUT Load Regulation
(LTC3388-3)
VOUT Line Regulation
(LTC3388-1)
TEMPERATURE (°C)
V
OUT
(V)
3.10
2.75
2.80
2.90
2.95
3.00
3.05
2.85
2.70
338813 G13
50 75 100 125–50 250–25
PGOOD FALLING
WAKE-UP THRESHOLD
SLEEP THRESHOLD
TEMPERATURE (°C)
V
OUT
(V)
3.40
3.00
3.05
3.20
3.25
3.30
3.35
3.10
3.15
2.95
338813 G14
50 75 100 125–50 250–25
PGOOD FALLING
WAKE-UP THRESHOLD
SLEEP THRESHOLD
TEMPERATURE (°C)
VOUT (V)
5.1
4.6
4.7
5.0
4.8
4.9
4.5
338813 G15
50 75 100 125–50 250–25
PGOOD FALLING
WAKE-UP THRESHOLD
SLEEP THRESHOLD
LOAD CURRENT (A)
VOUT (V)
1.56
1.46
1.48
1.54
1.50
1.52
1.44
338813 G16
1µ 10m100µ 1m10µ
VIN = 5.5V, L = 22µH, COUT = 100µF,
D1 = 0, D0 = 1
LOAD CURRENT (A)
V
OUT
(V)
3.36
3.26
3.28
3.34
3.30
3.32
3.24
338813 G17
1µ 10m100µ 1m10µ
VIN = 5.5V, L = 22µH, COUT = 100µF,
D1 = 1, D0 = 0
VIN (V)
V
OUT
(V)
3.36
3.32
3.34
3.28
3.30
3.26
3.24
338813 G19
12 14 16 18 204 1086
L = 22µH, ILOAD = 30mA, D1 = 0, D0 = 1
VIN (V)
V
OUT
(V)
1.56
1.52
1.54
1.48
1.50
1.46
1.44
338813 G18
12 14 16 18 204 1086
L = 22µH, ILOAD = 30mA, D1 = 0, D0 = 1
TEMPERATURE (°C)
I
VOUT
(nA)
80
40
50
60
70
30
20
338813 G20
50 75 100 125–50 250–25
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
TEMPERATURE (°C)
I
VOUT
(nA)
160
80
100
120
140
60
40
338813 G21
50 75 100 125–50 250–25
VOUT = 5.0V
VOUT = 3.3V
VOUT = 3.0V
VOUT = 2.8V
LTC3388-1/LTC3388-3
7
338813fa
For more information www.linear.com/LTC3388
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs ILOAD, L = 22µH
(LTC3388-1)
Efficiency vs VIN for ILOAD = 50mA,
L = 22µH (LTC3388-1)
Efficiency vs VIN for VOUT = 1.8V,
L = 22µH (LTC3388-1)
Efficiency vs ILOAD, L = 100µH
(LTC3388-1)
Efficiency vs VIN for ILOAD = 50mA,
L = 100µH (LTC3388-1)
Efficiency vs VIN for VOUT = 1.8V,
L = 100µH (LTC3388-1)
LOAD CURRENT (A)
EFFICIENCY (%)
100
40
50
60
70
80
90
30
20
10
0
338813 G22
10m1µ 1m100µ10µ
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VIN = 3.0V
LOAD CURRENT (A)
EFFICIENCY (%)
100
40
50
60
70
80
90
30
20
10
0
338813 G23
10m1µ 1m100µ10µ
VIN = 3.0V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VIN (V)
EFFICIENCY (%)
100
90
95
80
85
75
70
338813 G24
12 14 16 18 202 4 1086
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VIN (V)
EFFICIENCY (%)
100
90
95
80
85
75
70
338813 G25
12 14 16 18 202 4 1086
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VIN (V)
EFFICIENCY (%)
100
70
80
90
50
60
40
30
338813 G26
12 14 16 18 202 4 1086
ILOAD = 50mA
ILOAD = 100µA
ILOAD = 50µA
ILOAD = 30µA
ILOAD = 10µA
VIN (V)
EFFICIENCY (%)
100
70
80
90
50
60
40
30
338813 G27
12 14 16 18 202 4 1086
ILOAD = 50mA
ILOAD = 100µA
ILOAD = 50µA
ILOAD = 30µA
ILOAD = 10µA
LTC3388-1/LTC3388-3
8
338813fa
For more information www.linear.com/LTC3388
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs ILOAD, L = 100µH
(LTC3388-3)
Efficiency vs VIN for ILOAD = 50mA,
L = 100µH (LTC3388-3)
Efficiency vs VIN for VOUT = 3.3V,
L = 100µH (LTC3388-3)
Efficiency vs ILOAD, L = 22µH
(LTC3388-3)
Efficiency vs VIN for ILOAD = 50mA,
L = 22µH (LTC3388-3)
Efficiency vs VIN for VOUT = 3.3V,
L = 22µH (LTC3388-3)
LOAD CURRENT (A)
EFFICIENCY (%)
100
50
60
90
70
20
10
30
40
80
0
338813 G28
1µ 10m100µ 1m10µ
VOUT = 5.0V
VOUT = 3.3V
VOUT = 3.0V
VOUT = 2.8V
VIN = 6.0V
LOAD CURRENT (A)
EFFICIENCY (%)
100
50
60
90
70
20
10
30
40
80
0
338813 G29
1µ 10m100µ 1m10µ
VIN = 6.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 3.0V
VOUT = 2.8V
VIN (V)
EFFICIENCY (%)
100
80
85
90
95
75
70
338813 G30
141210 16 18 204 86
VOUT = 5.0V
VOUT = 3.3V
VOUT = 3.0V
VOUT = 2.8V
VIN (V)
EFFICIENCY (%)
100
80
85
90
95
75
70
338813 G31
141210 16 18 204 86
VOUT = 5.0V
VOUT = 3.3V
VOUT = 3.0V
VOUT = 2.8V
VIN (V)
EFFICIENCY (%)
100
70
80
90
50
60
40
30
338813 G32
12 14 16 18 204 1086
ILOAD = 50mA
ILOAD = 100µA
ILOAD = 50µA
ILOAD = 30µA
ILOAD = 10µA
VIN (V)
EFFICIENCY (%)
100
70
80
90
50
60
40
30
338813 G33
12 14 16 18 204 1086
ILOAD = 50mA
ILOAD = 100µA
ILOAD = 50µA
ILOAD = 30µA
ILOAD = 10µA
LTC3388-1/LTC3388-3
9
338813fa
For more information www.linear.com/LTC3388
PIN FUNCTIONS
EN (Pin 1): Enable Input. Logic level input referenced to
VIN2. A logic high on EN will enable the buck converter.
Driving EN to VIN2 will result in no additional quiescent
current on VIN. However, if EN is driven near VIH or VIL
40nA of additional quiescent current can appear on VIN.
STBY (Pin 2): Standby Input. Logic level input referenced
to VIN2. A logic high on STBY will place the part in standby
mode. Driving STBY to VIN2 will result in no additional
quiescent current on VIN. However, if STBY is driven
near VIH or VIL 40nA of additional quiescent current can
appear on VIN.
CAP (Pin 3): Internal rail referenced to VIN to serve as gate
drive for buck PMOS switch. A 1µF capacitor should be
connected between CAP and VIN. This pin is not intended
for use as an external system rail.
VIN (Pin 4): Input Voltage. A 2.2µF or larger capacitor
should be connected from VIN to GND.
SW (Pin 5): Switch Pin for the Buck Switching Regulator.
A 22µH or larger inductor should be connected from SW
to VOUT.
VOUT (Pin 6): Sense pin used to monitor the output volt-
age and adjust it through internal feedback.
VIN2 (Pin 7): Internal low voltage rail to serve as gate drive
for buck NMOS switch. Also serves as a logic high rail for
output voltage select bits D0 and D1. A 4.7µF capacitor
should be connected from VIN2 to GND. This pin is not
intended for use as an external system rail.
D1 (Pin 8): Output Voltage Select Bit. D1 should be tied
high to VIN2 or low to GND to select desired VOUT (see
Table 1).
D0 (Pin 9): Output Voltage Select Bit. D0 should be tied
high to VIN2 or low to GND to select desired VOUT (see
Table 1).
PGOOD (Pin 10): Power Good Open-Drain NMOS Output.
The PGOOD pin is Hi-Z when VOUT is above 92% of the
target value.
GND (Exposed Pad Pin 11): Ground. The exposed pad
should be connected to a continuous ground plane on the
second layer of the printed circuit board by several vias
directly under the LTC3388-1/LTC3388-3.
LTC3388-1/LTC3388-3
11
338813fa
For more information www.linear.com/LTC3388
OPERATION
The LTC3388-1/LTC3388-3 is an ultralow quiescent
current power supply designed to maintain a regulated
output voltage by means of a nanopower high efficiency
synchronous buck regulator.
Undervoltage Lockout (UVLO)
When the voltage on VIN rises above the UVLO rising
threshold the buck converter is enabled and charge is
transferred from the input capacitor to the output ca-
pacitor. If VIN falls below the UVLO falling threshold the
part will re-enter UVLO. In UVLO the quiescent current is
approximately 400nA and the buck converter is disabled.
Internal Rail Generation
Two internal rails, CAP and VIN2, are generated from VIN
and are used to drive the high side PMOS and low side
NMOS of the buck converter, respectively. Additionally the
VIN2 rail serves as logic high for EN, STBY, and output
voltage select bits D0 and D1. The VIN2 rail is regulated
at 4.6V above GND while the CAP rail is regulated at 4.8V
below VIN. The VIN2 and CAP rails are not intended to be
used as external rails. Bypass capacitors are connected
to the CAP and VIN2 pins to serve as energy reservoirs for
driving the buck switches. When VIN is below 4.6V, VIN2
is equal to VIN. CAP is at GND until VIN rises above 4.8V.
Figure 1 shows the ideal VIN, VIN2 and CAP relationship.
Buck Operation
The buck regulator uses a hysteretic voltage algorithm
to control the output through internal feedback from the
VOUT sense pin. The buck converter charges an output
capacitor through an inductor to a value slightly higher than
the regulation point. It does this by ramping the inductor
current up to 150mA through an internal PMOS switch and
then ramping it down to 0mA through an internal NMOS
switch. This efficiently delivers energy to the output ca-
pacitor. The ramp rate is determined by VIN, VOUT, and the
inductor value. When the buck brings the output voltage
into regulation the converter enters a low quiescent current
sleep state that monitors the output voltage with a sleep
comparator. During this operating mode load current is
provided by the buck output capacitor. When the output
voltage falls below the regulation point the buck regulator
wakes up and the cycle repeats. This hysteretic method
of providing a regulated output reduces losses associated
with FET switching and maintains an output at light loads.
The buck delivers a minimum of 50mA of average load
current when it is switching.
When the sleep comparator signals that the output has
reached the sleep threshold the buck converter may be
in the middle of a cycle with current still flowing through
the inductor. Normally both synchronous switches would
turn off and the current in the inductor would freewheel
to zero through the NMOS body diode. The LTC3388-1/
LTC3388-3 keeps the NMOS switch on during this time to
prevent the conduction loss that would occur in the diode
if the NMOS were off. If the PMOS is on when the sleep
comparator trips, the NMOS will turn on immediately in
order to ramp down the current. If the NMOS is on it will
be kept on until the current reaches zero.
Though the quiescent current when the buck is switching
is much greater than the sleep quiescent current, it is still
a small percentage of the average inductor current which
results in high efficiency over most load conditions. The
buck operates only when the output voltage discharges
to the sleep falling threshold. Thus, the buck operating
quiescent current is averaged with the low sleep quiescent
current. This allows the converter to remain very efficient
at loads as low as 10µA.
Figure 1. Ideal VIN, VIN2 and CAP Relationship
VIN (V)
0
VOLTAGE (V)
18
16
14
12
10
8
6
4
2
0
338813 F01
105 15
VIN
VIN2
CAP
LTC3388-1/LTC3388-3
12
338813fa
For more information www.linear.com/LTC3388
OPERATION
output is in regulation. The PGOOD pin will remain Hi-Z
until VOUT falls to 92% of the desired regulation voltage.
Additionally, if PGOOD is high and VIN falls below the
UVLO falling threshold, PGOOD will remain high until
VOUT falls to 92% of the desired regulation point. This
allows output energy to be used even if the input is lost.
Figure 2 shows the behavior for VOUT = 1.8V and a 10µA
load. At t = 2s VIN becomes high impedance and is dis-
charged by the quiescent current of the LTC3388-1 and
through servicing VOUT. VIN crosses UVLO falling but
PGOOD remains high until VOUT decreases to 92% of the
desired regulation point.
This scenario is likely for cases in which the selected
output voltage is below the UVLO falling threshold. If the
input becomes high impedance and begins to fall it will
be supported by the output through the body diode of
the PMOS switch. For a high enough output voltage the
part will not necessarily enter UVLO while VOUT remains
PGOOD. This is always true for the output voltages available
on the LTC3388-3.
The D0/D1 inputs can be switched while in regulation as
shown in Figure 3. If VOUT is programmed to a voltage with
a PGOOD falling threshold above the old VOUT, PGOOD will
transition low until the new regulation point is reached.
When VOUT is programmed to a lower voltage, PGOOD
will remain high through the transition.
The PGOOD pin is designed to drive a microprocessor or
other chip I/O and is not intended to drive higher current
loads such as an LED.
Figure 2. PGOOD Operation During Transition to UVLO Figure 3. PGOOD Operation During D0/D1 Transition
Four selectable voltages are available by tying the output
select bits, D0 and D1, to GND or VIN2. Table 1 shows the
four D0/D1 codes and their corresponding output voltages
as well as the difference in output voltages between the
LTC3388-1 and LTC3388-3.
Table 1. LTC3388-1/LTC3388-3 Output Voltage Selection
D1 D0 VOUT VOUT Quiescent Current (IVOUT)
0 0 1.2V/2.8V 28nA/66nA
0 1 1.5V/3.0V 36nA/72nA
1 0 1.8V/3.3V 43nA/78nA
1 1 2.5V/5.0V 60nA/120nA
The internal feedback network draws a small amount of
current from VOUT as listed in Table 1.
Dropout Operation
When the input supply voltage decreases towards the
output voltage, the rate of change of inductor current
decreases, reducing the switching frequency of the cur-
rent bursts. Further reduction in input supply voltage will
eventually cause the PMOS to be turned on 100%, i.e.,
DC. The output voltage will then be determined by the
input voltage minus the voltage drop across the PMOS
and the inductor.
Power Good Comparator
A power good comparator causes the PGOOD pin to
go Hi-Z the first time the converter reaches the sleep
threshold of the programmed VOUT, signaling that the
TIME (sec)
0
VOLTAGE (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
338813 F02
8642 10
VOUT
VIN
VIN = UVLO FALLING
PGOOD
CIN = 22µF, COUT = 100µF, ILOAD = 10µA
TIME (ms)
0
V
OUT
VOLTAGE (V)
6
5
4
3
2
1
0
338813 F03
8642 10 18161412 20
VOUT
COUT = 100µF, ILOAD = 50mA
PGOOD = LOGIC 1
D1=D0=0 D1=D0=1 D1=D0=0
LTC3388-1/LTC3388-3
13
338813fa
For more information www.linear.com/LTC3388
OPERATION
Enable and Standby Modes
Two logic pins, EN and STBY, determine the operating
mode of the LTC3388-1/LTC3388-3. When EN is high
and STBY is low the synchronous buck converter is
enabled and will regulate the output if the input voltage
is above the programmed output voltage and above the
UVLO threshold. If EN is low the buck converter circuitry
is powered down to save quiescent current. The internal
rail generation circuits are kept alive and the voltages at
VIN2 and CAP are maintained. When low, EN also shuts
down the PGOOD circuitry and pulls the PGOOD pin low.
If EN is high and the input falls below the UVLO threshold,
the buck converter is shut down.
While enabled, the LTC3388-1/LTC3388-3 can be placed
in standby mode by bringing STBY high. In standby mode
the buck converter is disabled, eliminating the quiescent
current used to run the buck circuitry. The PGOOD and
sleep comparators are kept alive to maintain the state of
the PGOOD pin.
The sleep comparator has lower quiescent current than the
PGOOD comparator and when the LTC3388-1/LTC3388-3
is in sleep mode the PGOOD comparator is shut down and
PGOOD is held high. The same occurs in standby mode.
If the LTC3388-1/LTC3388-3 was in sleep before entering
standby it will stay in sleep in standby, saving the quiescent
current of the PGOOD comparator. If VOUT falls below the
sleep falling threshold the PGOOD comparator will be
enabled. If VOUT falls below the PGOOD falling threshold
the PGOOD pin will be pulled low.
If STBY is driven high with EN low it will be ignored and
the LTC3388-1/LTC3388-3 will remain shut down.
If EN and STBY are driven high but near VIH or low but
near VIL, additional quiescent current may appear on VIN.
This additional quiescent current is typically 40nA and
depends on VIN and temperature. Driving EN or STBY to
0V or VIN2 will prevent additional quiescent current on VIN.
Figure 4 shows VOUT during a transition into and out of
standby. While in standby, the buck is off and VOUT is quiet.
Figure 4. LTC3388-3 Standby Transient,
VOUT = 3.3V, ILOAD = 5mA
500µs/DIV
0V
VOUT
50mV/DIV
AC-COUPLED
VIN = 5.5V,
L = 22µH, COUT = 100µF
STANDBY TRANSIENT
STANDBY
5V/DIV
338813 F04
LTC3388-1/LTC3388-3
14
338813fa
For more information www.linear.com/LTC3388
APPLICATIONS INFORMATION
Introduction
The basic LTC3388-1/LTC3388-3 application circuit is
shown on the front page. External components are selected
based on the performance requirements of the application.
Input Capacitor Selection
The input capacitor at VIN should be selected to adequately
bypass the LTC3388-1/LTC3388-3 and filter the switching
current presented by the buck regulator. The VIN capacitor
should be rated to withstand the highest voltage ever
present at VIN. It should be placed as close as possible
to the LTC3388-1/LTC3388-3 to force the high frequency
switching current into a tight local loop to minimize EMI. A
2.2μF ceramic X7R or X5R capacitor should be adequate
for bypassing.
High ripple current, high voltage rating, and low ESR make
ceramic capacitors ideal for switching regulator applica-
tions. However, care must be taken when these capacitors
are used at the input and output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, VIN. A sudden inrush of current
through the long wires can potentially cause a voltage
spike at VIN large enough to damage the part.
For such applications with inductive source impedance,
such as a long wire, a series RC network may be required
in parallel with CIN to dampen the ringing of the input
supply. Figure 5 shows this circuit and the typical values
required to dampen the ringing. The RC resistor may be
replaced by a single electrolytic capacitor that has an ESR
equivalent to the needed series resistance of the network.
See Application Note 88 for a complete discussion of this
phenomenon.
Output Capacitor Selection
The duration for which the regulator sleeps depends on
the load current and the size of the output capacitor.
The sleep time decreases as the load current increases
and/or as the output capacitor decreases. The DC sleep
hysteresis window, VHYST, is ±8mV and ±16mV around
the programmed output voltage on the LTC3388-1 and
LTC3388-3 respectively. Ideally this means that the sleep
time is determined by the following equation:
tSLEEP =COUT
V
HYST
I
LOAD
This is true for output capacitors on the order of 100μF
or larger, but as the output capacitor decreases towards
10μF delays in the internal sleep comparator along with
the load current may result in the VOUT voltage slewing
past the ±8mV/±16mV thresholds. This will lengthen the
sleep time and increase VOUT ripple. A capacitor less than
10μF is not recommended as VOUT ripple could increase
to an undesirable level.
338813 F05
VIN
LTC3388-1/
LTC3388-3
4•CIN CIN
LIN
R=LIN
CIN
Figure 5. Series RC to Reduce VIN Ringing
LTC3388-1/LTC3388-3
15
338813fa
For more information www.linear.com/LTC3388
If transient load currents above 50mA are required then a
larger capacitor can be used at the output. This capacitor
will be continuously discharged during a load condition and
the capacitor can be sized for an acceptable drop in VOUT:
COUT = (ILOAD – IBUCK )
t
LOAD
VOUT+– VOUT –
Here VOUT+ is the value of VOUT when PGOOD goes high
and VOUT– is the desired lower limit of VOUT. IBUCK is the
average current being delivered from the buck converter,
typically IPEAK/2.
A standard surface mount ceramic capacitor can be used
for COUT, though some applications may be better suited
to a low leakage aluminum electrolytic capacitor or a
supercapacitor. These capacitors can be obtained from
manufacturers such as Vishay, Illinois Capacitor, AVX,
or CAP-XX.
Inductor
The buck is optimized to work with an inductor of at least
22μH. This value represents a suitable trade-off between
size and efficiency for typical applications. A larger inductor
will benefit high voltage applications by increasing the
on-time of the PMOS switch and improving efficiency
by reducing gate charge loss. Choose an inductor with
APPLICATIONS INFORMATION
a DC current rating greater than 200mA. The DCR of the
inductor can have an impact on efficiency as it is a source
of loss. Trade-offs between price, size, and DCR should be
evaluated. Table 2 lists several inductors that work well
with the LTC3388-1/LTC3388-3.
Table 2. Recommended Inductors for LTC3388-1/LTC3388-3
INDUCTOR TYPE
L
(µH)
MAX
IDC
(mA)
MAX
DCR
(Ω)
SIZE in mm
(L × W × H)
MANU-
FACTURER
CDRH2D18/LDNP 22 300 0.320 3.2 × 3.2 × 2.0 Sumida
A997AS-220M 22 390 0.440 4.0 × 4.0 × 1.8 Toko
LPS5030-223MLC 22 700 0.190 4.9 × 4.9 × 3.0 Coilcraft
LPS4012-473MLC 47 350 1.400 4.0 × 4.0 × 1.2 Coilcraft
SLF7045T 100 500 0.250 7.0 × 7.0 × 4.5 TDK
VIN2 and CAP Capacitors
A 1μF capacitor should be connected between VIN and
CAP and a 4.7μF capacitor should be connected between
VIN2 and GND. These capacitors hold up the internal rails
during buck switching and compensate the internal rail
generation circuits. In applications where the input source
is limited to less than 6V, the CAP pin can be tied to GND
and the VIN2 pin can be tied to VIN as shown in Figure 6.
This circuit does not require the capacitors on VIN2 and
CAP, saving components and allowing a lower voltage
rating for the single VIN capacitor.
338813 F06
EN
STBY
VIN
VIN2
CAP
D1
D0
EN
STBY
PGOOD
SW
VOUT
PGOOD
LTC3388-1
GND
2.2µF
6V
2.7V TO 5.5V
10µF
6V
VOUT
1.2V
22µH
Figure 6. Smallest Solution Size 1.2V
Low Input Voltage Power Supply
LTC3388-1/LTC3388-3
16
338813fa
For more information www.linear.com/LTC3388
APPLICATIONS INFORMATION
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (η1 + η 2 + η 3 + ...)
where η1, η2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of
the losses: 1) DC VIN operating current while active and
in sleep, 2) MOSFET gate charge loss, and 3) I2R losses.
The VIN operating current dominates the efficiency loss
at very low load currents whereas the gate charge and
I2R loss dominates the efficiency loss at medium to high
load currents.
1. The DC VIN current is the average of the quiescent
supply currents, given in the electrical characteristics,
in the active and sleep modes. This can be estimated
with the following equation:
IVIN(AVG) =ILOAD
IBUCK
IQ(ACTIVE) +1−ILOAD
IBUCK
IQ(SLEEP)
where IBUCK is the average current being delivered
from the buck converter, typically IPEAK/2. For very
light loads IQ(SLEEP) will dominate this loss term which
is why the extremely low quiescent current in sleep of
the LTC3388-1/LTC3388-3 is critical.
2. Internal MOSFET gate charge currents result from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched
from high to low to high again, a packet of charge, dQ,
moves from VIN to ground. The resulting dQ/dt is the
current out of VIN that is typically larger than the DC
bias current. Of course, this switching current only
appears when the buck is on and is important at high
load currents. Gate charge loss can be reduced by in-
creasing the inductor, thereby reducing the switching
frequency when the buck is active.
3. I2R losses are calculated from the resistances of the
internal switches, RSW, and the external inductor DCR.
When switching, the average output current flowing
through the inductor is “chopped” between the high
side PMOS switch and the low side NMOS switch. Thus,
the series resistance looking back into the switch pin is
a function of the top and bottom switch on-resistance
and the duty cycle (DC = VOUT/VIN) as follows:
RSW = (RP,BUCK)DC + (RN,BUCK)(1 – DC)
The on-resistance for both the top and bottom MOSFETs
can be obtained from the curves in the Typical Perfor-
mance Characteristics section. Thus, to obtain the I2R
losses, simply add RSW to the DCR and multiply the
result by the square of the average output current:
I2R Loss = IO2(RSW + DCR)
This loss term only occurs when the buck is operating
and must be multiplied by the percentage of time the
buck is operating versus sleeping or ILOAD/IBUCK to see
its overall effect.
Other losses, including CIN and COUT ESR dissipative losses
and inductor core losses, generally account for less than
2% of the total power loss.
LTC3388-1/LTC3388-3
17
338813fa
For more information www.linear.com/LTC3388
APPLICATIONS INFORMATION
Interfacing with a Microprocessor
The PGOOD, STBY, and EN pins can be useful when pow-
ering a microprocessor from the LTC3388-1/LTC3388-3.
The PGOOD signal can be used to enable a sleeping micro-
processor or other circuitry when VOUT reaches regulation,
as shown in Figure 7. While active, a microprocessor may
draw a small load when operating sensors, and then draw a
large load to transmit data. Figure 7 shows the LTC3388-1/
LTC3388-3 responding smoothly to such a load step.
The microprocessor or other circuitry may require a quiet
supply for performing some functions. The STBY pin allows
the microprocessor to place the LTC3388-1/LTC3388-3
into standby mode where the buck converter is inactive. Any
ripple in the output voltage of the LTC3388-1/LTC3388-3
will cease and the output capacitor will support the load of
the microprocessor and other circuitry. While in standby
the output voltage will decrease as it’s loaded. The output
capacitor should be sized to minimize the decline.
The EN pin can be used to activate the LTC3388-1/LTC3388-3.
For instance, in Figure 8 the LTC3388-1 is enabled by the
PGOOD output of the LTC3588-1, a piezoelectric energy
harvesting power supply, to create a 1.2V rail. The quies-
cent current that the LTC3388-1 draws will appear at the
input of the LTC3588-1, reduced by the conversion ratio
of the LTC3588-1 buck converter. Because the LTC3388-1
is driven by a 3.3V supply no capacitors are needed for
the internal VIN2 and CAP rails.
Figure 7. 1.8V Step-Down Converter Powering a Microprocessor
with a Wireless Transmitter and 45mA Load Step Response
250µs/DIV
VOUT
20mV/DIV
AC-COUPLED
VIN = 5.5V
L = 22µH, COUT = 100µF
LOAD STEP BETWEEN 5mA AND 50mA
LOAD
CURRENT
25mA/DIV
0mA
338813 F07b
338813 F07a
VIN
VIN2
EN
D1
CAP
D0
STBY
PGOOD
SW
VOUT
STBY
EN
CORE
TX
LTC3388-1
GND
10µF
6V
Li-ION
2.7V TO 4.2V
+
47µF
6V
1M
22µH
1.8V
MICROPROCESSOR
GND
LTC3388-1/LTC3388-3
18
338813fa
For more information www.linear.com/LTC3388
APPLICATIONS INFORMATION
Figure 8. Piezoelectric Energy Harvester and 1.2V Secondary Rail
338813 F07
PZ1
VIN
CAP
VIN2
D1
D0
PZ2
PGOOD
SW
VOUT
LTC3588-1
MIDE V21BL
GND
10µF
25V
10µF
6V
1M
47µH
1µF
6V
4.7µF
6V
EN
VIN2
VIN
CAP
D1
D0
PGOOD
SW
VOUT
STBY
LTC3388-1
GND
47µF
6V
1.2V
3.3V
22µH
LTC3388-1/LTC3388-3
19
338813fa
For more information www.linear.com/LTC3388
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC3388-1/LTC3388-3
20
338813fa
For more information www.linear.com/LTC3388
MSOP (MSE) 0210 REV D
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
1234 5
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910
10
1
76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
1.68 ± 0.102
(.066 ± .004)
1.88 ± 0.102
(.074 ± .004)
0.50
(.0197)
BSC
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.68
(.066)
1.88
(.074)
0.1016 ± 0.0508
(.004 ± .002)
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev D)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC3388-1/LTC3388-3
21
338813fa
For more information www.linear.com/LTC3388
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/15 Modified COUT Equation 15
LTC3388-1/LTC3388-3
22
338813fa
For more information www.linear.com/LTC3388
LINEAR TECHNOLOGY CORPORATION 2010
LT 0815 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3388
RELATED PARTS
TYPICAL APPLICATION
Piezoelectric Energy Harvester with Dual, ±3.3V Outputs
338813 TA02
PZ1
VIN
CAP
VIN2
D1
D0
PZ2
PGOOD
SW
VOUT
LTC3588-1
GND
10µF
25V 47µF
6V
22µH
1µF
6V
4.7µF
6V
2.2µF
10V
1µF
6V
4.7µF
6V
VIN
CAP
VIN2
EN
D1
D0
PGOOD
SW
VOUT
STBY
LTC3388-3
*
GND
47µF
6V
–3.3V
3.3V
22µH
* EXPOSED PAD MUST BE ELECTRICALLY ISOLATED FROM
SYSTEM GROUND AND CONNECTED TO THE –3.3V RAIL.
PART NUMBER DESCRIPTION COMMENTS
LT1389 Nanopower Precision Shunt Voltage Reference 800nA Operating Current, 1.25V/2.5V/4.096V
LTC1540 Nanopower Comparator with Reference 0.3µA IQ, Drives 0.01µF, Adjustable Hysteresis, 2V to 11V Input Range
LT3009 3µA IQ, 20mA Low Dropout Linear Regulator Low 3µA IQ, 1.6V to 20V Range, 20mA Output Current
LTC3588-1 Piezoelectric Energy Harvesting Power Supply <1µA IQ in Regulation, 2.7V to 20V Input Range,
Integrated Bridge Rectifier
LTC3588-2 Piezoelectric Energy Harvesting Power Supply <1µA IQ in Regulation, UVLO Rising = 16V, UVLO Falling = 14V,
VOUT = 3.45V, 4.1V, 4.5V, 5.0V
LT3652 Power Tracking 2A Battery Charger for Solar Power MPPT for Solar, 4.95V to 32V, Up to 2A Charge Current
LT3970 40V, 350mA Step-Down Regulator with 2.5µA IQIntegrated Boost and Catch Diodes, 4.2V to 40V Operating Range
LT3971 38V, 1.2A, 2MHz Step-Down Regulator with 2.8µA IQ4.3V to 38V Operating Range, Low Ripple Burst Mode
®
Operation
LT3991 55V, 1.2A 2MHz Step-Down Regulator with 2.8µA IQ4.3V to 55V Operating Range, Low Ripple Burst Mode Operation
LTC3631 45V, 100mA, Synchronous Step-Down Regulator with 12µA IQ4.5V to 45V Operating Range, Overvoltage Lockout Up to 60V
LTC3642 45V, 50mA, Synchronous Step-Down Regulator with 12µA IQ4.5V to 45V Operating Range, Overvoltage Lockout Up to 60V
