
www.irf.com 1
10/6/05
IRF6621
DirectFET Power MOSFET
Description
The IRF6621 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the
lowest on-state resistance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile. The DirectFET package is compatible
with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering
techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows
dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF6621 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching
losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of processors
operating at higher frequencies. The IRF6621 has been optimized for parameters that are critical in synchronous buck operating from 12 volt
bus converters including Rds(on) and gate charge to minimize losses in the control FET socket.
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
Fig 1. Typical On-Resistance Vs. Gate Voltage
Typical values (unless otherwise specified)
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
l RoHs Compliant Containing No Lead and Bromide
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Ultra Low Package Inductance
l Optimized for High Frequency Switching
lIdeal for CPU Core DC-DC Converters
l Optimized for Control FET application
l Low Conduction and Switching Losses
l Compatible with existing Surface Mount Techniques
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
TC measured with thermocouple mounted to top (Drain) of part.
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 0.29mH, RG = 25Ω, IAS = 9.6A.
Notes:
DirectFET ISOMETRIC
SQ
2.0 4.0 6.0 8.0 10.0
VGS, Gate-to-Source Voltage (V)
5
10
15
20
25
Typical RDS(on) (
mΩ)
TJ = 25°C
TJ = 125°C
ID = 12A
0 4 8 12 16 20 24 28
QG Total Gate Charge (nC)
0
2
4
6
8
10
12
VGS, Gate-to-Source Voltage (V)
VDS= 24V
VDS= 15V
ID= 9.6A
VDSS VGS RDS(on) RDS(on)
30V max ±20V max 7.0mΩ@ 10V 9.3mΩ@ 4.5V
SQ SX ST MQ MX MT MP
Absolute Maximum Ratin
s
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V
e
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V
e
A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
f
IDM Pulsed Drain Current
g
EAS Single Pulse Avalanche Energy
h
mJ
IAR Avalanche Current
g
A
Max.
9.6
55
96
±20
30
12
13
9.6
Qg tot Qgd Qgs2 Qrr Qoss Vgs(th)
11.7nC 4.2nC 1.0nC 10nC 6.9nC 1.8V
PD - 97005A