Dp AC DS1258Y/AB (= DALLAS 128k x 16 Nonvolatile SRAM FEATURES PIN ASSIGNMENT 10-year minimum data retention in the cau Veo absence of external power CEL 2 WE = Data is automatically protected during a DQi5 #3 A16 powers | core fs ae = Separate upper byte and lower byte chip pai2 fe A13 select inputs DQi1 i7 A12 = Unlimited write cycles sce 8 Mo = Low-power CMOS Das AQ = Read and write access times as fast as 70 ns GND GND = Lithium energy source is electrically DQ7 A8 disconnected to retain freshness until power is D6 A7 applied for the first time Das x = Full +10% operating range (DS1258Y) bas AA = Optional +5% operating range (DS1258AB) bae A3 bat A2 DQo Al OE AO 40-Pin ENCAPSULATED PACKAGE 740-mil EXTENDED PIN DESCRIPTION AO - Al6 - Address Inputs DQO - DQ15 - Data In/Data Out CEU - Chip Enable Upper Byte CEL - Chip Enable Lower Byte WE - Write Enable OE - Output Enable Vec - Power (+5V) GND - Ground DESCRIPTION The DS1258 128k x 16 Nonvolatile SRAMs are 2,097,152-bit fully static, nonvolatile SRAMs, organized as 131,072 words by 16 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors Vcc for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package DS1258 devices can be used in place of solutions which build nonvolatile 128k x 16 memory by utilizing a variety of discrete components. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 8 111999DS1258Y/AB READ MODE The DS1258 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and either/both of CEU or CEL (Chip Enables) are active (low) and OE (Output Enable) is active (low). The unique address specified by the 17 address inputs (AQ-A16) defines which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will be available to the 16 data output drivers within tacc (Access Time) after the last address input signal is stable, providing that CEU, CEL and OE access times are also satisfied. If CEU, CEL, and OE access times are not satisfied, then data access must be measured from the later occurring signal, and the limiting parameter is either tco for CEU , CEL, or top for OE rather than address access. WRITE MODE The DS1258 devices execute a write cycle whenever WE and either/both of CEU or CEL are active (low) after address inputs are stable. The unique address specified by the 17 address inputs (AQ-A16) defines which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word is accessed. The write cycle is terminated by the earlier rising edge of CEU and/or CEL, or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (twr) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CEU and/or CEL, and OE active) then WE will disable the outputs in topw from its falling edge. READ/WRITE FUNCTION Table 1 __ _ _ _ Voc CYCLE OE WE CEL CEU CURRENT | DQ0-DQ7 | DQ8-DQ15 | PERFORMED H H xX xX Iceco High-Z High-Z Output Disabled L H L L Output Output L H L H Icco Output High-Z Read Cycle L H H L High-Z Output 4 L L L Input Input XxX L L H Icco Input High-Z Write Cycle 4 L H L High-Z Input XxX XxX H H Iccs High-Z High-Z Output Disabled DATA RETENTION MODE The DS1258AB provides full functional capability for Vcc greater than 4.75 volts, and write protects by 4.5 volts. The DS1258Y provides full functional capability for Vcc greater than 4.5 volts and write protects by 4.25 volts. Data is maintained in the absence of Vcc without any additional support circuitry. The nonvolatile static RAMs constantly monitor Vcc. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become dont care, and all outputs become high 2 of 8DS1258Y/AB impedance. As Vcc falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when Vcc rises above approximately 3.0 volts, the power switching circuit connects external Vcc to RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 4.75 volts for the DS1258AB and 4.5 volts for the DS1258Y. FRESHNESS SEAL The DS1258 devices are shipped from Dallas Semiconductor with the lithtum energy sources disconnected, guaranteeing full energy capacity. When Vcc is first applied at a level greater than Vp, the lithium energy source is enabled for battery backup operation. ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +7.0V Operating Temperature 0C to 70C Storage Temperature -40C to +70C Soldering Temperature 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS ta: 0C to 70C) PARAMETER SYMBOL | MIN | TYP | MAX | UNITS | NOTES DS1258AB Power Supply Voltage Voc 4.75 5.0 5.25 Vv DS1258AB Power Supply Voltage Voc 4.5 5.0 5.5 Vv Logic 1 Vin 2.2 Vec Vv Logic 0 Vi 0.0 +0.8 Vv DC ELECTRICAL (Vcc=5V + 5% for DS1258AB) CHARACTERISTICS (ta: OC to 70C) (Vcoc=5V + 10% for DS1258Y) PARAMETER SYMBOL | MIN | TYP | MAX | UNITS | NOTES Input Leakage Current Ih. -2.0 +2.0 LA I/O Leakage Current CE > Vin $ Vcc Tio -1.0 +1.0 LA Output Current @ 2.4V lou -1.0 mA Output Current @ 0.4V Ton 2.0 mA Standby Current CEU , CEL =2.2V Tees1 10 20 mA Standby Current CEU , CEL =Vcc-0.5V Iccs2 6 10 mA Operating Current Icco1 170 mA Write Protection Voltage (DS1258AB) Vip 4.50 4.62 4.75 Vv Write Protection Voltage (DS1258Y) Vip 4,25 4.37 4.5 V 3 of 8DS1258Y/AB CAPACITANCE (ty=25C) PARAMETER SYMBOL | MIN | TYP | MAX | UNITS | NOTES Input Capacitance Ci 20 25 pF Input/Output Capacitance Cro 5 10 pF AC ELECTRICAL (Vec=5V + 5% for DS1258AB) CHARACTERISTICS (ta: OC to 70C) (Vec=5V + 10% for DS1258Y) DS1258AB-70 | DS1258AB-100 DS1258Y-70 DS1258Y-100 PARAMETER SYMBOL | MIN | MAX | MIN | MAX | UNITS | NOTES Read Cycle Time trc 70 100 ns Access Time tacc 70 100 ns OE to Output Valid tor 35 50 ns CE to Output Valid tco 70 100 ns OE or CE to Output Valid tcor 5 5 ns 5 Output High Z from Deselection top 25 35 ns 5 Output Hold from Address Change tox 5 5 ns Write Cycle Time twc 70 100 ns Write Pulse Width twe 55 75 ns 3 Address Setup Time taw 0 0 ns Write Recovery Time twr1 5 5 ns 12 twr2 15 15 ns 13 Output High Z from WE topw 25 35 ns 5 Output Active from WE tozw 5 5 ns Data Setup Time tos 30 40 ns 4 Data Hold Time toni 0 0 ns 12 tor 10 10 ns 13 READ CYCLE x >| ADDRESSES Q : ye MA wn Va tacc on CEU, OL SQ ww Vv "69 2 ULL oO : [Me el LL top & SSssaa WALA / je top = + bon ___ ral 1 Sw DES SEE NOTE 1 4 of 8DS1258Y/AB WRITE CYCLE1 Le J we ADDRESSES ve vi Ma tw CEU, CEL IS Ve. WLLL a . fo Pa. en ee. i foew toow tor SOSCSESC SESE SLES ee SZSZSZSC LNLNLSLNSLNLNLNLY NAZNZNZN SL | tos tout Vn vi Dw DATA IN STABLE Vv Va, SEE NOTE 2, 3, 4, 6, 7, 8 AND 12 WRITE CYCLE 2 a two al al al KA Da SEE NOTES 2, 3,4, 6, 7 AND 13 5 of 8DS1258Y/AB POWER-DOWN/POWER-UP CONDITION Vcc Vtp 3.2V tp > ~< | ht tr too S | | el tres J ow RSS SFE |. SUPPLIEO FROM SS LITHIUM CELL _ DATA OE oN SEE NOTE 11 oR POWER-DOWN/POWER-UP TIMING ta: OC to 70C) PARAMETER SYMBOL | MIN | TYP | MAX | UNITS | NOTES CEU, CEL at Vi before Power-Down tpp 0 Ls 11 Vec slew from Vp to OV tr 300 Ls Vec slew from OV to Vrp tr 300 Ls CEU , CEL at Viy after Power-Up trEc 2 125 ms (ty=25C) PARAMETER SYMBOL | MIN | TYP | MAX | UNITS | NOTES Expected Data Retention Time tor 10 years 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high for a Read Cycle. 2. OF = Vypor Vy. If OF = Vin during write cycle, the output buffers remain in a high impedance state. 3. twp is specified as the logical AND of CEU or CEL and WE. twp is measured from the latter of CEU , CEL or WE going low to the earlier of CEU, CEL or WE going high. 4. tps is measured from the earlier of CEU or CEL or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. Ifthe CEU or CEL low transition occurs simultaneously with or later than the WE low transition in the output buffers remain in a high impedance state during this period. 7. Ifthe CEU or CEL high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high impedance state during this period. 6 of 8DS1258Y/AB 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CEU or CEL low transition, the output buffers remain in a high impedance state during this period. 9. Each DS1258 has a built-in switch that disconnects the lithium source until Vcc is first applied by the user. The expected tpr is defined as accumulative time in the absence of Vcc starting from the time power is first applied by the user. 10. All AC and DC electrical characteristics are valid over the full operating temperature range OC to 70C, 11. In a power-down condition the voltage on any pin may not exceed the voltage on Vcc. 12. twri, toni are measured from WE going high. 13. twee, tpH2 are measured from CEU OR CEL going high DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open Output Load: 100 pF + 1TTL Gate Cycle = 200 ns Input Pulse Levels: All voltages are referenced to ground 0.0 to 3.0 volts Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5 ns ORDERING INFORMATION DS1250,TTP,-SSS,- TI | Operating Temperature Range blank: OC to 70C Access Speed | 70: 70 ns 100: 100ns Package Type +_| blank: 40-pin, 600-mil DIP Vcc Tolerance | AB +5% Y: +10% 7 of 8DS1258Y/AB DS1258Y/AB NONVOLATILE SRAM 40-PIN, 740-MIL EXTENDED MODULE PKG 40-PIN DIM MIN MAX A IN. 2.080 2.100 MM 52.83 53.34 B IN. 0.715 0.740 MM 18.16 18.80 C IN. 0.345 0.365 MM 8.76 9.27 D IN. 0.085 0.115 MM 2.16 2.92 E IN. 0.015 0.030 MM 0.38 0.76 FIN. | 0.120 | 0.160 a bed wile ela mm | 3.05 | 4.06 , @ IN. | 0.090 | 0.110 mM | 229 | 279 H_ IN. 0.590 0.630 MM 14.99 16.00 JIN. 0.008 0.012 MM 0.20 0.30 K IN. 0.015 0.025 MM 0.43 0.58 8 of 8