Advisory October 28, 2003 TSWC01622/TSWC02622/TSWC03622/TSYN01622/TSYN03622 Device Version 1.1 Advisory The following data sheets are to be referenced: TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet (DS03-117HSPL-1). TSWC02622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet (DS03-118HSPL-1). TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet (DS03-120HSPL). TSYN01622 SONET/SDH/PDH/ATM Clock Synthesizer data sheet (DS03-119HSPL). TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer data sheet (DS03-130HSPL-1). Note: Customers must check with their Agere representative for the current version of this advisory; this is a continuously updated document. 1 TSWC01622 October 2002, Device Exceptions 1.1 Exception 1--Squelch Mode Applies to TSWC01622, TSWC02622, TSWC03622, TSYN01622, and TSYN03622. Active 622.08 MHz and 155.52 MHz LVDS clocks are not affected by the squelch signal; therefore, they are active outputs and not held in a low state when ENSQLN is enabled and all clocks (CLKA, CLKB, and CLKBU) have a fault. The LVPECL and CMOS outputs (including the LVPECL and CMOS sync outputs) are compatible with the data sheet regarding squelch and enable signals. The LVDS sync outputs are also compatible with the data sheet. Workaround: No known workaround. Corrective Action: None. 1.2 Exception 2--Switching Out of Backup Clock Mode in Autonomous Nonrevertive Mode Applies to TSWC01622, TSWC02622, and TSWC03622. In autonomous, nonrevertive mode, if the TSWC01622 switches to the backup clock, it will not switch back to clock A or clock B should either of the two input clocks become valid. Workaround: The device must be put into manual mode, and the appropriate input clock must be selected. Corrective Action: None. TSWC01622/TSWC02622/TSWC03622/TSYN01622/TSYN03622 Device Version 1.1 Advisory Advisory October 28, 2003 1.3 Exception 3--Backup Clock Input (CLKBU) Applies to TSWC01622, TSWC02622, and TSWC03622. The TSWC01622 may not provide precise phase and frequency lock to CLKBU when the backup clock is configured for a rate greater than 8 kHz. The TSWC01622 does provide precise phase and frequency lock when an 8 kHz backup clock rate is selected and an 8 kHz clock is applied to CLKBU. When the backup clock rate is configured for rates other than 8 kHz and the selected rate is applied to CLKBU, the output clocks of the TSWC01622 may not be in phase alignment with CLKBU. However, the average frequency of the TSWC01622 output clocks will be proportional to the input frequency. For example, if an input clock rate of 38.88 MHz + 10 ppm is applied to CLKBU, the TSWC01622 CMOS output CK19 will be at 19.44 MHz + 10 ppm. Workaround: Configure the TSWC01622 for a backup clock frequency of 8 kHz, and use a backup clock source of 8 kHz. Corrective Action: None. 1.4 Exception 4--Writing Registers Using the Serial Interface Applies to TSWC01622, TSWC02622, TSWC03622, TSYN01622, and TSYN03622. Occasionally, when executing a serial interface write operation, the write operation is not successful. Workaround: Two means can be applied as follows: After performing a write operation, perform a read operation and examine the register contents to which the write operation was intended. If the value contained in the register is incorrect, perform an additional write and read operation to verify register contents. Always perform two consecutive write operations to the same register without an intervening command. Two consecutive write operations have been verified to completely eliminate the occasional write operation error. Corrective Action: There is no additional corrective action deemed necessary for this issue as the work around completely eliminates this issue. 2 Agere Systems Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755 25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems, the Agere logo, Ultramapper, Hypermapper, and Supermapper are trademarks of Agere Systems Inc. Copyright (c) 2003 Agere Systems Inc. All Rights Reserved October 28, 2003 AY04-001HSPL (Replaces AY02-036HSPL, must accompany DS03-117HSPL-1, DS03-118HSPL-1, DS03-119HSPL, DS03-120HSPL, and DS03-130HSPL-1) Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 1 Introduction The last issue of this data sheet was June 20, 2003. A revision history is included in 21 Revision History on page 65. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically mentioned. Throughout this document references are made to the following application notes: Supports multiple input clock frequencies: 51.84 MHz 8.192 MHz 1.544 MHz TSWC01622/TSYN01622 Loop Filters: Compatible Components. 38.88 MHz 6.48 MHz 8 kHz 19.44 MHz 2.048 MHz Generates sync outputs at 8 kHz aligned to an 8 kHz input clock signal Low skew clock distribution balls Compatible with Agere Systems Inc. TDAT04622/ TADM04622 SONET/ATM/POS devices, STSI-144, TSI-16, TSI-8, TMXF84622 Ultramapper, and TMXF28155 Supermapper Single 3.3 V supply Multiple output technologies--CMOS, LVPECL, or LVDS Same functionality as TSWC01622 with looser jitter specifications Fully integrated clock synthesis 77.76 MHz 38.88 MHz 24.704 MHz 8.192 MHz 2.048 MHz Five frequency programmable clock outputs 1.1 Features 155.52 MHz 44.736 MHz 32.768 MHz 16.384 MHz 2.43 MHz Clock Requirements for the TSWC03622/TSYN03622 Devices for Ultramapper TM Family Devices. http://www.agere.com/enterprise_metro_access/ system_timing_devices.html Supports a wide choice of SONET/SDH output clock frequencies with jitter quality up to OC-12: 622.08 MHz 51.84 MHz 34.368 MHz 19.44 MHz 4.096 MHz 1.544 MHz TSWC01622 Power Supply Grouping and Filtering. The application notes can be obtained by contacting the Agere representative, or accessing the web at: Programmable via external balls or internal registers via serial interface 1.2 Applications SONET/SDH and PDH add/drop multiplexers, cross connects, switches, and routers Remote access servers TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table of Contents Contents Page 1 Introduction .........................................................................................................................................................................1 1.1 Features ......................................................................................................................................................................1 1.2 Applications .................................................................................................................................................................1 2 Description ..........................................................................................................................................................................7 3 Block Diagram ....................................................................................................................................................................8 4 Pin Information ...................................................................................................................................................................9 5 Functional Overview .........................................................................................................................................................17 6 Input Clock Specifications ................................................................................................................................................18 6.1 Input Clock Stability Requirements ............................................................................................................................18 6.2 Input Frequency Selection (FINSEL[3:0]) ..................................................................................................................18 6.3 Input Electrical Level Selection for Clock Input Signal (SELLVDS) ...........................................................................18 6.4 Input Clock Minimum Pulse-Width Specifications .....................................................................................................18 6.4.1 Input Clock Minimum Pulse Width ...................................................................................................................18 6.5 Input Sync Signal Functionality .................................................................................................................................18 7 Output Clock Specifications ..............................................................................................................................................19 7.1 Available Output Clocks ............................................................................................................................................19 8 Jitter Specifications ...........................................................................................................................................................21 9 Synchronization Output at 8 kHz ......................................................................................................................................23 9.1 Sync Output (SYNC8K, SYLVSP/N[1:0], SYPCLKP/N[1:0]) .....................................................................................23 9.2 Sync Duty Cycle Selection (SYDU) ...........................................................................................................................23 9.3 Sync Alignment ..........................................................................................................................................................23 9.4 Offset Programming (SYOFF[9:0], SYOFFPOS) ......................................................................................................23 10 Skew Specifications ........................................................................................................................................................25 11 Output Specifications During Phase-Locked Condition (Nontransient Condition) ..........................................................30 11.1 Maximum Time Interval Error (MTIE) Specifications ...............................................................................................30 11.2 Time Deviation (TDEV) Specifications ....................................................................................................................32 12 Other Input and PLL Specifications ................................................................................................................................34 12.1 Input Clock Maximum Rate of Phase Change During Transient .............................................................................34 12.2 External 38.88 MHz VCXO Requirements ..............................................................................................................34 12.3 Loop Filter Components for High-Speed PLL ..........................................................................................................35 12.4 Loop Filter Components for Low-Speed PLL ..........................................................................................................35 12.5 INLOSN ...................................................................................................................................................................36 12.6 RREF .......................................................................................................................................................................36 13 State Machine and Software Interface ...........................................................................................................................37 13.1 State Machine Behavior ..........................................................................................................................................37 13.2 Squelch ....................................................................................................................................................................37 13.3 Software Interfacing .................................................................................................................................................37 13.4 Loss of Clock Criteria ..............................................................................................................................................37 13.5 Interrupt Generation (INT[6, 5, 3, 0]) .......................................................................................................................37 14 Serial Interface and Internal Bus ....................................................................................................................................38 15 TSYN03622 Registers Map ............................................................................................................................................40 15.1 Control Block Registers ...........................................................................................................................................42 15.2 Input Clock Block Registers .....................................................................................................................................43 15.3 State Machine Block Registers ................................................................................................................................45 15.4 PDH Output Block Registers ...................................................................................................................................46 15.4.1 Fractional Dividers Registers: 40h--66h ........................................................................................................46 15.5 General Configuration Registers 80h--83h .............................................................................................................46 15.6 SDH/Sync Generation Block Registers ...................................................................................................................50 15.7 LVPECL Output Syncs and Clocks .........................................................................................................................54 15.8 CMOS Output Syncs and Clocks ............................................................................................................................54 15.9 LVDS Output Syncs and Clocks ..............................................................................................................................55 2 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table of Contents (continued) Contents Page 16 Absolute Maximum Ratings ............................................................................................................................................60 16.1 Handling Precautions ..............................................................................................................................................60 16.2 Operating Conditions ...............................................................................................................................................60 16.3 Powerup Conditions ................................................................................................................................................60 17 Electrical Characteristics ................................................................................................................................................61 17.1 LVPECL, LVDS, CMOS, Input and Output Balls .....................................................................................................61 18 Timing Characteristics ....................................................................................................................................................63 19 Packaging Diagram ........................................................................................................................................................64 19.1 208-Plastic Ball Grid Array (17 x 17), 0.63 mm Ball Size (4-Layer--Bottom View) .................................................64 20 Ordering Information .......................................................................................................................................................65 Agere Systems Inc. 3 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table of Contents (continued) Figures Page Figure 3-1. TSYN03622 Block Diagram .................................................................................................................................8 Figure 4-1. TSYN03622 208-Ball PBGA (Top View) ..............................................................................................................9 Figure 6-1. Input Clock Minimum Pulse-Width Requirement................................................................................................18 Figure 8-1. Phase Noise Characteristic for Differential Output Clock CK51 Using LSPLL Filter..........................................22 Figure 8-2. Phase Noise Characteristic for Differential Output Clock CK77 Using LSPLL Filter..........................................22 Figure 10-1. PECL Sync to PECL Clock Skew Case: Syncs Aligned to 622 MHz Clock .....................................................25 Figure 10-2. PECL Sync to PECL Clock Skew Case, Sync Aligned to 155 MHz Clock.......................................................26 Figure 10-3. LVDS Sync to LVDS Clock Skew Case, Sync Aligned to 622 MHz Clock.......................................................27 Figure 10-4. LVDS Sync to LVDS Clock Skew Case, Sync Aligned to 155 MHz Clock.......................................................28 Figure 10-5. CMOS Sync to CMOS Clock Skew Case, Sync Aligned to SONET CMOS Output Clock ..............................29 Figure 11-1. MTIE Wander Generation in Locked Condition................................................................................................30 Figure 11-2. Measured MTIE Wander Generation Performance..........................................................................................31 Figure 11-3. Wander Generation in Locked Condition .........................................................................................................32 Figure 11-4. Measured TDEV Wander Generation Performance.........................................................................................33 Figure 12-1. Recommended High-Speed Loop Filter Circuit................................................................................................35 Figure 12-2. Recommended Low-Speed Phase-Lock Loop (LSPLL) Filter Circuit for Smaller Phase Offsets ....................36 Figure 14-1. TSYN03622 Serial Interface ............................................................................................................................38 Figure 14-2. Serial Interface WRITE Frame Format.............................................................................................................38 Figure 14-3. Serial Interface READ Frame Format ..............................................................................................................38 Figure 14-4. Serial Interface Timing .....................................................................................................................................39 4 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table of Contents (continued) Tables Page Table 4-1. Ball Assignments for 208-Ball PBGA by Ball Number Order ...............................................................................10 Table 4-2. Physical Ball Orientation (Bumps Down) .............................................................................................................12 Table 4-3. Clock Inputs and Related Signal..........................................................................................................................13 Table 4-4. Analog and PLL Related Signals .........................................................................................................................13 Table 4-5. Output Clocks and Related Signals .....................................................................................................................14 Table 4-6. Control and Related Signals ................................................................................................................................15 Table 4-7. Serial Interface Signals........................................................................................................................................15 Table 4-8. Test and Reserved Signals ..................................................................................................................................15 Table 4-9. No-Connect Signals.............................................................................................................................................16 Table 4-10. Power Signals....................................................................................................................................................16 Table 6-1. Input Clock Frequency Selection .........................................................................................................................18 Table 7-1. SDH Output Clock Selection (SDHSEL[3:0]).......................................................................................................20 Table 7-2. PDH Output Clock Selection (PDHSEL[3:0]).......................................................................................................20 Table 8-1. Output Clock Jitter Specifications ........................................................................................................................21 Table 9-1. Sync Duty Cycle Selection (SYDU) .....................................................................................................................23 Table 9-2. SYNC Offset Programming..................................................................................................................................24 Table 9-3. Enhanced SYNC Offset Programming ................................................................................................................24 Table 10-1. PECL Sync to PECL Clock Skew Parameters (Single Clock Pulse Sync Output Shown) ................................25 Table 10-2. PECL Sync to PECL Clock Skew Parameters (Single Clock Pulse Sync Output Shown) ................................26 Table 10-3. LVDS Sync to LVDS Clock Skew Parameters (Single Clock Pulse Sync Output Shown) .................................27 Table 10-4. LVDS Sync to LVDS Clock Skew Parameters (Single Clock Pulse Sync Output Shown) .................................28 Table 10-5. CMOS Sync to CMOS Clock Skew Parameters (15 pF, 1 k) ..........................................................................29 Table 11-1. Wander Generation (Nontransient)--MTIE ........................................................................................................30 Table 11-2. Wander Generation (Nontransient)--TDEV.......................................................................................................32 Table 12-1. Recommended High-Speed Loop Filter Values.................................................................................................35 Table 12-2. Recommended Low-Speed Loop Filter Values for Smaller Phase Offsets........................................................35 Table 13-1. Interrupt Generation (INT[6, 5, 3, 0]) Active-High ..............................................................................................37 Table 14-1. Serial Interface Timing .......................................................................................................................................39 Table 15-1. TSYN03622 Registers .......................................................................................................................................40 Table 15-2. Hardware Reset for All TSYN03622 Blocks ......................................................................................................42 Table 15-3. Software Override..............................................................................................................................................43 Table 15-4. Loss of Clock Block Software Override and Reset ............................................................................................43 Table 15-5. FINSEL[3:0] Register.........................................................................................................................................44 Table 15-6. Loss of Clock Threshold ....................................................................................................................................44 Table 15-7. Loss of Clock Hysteresis ...................................................................................................................................44 Table 15-8. State Machine Block Control Register ...............................................................................................................45 Table 15-9. State Machine Block State Machine Register....................................................................................................45 Table 15-10. Squelch............................................................................................................................................................46 Table 15-11. PDH Control Register 1 ...................................................................................................................................46 Table 15-12. PDH Clock Outputs for the 16 Preset Configurations (Bit 81h[3] = 0) .............................................................47 Table 15-13. PDH Control Register 2 ...................................................................................................................................48 Table 15-14. Enhanced Software Mode Fractional Divider Selection...................................................................................48 Table 15-15. Software Mode Fractional Divider Selection....................................................................................................49 Table 15-16. Fractional Dividers Operation Mode ................................................................................................................49 Table 15-17. SDH/Sync Control Register .............................................................................................................................50 Table 15-18. SDHSEL Register ............................................................................................................................................51 Table 15-19. Sync Duty Cycle ..............................................................................................................................................51 Table 15-20. Output Syncs Duty Cycle.................................................................................................................................51 Table 15-21. Sync Offset ......................................................................................................................................................51 Table 15-22. Sync Source ....................................................................................................................................................52 Table 15-23. SONET/SDH Clock Enable..............................................................................................................................53 Table 15-24. LVPECL Output Clock Output Status when Influenced by Programmable Duty Cycle on Syncs....................54 Agere Systems Inc. 5 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table of Contents (continued) Tables Page Table 15-25. LVPECL Output Clock Output Status when Influenced by Programmable Duty Cycle on Syncs....................54 Table 15-26. LVDS Output Clock Output Status when Influenced by Programmable Duty Cycle on Syncs ........................55 Table 15-27. Sync Duty Cycle ..............................................................................................................................................55 Table 15-28. CMOS SONET Clock Edge Selection .............................................................................................................56 Table 15-29. Enhanced Sync Offset .....................................................................................................................................56 Table 15-30. Sync Rising Edge Position...............................................................................................................................57 Table 15-31. Sync Falling Edge Position ..............................................................................................................................57 Table 15-32. Sync Delta .......................................................................................................................................................58 Table 15-33. Sync Delta Rise ...............................................................................................................................................58 Table 15-34. Interrupt Status Register..................................................................................................................................59 Table 16-1. Absolute Maximum Ratings ...............................................................................................................................60 Table 16-2. Handling Precautions.........................................................................................................................................60 Table 16-3. Recommended Operation Conditions................................................................................................................60 Table 17-1. LVDS Output dc Characteristics ........................................................................................................................61 Table 17-2. LVDS Input dc Characteristics ...........................................................................................................................61 Table 17-3. CMOS Input dc Characteristics .........................................................................................................................62 Table 17-4. CMOS Output dc Characteristics.......................................................................................................................62 Table 17-5. LVPECL Output dc Characteristics....................................................................................................................62 Table 18-1. LVDS Input ac Timing Characteristics ...............................................................................................................63 Table 18-2. LVDS Output ac Timing Characteristics.............................................................................................................63 Table 18-3. CMOS Input ac Timing Characteristics..............................................................................................................63 Table 18-4. CMOS Output ac Timing Characteristics ...........................................................................................................63 Table 18-5. LVPECL Output ac Timing Characteristics ........................................................................................................63 Table 20-1. Ordering Information..........................................................................................................................................65 6 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 2 Description The Agere Systems TSYN03622 is designed for a wide variety of synchronous timing applications. It serves as a clock synthesizer and low skew clock fan-out device generating clocks at frequencies up to 622.08 MHz that are synchronized to the system reference clock. The TSYN03622 also delivers an output sync signal that is aligned to the input clock. If 8 kHz system sync signals are applied as the clock input, the TSYN03622 will generate an output sync signal that is phase aligned to the selected input sync. A programmable phase offset is provided to allow the user to offset the output sync relative to the input sync. The output sync can be used for global alignment of cells or frames in SONET/SDH/PDH cross connects or ATM switch applications. The device allows flexible choices of LVDS or LVCMOS input technologies and LVDS, LVPECL, or LVCMOS output technologies. The TSYN03622 can be programmed via external balls, or through a serial interface. Enhanced functionality is available through the serial interface including, programmable clock outputs through fractional synthesis, and the ability to enable or disable each output individually. Agere Systems Inc. 7 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 3 Block Diagram SYCLK CLKP CLKN CLK ENABLE/ DISABLE DIV_M LF0Z LOC LF[2:0] P D LF SELLVDS DIVIDE FINSEL[3:0] VCXO 38.88 MHz LSVCO LOC38 INLOSN LF[P:N] VC[P:N] TSTCLKP ENSQLN TSTCLKN VCO P RESETN D CONTROL AND STATE MACHINE DIVIDE CP SYOFF[9:0] SYNC OFFSET ENTSTCLK SYOFFPOS SYDU D DIVIDE Q SYNC8K SYLVSP[1:0] SYLVSN[1:0] INT[6,5,3,0] BASED ON SDHSEL SYPCLP[1:0] SYPCLN[1:0] RREF PCK622P PCK622N CK622P CK622N CKPDH5 CKPDH4 CKPDH3 CKPDH2 CKPDH1 PDH CLOCK GEN. SONET CLOCK GEN. PDHSEL[3:0] PCK155P[1:0] PCK155N[1:0] CK155P[1:0] CK155N[1:0] CK77 TSTMODE SERCLK SERENBLN SERIAL I/F REGISTER CONTROL SERDAT CK51 CK38 CK19 SDHSEL[3:0] Note: The magenta portions of the figure indicate test features. Figure 3-1. TSYN03622 Block Diagram 8 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 4 Pin Information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2360 (F) Figure 4-1. TSYN03622 208-Ball PBGA (Top View) Agere Systems Inc. 9 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 4.1 Pin Assignments Table 4-1. Ball Assignments for 208-Ball PBGA by Ball Number Order Note: -- refers to no ball. NC means do not connect any traces to this solder ball. 10 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 GND CK155N0 CK155P0 GND SYLVSN0 SYLVSP0 GND CK622N CK622P GND SYLVSN1 SYLVSP1 GND CK155N1 CK155P1 GND PCK155N0 CK19 VDDPDH CKPDH2 VDDPDH GND GND GND GND GND GND GND GND SYOFF6 TSTMODE TSTCLKP C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 PCK155P0 CK38 CKPDH1 CKPDH3 CKPDH5 VDDLVDS GND GND GND GND VDDSDH SYOFF2 SYOFF5 SYOFF8 VDDTCLK TSTCLKN VDDPECL VDDSDH GND GND CKPDH4 VDDPDH VDDLVDS RREF VDDLVDS SYOFF0 SYOFF1 SYOFF3 SYOFF4 SYOFF7 SYDU GND E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 SYPCLN0 FINSEL0 FINSEL3 SYNC8K -- -- -- -- -- -- -- -- SYOFF9 VDDHSPD VDDLSVCO LSVCO SYPCLP0 VDDPECL GND CK51 -- -- -- -- -- -- -- -- SYOFFPOS VDDHSPD VDDHSVCO GND G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 VDDPECL VDDPECL VDDPECL CK77 -- -- GND GND GND GND -- -- NC INLOSN LFN VCN PCK622N1 VDDPECL FINSEL2 FINSEL1 -- -- GND GND GND GND -- -- GND GND LFP VCP Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table 4-1. Ball Assignments for 208-Ball PBGA by Ball Number Order (continued) Note: -- refers to no ball. NC means do not connect any traces to this solder ball. Ball J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 Signal Name PCK622P VDDPECL VDDPECL GND -- -- GND GND GND GND -- -- GND VDDHSDIV VDDHSVCO NC VDDPECL VDDPECL GND SDHSEL2 -- -- GND GND GND GND -- -- NC VDDHSDIV LF0Z NC Agere Systems Inc. Ball L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 Signal Name SYPCLN1 SDHSEL0 SDHSEL3 SDHSEL1 -- -- -- -- -- -- -- -- NC NC NC NC SYPCLP1 VDDCNTL VDDCNTL SDH_HW -- -- -- -- -- -- -- -- GND NC NC NC Ball N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Signal Name VDDPECL SERDAT SERENBLN GND NC INT5 NC VDDFF NC INT0 NC SELLVDS GND ENSQLN RESETN SWCONTN PCK155N1 PDHSEL3 PDHSEL2 GND GND INT6 NC NC VDDFF SYCLK MON8K NC NC VDDLSPLL VDDLSPLL VDDCNTL Ball R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Signal Name PCK155P1 SERCLK GND GND PDHSEL0 NC INT3 GND GND NC GND NC GND GND GND GND VDDPECL VDDCLKBU NC PDHSEL1 GND NC NC NC GND CLKP CLKN CLK GND LF2 LF1 LF0 11 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 4.2 Physical Pin Orientation Table 4-2. Physical Ball Orientation (Bumps Down) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A GND CK155N0 CK155P0 GND SYLVSN0 SYLVSP0 GND CK622N CK622P GND SYLVSN1 SYLVSP1 GND CK155N1 CK155P1 GND B PCK155N0 CK19 VDDPDH CKPDH2 VDDPDH GND GND GND GND GND GND GND GND SYOFF6 TSTMODE TSTCLKP C PCK155P0 CK38 CKPDH1 CKPDH3 CKPDH5 VDDLVDS GND GND GND GND VDDSDH SYOFF2 SYOFF5 SYOFF8 VDDTCLK TSTCLKN D VDDPECL VDDSDH GND GND CKPDH4 VDDPDH VDDLVDS RREF VDDLVDS SYOFF0 SYOFF1 SYOFF3 SYOFF4 SYOFF7 SYDU GND E SYPCLN0 FINSEL0 FINSEL3 SYNC8K -- -- -- -- -- -- -- -- SYOFF9 VDDHSPD VDDLSVCO LSVCO F SYPCLP0 VDDPECL GND CK51 -- -- -- -- -- -- -- -- SYOFFPOS VDDHSPD VDDHSVCO GND G VDDPECL VDDPECL VDDPECL CK77 -- -- GND GND GND GND -- -- NC INLOSN LFN VCN H PCK622N1 VDDPECL FINSEL2 FINSEL1 -- -- GND GND GND GND -- -- GND GND LFP VCP J PCK622P VDDPECL VDDPECL GND -- -- GND GND GND GND -- -- GND VDDHSDIV VDDHSVCO NC K VDDPECL VDDPECL GND SDHSEL2 -- -- GND GND GND GND -- -- NC VDDHSDIV LF0Z NC L SYPCLN1 SDHSEL0 SDHSEL3 SDHSEL1 -- -- -- -- -- -- -- -- NC NC NC NC M SYPCLP1 VDDCNTL VDDCNTL SDH_HW -- -- -- -- -- -- -- -- GND NC NC NC N VDDPECL SERDAT SERENBLN GND NC INT5 NC VDDFF NC INT0 NC SELLVDS GND ENSQLN RESETN SWCONTN P PCK155N1 PDHSEL3 PDHSEL2 GND GND INT6 NC NC VDDFF SYCLK MON8K NC NC VDDLSPLL VDDLSPLL VDDCNTL R PCK155P1 SERCLK GND GND PDHSEL0 NC INT3 GND GND NC GND NC GND GND GND GND T VDDPECL VDDCLKBU NC PDHSEL1 GND NC NC NC GND CLKP CLKN CLK GND LF2 LF1 LF0 12 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table 4-3. Clock Inputs and Related Signal Ball Symbol* Type Level T10, T11 CLKP CLKN ID LVDS T12 CLK ID CMOS Input Clock. Used when CMOS level is desired for interfacing to input clock source. N12 SELLVDS IU CMOS Select Clock Level (LVDS/CMOS). Selects the LVDS or the CMOS input balls as the clock source: 0 = CMOS (CLK). 1 or no connection = LVDS (CLKP/N). E3, H3, H4, E2 FINSEL[3:0] IU CMOS Input Frequency Select. Program to indicate the input frequency of the clock source. P10 SYCLK ID CMOS Sync Input. CMOS synchronization input used to align output 8 kHz syncs to a system synchronization signal. Name/Description Input Clock. Used when LVDS level is desired for interfacing to input clock source. * Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low. I = input, O = output. IU indicates an internal 50 k pull-up resistor on this ball. ID indicates an internal 50 k pull-down resistor on this ball. Table 4-4. Analog and PLL Related Signals Ball Symbol* Type E16 LSVCO I T14, T15 LF2, LF1 Analog Level Name/Description CMOS 38.88 MHz VCXO. Connection to external VCXO output. -- Connect to Ground. -- 38.88 MHz PLL Loop Filter. T16 LF0 Analog K15 LF0Z IU H15, G15 LFP LFN Analog -- High-Speed PLL Loop Filter. Connect to external loop filter components and also connect LFP to VCP and LFN to VCN. H16, G16 VCP VCN Analog -- High-Speed VCO Control Voltage. Connect to external loop filter components and connect VCP to LFP and VCN to LFN. G14 INLOSN IU D8 RREF Analog CMOS 38.88 MHz PLL Loop Filter Enable. CMOS logic-high enables LF0. CMOS logic low sets output LF0 to high-impedance state. CMOS Input Loss of Signal. Active-low input signal forces control voltage on high-speed oscillator to the lowest end of the oscillator frequency range: 0 = force lowest-frequency operation in high-speed oscillator. 1 or no connection = normal operation. -- Resistor Reference. LVDS output voltage reference resistor. Insert a 1.5 k resistor from RREF to VDDLVDS. * Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low. I = input, O = output. IU indicates an internal 50 k pull-up resistor on this ball. ID indicates an internal 50 k pull-down resistor on this ball. Agere Systems Inc. 13 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 4-5. Output Clocks and Related Signals Ball Symbol* Type Level A9, A8 CK622P CK622N O LVDS J1, H1 PCK622P PCK622N O A15, A3, A14, A2 CK155P[1:0] CK155N[1:0] O R1, C1, P1, B1 PCK155P[1:0] PCK155N[1:0] O G4 CK77 O CMOS 77.76 MHz Output Clock. F4 CK51 O CMOS 51.84 MHz Output Clock. C2 CK38 O CMOS 38.88 MHz Output Clock. Name/Description 622.08 MHz Output Clock. LVPECL 622.08 MHz Output Clock. LVDS 155.52 MHz Output Clock. LVPECL 155.52 MHz Output Clock. B2 CK19 O CMOS 19.44 MHz Output Clock. L3, K4, L4, L2 SDHSEL[3:0] ID CMOS SDH Clock Output Selection. E4 SYNC8K O CMOS 8 kHz Output Sync. A12, A6, A11, A5 SYLVSP[1:0] SYLVSN[1:0] O LVDS 8 kHz Sync Buffers [1:0]. M1, F1, L1, E1 SYPCLP[1:0] SYPCLN[1:0] O E13, C14, D14, B14, C13, D13, D12, C12, D11, D10 SYOFF[9:0] ID CMOS Sync Offset. Programs the magnitude of the offset of the output syncs relative to an input 8 kHz clock/sync. F13 SYOFFPOS IU CMOS Sync Offset Positive or Negative. Selects the direction of the sync offset: 1 = positive offset. The output sync is delayed in time. 0 = negative offset. The output sync is advanced in time. D15 SYDU IU CMOS Sync Duty Cycle. Selects the duty cycle of the output sync signals: 1 = 50% duty cycle. 0 = sync logic high time equal to one period of the highestfrequency active SONET output clock. C5 CKPDH5 O CMOS Selectable PDH Output Clock. D5 CKPDH4 O CMOS Selectable PDH Output Clock. C4 CKPDH3 O CMOS Selectable PDH Output Clock. B4 CKPDH2 O CMOS Selectable PDH Output Clock. C3 CKPDH1 O CMOS Selectable PDH Output Clock. P2, P3, T4, R5 PDHSEL[3:0] ID CMOS PDH Clock Output Selection. LVPECL 8 kHz Sync Buffers [1:0]. * Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low. I = input, O = output. IU indicates an internal 50 k pull-up resistor on this ball. ID indicates an internal 50 k pull-down resistor on this ball. 14 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table 4-6. Control and Related Signals Type Level Ball Symbol* N16 SWCONTN IU Name/Description CMOS Software Control. Active-low signal, used with ENSQLN for output squelch control. See ENSQLN. 0 = software control is enabled. Device is in manual switching mode and, when instructed, switches to a clock even if it is in a loss of clock state. (Overrides AUTOSWN setting.) 1 = software control is disabled. User cannot switch to a clock in a loss of clock state. N14 IU ENSQLN CMOS Enable Squelch. Active-low signal enables automatic squelching of the clock and sync outputs whenever a fault is encountered. When squelching occurs, all output clock and sync signals will be held at a logic-low output level. If the device is not in software control mode (SWCONTN = 1), the outputs will be squelched if squelch is enabled and input clock is lost: 1 = automatic squelching of the outputs is disabled. 0 = automatic squelching of the outputs is enabled. If the device is in the software override mode (SWCONTN = 0), then ENSQLN can be used to manually squelch the device clock outputs: 1 = normal device clock output operation. 0 = manually squelch the device clock outputs. N15 RESETN P6, N6, R7, INT[6, 5, 3, 0] N10 IU CMOS Reset. Active-low asynchronous reset. O CMOS Interrupts. Active-high interrupts define fault conditions. See Table 13-1 on page 37 for individual interrupt definitions. I = input, O = output. IU indicates an internal 50 k pull-up resistor on this ball. ID indicates an internal 50 k pull-down resistor on this ball. Table 4-7. Serial Interface Signals Ball Symbol* Type R2 SERCLK IU SERENBLN U N3 N2 SERDAT Name/Description CMOS Serial Interface Clock. Serial interface clock that can operate up to 25 MHz. CMOS Serial Interface Enable. This signal must be low during register access. I I/O Level U CMOS Serial Data. This is a bidirectional ball for writing and reading software registers. U I = input, O = output. I indicates an internal 50 k pull-up resistor on this ball. ID indicates an internal 50 k pull-down resistor on this ball. Table 4-8. Test and Reserved Signals Ball Symbol* Type B15 TSTMODE ID CMOS Test Mode. Internal test observation signal used in test mode. Do not connect or apply any signal to this ball. B16, C16 TSTCLKP TSTCLKN ID LVDS P11 MON8K O CMOS Monitor 8 kHz from Input Clock. Internal test observation signal. Do not connect or apply any signal to this ball. (If input clock is setup and applied correctly, this signal should measure exactly 8 kHz.) M4 SDH_HW ID CMOS Internal Signal. Internal test signal. Do not connect or apply any signal to this ball. (When set to a CMOS logic high, the SDH block takes information directly from the external leads and does not use information from the internal bus (registers).) Level Name/Description Test Clock Input. Do not connect or apply any signal to these balls. * Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low. I = input, O = output. IU indicates an internal 50 k pull-up resistor on this ball. ID indicates an internal 50 k pull-down resistor on this ball. Agere Systems Inc. 15 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 4-9. No-Connect Signals Ball Symbol Type Level G13, J16, K13, K16, L13, L14, L15, L16, M14, M15, M16, N5, N7, N9, N11, P7, P8, P12, P13, R6, R10, R12, T3, T6, T7, T8 NC -- -- Name/Description Not connected. Table 4-10. Power Signals For information on power supply grouping and filtering, refer to Application Note: TSWC01622 Power Supply Grouping and Filtering. Ball Symbol Type Level Name/Description C11, D2 D1, F2, G1, G2, G3, H2, J2, J3, K1, K2, N1, T1 D9, C6, D7 M2, M3, P16 T2 N8, P9 P14, P15 K14, J14 J15, F15 E15 E14, F14 D6, B5, B3 C15 A1, A4, A7, A10, A13, A16, B6, B7, B8, B9, B10, B11, B12, B13, C7, C8, C9, C10, D3, D4, D16, F3, F16, G7, G8, G9, G10, H7, H8, H9, H10, H13, H14, J4, J7, J8, J9, J10, J13, K3, K7, K8, K9, K10, M13, N4, N13, P4, P5, R3, R4, R8, R9, R11, R13, R14, R15, R16, T5, T9, T13 VDDSDH VDDPECL VDDLVDS VDDCNTL VDDCLKBU VDDFF VDDLSPLL VDDHSDIV VDDHSVCO VDDLSVCO VDDHSPD VDDPDH VDDTCLK GND Power Power Power Power Power Power Power Power Power Power Power Power Power Ground -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 16 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 5 Functional Overview The TSYN03622 is designed to manage clock generation and timing distribution in SONET/SDH compliant line card solutions up to OC-12 data rates. The TSYN03622's output clocks are designed to meet relevant output clock jitter generation specifications and maximum time interval error (MTIE). It supports a range of common input frequencies from 8 kHz to 51.84 MHz. An integrated digital state machine monitors the presence of the input clock signal. Programming of the TSYN03622 can be accomplished through external ball control or through internal registers via a serial interface. A range of SONET and PDH clock frequencies are generated with 155 MHz and 622 MHz clocks available on multiple low-skew LVDS and LVPECL output buffers in order to provide fan-out and clock distribution sources for multiple chips within the system. An 8 kHz sync signal with a user-programmable offset is generated and is available on CMOS, LVDS, and LVPECL output buffers. The duty cycle of the 8 kHz output sync signal is selectable as either 50% or as the width of a single clock pulse determined by the maximum selected SONET/SDH related output frequency. Agere Systems Inc. 17 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 6 Input Clock Specifications 6.1 Input Clock Stability Requirements The clock input to the TSYN03622 must be compliant with all requirements for a SONET minimum clock (SMC) as defined in TelcordiaTM GR-253-CORE Section 5.4.4.2 (Issue 3, 9/2000), or for an ITU node clock as defined in G.812, in order for the TSYN03622 to meet its output clock specifications. 6.2 Input Frequency Selection (FINSEL[3:0]) The input clock signal frequencies that are supported on the clock input, as well as the appropriate frequency selection control ball programming, are given in Table 6-1. Input frequency selection can be performed using external balls FINSEL[3:0] or by programming register 0x21 bits 3:0 (with SDH_HW ball low). Table 6-1. Input Clock Frequency Selection Input Clock Frequency FINSEL3 FINSEL2 FINSEL1 FINSEL0 8 kHz 1.544 MHz 2.048 MHz 6.480 MHz 8.192 MHz 19.44 MHz 38.88 MHz 51.84 MHz NC NC NC NC NC NC NC NC 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 6.3 Input Electrical Level Selection for Clock Input Signal (SELLVDS) When SELLVDS = 0, the CLK CMOS level input buffer is selected as the clock inputs. When SELLVDS = 1 (or no connection is made to the SELLVDS ball), the CLKP/N LVDS level input buffers are selected as the clock input. 6.4 Input Clock Minimum Pulse-Width Specifications In order for the TSYN03622 to guarantee functionality, the input clock must maintain a minimum pulse width of tPW = 8 ns for an input frequency of 8 kHz, for input frequencies less than 8 kHz, a 50% 5% duty cycle is required, as shown in Figure 6-1. 6.4.1 Input Clock Minimum Pulse Width tPW CLOCK INPUT Figure 6-1. Input Clock Minimum Pulse-Width Requirement 6.5 Input Sync Signal Functionality If an 8 kHz (or a slower multiple of 8 kHz) is input, then the 8 kHz output signals (SYNC8K, SYLVSP/N[1:0], and SYPLP/N[1:0]) will be aligned to the active SYCLK with a small phase offset due to the delay through the chip. 18 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 7 Output Clock Specifications 7.1 Available Output Clocks The TSYN03622 supports the generation of the SONET/SDH and PDH frequencies given in Table 8-1, as well as the ability to program frequency output rates up to 65.536 MHz on CKPDH[1:3] and 38.88 MHz on CKPDH[4:5], using fractional synthesis. Not all PDH frequencies listed in Table 8-1 are available simultaneously. Table 7-1 and Table 7-2 illustrate the combination of output clock frequencies available simultaneously based on the PDHSEL[3:0] and SDHSEL[3:0] control words. There are several levels of programming the PDH1--PDH5 outputs. The PDHSEL[3:0] control word can be programmed using external balls PDHSEL[3:0] (with mode bits 0x81 bits 4:3 set to 00, which is the default state) or by programming register 0x80 bits 15:12 (with mode bits 0x81 bits 4:3 set to 10). Additionally, each PDH output can be programmed individually using registers 0x82 and 0x83 (with mode bits 0x81 bits 4:3 set to 01 or 11). If the mode for any PDH output is set to 0B1110, then any frequency can be programmed to the output, up to 65.536 MHz on CKPDH[1:3] and 38.88 MHz on CKPDH[4:5], using the outputs respective registers in the range 0x40 to 0x66. To program these registers, please contact Agere to get an automated program that provides programming instructions based on the desired frequency output. The SDHSEL[3:0] control word can be programmed using external balls SDHSEL[3:0] or by programming register 0xA1 bits 3:0 (with 0xA0 bit 1 high and SDH_HW ball low). Individual SONET/SDH output syncs and clocks can also be enabled or disabled individually using registers 0xA4 and 0xA5 respectively. Additionally, the CK77, CK51, CK38, and CK19 clocks can be aligned such that either the positive or the negative edge is aligned to an input 8 kHz signal using register 0xA7 (with 0xA0 bits 1 and 2 low). Agere Systems Inc. 19 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 7-1. SDH Output Clock Selection (SDHSEL[3:0]) Clock/Sync Output Name SDHSEL[3:0] State Value and Associated Output Signals* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CK622P/N Z 622.08 MHz 622.08 MHz Z 622.08 MHz Z 622.08 MHz Z Z Z Z Z Z Z Z Z PCK622P/N Z 622.08 MHz Z 622.08 MHz Z 622.08 MHz 0 Z 622.08 MHz Z Z Z Z Z Z Z CK155P/N[1] 155.52 MHz Z Z Z 155.52 MHz Z Z 155.52 MHz Z Z Z Z Z Z Z Z CK155P/N[0] 155.52 MHz Z 155.52 MHz Z 155.52 MHz Z Z 155.52 MHz Z Z Z Z Z Z Z Z PCK155P/N[1] 155.52 MHz 155.52 MHz Z Z Z 155.52 MHz Z Z Z 155.52 MHz Z Z Z Z Z Z PCK155P/N[0] 155.52 MHz 155.52 MHz Z 155.52 MHz Z 155.52 MHz Z Z Z 155.52 MHz Z Z Z Z Z Z CK77 Z 77.76 MHz Z Z Z Z Z Z Z Z 77.76 MHz 77.76 MHz Z Z Z Z CK51 51.84 MHz Z Z Z Z Z Z Z Z Z 51.84 MHz Z 51.84 MHz Z Z Z CK38 Z Z Z Z Z Z Z Z Z Z 38.88 MHz Z Z 38.88 MHz Z Z CK19 19.44 MHz Z Z Z Z Z Z Z Z Z 19.44 MHz Z Z Z 19.44 MHz Z Z 8.0 kHz Z Z Z Z Z Z Z Z 8.0 kHz 8.0 kHz 8.0 kHz 8.0 kHz 8.0 kHz Z SYLVSP/N[1] 8.0 kHz Z 8.0 kHz Z 8.0 kHz Z Z 8.0 kHz Z Z Z Z Z Z Z Z SYLVSP/N[0] 8.0 kHz 8.0 kHz 8.0 kHz Z 8.0 kHz Z 8.0 kHz 8.0 kHz Z Z Z Z Z Z Z Z SYPCLP/N[1] 8.0 kHz Z 8.0 kHz Z 8.0 kHz Z Z Z 8.0 kHz Z Z Z Z Z Z 8.0 kHz 8.0 kHz Z 8.0 kHz Z 8.0 kHz Z Z 8.0 kHz 8.0 kHz Z Z Z Z Z Z SYNC8K SYPCLP/N[0] Z * Z = high impedance. If SYDU = 0, duty cycle = 50%. If SYDU = 1, sync logic high time equal to one period of a 155.52 MHz clock (6.43 ns). If SYDU = 0, duty cycle = 50%. If SYDU = 1, sync logic high time equal to one period of a 622.08 MHz clock (1.6075 ns). Table 7-2. PDH Output Clock Selection (PDHSEL[3:0]) Clock/Sync Output Name PDHSEL[3:0] State Value and Associated Output Signals* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CKPDH5 2.43 MHz Z 1.544 MHz 1.544 MHz Z Z Z 2.43 MHz Z Z Z Z Z Z Z Z CKPDH4 1.544 MHz Z 2.048 MHz 2.048 MHz 1.544 MHz 1.544 MHz Z Z Z Z Z Z Z Z Z Z CKPDH3 2.048 MHz Z 24.704 MHz 24.704 MHz 2.048 MHz Z 2.048 MHz Z 4.096 MHz 8.192 MHz Z Z Z Z Z Z CKPDH2 32.768 MHz Z 32.768 MHz 32.768 MHz Z Z Z Z Z Z 16.384 MHz Z 32.768 MHz Z Z Z CKPDH1 44.736 MHz Z 34.368 MHz 44.736 MHz Z Z Z Z Z Z Z 24.704 MHz Z 34.368 MHz 44.736 MHz Z * Z = high impedance. 20 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 8 Jitter Specifications The clock frequencies listed in Table 8-1 are normally available at their respective output balls under the indicated conditions. The jitter specifications are met if the input clock complies with the input clock stability requirements. For representative jitter measurements for the CKPDH1--CKPDH5 outputs when used with the Agere Systems TMXF84622 device, consult the Clock Requirements for the TSWC03622/TSYN03622 Devices for Ultramapper Family Devices Application Note. Table 8-1. Output Clock Jitter Specifications Parameter Ball Output Frequency Typ (RMS Only) Max Unit Measurement Bandwidth Jitter Generation CK19 CK38 CK51 19.44 MHz 38.88 MHz 51.84 MHz -- -- 0.03 (See Figure 8-1.) --* --* <0.2 <2.0 <0.4 <4.0 <0.4 <4.0 <0.6 <6.0 <0.3 <3.0 <0.625 <6.25 <0.6 <6.0 <1.0 <10 <1.8 <18 <2.0 <20 -- -- mUIRMS mUIp-p mUIRMS mUIp-p mUIRMS mUIp-p mUIRMS mUIp-p mUIRMS mUIp-p mUIRMS mUIp-p mUIRMS mUIp-p mUIRMS mUIp-p mUIRMS mUIp-p mUIRMS mUIp-p -- -- 12 kHz--40 kHz (OC-1) 12 kHz--40 kHz (OC-1) 12 kHz--400 kHz (OC-1) 12 kHz--400 kHz (OC-1) 12 kHz--130 kHz (OC-3) 12 kHz--130 kHz (OC-3) 12 kHz--1.3 MHz (OC-3) 12 kHz--1.3 MHz (OC-3) 12 kHz--500 kHz (OC-12) 12 kHz--500 kHz (OC-12) 12 kHz--5 MHz (OC-12) 12 kHz--5 MHz (OC-12) 12 kHz--130 kHz (OC-3) 12 kHz--130 kHz (OC-3) 12 kHz--1.3 MHz (OC-3) 12 kHz--1.3 MHz (OC-3) 12 kHz--500 kHz (OC-12) 12 kHz--500 kHz (OC-12) 12 kHz--5 MHz (OC-12) 12 kHz--5 MHz (OC-12) 0.06 (See Figure 8-1.) 0.05 (See Figure 8-1.) 0.11 (See Figure 8-1.) CK77 77.76 MHz 0.09 (See Figure 8-2.) 0.20 (See Figure 8-2.) CK155P/N, 155.52 MHz PCK155P/N -- -- CK622P/N, 622.08 MHz PCK622P/N 0.7 1.2 * CK19 and CK38 signals are divided down from the CK77 output and have similar phase noise (jitter) performance to that of the CK77 output. For applications requiring lower generated jitter, please contact the Agere Systems representative. Agere Systems Inc. 21 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 SSB MAGNITUDE (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 FREQUENCY FROM CARRIER (Hz) Figure 8-1. Phase Noise Characteristic for Differential Output Clock CK51 Using LSPLL Filter SSB MAGNITUDE (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 FREQUENCY FROM CARRIER(dBc/Hz) FREQUENCY FROM CARRIER (dBc/Hz) Figure 8-2. Phase Noise Characteristic for Differential Output Clock CK77 Using LSPLL Filter Note: See Figure 12-2 for LSPLL filter diagram. 22 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 9 Synchronization Output at 8 kHz 9.1 Sync Output (SYNC8K, SYLVSP/N[1:0], SYPCLKP/N[1:0]) The TSYN03622 generates an output 8 kHz synchronization signal for use in frame and cell alignment in systems that require this capability. Typically, the output sync is meaningful only in systems that distribute 8 kHz synchronization signals as the timing references on the clock input. In these cases, the alignment of the output sync to the input sync (8 kHz on the clock input) is a critical aspect of system synchronization. When higher-speed clocks are distributed, the alignment of the sync with respect to the input clock becomes arbitrary. Sync outputs can be configured along with the SONET/SDH clock outputs with the SDHSEL[3:0] control word. The SDHSEL[3:0] control word can be programmed using external balls SDHSEL[3:0] or by programming register 0xA1 bits 3:0 (with 0xA0 bit 1 high and SDH_HW ball low). Individual SONET/ SDH output syncs can also be enabled or disabled individually using register 0xA4. 9.2 Sync Duty Cycle Selection (SYDU) There are several methods of controlling the sync output duty cycle. The first method is used with the SDHSEL[3:0] output frequency. In this method, the duty cycle of the 8 kHz sync signals is selectable as either 50% or as the width of a single SONET clock pulse width. When the duty cycle is selected to be a single clock pulse width, the pulse width of the respective sync signal is determined to be equal to one period of the highest-frequency active SONET output of similar output technology type (for example, the CMOS SYNC8K output will have the pulse width of the highest-frequency active SONET CMOS output). The frequencies of the active PDH clocks are not considered. Sync duty cycle selection can be performed using external ball SYDU or by programming register 0xA2 bit 0 (with register 0xA0 bit 2 high and SDH_HW ball low). Table 9-1. Sync Duty Cycle Selection (SYDU) SYDU 1 0 SYNC8K Duty Cycle 50% High for one period of highest-frequency active SONET clock output A second method is used when the sync outputs are individually enabled through register 0xA4. In this method, pulse-width options remain selectable as either 50% or as the width of a single SONET clock pulse width. Pulse widths are selected using register 0xA4 in conjunction with register 0xA6. The last method is to adjust the falling edge of the sync outputs using register 0xB2, which, in effect, adjusts the duty cycle. (The rising edge can be adjusted using the sync offset programming explained below.) 9.3 Sync Alignment When 8 kHz synchronization signals are applied as input timing on the clock input, the output sync is phase aligned to the input sync. Adjustments of this delay may be made using the TSYN03622 sync offset programmability feature. 9.4 Offset Programming (SYOFF[9:0], SYOFFPOS) Some system applications require the 8 kHz synchronization to be offset according to the demands of the system architecture. The TSYN03622 provides the capability of offsetting the output sync in increments of 1.6075 ns (one 622.08 MHz clock). The sync offset will apply to all output syncs (SYN8K, SYLVSP/N[1:0], SYPCLP/N[1:0]) simultaneously. There are two types of offset capability on the TSYN. The first has the capability to offset up to 1.644 s with a resolution of 1.6075 ns (1023 periods of a 622.08 MHz clock with a resolution of one period of the 622.08 MHz clock). This offset can be performed using external balls SYOFF[9:0] and SYOFFPOS or by programming register 0xA3 bits 10:0 (with register 0xA0 bit 3 high and SDH_HW ball low). Programming of the sync offset is described in Table 9-2. Agere Systems Inc. 23 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 9-2. SYNC Offset Programming Ball SYOFF[9:0] SYOFFPOS Function Sets the magnitude of the sync offset value in increments of 1/622.08 MHz or 1.6075 ns: SYOFF[9:0] = 0000000000 equals zero offset. SYOFF[9:0] = 1111111111 equals 1.644 s (1023/622.08 MHz) offset. Sets the sign or direction of the sync offset: SYOFFPOS = 1 is a positive offset. The output sync is delayed in time. SYOFFPOS = 0 is a negative offset. The output sync is advanced in time. The second type of sync offset is an enhanced capability that enables the sync to be offset over the entire 125 s period (in the same increments of 1.6075 ns). This is accomplished using 16 bits of offset and a positive/negative directional control. This functionality is available by programming registers 0xA8 and 0xA9 (with register 0xA0 bit 3 low and SDH_HW ball low). The programming is similar to the first offset type and is shown in Table 9-3. Note that there is a limit to the size of the offset, so the offset is not greater than one 125 s period. Table 9-3. Enhanced SYNC Offset Programming Ball Function SYOFF[16:0] Sets the magnitude of the sync offset value in increments of 1/622.08 MHz or 1.6075 ns: SYOFF[16:0] = 0 0000 0000 0000 0000 equals zero offset. SYOFF[16:0] = 1 0010 1111 0110 0000 equals 125 s (77760/622.08 MHz) offset. SYOFFPOS Sets the sign or direction of the sync offset: SYOFFPOS = 1 is a positive offset. The output sync is delayed in time. SYOFFPOS = 0 is a negative offset. The output sync is advanced in time. 24 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 10 Skew Specifications t100 t102 PCK622P/N SYPCLP/N[1:0] t101 t103 2364 (F) Figure 10-1. PECL Sync to PECL Clock Skew Case: Syncs Aligned to 622 MHz Clock Table 10-1. PECL Sync to PECL Clock Skew Parameters (Single Clock Pulse Sync Output Shown) Applicable Balls Symbol PCK622P/N SYPCLP/N[1:0] PCK622P/N PCK622P/N SYPCLP/N[1:0] t100 t101/t103 t102 Agere Systems Inc. Skew Parameter Min Max Typ Unit Clock Falling to Sync Rising 0 0.5 0.235 ns Clock Duty Cycle Clock Falling to Sync Falling 45 0 55 0.5 50 0.220 % ns 25 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 t200 t202 PCK155P/N[0] SYPCLP/N[0] t201 t203 t210 t212 PCK155P/N[1] SYPCLP/N[1] t211 t213 2365 (F) Figure 10-2. PECL Sync to PECL Clock Skew Case, Sync Aligned to 155 MHz Clock Table 10-2. PECL Sync to PECL Clock Skew Parameters (Single Clock Pulse Sync Output Shown) Applicable Balls Symbol PCK155P/N[0] SYPCLP/N[0] PCK155P/N[0] PCK155P/N[0] SYPCLP/N[0] PCK155P/N[1] SYPCLP/N[1] PCK155P/N[1] PCK155P/N[1] SYPCLP/N[1] t200 26 Skew Parameter Min Max Typ Unit Clock Falling to Sync Rising -1.0 0 --0.735 ns t201/t203 t202 Clock Duty Cycle Clock Falling to Sync Falling 45 -1.0 55 0 50 -0.745 % ns t210 Clock Falling to Sync Rising -1.0 0 -0.720 ns t211/t213 t212 Clock Duty Cycle Clock Falling to Sync Falling 45 -1.0 55 0 50 -0.700 % ns Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer t300 t302 CK622P/N SYLVSP/N[1:0] t301 t303 2366 (F) Figure 10-3. LVDS Sync to LVDS Clock Skew Case, Sync Aligned to 622 MHz Clock Table 10-3. LVDS Sync to LVDS Clock Skew Parameters (Single Clock Pulse Sync Output Shown) Applicable Balls Symbol CK622P/N SYLVSP/N[1:0] CK622P/N CK622P/N SYLVSP/N[1:0] t300 t301/t303 t302 Agere Systems Inc. Skew Parameter Min Max Typ Unit Clock Falling to Sync Rising 0 0.5 0.185 ns Clock Duty Cycle Clock Falling to Sync Falling 45 0 55 0.5 51 0.205 % ns 27 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 t400 t402 CK155P/N[0] SYLVSP/N[0] t401 t403 t410 t412 CK155P/N[1] SYLVSP/N[1] t411 t413 2367 (F) Figure 10-4. LVDS Sync to LVDS Clock Skew Case, Sync Aligned to 155 MHz Clock Table 10-4. LVDS Sync to LVDS Clock Skew Parameters (Single Clock Pulse Sync Output Shown) Applicable Balls Symbol CK155P/N[0] SYLVSP/N[0] CK155P/N[0] SYLVSP/N[0] CK155P/N[1] SYLVSP/N[1] CK155P/N[1] SYLVSP/N[1] t400 28 Skew Parameter Min Max Typ Unit Clock Falling to Sync Rising -1.0 0 -0.745 ns t402 Clock Falling to Sync Falling -1.0 0 -0.750 ns t410 Clock Falling to Sync Rising -1.0 0 -0.725 ns t412 Clock Falling to Sync Falling -1.0 0 -0.745 ns Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer t500 CK19, CK38, CK51, CK77 SYNC8K t502 t501 t503 Figure 10-5. CMOS Sync to CMOS Clock Skew Case, Sync Aligned to SONET CMOS Output Clock Table 10-5. CMOS Sync to CMOS Clock Skew Parameters (15 pF, 1 k) A single clock pulse sync output is shown. The parameters in this table are not tested, but are a result of device characterization data.) Applicable Balls Symbol Skew Parameter Min Max Typ Unit CK19, SYNC8K CK19 CK19, SYNC8K CK38, SYNC8K CK38 CK38, SYNC8K CK51, SYNC8K CK51 CK51, SYNC8K CK77, SYNC8K CK77 CK77, SYNC8K t500 t501/t503 t502 t500 t501/t503 t502 t500 t501/t503 t502 t500 t501/t503 t502 Clock Rising to Sync Rising Clock Duty Cycle Clock Rising to Sync Falling Clock Rising to Sync Rising Clock Duty Cycle Clock Rising to Sync Falling Clock Rising to Sync Rising Clock Duty Cycle Clock Rising to Sync Falling Clock Rising to Sync Rising Clock Duty Cycle Clock Rising to Sync Falling -0.50 -- 0.00 -0.50 -- 0.00 -0.50 -- 0.00 -0.50 -- 0.00 0.50 -- 1.50 0.50 -- 1.50 0.50 -- 1.50 0.50 -- 1.50 0.15 -- 0.80 0.05 -- 0.60 -0.05 -- 0.50 -0.20 -- 0.50 ns % ns ns % ns ns % ns ns % ns Agere Systems Inc. 29 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 11 Output Specifications During Phase-Locked Condition (Nontransient Condition) 11.1 Maximum Time Interval Error (MTIE) Specifications During the phase-locked condition, the TSYN03622 output clocks will meet wander generation as given in Table 11-1 and shown in Figure 11-1. When in the locked condition, the MTIE performance will be dominated by the MTIE of the incoming timing-signals on the clock input. The TSYN03622 will not add significantly to the MTIE performance. Measured performance is shown in Figure 11-2. Measured performance is shown in Figure 11-1. Table 11-1. Wander Generation (Nontransient)--MTIE Observation Interval TSYN03622 Max GR-253-CORE (s) (ns) Figure 5-17 (9/2000) (ns) s < 0.1 NA 0.1 < s < 1.0 20 1 < s < 10 20 x s GR-1244-CORE Figure 5-2 (6/95) (ns) ITU-T G.813 Option 2 Table 4 (8/96) (ns) NA NA NA 20 0.48 20 x s 40 0.48 40 x s 20 0.40 20 x s 0.48 10 < s < 100 60 60 100 60 100 < s < 1000 60 -- 100 60 s > 1000 100 -- 100 -- MTIE (ns) 1000 GR-1244 CORE 100 ITU-T G.813 OPTION 2 GR-253 CORE 10 0.1 1 10 100 1000 OBSERVATION INTERVAL (s) 2368 (F) Figure 11-1. MTIE Wander Generation in Locked Condition 30 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 1000 GR-253-CORE/ITU-T G.183 Opt 2 MTIE Requirement MTIE (ns) 100 10 1 0. 0.01 0.10 1.00 10.00 Time Time (sec)(s) 100.00 1000.00 Figure 11-2. Measured MTIE Wander Generation Performance Agere Systems Inc. 31 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 11.2 Time Deviation (TDEV) Specifications During the phase-locked condition, the TSYN03622 output clocks will meet TDEV as given in Table 11-2 and shown in Figure 11-3. When in the locked condition, the TDEV performance will be dominated by the incoming timing signals on the clock input and the TSYN03622 will not add significantly to the TDEV performance. Measured performance is shown in Figure 11-4. Measured performance is shown in Figure 11-3. Table 11-2. Wander Generation (Nontransient)--TDEV Integration Interval (s) TSYN03622 Max (ns) GR-253-CORE Figure 5-18 (9/2000) (ns) GR-1244-CORE Figure 5-1 (6/95) (ns) ITU-T G.813 Option 2 Table 5 (8/96) (ns) 0.1 < < 2.5 3.2 x -0.5 3.2 x -0.5 3.2 x -0.5 3.2 x -0.5 2.5 < < 40 2 2 2 2 40 < < 1000 0.32 x 0.5 0.32 x 0.5 0.32 x 0.5 0.32 x 0.5 > 1000 10 10 10 -- 1000 < < 10,000 10 -- -- 10 100 TDEV (ns) ITU-T G.813 OPTION 2 GR-253 CORE AND GR-1244 CORE 10 1 0.1 1 10 100 1000 10000 OBSERVATION INTERVAL (s) 2369 (F) Figure 11-3. Wander Generation in Locked Condition 32 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 100 GR-253-CORE/GR-1244-CORE/G.813 Opt. 2 TDEV Requirement TDEV (ns) 10 1 0.1 0.01 0.1 1 10 100 1000 10000 100000 Observation Interval (s) Figure 11-4. Measured TDEV Wander Generation Performance Agere Systems Inc. 33 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 12 Other Input and PLL Specifications 12.1 Input Clock Maximum Rate of Phase Change During Transient In order for the TSYN03622 to guarantee functionality and that all transient MTIE specifications are met, the clock input must have an instantaneous maximum rate of change consistent with the ITU G.812 requirements for a node clock and Telcordia GR-253-CORE Section 5.4.4.2 (Issue 3, 9/2000). 12.2 External 38.88 MHz VCXO Requirements The following is a brief specification for the 38.88 MHz VCXO unit: Supply voltage: 3.30 V 5% Control voltage range: 0.3 V minimum, 2.7 V maximum Temperature range (ambient): -40 C to +85 C Output buffer: -- Technology: CMOS (3.30 V) -- Duty cycle: 45/55% -- Transient times: 1 ns maximum (20% to 80%) Frequency (nominal): 38.88 MHz APR: 20 ppm Note: The APR must include the effects of temperature, supply voltage, shock, vibration, aging, and manufacturing (i.e., withstanding two solder reflows). Linearity: 20% (best linear fit 0.3 V to 2.7 V) Transfer function: monotonic, positive slope Center voltage: VDD/2 (nominal 1.65 V) Modulation bandwidth: 10 kHz at 38.88 MHz Input leakage current: <1 A Input resistance: >3 M Reference signal for control voltage: ground Phase jitter: 1 ps (RMS) maximum 12 kHz to 20 MHz (alternate spec may be expressed in dBc if required) Start-up time: 2 ms at maximum control voltage 34 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 12.3 Loop Filter Components for High-Speed PLL The recommended loop filter is shown in Figure 12-1. Connect the filter components and also connect LFP to VCP and connect LFN to VCN. The component values can be varied to adjust the loop dynamic response. Table 12-1 provides a set of recommended values to meet output jitter generation requirements in Table 8-1. Table 12-1. Recommended High-Speed Loop Filter Values Components Recommended Values C1* 0.1 F to 1.0 F 10% R1 3.9 k 5% *. Capacitor C1 should be either ceramic or nonpolar. LFP VCP C1 R1 VCN LFN Figure 12-1. Recommended High-Speed Loop Filter Circuit 12.4 Loop Filter Components for Low-Speed PLL The recommended loop filter for the low-speed PLL is shown in Figure 12-2 and Table 12-2. (This circuit can withstand an instantaneous phase jump of up to 30 ns. If a larger phase jump could exist, please contact your Agere Systems representative for more guidance. A smaller loop filter will be created in the future for conditions where there will be little or no instantaneous phase jump.) Analog switches are included in both circuits to reduce the lock time at start-up. The addition of the analog switch will reduce the nominal lock time from tens of seconds to less than 6 s. Note: For information on requirements for the various loop filter components and recommended solutions, consult the TSWC01622/TSYN01622 Loop Filters: Compatible Components Application Note. Table 12-2. Recommended Low-Speed Loop Filter Values for Smaller Phase Offsets Components C1* C2, C3 * R1 R2 R3 R4 U1 VCXO1 Recommended Values 10 F 20% 4.7 F 10% 392 k 1% (390 k 5%) 1.21 k 1% (1.2 k 5%) 20 k to 110 k 5% (lower value yields faster lock time) 383 k 1% (390 k 5%) Analog switch See VCXO requirements. * Capacitors C1, C2, and C3 should be either ceramic or nonpolar. 1% resistors are recommended for R1 and R2, as the low-speed PLL filter has high sensitivity to these resistors. However, if these 1% resistors are not available, the 5% resisters indicated in parentheses are compatible and will make the loop filter function correctly. For information on requirements for the various loop filter components and recommended solutions, consult the TSWC01622/TSYN01622 Loop Filters: Compatible Components Application Note. Agere Systems Inc. 35 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 R1 LF0 R3 R4 INT5 R2 U1 C3 C1 VC C2 VCXO1 RF OUT LSVCO Figure 12-2. Recommended Low-Speed Phase-Lock Loop (LSPLL) Filter Circuit for Smaller Phase Offsets 12.5 INLOSN The INLOSN signal will force the high-speed PLL to drift towards a lower clamped frequency, preventing an excessive highfrequency clock output under invalid input signal conditions. INLOSN may be used to limit the internal clock frequency ensuring proper state machine and control behavior under severe clock fault conditions. 12.6 RREF RREF should be tied to VDDLVDS through a 1.5 k resistor. 36 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 13 State Machine and Software Interface 13.1 State Machine Behavior The state machine of the TSYN03622 performs the following for control and monitoring purposes: Provides a squelch function to bring the device clock outputs to a logic low-state (squelched) if the clock input signal has a fault. Provides an asynchronous reset. Provides a loss of clock interrupt. Provide loss of lock interrupts for the low-speed PLL and the high-speed PLL. Provides a loss of external VCXO clock interrupt. 13.2 Squelch If the loss of clock interrupt goes active, the device will either do nothing or squelch the output clock and sync signals depending on the ENSQLN condition. If ENSQLN is low, the device output clock and sync signals will be forced low. 13.3 Software Interfacing The TSYN03622 is configured by an external controller via software. Whenever interaction with this software is needed, the following guidelines should be followed: The software must provision the device as desired, appropriately setting ENSQLN upon powerup and after the initial reset completes. The external controller may either use an active edge of one of the interrupts or a polling method (monitoring INT[6, 5, 3, 0]) to determine the interrupt states. 13.4 Loss of Clock Criteria Loss of clock detectors continuously monitor the condition of the input clock. A loss of clock condition is declared when transitions are absent on the clock input for between 2 and 3 periods of the input frequency. This level is programmable via register 0x23. The hysteresis for coming out of the loss of clock condition is also programmable in register 0x2E. 13.5 Interrupt Generation (INT[6, 5, 3, 0]) Interrupts are available on external balls INT[6, 5, 3, 0] and via the serial interface in register 0xE0. Table 13-1 defines the conditions under which interrupts are generated for the external balls INT[6, 5, 3, 0]. All of these interrupts are available in register 0xE0, with the addition of another interrupt that indicates when squelch is active or inactive. Table 13-1. Interrupt Generation (INT[6, 5, 3, 0]) Active-High INT 6 5 3 0 Condition Loss of lock; high-speed PLL Loss of lock; 38.88 MHz PLL Loss of external VCXO clock Loss of CLK Agere Systems Inc. 37 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 14 Serial Interface and Internal Bus The TSYN internal registers can be programmed via a serial interface. This serial interface allows reading or writing of any of the registers. Internally, the TSYN uses two different lines to transmit and receive data from the outside. Those two lines must be multiplexed by an input/output buffer to the single serial line (simplex communication). The serial line will be driven by the external controller except when a read process is requested. In that case, the TSYN will drive the line during the time it needs to transmit the requested data. During a period when no read or write process is requested, SERDAT is pulled internally to a CMOS logic high. As shown on Figure 14-1, there are three external pins related to the serial interface: the serial interface clock, SERCLK, the serial interface data line, SERDAT, and the serial interface enable, SERENBLN. TSYN03622 OUT SERDAT EXTERNAL CONTROLLER INTERFACE CONTROLLER IN SERCLK SERENBLN Figure 14-1. TSYN03622 Serial Interface The serial interface frames are composed of 32 bits. The first 2 bits are used to indicate the beginning of the frame (01). Then the address is transmitted in the next 8 bits, followed by 6 bits indicating if it is a read or write request. Finally, the 16 bits of data are transmitted by the external controller (write) or by the TSYN (read process). In case of a read process, the last 17 bits of the frame are driven by the TSYN, following a bit where no device is driving the line, leaving it in high impedance. As soon as the data has been transmitted, the external user continues to drive the line to a high-logic state waiting for the next frame to transmit. A representation of a WRITE is shown in Figure 14-2 and a READ in Figure 14-3. The transmission for both the data and address bits starts with the most significant bit. 8-bit Address SERDAT 0 1 A7 A6 A5 A4 A3 A2 A1 A0 0 16-bit Data 1 0 0 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SERCLK SERENBLN Figure 14-2. Serial Interface WRITE Frame Format Driven by External Controller Driven by TSWC01622 8-bit Address SERDAT 0 1 A7 A6 A5 A4 A3 A2 A1 A0 1 16-bit Data 0 0 0 Z 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SERCLK SERENBLN Figure 14-3. Serial Interface READ Frame Format 38 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Timing for the serial interface is shown in Figure 14-4. During a read, the address and read request bits are clocked on a rising edge, and the data that is clocked out (by the TSWC) transitions off the clock's rising edge. The signal coming from the TSWC, that is interpreting this serial stream, should use the following falling edge to avoid a race condition. DATA EYE T/2 CLOCK 40nSns TT=>=40 Figure 14-4. Serial Interface Timing Note: The maximum serial interface clock frequency is 25 MHz and the minimum clock period is 40 ns. Table 14-1. Serial Interface Timing Applicable Balls Symbol SERCLK SERENBLN SERCLK SERCLK SERDAT SERDAT SERCLK SERCLK SERDAT SERDAT SERCLK SERCLK SERCLK SERENBLN FMAX t500 Agere Systems Inc. t501 t502 t501 t502 t503 t504 Parameter Maximum Serial Interface Clock Frequency Enable to Clock Setup WRITE Clock to Data Setup WRITE Data Hold READ Clock to Data Setup READ Data Hold Clock Period Enable Hold After Last Clock Min Max Typ Unit -- -- 25 -- -- -- MHz ns -1.0 -- -- ns 3.6 -- -- ns 18 -- -- ns -- -- -- ns 40 -- -- -- -- -- ns ns 39 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 15 TSYN03622 Registers Map Table 15-1 summarizes all the TSYN registers. Table 15-1. TSYN03622 Registers Address Hex TSYN03622 Block 00 01 02--1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35--3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E Control Control -- Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input -- State Mach State Mach State Mach State Mach State Mach -- PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs -- PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs 40 Description Reset register. Serial interface or pin control. Not used. Software reset and software override. FINSEL[3:0]. Reserved. Threshold. For test purposes, set to 0x0002. For test purposes, set to 0x0002. For test purposes, set to 0x0002. For test purposes, set to 0x0002. For test purposes, set to 0x0003. For test purposes, set to 0x0001. For test purposes, set to 0x0001. For test purposes, set to 0x0001. For test purposes, set to 0x0001. For test purposes, set to 0x0001. Hysteresis. Not used. Software reset and software override. ENSQLN, SWCONTN. Reserved. Reserved. Reserved. Not used. Programmable output variable R0 for channel 1. Programmable output variable R1 for channel 1. Programmable output variable R2 for channel 1. Programmable output variable R3 for channel 1. Programmable output variable R4 for channel 1. Programmable output variable R5 for channel 1. Programmable output variable R6 for channel 1. Not used. Programmable output variable R0 for channel 2. Programmable output variable R1 for channel 2. Programmable output variable R2 for channel 2. Programmable output variable R3 for channel 2. Programmable output variable R4 for channel 2. Programmable output variable R5 for channel 2. Programmable output variable R6 for channel 2. Bits Reset 15:8 0 -- 1:0 3:0 3:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 -- 8:0 7:0 15:0 15:0 15:0 -- 9:0 9:0 9:0 9:0 9:0 9:0 2:0 -- 9:0 9:0 9:0 9:0 9:0 9:0 2:0 0xFFFF 0xFFFF -- 0xFFFF 0x000F 0x000F 0x0002 0x0002 0x0002 0x0002 0x0002 0x0003 0x0001 0x0001 0x0001 0x0001 0x0001 0x0004 -- 0xFFFF 0x00FF 0x0003 0x0800 0x4BEF -- 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 -- 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table 15-1. TSYN03622 Registers (continued) Address Hex TSYN03622 Block 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67--7F 80 81 82 83 84 85 86--9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA--AF B0 -- PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs -- PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs -- PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs -- PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs -- SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs -- SDH/SYNC Outputs Agere Systems Inc. Description Not used. Programmable output variable R0 for channel 3. Programmable output variable R1 for channel 3. Programmable output variable R2 for channel 3. Programmable output variable R3 for channel 3. Programmable output variable R4 for channel 3. Programmable output variable R5 for channel 3. Programmable output variable R6 for channel 3. Not used. Programmable output variable R0 for channel 4. Programmable output variable R1 for channel 4. Programmable output variable R2 for channel 4. Programmable output variable R3 for channel 4. Programmable output variable R4 for channel 4. Programmable output variable R5 for channel 4. Programmable output variable R6 for channel 4. Not used. Programmable output variable R0 for channel 5. Programmable output variable R1 for channel 5. Programmable output variable R2 for channel 5. Programmable output variable R3 for channel 5. Programmable output variable R4 for channel 5. Programmable output variable R5 for channel 5. Programmable output variable R6 for channel 5. Not used. Mode (PDHSEL) and powerdown. DIV2, CKMXSEL, MODESEL, and DELAY. Modes for C0, C1, C2, and C3. Modes for C4, C5, C6, and C7. Reserved. Reserved. Not used. Software reset and overrides. SDHSEL register. Duty cycle register. Sync offset and direction. Sync enables. Clock enables. Individual duty cycle changes. Clock edge selection. Sync offset when software override. Additional sync offset when software override. Not used. RISE[15:0]. Bits Reset -- 9:0 9:0 9:0 9:0 9:0 9:0 2:0 -- 9:0 9:0 9:0 9:0 9:0 9:0 2:0 -- 9:0 9:0 9:0 9:0 9:0 9:0 2:0 -- 15:12,0 9:0 15:0 15:12 -- -- -- 3:0 3:0 0 10:0 11:0 9:0 2:0 3:0 15:0 1:0 -- 15:0 -- 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 -- 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 -- 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 -- 0x0001 0x0000 0x0000 0x0000 -- -- -- 0x000F 0x0000 0x0001 0x0000 0x0000 0x0000 0x0007 0x000F 0x0000 0x0000 -- 0x2FC0 41 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 15-1. TSYN03622 Registers (continued) Address Hex TSYN03622 Block B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC--DF E0 SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs -- SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs -- Control Description RISE(16). FALL. DELTA. Not used. Not used. DELTARISE. Not used. For test purposes, read only. For test purposes, read only. For test purposes, read only. For test purposes, read only. Not used. Interrupt register. Bits Reset 0 15:0 3:0 -- -- 4:0 -- 0 15:0 0 15:0 -- 8:0 0x0001 0x97E0 0x0016 0x0016 0x0016 0x000B 0x0000 0x0001 0x2FAA 0x0000 0x97CA -- 0x0060 15.1 Control Block Registers Table 15-2. Hardware Reset for All TSYN03622 Blocks Address (Hex) Bit Name 0x00 15 RHSLOLN 14 RLOSCLKN 13 RSWSTATN 12 RESETFFN 11 RLSPLLN 10 RSYNCN 9 RPDHCLKN 8 RCONFIGN 7:0 -- 42 Description High-speed PLL powerdown. 1 = Block active. 0 = Block powered down. Loss of clock block powerdown. 1 = Block active. 0 = Block powered down. State machine powerdown. 1 = Block active. 0 = Block powered down. Feed-forward counters powerdown. 1 = Block active. 0 = Block powered down. Low-speed PLL powerdown. 1 = Block active. 0 = Block powered down. SDH/sync generation block powerdown. 1 = Block active. 0 = Block powered down. PDH block powerdown. 1 = Block active. 0 = Block powered down. Control block reset. 1 = Block active. 0 = Block reset for one 155.52 MHz clock cycle. Unused: program to one. Reset Value 1 1 1 1 1 1 1 1 00000000 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Register 00h contains power downs for all the TSYN blocks. Setting a bit to a low-level in this register will power down the corresponding block. The block will remain powered down until the bit is again set to high, except for bit 00h(8), which resets the control block only for one 155 MHz clock cycle. This register is initialized to all zeros, and bits 00h[7:0] are not used. The reset register can be written at any time to reset a specific block, although the software reset implemented in each block can also be used. After a general hardware reset, the control block will be setting the reset register bits to a high level following a certain reset sequence. If a block is powered down and it is desired to power it up, a hardware reset is necessary. Table 15-3. Software Override Address (Hex) Bit Name 0x01 15:1 0 -- OVERRIDE Description Unused: program to one. Software override bit. 1 = Software programming disabled (hardware mode). 0 = Software programming enabled (software mode). Reset 111111111111111 1 Register 01h contains the software override bit which must be set to low prior to any write operation. If bit 01h(0) is high, the control block will not write any register except for 01h itself. This register is initialized to all ones, although bits 01h[15:1] are not used, so right after initialization no write process is allowed. Bit 01h(0) must be set low. 15.2 Input Clock Block Registers The loss of clock block monitors the input clock CLK and the 38.88 MHz clock generated by the external VCXO. Table 15-4. Loss of Clock Block Software Override and Reset Address (Hex) Bit Name 20 15:2 1 0 -- SWOVRDN SWRSTN Description Unused: program to one. Reserved. Input clock block powerdown. 1 = Block active. 0 = Block powered down. Reset 11111111111111 1 1 Register 20h contains only 2 bits. These bits are the software powerdown 20h(0) and the software override 20h(1). Both are active-low level, so register 20h is initialized to all ones if bit 20h(1) is low, the input clock block will be operating in software mode, enabling all the programming capabilities and allowing access to the full flexibility of the block. Agere Systems Inc. 43 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 15-5. FINSEL[3:0] Register Address (Hex) Bit Name 21 15:4 3:0 -- FINSEL[3:0] Description Unused: program to one. Clock A and clock B input frequency select. (Bit 3 is a don't care). 1111, 0111 = 51.84 MHz. 1110, 0110 = 38.88 MHz. 1101, 0101 = 19.44 MHz. 1100, 0100 = 8.192 MHz. 1011, 0011 = 6.480 MHz. 1010, 0010 = 2.048 MHz. 1001, 0001 = 1.544 MHz. 1000, 0000 = 8 kHz. Reset 111111111111 1111 Register 21h is written by the control block, which monitors the external pin FINSEL for any change. The FINSEL register must indicate the input clock frequency (FINSEL for CLK). This register is initialized to all ones. It can be written at any time via serial interface (even in hardware mode). Only in hardware mode will any change in these registers reprogram the fractional dividers by rewriting registers 24h--2Dh. Table 15-6. Loss of Clock Threshold Address (Hex) Bit 23 15:0 Name Description Reset THRESHOLD Loss of clock threshold value (number of missing consec- 0000000000000010 utive clock cycles needed to trigger loss of clock interrupt). Register 23h is used to program the threshold time, which is the number of absent input cycles needed to raise the loss of clock interrupt. This values is shared by all the loss of clock detectors. Register 23h can be written at any time (even in hardware mode). The minimum value for this register is a value of 2. If a lower value is written, the threshold will be set to a values of 2. Table 15-7. Loss of Clock Hysteresis Address (Hex) Bit 2E 15:0 Name Description Reset HYSTERESIS Loss of clock hysteresis value (number of consecutive clock cycles needed to erase loss of clock interrupt, once clock is back). 00000000 00000100 Register 2Eh is used to program the hysteresis time, which is the number of input clock cycles needed to erase the loss of clock flag once the clock is back. This values is shared by all the loss of clock detectors. Register 2Eh can be written at any time (even in hardware mode). The minimum value for this register is a value of 4. If a lower value is written, the hysteresis will be set to a values of 4. 44 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 15.3 State Machine Block Registers The address space for the state machine control circuit is 30h--34h. Table 15-8. State Machine Block Control Register Address (Hex) Bit Name 30 15:9 8 7 6 5 4 3 2 1 -- Reserved Reserved LOCN Reserved BUSYN TESTN Reserved SWOVRDN 0 SWRSTN Description Unused: program to ones. For test purposes, set to 1. For test purposes, set to 1. For test purposes, set to 1. For test purposes, set to 1. For test purposes, set to 1. For test purposes, set to 1. -- Software override bit. 1 = Hardware mode (registers 32, 33, and 34 use their default values). 0 = Software mode (user can overwrite registers 32, 33, and 34). State machine block software powerdown. 1 = Block active. 0 = State machine control circuits powered down except for microprocessor interface. Reset 1111111 1 1 1 1 1 1 1 1 1 Bits 30h[8:3] are used for test purposes, and they must be high in normal operation mode, specially bit 30h[3], which is the test mode bit. Table 15-9. State Machine Block State Machine Register Address (Hex) Bit Name 31 15:8 7 -- ENSQLN 6 5 4 Reserved Reserved SWCONTN 3 2 1 0 Reserved Reserved Reserved Reserved Description Reset Unused. 00000000 1 Squelch enable. 1 = Squelch disabled. 0 = Squelch enabled. (Squelch active conditions are listed in Table 15-10). Reserved, set to 1. 1 Reserved, set to 1. 1 1 Software control. Used with ENSQLN for output squelch control. See ENSQLN. 0 = Software control is enabled. 1 = Software control is disabled. Reserved, set to 1. 1 Reserved, set to 1. 1 Reserved, set to 1. 1 Reserved, set to 1. 1 Conditions for use of this register: 01h(0) = 0. Register 31h is initialized to all ones. Positions [15:8] will always read as zeros. This register is updated by the TSYN control block based on the input pins state, although they can also be modified via serial interface. This register will therefore reflect the input pins with the same name given that the TSYN control block updates register 31h via internal bus. The TSYN03622 will use the respective external balls for control when register 01h bit 0 is high, and it will use the configuration from register 31h when register 01h bit 0 is low. All bits in register 31h are active-low. Bit 31h[7] is the squelch enable ENSQLN. Setting this bit low, the SDH and PDH output clocks will be squelched if one of the next conditions, in the table below, are met. Agere Systems Inc. 45 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 15-10. Squelch Mode of Operation Conditions Needed to Squelch the Output Clocks when ENSQLN = 0 SWCONTN = 1 SWCONTN = 0 The output clocks will be squelched if the input clock reference is lost (LOC = 1). The output clocks will be squelched always if ENSQLN is low, no matter the conditions of the input clocks are. As indicated in the previous table, when operating with SWCONTN = 0, the squelch enable is used to squelch the output clocks, whereas for the other operation mode the squelch enable allows squelching when the special conditions are met. 15.4 PDH Output Block Registers 15.4.1 Fractional Dividers Registers: 40h--66h The PDH fractional dividers enable each of the five PDH CMOS output clocks to be fully programmable. Registers 40h--66h contain the parameters to set the respective frequencies, setting the frequencies is enable in registers 80h--83h. Each fractional divider includes seven registers. Those registers are located at consecutive addresses. The address of each register can be specified by the base address of the corresponding fractional divider and the relative offset. Base Address Fractional divider 1 Fractional divider 2 Fractional divider 3 Fractional divider 4 Fractional divider 5 40h 48h 50h 58h 60h To calculate the values for the respective dividers, a software program is available to automate the process. Please contact your Agere Systems representative to get a copy of the program. All registers are initialized to all zeros at reset. 15.5 General Configuration Registers 80h--83h Registers 80h--83h are the general configuration registers, which control the operation mode of the PDH block. The first two registers 80h and 81h control the general behavior of the PDH block, whereas registers 82h and 83h control the five fractional dividers used to generate the PDH rates. Table 15-11. PDH Control Register 1 Address (Hex) Bit 80 15:12 11:1 0 Name Description Reset PDHSEL Software PDH output clock select. See Table 15-12 for preset configurations. To use this register, 81h(4:3) must be set to 10. -- Reserved. SWRSTN PDH block software powerdown. 1 = Block active. 0 = PDH output block powered down except for microprocessor interface. 0000 00000000000 1 Register 80h contains the software reset bit 80h(0) and the four PDHSEL[3:0] bits used to select one of the sixteen preset configurations when 81h[4:3] = 10 (basic software control) generating the most needed PDH rates. Bit 80h[0] is the software reset used to power down the PDH block except for the microprocessor used to read and write registers. The microprocessor can only be reset by hardware reset. Register 80h is initialized with all bits low except for 80h(0), which is high. Bits [10:1] can be written and read as they were written, but they are not used by the PDH block. 46 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table 15-12. PDH Clock Outputs for the 16 Preset Configurations (Bit 81h[3] = 0) PDHSEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Agere Systems Inc. Clock 1 Clock 2 Clock 3 Disabled Clock 4 Clock 5 44.736 MHz Disabled 34.368 MHz Disabled Disabled 32.768 MHz Disabled 24.704 MHz Disabled Disabled 16.384 MHz Disabled Disabled 8.192 MHz Disabled Disabled 4.096 MHz Disabled Disabled 2.43 MHz Disabled 2.048 MHz Disabled Disabled 1.544 MHz Disabled Disabled 2.048 MHz 1.544 MHz Disabled 44.736 MHz 32.768 MHz 24.704 MHz 2.048 MHz 1.544 MHz 34.368 MHz 32.768 MHz 24.704 MHz 2.048 MHz 1.544 MHz Disabled 44.736 MHz 32.768 MHz 2.048 MHz 1.544 MHz 2.43 MHz 47 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 15-13. PDH Control Register 2 Address (Hex) Bit Name Description Reset 81 15:10 9:8 7:5 4:3 -- DIV2N CKMXSEL MODESEL Reserved. For Test Purposes Only. Program to 00. For Test Purposes Only. Program to 000. 00--Hardware control. This mode allows to control the PDH block through the external PDHSEL[3:0] pins in case the TSYN control block fails. These pins reach the PDH block, so the PDH block behavior is independent of the TSYN control block. This mode offers 16 presets, which generate the most needed PDH frequencies. Every one of those configurations programs each fractional divider to work in one of the 16 modes listed in Table 15-15. 000000 00 000 00 10--Basic software control. This mode is intended to be used in conjunction with the TSYN control block. The PDH block operates in the same way as in hardware control offering the same 16 presets, but this time instead of reading the external pins directly, the four PDHSEL[3:0] bits are read from register 80h (four most significant bits). This register is written by the control block at initialization or when any change is made on the external pins, as the control block monitors the external pins in a continuous basis. Register 80h can also be written via serial interface (software override). 2:0 DELAY X1--Enhanced software control. This mode can only be used by programming the PDH block via serial interface. This third alternative allows individual selection of the operating mode for each fractional divider. Registers 82h and 83h contain the 20 bits needed to specify the operating mode for each of the five fractional dividers (4 bits per fractional divider). For Test Purpose Only. Program to 00. 000 Table 15-14. Enhanced Software Mode Fractional Divider Selection Address (Hex) Bit 82 15:12 11:8 7:4 3:0 83 15:12 11:0 Name Description Reset FD 1 MODE PDH1 fractional divider mode, see text below and Table 15-15 to program value. FD 2 MODE PDH2 fractional divider mode, see text below and Table 15-15 to program value. FD 3 MODE PDH3 fractional divider mode, see text below and Table 15-15 to program value. FD 4 MODE PDH4 fractional divider mode, see text below and Table 15-15 to program value. FD 5 MODE PDH5 fractional divider mode, see text below and Table 15-15 to program value. -- Reserved. 0000 0000 0000 0000 0000 000000000000 Registers 82h and 83h indicate the operation mode of each fractional divider when bit 81h[3] is high. There are 4 bits for each fractional divider. These registers are reset to all zeros. Each fractional divider can be operated in sixteen different modes. These modes are described in Table 15-15. 48 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table 15-15. Software Mode Fractional Divider Selection Mode Mode Bits [3:0] Divides By 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 13 + 211/233 18 + 18/179 18 + 63/64 25 + 35/193 37 + 31/32 75 + 15/16 100 + 140/193 64 151 + 7/8 303 + 3/4 256 402 + 174/193 32 Reserved Programmable Power down In mode 14, the fractional divider can be programmed through the registers located inside the fractional divider. Fractional dividers 1--3 use the 622.08 MHz clock as input, where fractional dividers four and five use the 155.52 MHz clock. Based on the previous table, the input frequency to each fractional divider and the division factor indicated in Table 15-16, the sixteen presets will generate the output clocks (each clock is generated by the fractional divider with the same number) shown in Table 15-12. Table 15-16 summarizes the operation mode for the five fractional dividers when bit 80[3] is low. In that case, the PDH block offers sixteen preset configurations that can be selected by the external pins (when 81h[4] = 0) or writing register 80h (when 81h[4] = 1). Table 15-16. Fractional Dividers Operation Mode This table shows the fractional dividers operation mode as a function of the external pins PDHSEL[3:0] or bits 80h[15:12] (bit 81h[3] must be low). PDHSEL[3:0] or Bits 80h[15:12] FD 1 FD 2 FD 3 FD 4 FD 5 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 15 0 1 15 3 15 15 15 15 15 15 15 0 1 15 0 15 15 15 2 15 4 5 15 15 15 15 15 2 2 15 2 15 15 15 15 15 15 15 8 15 9 15 9 3 3 15 9 15 15 15 15 15 15 15 15 15 15 6 6 5 5 15 6 15 15 15 15 15 15 15 15 7 15 15 15 6 6 15 7 Agere Systems Inc. 49 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 15.6 SDH/Sync Generation Block Registers Table 15-17. SDH/Sync Control Register Address Bit (Hex) A0 Name Description 15:4 -- Reserved. 3 SYNC OFFSET OVERRIDE Sync offset override. 1 = Sync offset read from register A3h. 0 = Sync offset read from registers A8h and A9h (which has a wider range than external pins, covering a complete 8 kHz cycle). Conditions for use of this feature: SDH_HW pin low. 2 DUTY CYCLE OVERRIDE Duty cycle override. 1 = Duty cycle read from register A2h. 0 = Duty cycle read from A6h (which allows for different duty cycles for the three kinds of output syncs). Conditions for use of this feature: SDH_HW pin low. 1 SDHSEL OVERRIDE SDHSEL override. 1 = Output clocks enables read from SDHSEL, read from register A1h. 0 = Output clocks enables read from register A5h. Conditions for use of this feature: SDH_HW pin low. 0 SRESETN SDH/Sync block software powerdown. 1 = Active. 0 = Powered down except for microprocessor interface. Conditions for use of this feature: SDH_HW pin low. Reset 000000000000 1 1 1 1 Bit 0 is the software reset used to reset the SDH/sync block. Bits 1, 2, and 3 are overrides (active-low level). When the SDH_HW pin is high, the values used as SDHSEL, DUTY, and SYNCOFFSET are read from the external pins. When that pin is low, those values will be set via serial interface. If bits 1, 2, and 3 are high, the values will be read from the same registers as if the TSYN was in pin control; that is, SDHSEL is stored in register A1h, DUTY is in register A2h, and SYNCOFFSET is in register A3h. When bit A0h(1) is low (SDH_HW = 0), the enables for the output clocks will be taken from register A5, which is a bit-toenable register. If bit A0h(2) is low (SDH_HW = 0), the duty cycle is specified by register A6h, which allows different duty cycles for the three kinds of output syncs. Setting bit A0h(3) to a low level and SDH_HW = 0 allows the user to specify the offset in the output sync with registers A8h and A9h. Those registers give a wider range to position the output sync than the external pins or register A3h. By using these registers, the user may be able to place the output sync in any position of the 8 kHz cycle. 50 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table 15-18. SDHSEL Register Address (Hex) A1 Bit Name Description Reset 15:4 -- Reserved. 3:0 SDHSEL SDH clock and sync selection. See Table 7-1 on page 20. Conditions for use of this feature: A0h(1) = 1 and SDH_HW pin low. 000000000000 0000 This is the SDHSEL[3:0] register used to select one of the sixteen presets when the SDH_HW pin is low and bit A0h(1) is high (basic software enables configuration). Each of the sixteen presets controls the clock and sync enables as the SDHSEL[3:0] external pins do when the SDH_HW pin is high. This register is initialized at 0000, selecting the preset number zero, which disables all clock and sync outputs. Table 15-19. Sync Duty Cycle Address (Hex) A2 Bit Name Description 15:1 -- Reserved. 0 Duty Cycle Sync duty cycle. 1 = 50%. 0 = Pulse width per conditions for use of this feature: A0h(2) = 1 and SDH_HW pin low. Reset 000000000000000 1 Register A2h is the duty cycle register, where bit A2h(0) is the duty cycle bit. A2h(0) is used to select the duty cycle of the output syncs only when the SDH_HW pin is low and the duty cycle override bit A0h(2) is high (basic software duty cycle configuration). It works as the external pin SYDU when pin SDH_HW is high. If the duty cycle bit is high, the duty cycle of all output syncs will be 50%, although it can be programmed to take a different value through the algorithm control registers B0h, B1h, and B2h. If the duty cycle bit is zero, each output sync will have the default pulse width, depending on the selected sync for each output. Table 15-20. Output Syncs Duty Cycle Sync Output Pulse Width PECL0/PECL1, LVDS0/LVDS1 CMOS One cycle of the 155 MHz or 622 MHz clock. One cycle of the 77.76 MHz, 51.84 MHz, 38.88 MHz, or 19.44 MHz. The duty cycle bit is initialized to one, so the output syncs will have 50% duty cycle. Table 15-21. Sync Offset Address (Hex) Bit A3 15:11 10 9:0 Name Description -- Reserved. SYOFFPOS Positive of negative offset bit. 1 = Positive. 0 = Negative. Conditions for use of this feature: A0h(3) = 1 and SDH_HW pin low. SYOFF Sync offset. Value of this offset indicates number of 1/622.08 (~1.6) ns increments. Conditions for use of this feature: A0h(3) = 1 and SDH_HW pin low. Reset 00000 0 0 This is the sync offset and direction register used in the same way as the external pins SYOFF[9:0] and SYOFFPOS. This register will be used only when the SDH_HW pin is low and bit A0h(3) is high (basic software offset configuration). Bits A3h[9:0] are the sync offset and bit A3h(10) is the direction. In order to get a positive delay, that is, to delay the output sync with respect to the negative edge of the input sync, that bit, A3h(10), must be high. Register A3h is reset to all zero. Agere Systems Inc. 51 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 15-22. Sync Source Address (Hex) Bit Name Description Reset A4 15:12 11* 10 9 8 -- SYPCL6221 SYPCL6220 SYPCL1551 SYPCL1550 0000 0 0 0 0 7 6 5 4 SYNC8K78 SYNC8K51 SYNC8K38 SYNC8K19 3 2 1 0 SYLVS6221 SYLVS6220 SYLVS1551 SYLVS1550 Reserved. LVPECL Sync Enable. These registers [11:8] control the enables and sources of the LVPECL syncs. Bits 10 and 8 control SYPCLP/N[0] and bits 11 and 9 control SYPCLP/N[1] as follows: SYPCLP/N[0] X0X0 = Disabled. X0X1 = Enabled, pulse width based on SYNC155, as defined in A6h(1). X1X0 = Enabled, pulse width based on SYNC622, as defined in A6h(0). X1X1 = Disabled. SYPCLP/N[0] 0X0X = Disabled. 0X1X = Enabled, pulse width based on SYNC155, as defined in A6h(1). 1X0X = Enabled, pulse width based on SYNC622, as defined in A6h(0). 1X1X = SYPCLP/N[1] disabled. Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0. CMOS Sync Enable. These registers [7:4] control the enable and source of the CMOS sync. The pulse width is based on A6h(2). If A6h(2) is high, the pulse width is based on the configuration below. 0001, 0010, 0100, or 1000: pulse width is 50% of sync period. Other = Disabled. If A6h(2) is low, the pulse width is based on the configuration below. 0001 = One cycle of the 19.44 MHz clock. 0010 = One cycle of the 38.88 MHz clock. 0100 = One cycle of the 51.84 MHz clock. 1000 = One cycle of the 77.76 MHz clock. Other = Disabled. Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0. LVDS sync enable. These registers [3:0] control the enables and sources of the LVDS syncs. Bits 2 and 0 control SYLVSP/N[0], and bits 3 and 1 control SYLVSP/N[1] as follows: SYLVSP/N[0] X0X0 = Disabled. X0X1 = Enabled, pulse width based on SYNC155, as defined in A6h(1). X1X0 = Enabled, pulse width based on SYNC622, as defined in A6h(0). X1X1 = Disabled. SYLVSP/N[1] 0X0X = Disabled. 0X1X = Enabled, pulse width based on SYNC155, as defined in A6h(1). 1X0X = Enabled. pulse width based on SYNC622, as defined in A6h(0). 1X1X = Disabled. Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0. 0 0 0 0 0 0 0 0 * In Version 1.0 and 1.1 of the TSYN03622, there is an errata with bit 11 of register A4h. This register can be written, but does not respond correctly to a read. When this bit is read, it will return a 0, regardless of the true value in the register. This register is used with register A5h for enhanced software enables configuration, it will only be used when the SDH_HW pin is low and bit A0h(1) is low (override enables). It controls the output sync enables, so it selects the output sync pulse width when the duty cycle bit is low (not 50%). This register is initialized to zero. 52 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table 15-23. SONET/SDH Clock Enable Address (Hex) Bit Name A5 15:10 9 -- PECL622 8 PECL1551 7 PECL1550 6 CK78 5 CK51 4 CK38 3 CK19 2 LVDS622 1 LVDS1551 0 LVDS1550 Description Reserved. Enable for the 622.08 MHz PECL differential output (PECL622). 1 = Enabled, 0 = Disabled. Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low. Enable for the 155.52 MHz PECL differential output (PECL1551). 1 = Enabled, 0 = Disabled. Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low. Enable for the 155.52 MHz PECL differential output (PECL1550). 1 = Enabled, 0 = Disabled. Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low. Enable for the 77.76 MHz single-ended CMOS output. 1 = Enabled, 0 = Disabled. Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low. Enable for the 51.84 MHz single-ended CMOS output. 1 = Enabled, 0 = Disabled. Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low. Enable for the 38.88 MHz single-ended CMOS output. 1 = Enabled, 0 = Disabled. Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low. Enable for the 19.44 MHz single-ended CMOS output. 1 = Enabled, 0 = Disabled. Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low. Enable for the 622.08 MHz LVDS differential output (LVDS622). 1 = Enabled, 0 = Disabled. Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low. Enable for the 155.52 MHz LVDS differential output (LVDS1551). 1 = Enabled, 0 = Disabled. Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low. Enable for the 155.52 MHz LVDS differential output (LVDS1550). 1 = Enabled, 0 = Disabled. Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low. Reset 000000 0 0 0 0 0 0 0 0 0 0 This register controls the individual SDH clock enables when the SDH_HW pin is low and bit A0h(1) = 0 (enhanced software enables configuration). A low-zero means that the corresponding output clock will be disabled. Recall that regarding the 155.52 MHz and 622.08 MHz clocks, only the enable signals are generated by the SDH block. The clocks are generated by other circuits external to the SDH block. Register A5h is initialized to zero (all clocks disabled). When A0h[2] is low, the sync outputs (SYNC8K, SYPCL[1:0], and SYLVS[0:1]) duty cycles will be programmed from registers A4h and A6h. In register A6h, if any of the used bits are set low, then the pulse widths for the selected syncs will be set by the respective control in register A4h. If a respective sync output is programmed to have a duty cycle less then 50% per the previous conditions, then the clock outputs per Table 15-24 through Table 15-26 will be active, regardless of the clock enable status in register A5h. Agere Systems Inc. 53 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 15.7 LVPECL Output Syncs and Clocks Table 15-24. LVPECL Output Clock Status when Influenced by Programmable Duty Cycle on Syncs Setting in Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Register A4h[11:8] Setting in Binary Bit 11 Bit 10 Bit 9 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Bit 8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PCK155P/N0 Clock Output Status PCK155P/N1 PCK622P/N Set by A5h[7] Active Set by A5h[7] Active Set by A5h[7] Active Set by A5h[7] Active Set by A5h[7] Active Set by A5h[7] Active Set by A5h[7] Active Set by A5h[7] Active Set by A5h[8] Set by A5h[8] Active Active Set by A5h[8] Set by A5h[8] Active Active Set by A5h[8] Set by A5h[8] Active Active Set by A5h[8] Set by A5h[8] Active Active Set by A5h[8] Set by A5h[8] Set by A5h[8] Set by A5h[8] Active Active Active Active Active Active Active Active Active Active Active Active 15.8 CMOS Output Syncs and Clocks : Table 15-25. LVPECL Output Clock Status when Influenced by Programmable Duty Cycle on Syncs Setting in Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F 54 Register 0xA4[7:4] Setting in Binary Bit 7 Bit 6 Bit 5 Bit 4 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 CK19 Set by A5h[3] Active Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Set by A5h[3] Clock Output Status CK38 CK51 Set by A5h[4] Set by A5h[4] Active Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[4] Set by A5h[5] Set by A5h[5] Set by A5h[5] Set by A5h[5] Active Set by A5h[5] Set by A5h[5] Set by A5h[5] Set by A5h[5] Set by A5h[5] Set by A5h[5] Set by A5h[5] Set by A5h[5] Set by A5h[5] Set by A5h[5] Set by A5h[5] CK77 Set by A5h[6] Set by A5h[6] Set by A5h[6] Set by A5h[6] Set by A5h[6] Set by A5h[6] Set by A5h[6] Set by A5h[6] Active Set by A5h[6] Set by A5h[6] Set by A5h[6] Set by A5h[6] Set by A5h[6] Set by A5h[6] Set by A5h[6] Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 15.9 LVDS Output Syncs and Clocks Table 15-26. LVDS Output Clock Status when Influenced by Programmable Duty Cycle on Syncs Register 0xA4[3:0] Setting in Binary Bit 3 Bit 2 Bit 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Setting in Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CK155P/N0 Clock Output Status CK155P/N1 CK622P/N Set by A5h[0] Active Set by A5h[0] Active Set by A5h[0] Active Set by A5h[0] Active Set by A5h[0] Active Set by A5h[0] Active Set by A5h[0] Active Set by A5h[0] Active Set by A5h[1] Set by A5h[1] Active Active Set by A5h[1] Set by A5h[1] Active Active Set by A5h[1] Set by A5h[1] Active Active Set by A5h[1] Set by A5h[1] Active Active Set by A5h[2] Set by A5h[2] Set by A5h[2] Set by A5h[2] Active Active Active Active Active Active Active Active Active Active Active Active Table 15-27. Sync Duty Cycle Address (Hex) Bit A6 15:3 2 1 0 Name Description -- Reserved. DUTY CYCLE SYNCCMOS Set duty cycle for the CMOS sync. 1 = 50%. 0 = Pulse width as set by A4h(7:4). Conditions for use of this feature: A0h(2) = 0 and SDH_HW pin low. DUTY CYCLE SYNC155 Set duty cycle for the SYNC155. 1 = 50%. 0 = One 155.52 MHz clock cycle. Conditions for use of this feature: A0h(2) = 0 and SDH_HW pin low. DUTY CYCLE SYNC622 Set duty cycle for the SYNC622. 1 = 50%. 0 = One 622.08 MHz clock cycle. Conditions for use of this feature: A0h(2) = 0 and SDH_HW pin low. Reset 0000000000000 1 1 1 This register is used to control the individual syncs duty cycle when the SDH_HW pin is low and bit A0h(2) = 0 (enhanced software duty cycle configuration). Only the three least significant bits are used as there are only three types of output syncs (SYC155, SYNC622, and CMOS). A high-duty cycle bit selects the duty cycle of the corresponding sync to be 50%. If the bit is low, the sync pulse width will be equal to one 622.08 MHz clock cycle for SYNC622, and one 155.52 MHz clock cycle for SYNC155; and for the CMOS sync, the pulse width can be programmed to be one clock cycle of the 77.76 MHz, 51.84 MHz, 38.88 MHz, or 19.44 MHZ clock. Register A6 is initialized to 111; that is, all 50% duty cycle. Agere Systems Inc. 55 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 15-28. CMOS SONET Clock Edge Selection Address (Hex) Bit Name A7 15:4 3 -- CK78 2 CK51 1 CK38 0 CK19 Description Reserved. Edge selection for the 77.76 MHz clock. 1 = Rising edge of corresponding clock aligned to input sync. 0 = Falling edge of corresponding clock aligned to input sync. Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0. Edge selection for the 51.84 MHz clock. 1 = Rising edge of corresponding clock aligned to input sync. 0 = Falling edge of corresponding clock aligned to input sync. Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0. Edge selection for the 38.88 MHz clock. 1 = Rising edge of corresponding clock aligned to input sync. 0 = Falling edge of corresponding clock aligned to input sync. Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0. Edge selection for the 19.44 MHz clock. 1 = Rising edge of corresponding clock aligned to input sync. 0 = Falling edge of corresponding clock aligned to input sync. Reset 000000000000 1 1 1 1 Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0. This is the edge selection for the four SDH clocks generated by the SDH block. A high bit means that the corresponding clock's rising edge will be synchronized to the negative edge of the input sync (actually it will lead the sync by 1--2 cycles of a 622 MHz clock). If the edge selection bit is low, the falling edge of the corresponding clock will be aligned to the input sync. This register is set to 1111 at reset, aligning the rising edges of the clocks to the input sync. Table 15-29. Enhanced Sync Offset Address (Hex) Bit Name A8 A9 15:0 15:2 1 0 SSYNCOFFSET -- SYOFFPOS SSYNCOFFSET(16) Description Enhanced sync offset. Bits A9h(0) (MSB) and A8h(15:0) contain the sync offset value, calculated in increments of 1/622.08 (~1.6) ns. To be used with A9h[1:0] SSYOFFPOS. Reset 0000000000000000 00000000000000 0 0 Bit A9h(1): Denotes whether enhanced offset is positive or negative: 1 = Positive. 0 = Negative. Bits A9h(15:2): Reserved. Conditions for use of this feature: A0h(3) = 0 and SDH_HW pin low. These registers are used to increase the possible offset between the input and output syncs. They will be used in enhanced software offset configuration (pin SDH_HW = 0 and bit A0h(3) = 0), giving 17 bits for the absolute value of the offset as opposed to the 10 bits available in hardware and basic software offset configuration. Those 17 bits are the 16 bits of register A8h and bit A9h(0), which is the most significant bit of the offset. Bit A9h(1) is the direction of the offset (1 means that the output sync will be delayed from the input sync). These registers are initialized to zero. In order to write registers A8h and A9h, first A8h must be written. However, register A8h will not be actually written until register A9h is also written. 56 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table 15-30. Sync Rising Edge Position Address (Hex) B0 B1 Bit Name Description 15:0 RISE Sync rising edge position. 15:1 -- Bits B1h(0) (MSB) and B0h(15:0) contain the sync rising edge position, 0 RISE(16) calculated in increments of 1/622.08 (~1.6) ns. Reset 0x2FC0 000000000000000 1 Bits B1h(15:1): reserved. Register B0h--B6h will only be recalculated (and affect the sync outputs) by the internal state machine after one of the following actions occur: The SDH_HW pin is high and the user changes the SYOFF or SYOFFPOS pins. SDH_HW is low, A0(3) is high and the user writes to register A3. SDH_HW is low, A0(3) is low and the user changes A8h or A9h. These registers contain the value RISE used by the algorithm to calculate the position of the rising edge of the output sync. These two registers together offer 17 bits to define the value of RISE. Bit B1h(0) is the most significant bit. At initialization, these registers have the value B1h(0) and Bh0 = 1001011111100000 = 77,760. These registers are also used in conjunction with register B6h to generate the parameter tcnt, used by the high-speed sync generation block. It is not recommended that rise position of the sync outputs be adjusted in this fashion, as the frequency of the sync outputs may be affected. It is recommended instead to use the offset functionality in registers A8h and A9h to control the rise of the sync outputs and then use register B2h to control the fall position. Table 15-31. Sync Falling Edge Position Address (Hex) Bit B2 15:0 Name Description FALL Sync falling edge position. Contains the sync falling edge position, calculated in increments of 1/622.08 (~1.6) ns. Reset 0x97E0 Sync outputs must be set to 50% duty cycle for this feature. This can be set by the following: with A0h(2) high, set A2h(0) high; with A0h(2) low, set respective bits of A6h high, for CMOS specifically, A4h[7:4] must be set either to 0001, 0010, 0100 or 1000. Register B0h--B6h will only be recalculated (and affect the sync outputs) by the internal state machine after one of the following actions occur: The SDH_HW pin is high and the user changes the SYOFF or SYOFFPOS pins. SDH_HW is low, A0(3) is high, and the user writes to register A3. SDH_HW is low, A0(3) is low, and the user changes A8h or A9h. Register B2h is used to store the value of the parameter FALL used by the sync generation algorithm. This register can be modified to obtain any desired duty cycle on the output syncs. It is initialized at 1001011111100000 = 38,880. Given that value, with the initial value of registers B0h and B1h, the output syncs will have 50% duty cycle when the corresponding duty cycle bit is high. Agere Systems Inc. 57 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 15-32. Sync Delta Address (Hex) Bit B3 15:5 4:0 Name Description Reset -- Reserved. DELTA Compensation for the delay between the negative edge of the input sync and the positive edge of the output sync when the regular offset is zero. Value of this offset indicates number of 1/622.08 (~1.6) ns increments. 00000000000 10110 Register B0h--B6h will only be recalculated (and affect the sync outputs) by the internal state machine after one of the following actions occur: The SDH_HW pin is high and the user changes the SYOFF or SYOFFPOS pins. SDH_HW is low, A0(3) is high and the user writes to register A3. SDH_HW is low, A0(3) is low and the user changes A8h or A9h. This register gives an extra offset to compensate the delay due to the circuits. This offset is always negative, as opposed to the regular offset defined by registers A3h or A8h/A9h, which can be positive or negative (positive offset increases the delay of the output sync in relation to the negative edge of the input sync. This register is initialized to 10110 = 22. That value compensates the delay between the negative edge of the input sync and the positive edge of the output sync when the regular offset is zero. Without this extra offset, the output sync would be delayed 22 622 MHz clock cycles. Register B3h is therefore parameter DELTA used by the sync generation algorithm. Table 15-33. Sync Delta Rise Address (Hex) B6 Bit Name Description Reset 15:5 -- Reserved. 00000000000 4:0 DELTARISE The five bits of register B6h are used in conjunction with registers B0h/B1h 01011 to calculate the value of the parameter tcnt used by the sync generation algorithm (tcnt = RISE - B6h). The value of B6h will be subtracted from the value of registers B0h/B1h to calculate tcnt. Register B0h--B6h will only be recalculated (and affect the sync outputs) by the internal state machine after one of the following actions occur: The SDH_HW pin is high and the user changes the SYOFF or SYOFFPOS pins. SDH_HW is low, A0(3) is high and the user writes to register A3. SDH_HW is low, A0(3) is low and the user changes A8h or A9h. The 5 bits of register B6h are used in conjunction with registers B0h/B1h to calculate the value of the parameter tcnt used by the sync generation algorithm (tcnt = RISE - B6h). The value of B6h will be subtracted form the value of registers B0h/B1h to calculate tcnt. The initial value at reset is 01011 = 11. As it can be seen in the previous algorithm description, this value is needed to generate the proper value for tcnt. It is not recommended that rise position of the sync outputs be adjusted in this fashion, since the frequency of the sync outputs may be affected. It is recommended instead to use the offset functionality in registers A8h and A9h to control the rise of the sync outputs and then use register B2h to control the fall position. 58 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Table 15-34. Interrupt Status Register Address (Hex) Bit Name Description Reset E0 15:10 9 -- SQUELCH 111111 1 8 7 6 Reserved Reserved HSLOL 5 LSLOL 4 3 Reserved LOCLS 2 1 0 Reserved Reserved LOCA Reserved. The output clocks have been squelched due to a problem. 1 = Squelch inactive. 0 = Squelch active. Reserved. Reserved. Loss of lock--high-speed PLL. 1 = Loss of lock. 0 = In lock. Loss of lock--low-speed PLL. 1 = Loss of lock. 0 = In lock. Reserved. Loss of external 38.88 MHz VCXO clock. 1 = Loss of clock. 0 = No loss of clock. Reserved. Reserved. Loss of clock A. 1 = Loss of clock. 0 = No loss of clock. 1 1 1 1 1 1 1 1 1 The interrupt register E0h is a read-only and clear-on-read register, which reflects the status of the TSYN interrupts. Whenever there is an interrupt, the corresponding bit will be set high and will remain high until the register is read, even if the event which generated the interrupt is over. However, the interrupt external pins reflect the interrupts only while they are active, so the corresponding pin goes low as soon as the event has finished. Agere Systems Inc. 59 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 16 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this device specification. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 16-1. Absolute Maximum Ratings Parameter Power Supply Voltage (VDD) Storage Temperature Ball Voltage Min Max Unit -0.50 -40 GND - 0.5 4.2 125 VDD + 0.5 V C V 16.1 Handling Precautions Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. Table 16-2. Handling Precautions Device Minimum HBM Threshold Minimum CDM Threshold TSYN03622 1500 V 200 V 16.2 Operating Conditions Table 16-3. Recommended Operation Conditions Parameter Power Supply (dc voltage) Temperature: Ambient Power Dissipation Symbol Min Typ Max Unit VDD 3.135 3.3 3.465 V -- PD -40 -- 25 1.0 85 TBD C W Note: For conditions of SDHSEL[3:0] = 1111 and PDHSEL[3:0] = 1100, power dissipation will vary based on specific device configuration and customer applications. For further information, contact the Agere Systems representative. 16.3 Powerup Conditions No special powerup sequence is necessary; however, the device needs to be reset on powerup. The output clocks will be active, i.e., free running, based on the pin configurations. CKPDHx clocks will not be active until the high-speed PLL is locked. 60 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 17 Electrical Characteristics 17.1 LVPECL, LVDS, CMOS, Input, and Output Balls Note: For Table 17-1 through Table 17-5, VDD = 3.3 V 5%, TAMBIENT = -40 C to +85 C. Table 17-1. LVDS Output dc Characteristics Applicable Balls CK622P/N, CK155P/N[1:0], SYLVSP/N[1:0] Parameter Output Voltage High, VOA or VOB Output Voltage Low, VOA or VOB Output Differential Voltage Output Offset Voltage Differential Output Impedance RO Mismatch Between A and B Change in |VOD| Between Logic 0 and Logic 1 Change in |VOS| Between Logic 0 and Logic 1 Output Current Output Current Symbol Conditions Min Typ Max Unit VOH VOL |VOD| VOS RO Ro |VOD| RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% VCM = 1.0 V and 1.4 V VCM = 1.0 V and 1.4 V RLOAD = 100 1% 1350 925 250 1125 80 -- -- -- -- -- -- 100 -- -- 1475 1100 400 1275 120 20 25 mV mV mV mV % mV |VOS| RLOAD = 100 1% -- -- 25 mV ISA, ISB ISAB Driver shorted to GND Drivers shorted together -- -- -- -- 24 12 mA mA Table 17-2. LVDS Input dc Characteristics Applicable Balls CLKP/N Parameter Input Common-mode Voltage Range Input Peak Differential Voltage Input Differential Threshold Differential Input Impedance* Symbol Conditions Min Typ Max Unit VCM VDIFF VIDTH RIN Avg (VIA, VIB) |VIA -VIB| VIA -VIB Measure at dc 0 100 -100 80 1200 -- -- 100 2400 800 100 120 mV mV mV * Looser than IEEE(R) specification of 10 . Agere Systems Inc. 61 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 Table 17-3. CMOS Input dc Characteristics Applicable Balls Parameter Symbol Conditions Min Max Unit LSVCO Input Voltage High Input Voltage Low Input Current High Leakage Input Current Low Leakage Input Voltage High Input Voltage Low Input Current High Leakage Input Current Low Leakage VIH VIL IIH IIL VIH VIL IIH IIL -- -- VIN = VDD VIN = GND -- -- VIN = VDD VIN = GND VDD - 1.0 GND -- -10 VDD - 1.0 GND -- -10 VDD 0.8 10 -- VDD 0.8 225 -- V V A A V V A A Input Voltage High Input Voltage Low Input Current High Leakage Input Current Low Leakage VIH VIL IIH IIL -- -- VIN = VDD VIN = GND VDD -1.0 GND -- -225 VDD 0.8 10 -- V V A A Symbol Conditions Min Max Unit Output Voltage High Output Voltage Low Output Load Capacitance VOH VOL CL IOH = -4.0 mA IOL = 4.0 mA -- VDD - 0.5 GND -- VDD 0.5 15 V V pF Output Voltage High Output Voltage Low Output Load Capacitance VOH VOL CL IOH = -1.0 mA IOL = 1.0 mA -- VDD - 0.5 GND -- VDD 0.5 15 V V pF Typ Max Unit VDD - 1.135 VDD - 1.935 0.800 VDD - 1.06 VDD - 1.86 0.950 V V V CLK, SYCLK, SDHSEL[3:0] SYOFF[9:0], PDHSEL[3:0], SDH_HW, TSTMODE SELLVDS, FINSEL[3:0], INLOSN, SYOFFPOS, SYDU, SWCONTN, ENSQLN, RESETN, LF0Z, SERCLK, SERENBLN, SERDAT Table 17-4. CMOS Output dc Characteristics Applicable Balls CK77,CK51, CK38, CK19, SYNC8K, CKPDH5, CKPDH4, CKPDH3, CKPDH2, CKPDH1, MON8K, SERDAT INT[6, 5, 3, 0] Parameter Table 17-5. LVPECL Output dc Characteristics 62 Applicable Balls Parameter Symbol PCK622P/N, PCK155P/N[1:0], SYPCLP/N[1:0] Output Voltage High Output Voltage Low Output Differential Voltage VOH VOL |VOD| Conditions Min Load = 50 VDD - 1.21 connected to VDD - 2.01 VDD - 2.0 V 0.650 Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 18 Timing Characteristics Table 18-1. LVDS Input ac Timing Characteristics Applicable Balls Symbol CLKP/N tPW -- Parameter Pulse Width Duty Cycle Conditions Min Typ Max Unit Input frequencies greater than 8 kHz Input frequency of 8 kHz 8 45 -- 50 -- 55 ns % Table 18-2. LVDS Output ac Timing Characteristics Applicable Balls Symbol CK622P/N, CK155P/N[1:0] SYLVSP/N[1:0] tRISE tFALL tSKEW1* Parameter Rise Time, 20% to 80% Fall Time, 20% to 80% Differential Skew Conditions Min Typ Max Unit ZLOAD = 100 1% ZLOAD = 100 1% -- 200 200 -- -- -- -- 300 300 50 ps ps ps *As defined in the IEEE standard 1596.3 -1996. Table 18-3. CMOS Input ac Timing Characteristics Applicable Balls Symbol CLK, SYCLK tPW -- Parameter Pulse Width Duty Cycle Conditions Min Typ Max Unit Input frequencies greater than 8 kHz Input frequency of 8 kHz 8 45 -- 50 -- 55 ns % Min Typ Max Unit Table 18-4. CMOS Output ac Timing Characteristics Applicable Balls Symbol Parameter Conditions CK77,CK51, CK38, CK19, SYNC8K, CKPDH5, CKPDH4, CKPDH3, CKPDH2, CKPDH1, INT[6, 5, 3, 0] tRISE tFALL Rise Time, 20% to 80% Fall Time, 20% to 80% Load = 15 pF, 1k -- -- ps ps Table 18-5. LVPECL Output ac Timing Characteristics Applicable Balls Symbol Parameter Conditions PCK622P/N, PCK155P/N[1:0] SYPCLP/N[1:0] tRISE tFALL Rise Time, 20% to 80% Fall Time, 20% to 80% Load = 50 connected to VDD - 2.0 V Agere Systems Inc. Min Typ -- -- Max Unit ps ps 63 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer Data Sheet, Revision 1 August 26, 2003 19 Packaging Diagram 19.1 208-Plastic Ball Grid Array (17 x 17), 0.63 mm Ball Size (4-Layer--Bottom View) Dimensions are in millimeters. $%$// ,'(17,),(5=21( 6($7,1*3/$1( 62/'(5%$// 63$&(6# 7 5 3 1 0 / . - 63$&(6 # + * ) ( ' & % $ $%$// &251(5 64 5-7809.b (F) Agere Systems Inc. Data Sheet, Revision 1 August 26, 2003 TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer 20 Ordering Information Table 20-1. Ordering Information Device Code Package Temperature Comcode (Ordering Number) TSYN03622 208 PBGAM1 -40 C to +85 C 700034203 21 Revision History 21.1 Navigating Through an Adobe Acrobat (R) Document If the reader displays this document in Adobe Acrobat Reader (R), clicking on any blue entry in the text will bring the reader to that reference point. Clicking on the back arrow in Acrobat Reader, will bring the reader back to the starting point. 21.2 Changes Changes that were made to this document (since the June 20, 2003 issue) are listed below. On page 8: Figure 3-1 was updated to reflect LF0Z, LF[0:2]. SYCLKA was changed to SYCLK. On page 10: The entries for Table 4-1, Ball Assignments for 208-Ball PBGA by Ball Number Order, were reordered. Names for pins A2, A3, A14, and A15 were corrected. Pin name for H1 was changed from PCK622N to PCK622N1. On page 12: In Table 4-2, Physical Ball Orientation (Bumps Down), pin name for H1 was changed from PCK622N to the correct name: PCK622N1. On page 37: The first paragraph under Section 13.5, Interrupt Generation (INT[6, 5, 3, 0]), was updated. On page 57 Table 15-31, Sync Falling Edge Position, was updated. On page 63: In Table 18-3, CMOS Input ac Timing Characteristics, pin SYCLKA was changed to SYCLK. Agere Systems Inc. 65 For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755 25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems, the Agere logo, Ultramapper, Hypermapper, and Supermapper are trademarks of Agere Systems Inc. Copyright (c) 2003 Agere Systems Inc. All Rights Reserved August 26, 2003 DS03-130HSPL-1 (Replaces DS03-130HSPL)