TSYN03622 - Agere Systems, Inc. - Datasheet.Directory

Advisory

October 28, 2003

TSWC01622/TSWC02622/TSWC03622/TSYN01622/TSYN03622

Device Version 1.1 Advisory

The following data sheets are to be referenced:

■TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet (DS03-117HSPL-1).

■TSWC02622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet (DS03-118HSPL-1).

■TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch data sheet (DS03-120HSPL).

■TSYN01622 SONET/SDH/PDH/ATM Clock Synthesizer data sheet (DS03-119HSPL).

■TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer data sheet (DS03-130HSPL-1).

Note: Customers must check with their Agere representative for the current version of this advisory; this is a continuously

updated document.

1 TSWC01622 October 2002, Device Exceptions

1.1 Exception 1—Squelch Mode

Applies to TSWC01622, TSWC02622, TSWC03622, TSYN01622, and TSYN03622.

Active 622.08 MHz and 155.52 MHz LVDS clocks are not affected by the squelch signal; therefore, they are active outputs

and not held in a low state when ENSQLN is enabled and all clocks (CLKA, CLKB, and CLKBU) have a fault.

The LVPECL and CMOS outputs (including the LVPECL and CMOS sync outputs) are compatible with the data sheet re-

garding squelch and enable signals. The LVDS sync outputs are also compatible with the data sheet.

Workaround: No known workaround.

Corrective Action: None.

1.2 Exception 2—Switching Out of Backup Clock Mode in Autonomous Nonrevertive Mode

Applies to TSWC01622, TSWC02622, and TSWC03622.

In autonomous, nonrevertive mode, if the TSWC01622 switches to the backup clock, it will not switch back to clock A or

clock B should either of the two input clocks become valid.

Workaround: The device must be put into manual mode, and the appropriate input clock must be selected.

Corrective Action: None.

TSWC01622/TSWC02622/TSWC03622/TSYN01622/TSYN03622 Advisory

Device Version 1.1 Advisory October 28, 2003

22 Agere Systems Inc.

1.3 Exception 3—Backup Clock Input (CLKBU)

Applies to TSWC01622, TSWC02622, and TSWC03622.

The TSWC01622 may not provide precise phase and frequency lock to CLKBU when the backup clock is configured for a

rate greater than 8 kHz. The TSWC01622 does provide precise phase and frequency lock when an 8 kHz backup clock rate

is selected and an 8 kHz clock is applied to CLKBU.

When the backup clock rate is configured for rates other than 8 kHz and the selected rate is applied to CLKBU, the output

clocks of the TSWC01622 may not be in phase alignment with CLKBU. However, the average frequency of the TSWC01622

output clocks will be proportional to the input frequency. For example, if an input clock rate of 38.88 MHz + 10 ppm is applied

to CLKBU, the TSWC01622 CMOS output CK19 will be at 19.44 MHz + 10 ppm.

Workaround: Configure the TSWC01622 for a backup clock frequency of 8 kHz, and use a backup clock source of 8 kHz.

Corrective Action: None.

1.4 Exception 4—Writing Registers Using the Serial Interface

Applies to TSWC01622, TSWC02622, TSWC03622, TSYN01622, and TSYN03622.

Occasionally, when executing a serial interface write operation, the write operation is not successful.

Workaround: Two means can be applied as follows:

After performing a write operation, perform a read operation and examine the register contents to which the write operation

was intended. If the value contained in the register is incorrect, perform an additional write and read operation to verify reg-

ister contents.

Always perform two consecutive write operations to the same register without an intervening command. Two consecutive

write operations have been verified to completely eliminate the occasional write operation error.

Corrective Action: There is no additional corrective action deemed necessary for this issue as the work around completely

eliminates this issue.

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere is a registered trademark of Agere Systems Inc. Agere Systems, the Agere logo, Ultramapper, Hypermapper, and Supermapper are trademarks of Agere Systems Inc.

October 28, 2003

AY04-001HSPL (Replaces AY02-036HSPL, must accompany DS03-117HSPL-1, DS03-118HSPL-1, DS03-119HSPL,

DS03-120HSPL, and DS03-130HSPL-1)

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 755 25881122 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

EUROPE: Tel. (44) 1344 296 400

Data Sheet, Revision 1

August 26, 2003

TSYN03622 SONET/SDH/PDH/ATM

Clock Synthesizer

1 Introduction

The last issue of this data sheet was June 20, 2003. A revi-

sion history is included in 21 Revision History on page 65.

Red change bars have been installed on all text, figures,

and tables that were added or changed. All changes to the

text are highlighted in red. Changes within figures, and the

figure title itself, are highlighted in red, if feasible. Format-

ting or grammatical changes have not been highlighted.

Deleted sections, paragraphs, figures, or tables will be spe-

cifically mentioned.

Throughout this document references are made to the fol-

lowing application notes:

■TSWC01622 Power Supply Grouping and Filtering.

■Clock Requirements for the TSWC03622/TSYN03622

Devices for Ultramapper ™ Family Devices.

■TSWC01622/TSYN01622 Loop Filters: Compatible

Components.

The application notes can be obtained by contacting the

Agere representative, or accessing the web at:

http://www.agere.com/enterprise_metro_access/

system_timing_devices.html

1.1 Features

■Same functionality as TSWC01622 with looser jitter

specifications

■Fully integrated clock synthesis

■Supports a wide choice of SONET/SDH output clock fre-

quencies with jitter quality up to OC-12:

622.08 MHz 155.52 MHz 77.76 MHz

51.84 MHz 44.736 MHz 38.88 MHz

34.368 MHz 32.768 MHz 24.704 MHz

19.44 MHz 16.384 MHz 8.192 MHz

4.096 MHz 2.43 MHz 2.048 MHz

1.544 MHz

■Five frequency programmable clock outputs

■Supports multiple input clock frequencies:

51.84 MHz 38.88 MHz 19.44 MHz

8.192 MHz 6.48 MHz 2.048 MHz

1.544MHz 8kHz

■Generates sync outputs at 8 kHz aligned to an 8 kHz

input clock signal

■Low skew clock distribution balls

■Compatible with Agere Systems Inc. TDAT04622/

TADM04622 SONET/ATM/POS devices, STSI-144,

TSI-16, TSI-8, TMXF84622 Ultramapper, and

TMXF28155 Supermapper

■Single 3.3 V supply

■Multiple output technologies—CMOS, LVPECL, or LVDS

■Programmable via external balls or internal registers via

serial interface

1.2 Applications

■SONET/SDH and PDH add/drop multiplexers, cross con-

nects, switches, and routers

■Remote access servers

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

Table of Contents

Contents Page

22 Agere Systems Inc.

1 Introduction .........................................................................................................................................................................1

1.1 Features ......................................................................................................................................................................1

1.2 Applications .................................................................................................................................................................1

2 Description ..........................................................................................................................................................................7

3 Block Diagram ....................................................................................................................................................................8

4 Pin Information ...................................................................................................................................................................9

5 Functional Overview .........................................................................................................................................................17

6 Input Clock Specifications ................................................................................................................................................18

6.1 Input Clock Stability Requirements ............................................................................................................................18

6.2 Input Frequency Selection (FINSEL[3:0]) ..................................................................................................................18

6.3 Input Electrical Level Selection for Clock Input Signal (SELLVDS) ...........................................................................18

6.4 Input Clock Minimum Pulse-Width Specifications .....................................................................................................18

6.4.1 Input Clock Minimum Pulse Width ...................................................................................................................18

6.5 Input Sync Signal Functionality .................................................................................................................................18

7 Output Clock Specifications ..............................................................................................................................................19

7.1 Available Output Clocks ............................................................................................................................................19

8 Jitter Specifications ...........................................................................................................................................................21

9 Synchronization Output at 8 kHz ......................................................................................................................................23

9.1 Sync Output (SYNC8K, SYLVSP/N[1:0], SYPCLKP/N[1:0]) .....................................................................................23

9.2 Sync Duty Cycle Selection (SYDU) ...........................................................................................................................23

9.3 Sync Alignment ..........................................................................................................................................................23

9.4 Offset Programming (SYOFF[9:0], SYOFFPOS) ......................................................................................................23

10 Skew Specifications ........................................................................................................................................................25

11 Output Specifications During Phase-Locked Condition (Nontransient Condition) ..........................................................30

11.1 Maximum Time Interval Error (MTIE) Specifications ...............................................................................................30

11.2 Time Deviation (TDEV) Specifications ....................................................................................................................32

12 Other Input and PLL Specifications ................................................................................................................................34

12.1 Input Clock Maximum Rate of Phase Change During Transient .............................................................................34

12.2 External 38.88 MHz VCXO Requirements ..............................................................................................................34

12.3 Loop Filter Components for High-Speed PLL ..........................................................................................................35

12.4 Loop Filter Components for Low-Speed PLL ..........................................................................................................35

12.5 INLOSN ...................................................................................................................................................................36

12.6 RREF .......................................................................................................................................................................36

13 State Machine and Software Interface ...........................................................................................................................37

13.1 State Machine Behavior ..........................................................................................................................................37

13.2 Squelch ....................................................................................................................................................................37

13.3 Software Interfacing .................................................................................................................................................37

13.4 Loss of Clock Criteria ..............................................................................................................................................37

13.5 Interrupt Generation (INT[6, 5, 3, 0]) .......................................................................................................................37

14 Serial Interface and Internal Bus ....................................................................................................................................38

15 TSYN03622 Registers Map ............................................................................................................................................40

15.1 Control Block Registers ...........................................................................................................................................42

15.2 Input Clock Block Registers .....................................................................................................................................43

15.3 State Machine Block Registers ................................................................................................................................45

15.4 PDH Output Block Registers ...................................................................................................................................46

15.4.1 Fractional Dividers Registers: 40h—66h ........................................................................................................46

15.5 General Configuration Registers 80h—83h .............................................................................................................46

15.6 SDH/Sync Generation Block Registers ...................................................................................................................50

15.7 LVPECL Output Syncs and Clocks .........................................................................................................................54

15.8 CMOS Output Syncs and Clocks ............................................................................................................................54

15.9 LVDS Output Syncs and Clocks ..............................................................................................................................55

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Table of Contents (continued)

Contents Page

Agere Systems Inc. 3

16 Absolute Maximum Ratings ............................................................................................................................................60

16.1 Handling Precautions ..............................................................................................................................................60

16.2 Operating Conditions ...............................................................................................................................................60

16.3 Powerup Conditions ................................................................................................................................................60

17 Electrical Characteristics ................................................................................................................................................61

17.1 LVPECL, LVDS, CMOS, Input and Output Balls .....................................................................................................61

18 Timing Characteristics ....................................................................................................................................................63

19 Packaging Diagram ........................................................................................................................................................64

19.1 208-Plastic Ball Grid Array (17 x 17), 0.63 mm Ball Size (4-Layer—Bottom View) .................................................64

20 Ordering Information .......................................................................................................................................................65

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

Table of Contents (continued)

Figures Page

44 Agere Systems Inc.

Figure 3-1. TSYN03622 Block Diagram .................................................................................................................................8

Figure 4-1. TSYN03622 208-Ball PBGA (Top View) ..............................................................................................................9

Figure 6-1. Input Clock Minimum Pulse-Width Requirement................................................................................................18

Figure 8-1. Phase Noise Characteristic for Differential Output Clock CK51 Using LSPLL Filter..........................................22

Figure 8-2. Phase Noise Characteristic for Differential Output Clock CK77 Using LSPLL Filter..........................................22

Figure 10-1. PECL Sync to PECL Clock Skew Case: Syncs Aligned to 622 MHz Clock .....................................................25

Figure 10-2. PECL Sync to PECL Clock Skew Case, Sync Aligned to 155 MHz Clock.......................................................26

Figure 10-3. LVDS Sync to LVDS Clock Skew Case, Sync Aligned to 622 MHz Clock.......................................................27

Figure 10-4. LVDS Sync to LVDS Clock Skew Case, Sync Aligned to 155 MHz Clock.......................................................28

Figure 10-5. CMOS Sync to CMOS Clock Skew Case, Sync Aligned to SONET CMOS Output Clock ..............................29

Figure 11-1. MTIE Wander Generation in Locked Condition................................................................................................30

Figure 11-2. Measured MTIE Wander Generation Performance..........................................................................................31

Figure 11-3. Wander Generation in Locked Condition .........................................................................................................32

Figure 11-4. Measured TDEV Wander Generation Performance.........................................................................................33

Figure 12-1. Recommended High-Speed Loop Filter Circuit................................................................................................35

Figure 12-2. Recommended Low-Speed Phase-Lock Loop (LSPLL) Filter Circuit for Smaller Phase Offsets ....................36

Figure 14-1. TSYN03622 Serial Interface ............................................................................................................................38

Figure 14-2. Serial Interface WRITE Frame Format.............................................................................................................38

Figure 14-3. Serial Interface READ Frame Format ..............................................................................................................38

Figure 14-4. Serial Interface Timing .....................................................................................................................................39

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Table of Contents (continued)

Tables Page

Agere Systems Inc. 5

Table 4-1. Ball Assignments for 208-Ball PBGA by Ball Number Order ...............................................................................10

Table 4-2. Physical Ball Orientation (Bumps Down) .............................................................................................................12

Table 4-3. Clock Inputs and Related Signal..........................................................................................................................13

Table 4-4. Analog and PLL Related Signals .........................................................................................................................13

Table 4-5. Output Clocks and Related Signals .....................................................................................................................14

Table 4-6. Control and Related Signals ................................................................................................................................15

Table 4-7. Serial Interface Signals........................................................................................................................................15

Table 4-8. Test and Reserved Signals ..................................................................................................................................15

Table 4-9. No-Connect Signals.............................................................................................................................................16

Table 4-10. Power Signals....................................................................................................................................................16

Table 6-1. Input Clock Frequency Selection .........................................................................................................................18

Table 7-1. SDH Output Clock Selection (SDHSEL[3:0]).......................................................................................................20

Table 7-2. PDH Output Clock Selection (PDHSEL[3:0]).......................................................................................................20

Table 8-1. Output Clock Jitter Specifications ........................................................................................................................21

Table 9-1. Sync Duty Cycle Selection (SYDU) .....................................................................................................................23

Table 9-2. SYNC Offset Programming..................................................................................................................................24

Table 9-3. Enhanced SYNC Offset Programming ................................................................................................................24

Table 10-1. PECL Sync to PECL Clock Skew Parameters (Single Clock Pulse Sync Output Shown) ................................25

Table 10-2. PECL Sync to PECL Clock Skew Parameters (Single Clock Pulse Sync Output Shown) ................................26

Table 10-3. LVDS Sync to LVDS Clock Skew Parameters (Single Clock Pulse Sync Output Shown) .................................27

Table 10-4. LVDS Sync to LVDS Clock Skew Parameters (Single Clock Pulse Sync Output Shown) .................................28

Table 10-5. CMOS Sync to CMOS Clock Skew Parameters (15 pF, 1 kΩ) ..........................................................................29

Table 11-1. Wander Generation (Nontransient)—MTIE ........................................................................................................30

Table 11-2. Wander Generation (Nontransient)—TDEV.......................................................................................................32

Table 12-1. Recommended High-Speed Loop Filter Values.................................................................................................35

Table 12-2. Recommended Low-Speed Loop Filter Values for Smaller Phase Offsets........................................................35

Table 13-1. Interrupt Generation (INT[6, 5, 3, 0]) Active-High ..............................................................................................37

Table 14-1. Serial Interface Timing.......................................................................................................................................39

Table 15-1. TSYN03622 Registers .......................................................................................................................................40

Table 15-2. Hardware Reset for All TSYN03622 Blocks ......................................................................................................42

Table 15-3. Software Override..............................................................................................................................................43

Table 15-4. Loss of Clock Block Software Override and Reset ............................................................................................43

Table 15-5. FINSEL[3:0] Register.........................................................................................................................................44

Table 15-6. Loss of Clock Threshold ....................................................................................................................................44

Table 15-7. Loss of Clock Hysteresis ...................................................................................................................................44

Table 15-8. State Machine Block Control Register ...............................................................................................................45

Table 15-9. State Machine Block State Machine Register....................................................................................................45

Table 15-10. Squelch............................................................................................................................................................46

Table 15-11. PDH Control Register 1 ...................................................................................................................................46

Table 15-12. PDH Clock Outputs for the 16 Preset Configurations (Bit 81h[3] = 0) .............................................................47

Table 15-13. PDH Control Register 2 ...................................................................................................................................48

Table 15-14. Enhanced Software Mode Fractional Divider Selection...................................................................................48

Table 15-15. Software Mode Fractional Divider Selection....................................................................................................49

Table 15-16. Fractional Dividers Operation Mode ................................................................................................................49

Table 15-17. SDH/Sync Control Register .............................................................................................................................50

Table 15-18. SDHSEL Register ............................................................................................................................................51

Table 15-19. Sync Duty Cycle ..............................................................................................................................................51

Table 15-20. Output Syncs Duty Cycle.................................................................................................................................51

Table 15-21. Sync Offset ......................................................................................................................................................51

Table 15-22. Sync Source ....................................................................................................................................................52

Table 15-23. SONET/SDH Clock Enable..............................................................................................................................53

Table 15-24. LVPECL Output Clock Output Status when Influenced by Programmable Duty Cycle on Syncs....................54

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

Table of Contents (continued)

Tables Page

66 Agere Systems Inc.

Table 15-25. LVPECL Output Clock Output Status when Influenced by Programmable Duty Cycle on Syncs....................54

Table 15-26. LVDS Output Clock Output Status when Influenced by Programmable Duty Cycle on Syncs ........................55

Table 15-27. Sync Duty Cycle ..............................................................................................................................................55

Table 15-28. CMOS SONET Clock Edge Selection .............................................................................................................56

Table 15-29. Enhanced Sync Offset .....................................................................................................................................56

Table 15-30. Sync Rising Edge Position...............................................................................................................................57

Table 15-31. Sync Falling Edge Position ..............................................................................................................................57

Table 15-32. Sync Delta .......................................................................................................................................................58

Table 15-33. Sync Delta Rise ...............................................................................................................................................58

Table 15-34. Interrupt Status Register..................................................................................................................................59

Table 16-1. Absolute Maximum Ratings ...............................................................................................................................60

Table 16-2. Handling Precautions.........................................................................................................................................60

Table 16-3. Recommended Operation Conditions................................................................................................................60

Table 17-1. LVDS Output dc Characteristics ........................................................................................................................61

Table 17-2. LVDS Input dc Characteristics ...........................................................................................................................61

Table 17-3. CMOS Input dc Characteristics .........................................................................................................................62

Table 17-4. CMOS Output dc Characteristics.......................................................................................................................62

Table 17-5. LVPECL Output dc Characteristics....................................................................................................................62

Table 18-1. LVDS Input ac Timing Characteristics ...............................................................................................................63

Table 18-2. LVDS Output ac Timing Characteristics.............................................................................................................63

Table 18-3. CMOS Input ac Timing Characteristics..............................................................................................................63

Table 18-4. CMOS Output ac Timing Characteristics ...........................................................................................................63

Table 18-5. LVPECL Output ac Timing Characteristics ........................................................................................................63

Table 20-1. Ordering Information..........................................................................................................................................65

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 7

2 Description

The Agere Systems TSYN03622 is designed for a wide variety of synchronous timing applications. It serves as a clock syn-

thesizer and low skew clock fan-out device generating clocks at frequencies up to 622.08 MHz that are synchronized to the

system reference clock. The TSYN03622 also delivers an output sync signal that is aligned to the input clock. If 8 kHz sys-

tem sync signals are applied as the clock input, the TSYN03622 will generate an output sync signal that is phase aligned to

the selected input sync. A programmable phase offset is provided to allow the user to offset the output sync relative to the

input sync. The output sync can be used for global alignment of cells or frames in SONET/SDH/PDH cross connects or

ATM switch applications. The device allows flexible choices of LVDS or LVCMOS input technologies and LVDS, LVPECL,

or LVCMOS output technologies.

The TSYN03622 can be programmed via external balls, or through a serial interface. Enhanced functionality is available

through the serial interface including, programmable clock outputs through fractional synthesis, and the ability to enable or

disable each output individually.

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

88 Agere Systems Inc.

3 Block Diagram

Note: The magenta portions of the figure indicate test features.

Figure 3-1. TSYN03622 Block Diagram

SDHSEL[3:0]

CK19

CK38

CK51

CK77

CK155N[1:0]

CK155P[1:0]

PCK155N[1:0]

PCK155P[1:0]

CK622N

CK622P

PCK622N

PCK622P

SYPCLN[1:0]

SYPCLP[1:0]

SYLVSN[1:0]

SYLVSP[1:0]

SYNC8K

SYDU

SYOFFPOS

SYOFF[9:0]

TSTCLKN

TSTCLKP

VC[P:N]

LF[P:N]

INLOSN

LSVCO

LF[2:0]

RREF

DIVIDE

LOC38

DIVIDE

SYNC

OFFSET

BASED ON SDHSEL

SONET

CLOCK

GEN.

DIVIDE

VCO

CONTROL

AND

STATE

MACHINE

PDH

CLOCK

GEN.

SERIAL I/F

CONTROL

LOC

DIV_M

CLKP

CLKN

CLK

SELLVDS

FINSEL[3:0]

ENSQLN

RESETN

INT[6,5,3,0]

CKPDH5

CKPDH4

CKPDH3

CKPDH2

CKPDH1

PDHSEL[3:0]

TSTMODE

SERCLK

SERENBLN

SERDAT

ENTSTCLK

VCXO

38.88 MHz

SYCLK

ENABLE/

DISABLE LF0Z

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 9

4 Pin Information

2360 (F)

Figure 4-1. TSYN03622 208-Ball PBGA (Top View)

234 67891011121314151615

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

1010 Agere Systems Inc.

4.1 Pin Assignments

Table 4-1. Ball Assignments for 208-Ball PBGA by Ball Number Order

Note: — refers to no ball. NC means do not connect any traces to this solder ball.

Ball Signal Name

A1 GND

A2 CK155N0

A3 CK155P0

A4 GND

A5 SYLVSN0

A6 SYLVSP0

A7 GND

A8 CK622N

A9 CK622P

A10 GND

A11 SYLVSN1

A12 SYLVSP1

A13 GND

A14 CK155N1

A15 CK155P1

A16 GND

B1 PCK155N0

B2 CK19

B3 VDDPDH

B4 CKPDH2

B5 VDDPDH

B6 GND

B7 GND

B8 GND

B9 GND

B10 GND

B11 GND

B12 GND

B13 GND

B14 SYOFF6

B15 TSTMODE

B16 TSTCLKP

C1 PCK155P0

C2 CK38

C3 CKPDH1

C4 CKPDH3

C5 CKPDH5

C6 VDDLVDS

C7 GND

C8 GND

C9 GND

C10 GND

C11 VDDSDH

C12 SYOFF2

C13 SYOFF5

C14 SYOFF8

C15 VDDTCLK

C16 TSTCLKN

D1 VDDPECL

D2 VDDSDH

D3 GND

D4 GND

D5 CKPDH4

D6 VDDPDH

D7 VDDLVDS

D8 RREF

D9 VDDLVDS

D10 SYOFF0

D11 SYOFF1

D12 SYOFF3

D13 SYOFF4

D14 SYOFF7

D15 SYDU

D16 GND

Ball Signal Name

E1 SYPCLN0

E2 FINSEL0

E3 FINSEL3

E4 SYNC8K

E5 —

E6 —

E7 —

E8 —

E9 —

E10 —

E11 —

E12 —

E13 SYOFF9

E14 VDDHSPD

E15 VDDLSVCO

E16 LSVCO

F1 SYPCLP0

F2 VDDPECL

F3 GND

F4 CK51

F5 —

F6 —

F7 —

F8 —

F9 —

F10 —

F11 —

F12 —

F13 SYOFFPOS

F14 VDDHSPD

F15 VDDHSVCO

F16 GND

Ball Signal Name

G1 VDDPECL

G2 VDDPECL

G3 VDDPECL

G4 CK77

G5 —

G6 —

G7 GND

G8 GND

G9 GND

G10 GND

G11 —

G12 —

G13 NC

G14 INLOSN

G15 LFN

G16 VCN

H1 PCK622N1

H2 VDDPECL

H3 FINSEL2

H4 FINSEL1

H5 —

H6 —

H7 GND

H8 GND

H9 GND

H10 GND

H11 —

H12 —

H13 GND

H14 GND

H15 LFP

H16 VCP

Ball Signal Name

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 11

Table 4-1. Ball Assignments for 208-Ball PBGA by Ball Number Order (continued)

Note: — refers to no ball. NC means do not connect any traces to this solder ball.

Ball Signal Name

J1 PCK622P

J2 VDDPECL

J3 VDDPECL

J4 GND

J5 —

J6 —

J7 GND

J8 GND

J9 GND

J10 GND

J11 —

J12 —

J13 GND

J14 VDDHSDIV

J15 VDDHSVCO

J16 NC

K1 VDDPECL

K2 VDDPECL

K3 GND

K4 SDHSEL2

K5 —

K6 —

K7 GND

K8 GND

K9 GND

K10 GND

K11 —

K12 —

K13 NC

K14 VDDHSDIV

K15 LF0Z

K16 NC

Ball Signal Name

L1 SYPCLN1

L2 SDHSEL0

L3 SDHSEL3

L4 SDHSEL1

L5 —

L6 —

L7 —

L8 —

L9 —

L10 —

L11 —

L12 —

L13 NC

L14 NC

L15 NC

L16 NC

M1 SYPCLP1

M2 VDDCNTL

M3 VDDCNTL

M4 SDH_HW

M5 —

M6 —

M7 —

M8 —

M9 —

M10 —

M11 —

M12 —

M13 GND

M14 NC

M15 NC

M16 NC

Ball Signal Name

N1 VDDPECL

N2 SERDAT

N3 SERENBLN

N4 GND

N5 NC

N6 INT5

N7 NC

N8 VDDFF

N9 NC

N10 INT0

N11 NC

N12 SELLVDS

N13 GND

N14 ENSQLN

N15 RESETN

N16 SWCONTN

P1 PCK155N1

P2 PDHSEL3

P3 PDHSEL2

P4 GND

P5 GND

P6 INT6

P7 NC

P8 NC

P9 VDDFF

P10 SYCLK

P11 MON8K

P12 NC

P13 NC

P14 VDDLSPLL

P15 VDDLSPLL

P16 VDDCNTL

Ball Signal Name

R1 PCK155P1

R2 SERCLK

R3 GND

R4 GND

R5 PDHSEL0

R6 NC

R7 INT3

R8 GND

R9 GND

R10 NC

R11 GND

R12 NC

R13 GND

R14 GND

R15 GND

R16 GND

T1 VDDPECL

T2 VDDCLKBU

T3 NC

T4 PDHSEL1

T5 GND

T6 NC

T7 NC

T8 NC

T9 GND

T10 CLKP

T11 CLKN

T12 CLK

T13 GND

T14 LF2

T15 LF1

T16 LF0

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

1212 Agere Systems Inc.

4.2 Physical Pin Orientation

Table 4-2. Physical Ball Orientation (Bumps Down)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

AGND CK155N0 CK155P0 GND SYLVSN0 SYLVSP0 GND CK622N CK622P GND SYLVSN1 SYLVSP1 GND CK155N1 CK155P1 GND

BPCK155N0 CK19 VDDPDH CKPDH2 VDDPDH GND GND GND GND GND GND GND GND SYOFF6 TSTMODE TSTCLKP

CPCK155P0 CK38 CKPDH1 CKPDH3 CKPDH5 VDDLVDS GND GND GND GND VDDSDH SYOFF2 SYOFF5 SYOFF8 VDDTCLK TSTCLKN

DVDDPECL VDDSDH GND GND CKPDH4 VDDPDH VDDLVDS RREF VDDLVDS SYOFF0 SYOFF1 SYOFF3 SYOFF4 SYOFF7 SYDU GND

ESYPCLN0 FINSEL0 FINSEL3 SYNC8K — — — — — — — — SYOFF9 VDDHSPD VDDLSVCO LSVCO

FSYPCLP0 VDDPECL GND CK51 — — — — — — — — SYOFFPOS VDDHSPD VDDHSVCO GND

GVDDPECL VDDPECL VDDPECL CK77 — — GND GND GND GND — — NC INLOSN LFN VCN

HPCK622N1 VDDPECL FINSEL2 FINSEL1 — — GND GND GND GND — — GND GND LFP VCP

JPCK622P VDDPECL VDDPECL GND — — GND GND GND GND — — GND VDDHSDIV VDDHSVCO NC

KVDDPECL VDDPECL GND SDHSEL2 — — GND GND GND GND — — NC VDDHSDIV LF0Z NC

LSYPCLN1 SDHSEL0 SDHSEL3 SDHSEL1 — — — — — — — — NC NC NC NC

MSYPCLP1 VDDCNTL VDDCNTL SDH_HW — — — — — — — — GND NC NC NC

NVDDPECL SERDAT SERENBLN GND NC INT5 NC VDDFF NC INT0 NC SELLVDS GND ENSQLN RESETN SWCONTN

PPCK155N1 PDHSEL3 PDHSEL2 GND GND INT6 NC NC VDDFF SYCLK MON8K NC NC VDDLSPLL VDDLSPLL VDDCNTL

RPCK155P1 SERCLK GND GND PDHSEL0 NC INT3 GND GND NC GND NC GND GND GND GND

TVDDPECL VDDCLKBU NC PDHSEL1 GND NC NC NC GND CLKP CLKN CLK GND LF2 LF1 LF0

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 13

* Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

* Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

Table 4-3. Clock Inputs and Related Signal

Ball Symbol*Type†Level Name/Description

T10,

T11

CLKP

CLKN

IDLVDS Input Clock. Used when LVDS level is desired for interfacing to

input clock source.

T12 CLK IDCMOS Input Clock. Used when CMOS level is desired for interfacing to

input clock source.

N12 SELLVDS IUCMOS Select Clock Level (LVDS/CMOS). Selects the LVDS or the

CMOS input balls as the clock source:

0 = CMOS (CLK).

1 or no connection = LVDS (CLKP/N).

E3, H3, H4, E2 FINSEL[3:0] IUCMOS Input Frequency Select. Program to indicate the input frequency

of the clock source.

P10 SYCLK IDCMOS Sync Input. CMOS synchronization input used to align output

8 kHz syncs to a system synchronization signal.

Table 4-4. Analog and PLL Related Signals

Ball Symbol*Type†Level Name/Description

E16 LSVCO ICMOS 38.88 MHz VCXO. Connection to external VCXO output.

T14, T15 LF2, LF1 Analog —Connect to Ground.

T16 LF0 Analog —38.88 MHz PLL Loop Filter.

K15 LF0Z IUCMOS 38.88 MHz PLL Loop Filter Enable. CMOS logic-high enables LF0.

CMOS logic low sets output LF0 to high-impedance state.

H15,

G15

LFP

LFN

Analog —High-Speed PLL Loop Filter. Connect to external loop filter compo-

nents and also connect LFP to VCP and LFN to VCN.

H16,

G16

VCP

VCN

Analog —High-Speed VCO Control Voltage. Connect to external loop filter

components and connect VCP to LFP and VCN to LFN.

G14 INLOSN IUCMOS Input Loss of Signal. Active-low input signal forces control voltage on

high-speed oscillator to the lowest end of the oscillator frequency

range:

0 = force lowest-frequency operation in high-speed oscillator.

1 or no connection = normal operation.

D8 RREF Analog —Resistor Reference. LVDS output voltage reference resistor. Insert a

1.5 kΩ resistor from RREF to VDDLVDS.

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

1414 Agere Systems Inc.

* Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

Table 4-5. Output Clocks and Related Signals

Ball Symbol*Type†Level Name/Description

A9,

CK622P

CK622N

OLVDS 622.08 MHz Output Clock.

J1,

PCK622P

PCK622N

OLVPECL 622.08 MHz Output Clock.

A15, A3,

A14, A2

CK155P[1:0]

CK155N[1:0]

OLVDS 155.52 MHz Output Clock.

R1, C1,

P1, B1

PCK155P[1:0]

PCK155N[1:0]

OLVPECL 155.52 MHz Output Clock.

G4 CK77 OCMOS 77.76 MHz Output Clock.

F4 CK51 OCMOS 51.84 MHz Output Clock.

C2 CK38 OCMOS 38.88 MHz Output Clock.

B2 CK19 OCMOS 19.44 MHz Output Clock.

L3, K4, L4, L2 SDHSEL[3:0] IDCMOS SDH Clock Output Selection.

E4 SYNC8K OCMOS 8 kHz Output Sync.

A12, A6,

A11, A5

SYLVSP[1:0]

SYLVSN[1:0]

OLVDS 8 kHz Sync Buffers [1:0].

M1, F1,

L1, E1

SYPCLP[1:0]

SYPCLN[1:0]

OLVPECL 8 kHz Sync Buffers [1:0].

E13, C14, D14, B14,

C13, D13, D12, C12,

D11, D10

SYOFF[9:0] IDCMOS Sync Offset. Programs the magnitude of the offset of the

output syncs relative to an input 8 kHz clock/sync.

F13 SYOFFPOS IUCMOS Sync Offset Positive or Negative. Selects the direction of

the sync offset:

1 = positive offset. The output sync is delayed in time.

0 = negative offset. The output sync is advanced in time.

D15 SYDU IUCMOS Sync Duty Cycle. Selects the duty cycle of the output sync

signals:

1 = 50% duty cycle.

0 = sync logic high time equal to one period of the highest-

frequency active SONET output clock.

C5 CKPDH5 OCMOS Selectable PDH Output Clock.

D5 CKPDH4 OCMOS Selectable PDH Output Clock.

C4 CKPDH3 OCMOS Selectable PDH Output Clock.

B4 CKPDH2 OCMOS Selectable PDH Output Clock.

C3 CKPDH1 OCMOS Selectable PDH Output Clock.

P2, P3, T4, R5 PDHSEL[3:0] IDCMOS PDH Clock Output Selection.

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 15

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

* Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

Table 4-6. Control and Related Signals

Ball Symbol*Type †Level Name/Description

N16 SWCONTN IUCMOS Software Control. Active-low signal, used with ENSQLN for output squelch

control. See ENSQLN.

0 = software control is enabled. Device is in manual switching mode and,

when instructed, switches to a clock even if it is in a loss of clock state.

(Overrides AUTOSWN setting.)

1 = software control is disabled. User cannot switch to a clock in a loss of

clock state.

N14 ENSQLN IUCMOS Enable Squelch. Active-low signal enables automatic squelching of the

clock and sync outputs whenever a fault is encountered. When squelching

occurs, all output clock and sync signals will be held at a logic-low output

level.

If the device is not in software control mode (SWCONTN = 1), the outputs

will be squelched if squelch is enabled and input clock is lost:

1 = automatic squelching of the outputs is disabled.

0 = automatic squelching of the outputs is enabled.

If the device is in the software override mode (SWCONTN = 0), then

ENSQLN can be used to manually squelch the device clock outputs:

1 = normal device clock output operation.

0 = manually squelch the device clock outputs.

N15 RESETN IUCMOS Reset. Active-low asynchronous reset.

P6, N6, R7,

N10

INT[6, 5, 3, 0] OCMOS Interrupts. Active-high interrupts define fault conditions. See Table 13-1 on

page 37 for individual interrupt definitions.

Table 4-7. Serial Interface Signals

Ball Symbol*Type†Level Name/Description

R2 SERCLK IUCMOS Serial Interface Clock. Serial interface clock that can operate up to 25 MHz.

N3 SERENBLN IUCMOS Serial Interface Enable. This signal must be low during register access.

N2 SERDAT I/OUCMOS Serial Data. This is a bidirectional ball for writing and reading software registers.

Table 4-8. Test and Reserved Signals

Ball Symbol*Type†Level Name/Description

B15 TSTMODE IDCMOS Test Mode. Internal test observation signal used in test mode. Do not connect or

apply any signal to this ball.

B16,

C16

TSTCLKP

TSTCLKN

IDLVDS Test Clock Input. Do not connect or apply any signal to these balls.

P11 MON8K OCMOS Monitor 8 kHz from Input Clock. Internal test observation signal. Do not connect

or apply any signal to this ball. (If input clock is setup and applied correctly, this sig-

nal should measure exactly 8 kHz.)

M4 SDH_HW IDCMOS Internal Signal. Internal test signal. Do not connect or apply any signal to this ball.

(When set to a CMOS logic high, the SDH block takes information directly from the

external leads and does not use information from the internal bus (registers).)

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

1616 Agere Systems Inc.

Table 4-9. No-Connect Signals

Ball Symbol Type Level Name/Description

G13, J16, K13, K16, L13, L14, L15, L16, M14, M15, M16, N5, N7, N9,

N11, P7, P8, P12, P13, R6, R10, R12, T3, T6, T7, T8

NC — — Not connected.

Table 4-10. Power Signals

For information on power supply grouping and filtering, refer to Application Note: TSWC01622 Power Supply Grouping and

Filtering.

Ball Symbol Type Level Name/Description

C11, D2 VDDSDH Power — —

D1, F2, G1, G2, G3, H2, J2, J3, K1, K2, N1, T1 VDDPECL Power — —

D9, C6, D7 VDDLVDS Power — —

M2, M3, P16 VDDCNTL Power — —

T2 VDDCLKBU Power — —

N8, P9 VDDFF Power — —

P14, P15 VDDLSPLL Power — —

K14, J14 VDDHSDIV Power — —

J15, F15 VDDHSVCO Power — —

E15 VDDLSVCO Power — —

E14, F14 VDDHSPD Power — —

D6, B5, B3 VDDPDH Power — —

C15 VDDTCLK Power — —

A1, A4, A7, A10, A13, A16, B6, B7, B8, B9, B10, B11, B12, B13,

C7, C8, C9, C10, D3, D4, D16, F3, F16, G7, G8, G9, G10, H7,

H8, H9, H10, H13, H14, J4, J7, J8, J9, J10, J13, K3, K7, K8, K9,

K10, M13, N4, N13, P4, P5, R3, R4, R8, R9, R11, R13, R14,

R15, R16, T5, T9, T13

GND Ground — —

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 17

5 Functional Overview

The TSYN03622 is designed to manage clock generation and timing distribution in SONET/SDH compliant line card solu-

tions up to OC-12 data rates. The TSYN03622’s output clocks are designed to meet relevant output clock jitter generation

specifications and maximum time interval error (MTIE). It supports a range of common input frequencies from 8 kHz to

51.84 MHz. An integrated digital state machine monitors the presence of the input clock signal. Programming of the

TSYN03622 can be accomplished through external ball control or through internal registers via a serial interface. A range

of SONET and PDH clock frequencies are generated with 155 MHz and 622 MHz clocks available on multiple low-skew

LVDS and LVPECL output buffers in order to provide fan-out and clock distribution sources for multiple chips within the sys-

tem. An 8 kHz sync signal with a user-programmable offset is generated and is available on CMOS, LVDS, and LVPECL

output buffers. The duty cycle of the 8 kHz output sync signal is selectable as either 50% or as the width of a single clock

pulse determined by the maximum selected SONET/SDH related output frequency.

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

1818 Agere Systems Inc.

6 Input Clock Specifications

6.1 Input Clock Stability Requirements

The clock input to the TSYN03622 must be compliant with all requirements for a SONET minimum clock (SMC) as defined

in Telcordia™ GR-253-CORE Section 5.4.4.2 (Issue 3, 9/2000), or for an ITU node clock as defined in G.812, in order for

the TSYN03622 to meet its output clock specifications.

6.2 Input Frequency Selection (FINSEL[3:0])

The input clock signal frequencies that are supported on the clock input, as well as the appropriate frequency selection

control ball programming, are given in Table 6-1. Input frequency selection can be performed using external balls

FINSEL[3:0] or by programming register 0x21 bits 3:0 (with SDH_HW ball low).

6.3 Input Electrical Level Selection for Clock Input Signal (SELLVDS)

When SELLVDS = 0, the CLK CMOS level input buffer is selected as the clock inputs. When SELLVDS = 1 (or no connec-

tion is made to the SELLVDS ball), the CLKP/N LVDS level input buffers are selected as the clock input.

6.4 Input Clock Minimum Pulse-Width Specifications

In order for the TSYN03622 to guarantee functionality, the input clock must maintain a minimum pulse width of

tPW = 8 ns for an input frequency of 8 kHz, for input frequencies less than 8 kHz, a 50% ± 5% duty cycle is required, as

shown in Figure 6-1.

6.4.1 Input Clock Minimum Pulse Width

Figure 6-1. Input Clock Minimum Pulse-Width Requirement

6.5 Input Sync Signal Functionality

If an 8 kHz (or a slower multiple of 8 kHz) is input, then the 8 kHz output signals (SYNC8K, SYLVSP/N[1:0], and

SYPLP/N[1:0]) will be aligned to the active SYCLK with a small phase offset due to the delay through the chip.

Table 6-1. Input Clock Frequency Selection

Input Clock Frequency FINSEL3 FINSEL2 FINSEL1 FINSEL0

8kHz NC 0 0 0

1.544 MHz NC 0 0 1

2.048 MHz NC 0 1 0

6.480 MHz NC 0 1 1

8.192 MHz NC 1 0 0

19.44 MHz NC 1 0 1

38.88 MHz NC 1 1 0

51.84 MHz NC 1 1 1

CLOCK INPUT

tPW

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 19

7 Output Clock Specifications

7.1 Available Output Clocks

The TSYN03622 supports the generation of the SONET/SDH and PDH frequencies given in Table 8-1, as well as the ability

to program frequency output rates up to 65.536 MHz on CKPDH[1:3] and 38.88 MHz on CKPDH[4:5], using fractional syn-

thesis. Not all PDH frequencies listed in Table 8-1 are available simultaneously. Table 7-1 and Ta b l e 7 - 2 illustrate the com-

bination of output clock frequencies available simultaneously based on the PDHSEL[3:0] and SDHSEL[3:0] control words.

There are several levels of programming the PDH1—PDH5 outputs. The PDHSEL[3:0] control word can be programmed

using external balls PDHSEL[3:0] (with mode bits 0x81 bits 4:3 set to 00, which is the default state) or by programming reg-

ister 0x80 bits 15:12 (with mode bits 0x81 bits 4:3 set to 10). Additionally, each PDH output can be programmed individually

using registers 0x82 and 0x83 (with mode bits 0x81 bits 4:3 set to 01 or 11). If the mode for any PDH output is set to

0B1110, then any frequency can be programmed to the output, up to 65.536 MHz on CKPDH[1:3] and 38.88 MHz on

CKPDH[4:5], using the outputs respective registers in the range 0x40 to 0x66. To program these registers, please contact

Agere to get an automated program that provides programming instructions based on the desired frequency output.

The SDHSEL[3:0] control word can be programmed using external balls SDHSEL[3:0] or by programming register 0xA1

bits 3:0 (with 0xA0 bit 1 high and SDH_HW ball low). Individual SONET/SDH output syncs and clocks can also be enabled

or disabled individually using registers 0xA4 and 0xA5 respectively. Additionally, the CK77, CK51, CK38, and CK19 clocks

can be aligned such that either the positive or the negative edge is aligned to an input 8 kHz signal using register 0xA7

(with 0xA0 bits 1 and 2 low).

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

2020 Agere Systems Inc.

* Z = high impedance.

† If SYDU = 0, duty cycle = 50%. If SYDU = 1, sync logic high time equal to one period of a 155.52 MHz clock (6.43 ns).

‡ If SYDU = 0, duty cycle = 50%. If SYDU = 1, sync logic high time equal to one period of a 622.08 MHz clock (1.6075 ns).

*Z = high impedance.

Table 7-1. SDH Output Clock Selection (SDHSEL[3:0])

Clock/Sync

Output Name

SDHSEL[3:0] State Value and Associated Output Signals*

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CK622P/N Z622.08

MHz

622.08

MHz

Z622.08

MHz

Z622.08

MHz

Z Z Z Z Z Z Z Z Z

PCK622P/N Z622.08

MHz

Z622.08

MHz

Z622.08

MHz

0 Z 622.08

MHz

Z Z Z Z Z Z Z

CK155P/N[1] 155.52

MHz

ZZZ155.52

MHz

Z Z 155.52

MHz

Z Z Z Z Z Z Z Z

CK155P/N[0] 155.52

MHz

Z155.52

MHz

Z155.52

MHz

Z Z 155.52

MHz

Z Z Z Z Z Z Z Z

PCK155P/N[1] 155.52

MHz

155.52

MHz

Z Z Z 155.52

MHz

ZZZ155.52

MHz

Z Z Z Z Z Z

PCK155P/N[0] 155.52

MHz

155.52

MHz

Z155.52

MHz

Z155.52

MHz

ZZZ155.52

MHz

Z Z Z Z Z Z

CK77 Z77.76

MHz

ZZZZZZZZ77.76

MHz

77.76

MHz

Z Z Z Z

CK51 51.84

MHz

ZZZZZZZZZ51.84

MHz

Z51.84

MHz

Z Z Z

CK38 ZZZZZZZZZZ38.88

MHz

Z Z 38.88

MHz

Z Z

CK19 19.44

MHz

ZZZZZZZZZ19.44

MHz

Z Z Z 19.44

MHz

SYNC8K Z8.0 kHz ZZZZZZZZ8.0

kHz

8.0

kHz

8.0

kHz

8.0

kHz

8.0

kHz

SYLVSP/N[1] 8.0 kHz†Z8.0 kHz‡Z8.0 kHz†Z Z 8.0 kHz†Z Z Z Z Z Z Z Z

SYLVSP/N[0] 8.0 kHz†8.0 kHz‡8.0 kHz†Z8.0 kHz†Z8.0 kHz‡8.0 kHz†Z Z Z Z Z Z Z Z

SYPCLP/N[1] Z8.0 kHz†Z8.0 kHz‡Z8.0 kHz†ZZZ8.0 kHz†Z Z Z Z Z Z

SYPCLP/N[0] 8.0 kHz†8.0 kHz†Z8.0 kHz†Z8.0 kHz†Z Z 8.0 kHz‡8.0 kHz†Z Z Z Z Z Z

Table 7-2. PDH Output Clock Selection (PDHSEL[3:0])

Clock/Sync

Output Name

PDHSEL[3:0] State Value and Associated Output Signals*

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CKPDH5 2.43

MHz

Z1.544

MHz

1.544

MHz

ZZZ2.43

MHz

ZZZZZZZZ

CKPDH4 1.544

MHz

Z2.048

MHz

2.048

MHz

1.544

MHz

1.544

MHz

Z Z Z Z Z Z Z Z Z Z

CKPDH3 2.048

MHz

Z24.704

MHz

24.704

MHz

2.048

MHz

Z2.048

MHz

Z4.096

MHz

8.192

MHz

Z Z Z Z Z Z

CKPDH2 32.768

MHz

Z32.768

MHz

32.768

MHz

Z Z Z Z Z Z 16.384

MHz

Z32.768

MHz

Z Z Z

CKPDH1 44.736

MHz

Z34.368

MHz

44.736

MHz

ZZZZZZZ24.704

MHz

Z34.368

MHz

44.736

MHz

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 21

8 Jitter Specifications

The clock frequencies listed in Table 8-1 are normally available at their respective output balls under the indicated condi-

tions. The jitter specifications are met if the input clock complies with the input clock stability requirements. For representa-

tive jitter measurements for the CKPDH1—CKPDH5 outputs when used with the Agere Systems TMXF84622 device,

consult the Clock Requirements for the TSWC03622/TSYN03622 Devices for Ultramapper Family Devices Application

Note.

* CK19 and CK38 signals are divided down from the CK77 output and have similar phase noise (jitter) performance to that of the CK77 output.

† For applications requiring lower generated jitter, please contact the Agere Systems representative.

Table 8-1. Output Clock Jitter Specifications

Parameter Ball Output

Frequency

Typ (RMS Only) Max Unit Measurement

Bandwidth

Jitter

Generation

CK19 19.44 MHz — —* — —

CK38 38.88 MHz — —* — —

CK51 51.84 MHz 0.03 (See Figure 8-1.) <0.2

<2.0

mUIRMS

mUIp-p

12 kHz—40 kHz (OC-1)

0.06 (See Figure 8-1.) <0.4

<4.0

mUIRMS

mUIp-p

12 kHz—400 kHz (OC-1)

0.05 (See Figure 8-1.) <0.4

<4.0

mUIRMS

mUIp-p

12 kHz—130 kHz (OC-3)

0.11 (See Figure 8-1.) <0.6

<6.0

mUIRMS

mUIp-p

12 kHz—1.3 MHz (OC-3)

CK77 77.76 MHz 0.09 (See Figure 8-2.) <0.3

<3.0

mUIRMS

mUIp-p

12 kHz—500 kHz (OC-12)

0.20 (See Figure 8-2.) <0.625

<6.25

mUIRMS

mUIp-p

12 kHz—5 MHz (OC-12)

CK155P/N,

PCK155P/N

155.52 MHz —<0.6

<6.0

mUIRMS

mUIp-p

12 kHz—130 kHz (OC-3)

—<1.0†

<10†

mUIRMS

mUIp-p

12 kHz—1.3 MHz (OC-3)

CK622P/N,

PCK622P/N

622.08 MHz 0.7 <1.8†

<18†

mUIRMS

mUIp-p

12 kHz—500 kHz (OC-12)

1.2 <2.0†

<20†

mUIRMS

mUIp-p

12 kHz—5 MHz (OC-12)

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

2222 Agere Systems Inc.

Figure 8-1. Phase Noise Characteristic for Differential Output Clock CK51 Using LSPLL Filter

Figure 8-2. Phase Noise Characteristic for Differential Output Clock CK77 Using LSPLL Filter

Note: See Figure 12-2 for LSPLL filter diagram.

-140

-130

-120

-110

-100

-90

-80

1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07

FREQUENCY FROM CARRIER (Hz)

SSB MAGNITUDE (dBc/Hz)

-140

-130

-120

-110

-100

-90

-80

1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07

FREQUENCY FROM CARRIER(dBc/Hz)

SSB MAGNITUDE (dBc/Hz)

FREQUENCY FROM CARRIER (dBc/Hz)

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

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Agere Systems Inc. 23

9 Synchronization Output at 8 kHz

9.1 Sync Output (SYNC8K, SYLVSP/N[1:0], SYPCLKP/N[1:0])

The TSYN03622 generates an output 8 kHz synchronization signal for use in frame and cell alignment in systems that

require this capability. Typically, the output sync is meaningful only in systems that distribute 8 kHz synchronization signals

as the timing references on the clock input. In these cases, the alignment of the output sync to the input sync (8 kHz on the

clock input) is a critical aspect of system synchronization. When higher-speed clocks are distributed, the alignment of the

sync with respect to the input clock becomes arbitrary. Sync outputs can be configured along with the SONET/SDH clock

outputs with the SDHSEL[3:0] control word. The SDHSEL[3:0] control word can be programmed using external balls

SDHSEL[3:0] or by programming register 0xA1 bits 3:0 (with 0xA0 bit 1 high and SDH_HW ball low). Individual SONET/

SDH output syncs can also be enabled or disabled individually using register 0xA4.

9.2 Sync Duty Cycle Selection (SYDU)

There are several methods of controlling the sync output duty cycle. The first method is used with the SDHSEL[3:0] output

frequency. In this method, the duty cycle of the 8 kHz sync signals is selectable as either 50% or as the width of a single

SONET clock pulse width. When the duty cycle is selected to be a single clock pulse width, the pulse width of the respec-

tive sync signal is determined to be equal to one period of the highest-frequency active SONET output of similar output

technology type (for example, the CMOS SYNC8K output will have the pulse width of the highest-frequency active SONET

CMOS output). The frequencies of the active PDH clocks are not considered. Sync duty cycle selection can be performed

using external ball SYDU or by programming register 0xA2 bit 0 (with register 0xA0 bit 2 high and SDH_HW ball low).

A second method is used when the sync outputs are individually enabled through register 0xA4. In this method, pulse-width

options remain selectable as either 50% or as the width of a single SONET clock pulse width. Pulse widths are selected

using register 0xA4 in conjunction with register 0xA6.

The last method is to adjust the falling edge of the sync outputs using register 0xB2, which, in effect, adjusts the duty cycle.

(The rising edge can be adjusted using the sync offset programming explained below.)

9.3 Sync Alignment

When 8 kHz synchronization signals are applied as input timing on the clock input, the output sync is phase aligned to the

input sync. Adjustments of this delay may be made using the TSYN03622 sync offset programmability feature.

9.4 Offset Programming (SYOFF[9:0], SYOFFPOS)

Some system applications require the 8 kHz synchronization to be offset according to the demands of the system architec-

ture. The TSYN03622 provides the capability of offsetting the output sync in increments of 1.6075 ns (one 622.08 MHz

clock).

The sync offset will apply to all output syncs (SYN8K, SYLVSP/N[1:0], SYPCLP/N[1:0]) simultaneously. There are two

types of offset capability on the TSYN. The first has the capability to offset up to ±1.644 µs with a resolution of 1.6075 ns

(±1023 periods of a 622.08 MHz clock with a resolution of one period of the 622.08 MHz clock). This offset can be per-

formed using external balls SYOFF[9:0] and SYOFFPOS or by programming register 0xA3 bits 10:0 (with register 0xA0

bit 3 high and SDH_HW ball low). Programming of the sync offset is described in Ta b l e 9 - 2 .

Table 9-1. Sync Duty Cycle Selection (SYDU)

SYDU SYNC8K Duty Cycle

150%

0High for one period of highest-frequency active SONET clock output

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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2424 Agere Systems Inc.

The second type of sync offset is an enhanced capability that enables the sync to be offset over the entire 125 µs period (in

the same increments of 1.6075 ns). This is accomplished using 16 bits of offset and a positive/negative directional control.

This functionality is available by programming registers 0xA8 and 0xA9 (with register 0xA0 bit 3 low and SDH_HW ball

low). The programming is similar to the first offset type and is shown in Table 9-3. Note that there is a limit to the size of the

offset, so the offset is not greater than one 125 µs period.

Table 9-2. SYNC Offset Programming

Ball Function

SYOFF[9:0] Sets the magnitude of the sync offset value in increments of 1/622.08 MHz or 1.6075 ns:

SYOFF[9:0] = 0000000000 equals zero offset.

SYOFF[9:0] = 1111111111 equals 1.644 µs (1023/622.08 MHz) offset.

SYOFFPOS Sets the sign or direction of the sync offset:

SYOFFPOS = 1 is a positive offset. The output sync is delayed in time.

SYOFFPOS = 0 is a negative offset. The output sync is advanced in time.

Table 9-3. Enhanced SYNC Offset Programming

Ball Function

SYOFF[16:0] Sets the magnitude of the sync offset value in increments of 1/622.08 MHz or 1.6075 ns:

SYOFF[16:0] = 0 0000 0000 0000 0000 equals zero offset.

SYOFF[16:0] = 1 0010 1111 0110 0000 equals 125 µs (77760/622.08 MHz) offset.

SYOFFPOS Sets the sign or direction of the sync offset:

SYOFFPOS = 1 is a positive offset. The output sync is delayed in time.

SYOFFPOS = 0 is a negative offset. The output sync is advanced in time.

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

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10 Skew Specifications

2364 (F)

Figure 10-1. PECL Sync to PECL Clock Skew Case: Syncs Aligned to 622 MHz Clock

Table 10-1. PECL Sync to PECL Clock Skew Parameters (Single Clock Pulse Sync Output Shown)

Applicable

Balls

Symbol Skew Parameter Min Max Typ Unit

PCK622P/N

SYPCLP/N[1:0]

t100 Clock Falling to Sync Rising 00.5 0.235 ns

PCK622P/N t101/t103 Clock Duty Cycle 45 55 50 %

PCK622P/N

SYPCLP/N[1:0]

t102 Clock Falling to Sync Falling 00.5 0.220 ns

PCK622P/N

t100

SYPCLP/N[1:0]

t102

t103

t101

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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2365 (F)

Figure 10-2. PECL Sync to PECL Clock Skew Case, Sync Aligned to 155 MHz Clock

Table 10-2. PECL Sync to PECL Clock Skew Parameters (Single Clock Pulse Sync Output Shown)

Applicable

Balls

Symbol Skew Parameter Min Max Typ Unit

PCK155P/N[0]

SYPCLP/N[0]

t200 Clock Falling to Sync Rising –1.0 0–-0.735 ns

PCK155P/N[0] t201/t203 Clock Duty Cycle 45 55 50 %

PCK155P/N[0]

SYPCLP/N[0]

t202 Clock Falling to Sync Falling –1.0 0–0.745 ns

PCK155P/N[1]

SYPCLP/N[1]

t210 Clock Falling to Sync Rising –1.0 0–0.720 ns

PCK155P/N[1] t211/t213 Clock Duty Cycle 45 55 50 %

PCK155P/N[1]

SYPCLP/N[1]

t212 Clock Falling to Sync Falling –1.0 0–0.700 ns

PCK155P/N[0]

t200

SYPCLP/N[0]

t202

t203

t201

PCK155P/N[1]

t210

SYPCLP/N[1]

t212

t213

t211

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

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2366 (F)

Figure 10-3. LVDS Sync to LVDS Clock Skew Case, Sync Aligned to 622 MHz Clock

Table 10-3. LVDS Sync to LVDS Clock Skew Parameters (Single Clock Pulse Sync Output Shown)

Applicable

Balls

Symbol Skew Parameter Min Max Typ Unit

CK622P/N

SYLVSP/N[1:0]

t300 Clock Falling to Sync Rising 00.5 0.185 ns

CK622P/N t301/t303 Clock Duty Cycle 45 55 51 %

CK622P/N

SYLVSP/N[1:0]

t302 Clock Falling to Sync Falling 00.5 0.205 ns

CK622P/N

t300

SYLVSP/N[1:0]

t302

t303

t301

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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2828 Agere Systems Inc.

2367 (F)

Figure 10-4. LVDS Sync to LVDS Clock Skew Case, Sync Aligned to 155 MHz Clock

Table 10-4. LVDS Sync to LVDS Clock Skew Parameters (Single Clock Pulse Sync Output Shown)

Applicable

Balls

Symbol Skew Parameter Min Max Typ Unit

CK155P/N[0]

SYLVSP/N[0]

t400 Clock Falling to Sync Rising –1.0 0–0.745 ns

CK155P/N[0]

SYLVSP/N[0]

t402 Clock Falling to Sync Falling –1.0 0–0.750 ns

CK155P/N[1]

SYLVSP/N[1]

t410 Clock Falling to Sync Rising –1.0 0–0.725 ns

CK155P/N[1]

SYLVSP/N[1]

t412 Clock Falling to Sync Falling –1.0 0–0.745 ns

CK155P/N[0]

t400

SYLVSP/N[0]

t402

t403

t401

CK155P/N[1]

t410

SYLVSP/N[1]

t412

t413

t411

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

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Figure 10-5. CMOS Sync to CMOS Clock Skew Case, Sync Aligned to SONET CMOS Output Clock

Table 10-5. CMOS Sync to CMOS Clock Skew Parameters (15 pF, 1 kΩ)

A single clock pulse sync output is shown. The parameters in this table are not tested, but are a result of device character-

ization data.)

Applicable

Balls

Symbol Skew Parameter Min Max Typ Unit

CK19, SYNC8K t500 Clock Rising to Sync Rising –0.50 0.50 0.15 ns

CK19 t501/t503 Clock Duty Cycle — — — %

CK19, SYNC8K t502 Clock Rising to Sync Falling 0.00 1.50 0.80 ns

CK38, SYNC8K t500 Clock Rising to Sync Rising –0.50 0.50 0.05 ns

CK38 t501/t503 Clock Duty Cycle — — — %

CK38, SYNC8K t502 Clock Rising to Sync Falling 0.00 1.50 0.60 ns

CK51, SYNC8K t500 Clock Rising to Sync Rising –0.50 0.50 –0.05 ns

CK51 t501/t503 Clock Duty Cycle — — — %

CK51, SYNC8K t502 Clock Rising to Sync Falling 0.00 1.50 0.50 ns

CK77, SYNC8K t500 Clock Rising to Sync Rising –0.50 0.50 –0.20 ns

CK77 t501/t503 Clock Duty Cycle — — — %

CK77, SYNC8K t502 Clock Rising to Sync Falling 0.00 1.50 0.50 ns

t500

t502

t501

t503

CK19, CK38,

CK51, CK77

SYNC8K

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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11 Output Specifications During Phase-Locked Condition (Nontransient Condition)

11.1 Maximum Time Interval Error (MTIE) Specifications

During the phase-locked condition, the TSYN03622 output clocks will meet wander generation as given in Table 11-1 and

shown in Figure 11-1. When in the locked condition, the MTIE performance will be dominated by the MTIE of the incoming

timing-signals on the clock input. The TSYN03622 will not add significantly to the MTIE performance. Measured perfor-

mance is shown in Figure 11-2. Measured performance is shown in Figure 11-1.

2368 (F)

Figure 11-1. MTIE Wander Generation in Locked Condition

Table 11-1. Wander Generation (Nontransient)—MTIE

Observation Interval

(s)

TSYN03622 Max

(ns)

GR-253-CORE

Figure 5-17 (9/2000) (ns)

GR-1244-CORE

Figure 5-2 (6/95) (ns)

ITU-T

G.813 Option 2

Table 4 (8/96) (ns)

s < 0.1 NA NA NA NA

0.1 < s < 1.0 20 20 40 20

1 < s < 10 20 x s 0.48 20 x s 0.48 40 x s 0.40 20 x s 0.48

10 < s < 100 60 60 100 60

100 < s < 1000 60 —100 60

s > 1000 100 —100 —

100

1000

1 10 100 1000

0.1

OBSERVATION INTERVAL (s)

GR-253 CORE

ITU-T G.813 OPTION 2

GR-1244 CORE

MTIE (ns)

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

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Figure 11-2. Measured MTIE Wander Generation Performance

100

1000

0.01 0.10 1.00 10.00 100.00 1000.00

MTIE (ns)

Time (sec)

GR-253-CORE/ITU-T G.183 Opt 2

MTIE Requirement

Time (s)

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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11.2 Time Deviation (TDEV) Specifications

During the phase-locked condition, the TSYN03622 output clocks will meet TDEV as given in Table 11-2 and shown in

Figure 11-3. When in the locked condition, the TDEV performance will be dominated by the incoming timing signals on the

clock input and the TSYN03622 will not add significantly to the TDEV performance. Measured performance is shown in

Figure 11-4. Measured performance is shown in Figure 11-3.

2369 (F)

Figure 11-3. Wander Generation in Locked Condition

Table 11-2. Wander Generation (Nontransient)—TDEV

Integration Interval

(s)

TSYN03622 Max

(ns)

GR-253-CORE

Figure 5-18 (9/2000)

(ns)

GR-1244-CORE

Figure 5-1 (6/95)

(ns)

ITU-T

G.813 Option 2

Table 5 (8/96) (ns)

0.1 < τ < 2.5 3.2 x τ –0.5 3.2 x τ –0.5 3.2 x τ –0.5 3.2 x τ –0.5

2.5 < τ < 40 2 2 2 2

40 < τ < 1000 0.32 x τ 0.5 0.32 x τ 0.5 0.32 x τ 0.5 0.32 x τ 0.5

τ > 1000 10 10 10 —

1000 < τ < 10,000 10 — — 10

100

1 10 100 1000

0.1

OBSERVATION INTERVAL (s)

GR-253 CORE

TDEV (ns)

10000

ITU-T G.813 OPTION 2

AND GR-1244 CORE

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

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Figure 11-4. Measured TDEV Wander Generation Performance

0.01

0.1

100

0.1 1 10 100 1000 10000 100000

Observation Interval (s)

TDEV (ns)

GR-253-CORE/GR-1244-CORE/G.813 Opt. 2

TDEV Requirement

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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12 Other Input and PLL Specifications

12.1 Input Clock Maximum Rate of Phase Change During Transient

In order for the TSYN03622 to guarantee functionality and that all transient MTIE specifications are met, the clock input

must have an instantaneous maximum rate of change consistent with the ITU G.812 requirements for a node clock and

Telcordia GR-253-CORE Section 5.4.4.2 (Issue 3, 9/2000).

12.2 External 38.88 MHz VCXO Requirements

The following is a brief specification for the 38.88 MHz VCXO unit:

■Supply voltage: 3.30 V ± 5%

■Control voltage range: 0.3 V minimum, 2.7 V maximum

■Temperature range (ambient): –40 °C to +85 °C

■Output buffer:

— Technology: CMOS (3.30 V)

— Duty cycle: 45/55%

— Transient times: 1 ns maximum (20% to 80%)

■Frequency (nominal): 38.88 MHz

■APR: ± 20 ppm

Note: The APR must include the effects of temperature, supply voltage, shock, vibration, aging, and manufacturing (i.e.,

withstanding two solder reflows).

■Linearity: ±20% (best linear fit 0.3 V to 2.7 V)

■Transfer function: monotonic, positive slope

■Center voltage: VDD/2 (nominal 1.65 V)

■Modulation bandwidth: 10 kHz at 38.88 MHz

■Input leakage current: <1 µA

■Input resistance: >3 MΩ

■Reference signal for control voltage: ground

■Phase jitter: 1 ps (RMS) maximum 12 kHz to 20 MHz (alternate spec may be expressed in dBc if required)

■Start-up time: 2 ms at maximum control voltage

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

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12.3 Loop Filter Components for High-Speed PLL

The recommended loop filter is shown in Figure 12-1. Connect the filter components and also connect LFP to VCP and

connect LFN to VCN. The component values can be varied to adjust the loop dynamic response. Table 12-1 provides a set

of recommended values to meet output jitter generation requirements in Ta b l e 8 - 1 .

Figure 12-1. Recommended High-Speed Loop Filter Circuit

12.4 Loop Filter Components for Low-Speed PLL

The recommended loop filter for the low-speed PLL is shown in Figure 12-2 and Table 12-2. (This circuit can withstand an

instantaneous phase jump of up to ± 30 ns. If a larger phase jump could exist, please contact your Agere Systems repre-

sentative for more guidance. A smaller loop filter will be created in the future for conditions where there will be little or no

instantaneous phase jump.)

Analog switches are included in both circuits to reduce the lock time at start-up. The addition of the analog switch will

reduce the nominal lock time from tens of seconds to less than 6 s.

Note: For information on requirements for the various loop filter components and recommended solutions, consult the

TSWC01622/TSYN01622 Loop Filters: Compatible Components Application Note.

* Capacitors C1, C2, and C3 should be either ceramic or nonpolar.

† 1% resistors are recommended for R1 and R2, as the low-speed PLL filter has high sensitivity to these resistors. However, if these 1% resistors are not

available, the 5% resisters indicated in parentheses are compatible and will make the loop filter function correctly.

‡ For information on requirements for the various loop filter components and recommended solutions, consult the TSWC01622/TSYN01622 Loop Filters:

Compatible Components Application Note.

Table 12-1. Recommended High-Speed Loop Filter Values

Components Recommended Values

C1*

*. Capacitor C1 should be either ceramic or nonpolar.

0.1 µF to 1.0 µF ± 10%

R1 3.9 kΩ ± 5%

Table 12-2. Recommended Low-Speed Loop Filter Values for Smaller Phase Offsets

Components Recommended Values

C1* 10 µF ± 20%

C2, C3 * 4.7 µF ± 10%

R1†392 kΩ ± 1% (390 kΩ ± 5%)

R2†1.21 kΩ ± 1% (1.2 kΩ ± 5%)

R3 20 kΩ to 110 kΩ ± 5% (lower value yields faster lock time)

R4 383 kΩ ± 1% (390 kΩ ± 5%)

U1‡Analog switch

VCXO1 See VCXO requirements.

LFP

LFN

VCN

VCP

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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3636 Agere Systems Inc.

Figure 12-2. Recommended Low-Speed Phase-Lock Loop (LSPLL) Filter Circuit for Smaller Phase Offsets

12.5 INLOSN

The INLOSN signal will force the high-speed PLL to drift towards a lower clamped frequency, preventing an excessive high-

frequency clock output under invalid input signal conditions. INLOSN may be used to limit the internal clock frequency

ensuring proper state machine and control behavior under severe clock fault conditions.

12.6 RREF

RREF should be tied to VDDLVDS through a 1.5 kΩ resistor.

LF0

INT5

VCXO1

LSVCO

OUT

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

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13 State Machine and Software Interface

13.1 State Machine Behavior

The state machine of the TSYN03622 performs the following for control and monitoring purposes:

■Provides a squelch function to bring the device clock outputs to a logic low-state (squelched) if the clock input signal has

a fault.

■Provides an asynchronous reset.

■Provides a loss of clock interrupt.

■Provide loss of lock interrupts for the low-speed PLL and the high-speed PLL.

■Provides a loss of external VCXO clock interrupt.

13.2 Squelch

If the loss of clock interrupt goes active, the device will either do nothing or squelch the output clock and sync signals

depending on the ENSQLN condition. If ENSQLN is low, the device output clock and sync signals will be forced low.

13.3 Software Interfacing

The TSYN03622 is configured by an external controller via software. Whenever interaction with this software is needed, the

following guidelines should be followed:

■The software must provision the device as desired, appropriately setting ENSQLN upon powerup and after the initial

reset completes.

■The external controller may either use an active edge of one of the interrupts or a polling method (monitoring

INT[6, 5, 3, 0]) to determine the interrupt states.

13.4 Loss of Clock Criteria

Loss of clock detectors continuously monitor the condition of the input clock. A loss of clock condition is declared when

transitions are absent on the clock input for between 2 and 3 periods of the input frequency. This level is programmable via

13.5 Interrupt Generation (INT[6, 5, 3, 0])

Interrupts are available on external balls INT[6, 5, 3, 0] and via the serial interface in register 0xE0. Table 13-1 defines the

conditions under which interrupts are generated for the external balls INT[6, 5, 3, 0]. All of these interrupts are available in

Table 13-1. Interrupt Generation (INT[6, 5, 3, 0]) Active-High

INT Condition

6Loss of lock; high-speed PLL

5Loss of lock; 38.88 MHz PLL

3Loss of external VCXO clock

0Loss of CLK

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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14 Serial Interface and Internal Bus

The TSYN internal registers can be programmed via a serial interface. This serial interface allows reading or writing of any

of the registers. Internally, the TSYN uses two different lines to transmit and receive data from the outside. Those two lines

must be multiplexed by an input/output buffer to the single serial line (simplex communication). The serial line will be driven

by the external controller except when a read process is requested. In that case, the TSYN will drive the line during the time

it needs to transmit the requested data. During a period when no read or write process is requested, SERDAT is pulled

internally to a CMOS logic high. As shown on Figure 14-1, there are three external pins related to the serial interface: the

serial interface clock, SERCLK, the serial interface data line, SERDAT, and the serial interface enable, SERENBLN.

Figure 14-1. TSYN03622 Serial Interface

The serial interface frames are composed of 32 bits. The first 2 bits are used to indicate the beginning of the frame (01).

Then the address is transmitted in the next 8 bits, followed by 6 bits indicating if it is a read or write request. Finally, the

16 bits of data are transmitted by the external controller (write) or by the TSYN (read process). In case of a read process,

the last 17 bits of the frame are driven by the TSYN, following a bit where no device is driving the line, leaving it in high

impedance. As soon as the data has been transmitted, the external user continues to drive the line to a high-logic state

waiting for the next frame to transmit. A representation of a WRITE is shown in Figure 14-2 and a READ in Figure 14-3.

The transmission for both the data and address bits starts with the most significant bit.

Figure 14-2. Serial Interface WRITE Frame Format

Figure 14-3. Serial Interface READ Frame Format

EXTERNAL

CONTROLLER

INTERFACE

CONTROLLER

OUT

TSYN03622

SERDAT

SERCLK

SERENBLN

0 1 010010

SERDAT

SERCLK

SERENBLN

8-bit Address 16-bit Data

A7 A6 A5 A4 A3 A2 A0A1 D15 D14 D13 D12 D11 D10 D8D9 D7 D6 D5 D4 D3 D2 D0D10 1 010010

SERDAT

SERCLK

SERENBLN

8-bit Address 16-bit Data

A7 A6 A5 A4 A3 A2 A0A1 D15 D14 D13 D12 D11 D10 D8D9 D7 D6 D5 D4 D3 D2 D0D1

1 A7A6A5A4A3A2 A0A1 1000Z00

SERDAT

SERCLK

SERENBLN

8-bit Address 16-bit Data

Driven by External Controller Driven by TSWC01622

D15 D14 D13 D12 D11 D10 D8D9 D7 D6 D5 D4 D3 D2 D0D11 A7A6A5A4A3A2 A0A1 1000Z00

SERDAT

SERCLK

SERENBLN

8-bit Address 16-bit Data

Driven by External Controller Driven by TSWC01622

D15 D14 D13 D12 D11 D10 D8D9 D7 D6 D5 D4 D3 D2 D0D1

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

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Timing for the serial interface is shown in Figure 14-4. During a read, the address and read request bits are clocked on a

rising edge, and the data that is clocked out (by the TSWC) transitions off the clock's rising edge. The signal coming from

the TSWC, that is interpreting this serial stream, should use the following falling edge to avoid a race condition.

Figure 14-4. Serial Interface Timing

Note: The maximum serial interface clock frequency is 25 MHz and the minimum clock period is 40 ns.

Table 14-1. Serial Interface Timing

Applicable

Balls

Symbol Parameter Min Max Typ Unit

SERCLK FMAX Maximum Serial Interface Clock Frequency — 25 — MHz

SERENBLN

SERCLK

t500 Enable to Clock Setup — — — ns

SERCLK

SERDAT

t501 WRITE

Clock to Data Setup

–1.0 — — ns

SERDAT

SERCLK

t502 WRITE

Data Hold

3.6 — — ns

SERCLK

SERDAT

t501 READ

Clock to Data Setup

18 — — ns

SERDAT

SERCLK

t502 READ

Data Hold

———ns

SERCLK t503 Clock Period 40 — — ns

SERCLK

SERENBLN

t504 Enable Hold After Last Clock — — — ns

T => 40 nS

T/2

DATA EYE

CLOCK

T = 40 ns

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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15 TSYN03622 Registers Map

Table 15-1 summarizes all the TSYN registers.

Table 15-1. TSYN03622 Registers

Address

Hex

TSYN03622 Block Description Bits Reset

00 Control Reset register. 15:8 0xFFFF

01 Control Serial interface or pin control. 0 0xFFFF

02—1F — Not used. — —

20 Clock Input Software reset and software override. 1:0 0xFFFF

21 Clock Input FINSEL[3:0]. 3:0 0x000F

22 Clock Input Reserved. 3:0 0x000F

23 Clock Input Threshold. 15:0 0x0002

24 Clock Input For test purposes, set to 0x0002. 15:0 0x0002

25 Clock Input For test purposes, set to 0x0002. 15:0 0x0002

26 Clock Input For test purposes, set to 0x0002. 15:0 0x0002

27 Clock Input For test purposes, set to 0x0002. 15:0 0x0002

28 Clock Input For test purposes, set to 0x0003. 15:0 0x0003

29 Clock Input For test purposes, set to 0x0001. 15:0 0x0001

2A Clock Input For test purposes, set to 0x0001. 15:0 0x0001

2B Clock Input For test purposes, set to 0x0001. 15:0 0x0001

2C Clock Input For test purposes, set to 0x0001. 15:0 0x0001

2D Clock Input For test purposes, set to 0x0001. 15:0 0x0001

2E Clock Input Hysteresis. 15:0 0x0004

2F — Not used. — —

30 State Mach Software reset and software override. 8:0 0xFFFF

31 State Mach ENSQLN, SWCONTN. 7:0 0x00FF

32 State Mach Reserved. 15:0 0x0003

33 State Mach Reserved. 15:0 0x0800

34 State Mach Reserved. 15:0 0x4BEF

35—3F — Not used. — —

40 PDH Outputs Programmable output variable R0 for channel 1. 9:0 0x0000

41 PDH Outputs Programmable output variable R1 for channel 1. 9:0 0x0000

42 PDH Outputs Programmable output variable R2 for channel 1. 9:0 0x0000

43 PDH Outputs Programmable output variable R3 for channel 1. 9:0 0x0000

44 PDH Outputs Programmable output variable R4 for channel 1. 9:0 0x0000

45 PDH Outputs Programmable output variable R5 for channel 1. 9:0 0x0000

46 PDH Outputs Programmable output variable R6 for channel 1. 2:0 0x0000

47 — Not used. — —

48 PDH Outputs Programmable output variable R0 for channel 2. 9:0 0x0000

49 PDH Outputs Programmable output variable R1 for channel 2. 9:0 0x0000

4A PDH Outputs Programmable output variable R2 for channel 2. 9:0 0x0000

4B PDH Outputs Programmable output variable R3 for channel 2. 9:0 0x0000

4C PDH Outputs Programmable output variable R4 for channel 2. 9:0 0x0000

4D PDH Outputs Programmable output variable R5 for channel 2. 9:0 0x0000

4E PDH Outputs Programmable output variable R6 for channel 2. 2:0 0x0000

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 41

4F — Not used. — —

50 PDH Outputs Programmable output variable R0 for channel 3. 9:0 0x0000

51 PDH Outputs Programmable output variable R1 for channel 3. 9:0 0x0000

52 PDH Outputs Programmable output variable R2 for channel 3. 9:0 0x0000

53 PDH Outputs Programmable output variable R3 for channel 3. 9:0 0x0000

54 PDH Outputs Programmable output variable R4 for channel 3. 9:0 0x0000

55 PDH Outputs Programmable output variable R5 for channel 3. 9:0 0x0000

56 PDH Outputs Programmable output variable R6 for channel 3. 2:0 0x0000

57 — Not used. — —

58 PDH Outputs Programmable output variable R0 for channel 4. 9:0 0x0000

59 PDH Outputs Programmable output variable R1 for channel 4. 9:0 0x0000

5A PDH Outputs Programmable output variable R2 for channel 4. 9:0 0x0000

5B PDH Outputs Programmable output variable R3 for channel 4. 9:0 0x0000

5C PDH Outputs Programmable output variable R4 for channel 4. 9:0 0x0000

5D PDH Outputs Programmable output variable R5 for channel 4. 9:0 0x0000

5E PDH Outputs Programmable output variable R6 for channel 4. 2:0 0x0000

5F — Not used. — —

60 PDH Outputs Programmable output variable R0 for channel 5. 9:0 0x0000

61 PDH Outputs Programmable output variable R1 for channel 5. 9:0 0x0000

62 PDH Outputs Programmable output variable R2 for channel 5. 9:0 0x0000

63 PDH Outputs Programmable output variable R3 for channel 5. 9:0 0x0000

64 PDH Outputs Programmable output variable R4 for channel 5. 9:0 0x0000

65 PDH Outputs Programmable output variable R5 for channel 5. 9:0 0x0000

66 PDH Outputs Programmable output variable R6 for channel 5. 2:0 0x0000

67—7F — Not used. — —

80 PDH Outputs Mode (PDHSEL) and powerdown. 15:12,0 0x0001

81 PDH Outputs DIV2, CKMXSEL, MODESEL, and DELAY. 9:0 0x0000

82 PDH Outputs Modes for C0, C1, C2, and C3. 15:0 0x0000

83 PDH Outputs Modes for C4, C5, C6, and C7. 15:12 0x0000

84 PDH Outputs Reserved. — —

85 PDH Outputs Reserved. — —

86—9F — Not used. — —

A0 SDH/SYNC Outputs Software reset and overrides. 3:0 0x000F

A1 SDH/SYNC Outputs SDHSEL register. 3:0 0x0000

A2 SDH/SYNC Outputs Duty cycle register. 0 0x0001

A3 SDH/SYNC Outputs Sync offset and direction. 10:0 0x0000

A4 SDH/SYNC Outputs Sync enables. 11:0 0x0000

A5 SDH/SYNC Outputs Clock enables. 9:0 0x0000

A6 SDH/SYNC Outputs Individual duty cycle changes. 2:0 0x0007

A7 SDH/SYNC Outputs Clock edge selection. 3:0 0x000F

A8 SDH/SYNC Outputs Sync offset when software override. 15:0 0x0000

A9 SDH/SYNC Outputs Additional sync offset when software override. 1:0 0x0000

AA—AF — Not used. — —

B0 SDH/SYNC Outputs RISE[15:0]. 15:0 0x2FC0

Table 15-1. TSYN03622 Registers (continued)

Address

Hex

TSYN03622 Block Description Bits Reset

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

4242 Agere Systems Inc.

15.1 Control Block Registers

B1 SDH/SYNC Outputs RISE(16). 0 0x0001

B2 SDH/SYNC Outputs FALL. 15:0 0x97E0

B3 SDH/SYNC Outputs DELTA. 3:0 0x0016

B4 SDH/SYNC Outputs Not used. — 0x0016

B5 SDH/SYNC Outputs Not used. — 0x0016

B6 SDH/SYNC Outputs DELTARISE. 4:0 0x000B

B7 — Not used. — 0x0000

B8 SDH/SYNC Outputs For test purposes, read only. 0 0x0001

B9 SDH/SYNC Outputs For test purposes, read only. 15:0 0x2FAA

BA SDH/SYNC Outputs For test purposes, read only. 0 0x0000

BB SDH/SYNC Outputs For test purposes, read only. 15:0 0x97CA

BC—DF — Not used. — —

E0 Control Interrupt register. 8:0 0x0060

Table 15-2. Hardware Reset for All TSYN03622 Blocks

Address

(Hex)

Bit Name Description Reset Value

0x00 15 RHSLOLN High-speed PLL powerdown.

1 = Block active.

0 = Block powered down.

14 RLOSCLKN Loss of clock block powerdown.

1 = Block active.

0 = Block powered down.

13 RSWSTATN State machine powerdown.

1 = Block active.

0 = Block powered down.

12 RESETFFN Feed-forward counters powerdown.

1 = Block active.

0 = Block powered down.

11 RLSPLLN Low-speed PLL powerdown.

1 = Block active.

0 = Block powered down.

10 RSYNCN SDH/sync generation block powerdown.

1 = Block active.

0 = Block powered down.

9 RPDHCLKN PDH block powerdown.

1 = Block active.

0 = Block powered down.

8 RCONFIGN Control block reset.

1 = Block active.

0 = Block reset for one 155.52 MHz clock cycle.

7:0 — Unused: program to one. 00000000

Table 15-1. TSYN03622 Registers (continued)

Address

Hex

TSYN03622 Block Description Bits Reset

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 43

Register 00h contains power downs for all the TSYN blocks. Setting a bit to a low-level in this register will power down the

corresponding block. The block will remain powered down until the bit is again set to high, except for bit 00h(8), which

resets the control block only for one 155 MHz clock cycle. This register is initialized to all zeros, and bits 00h[7:0] are not

used. The reset register can be written at any time to reset a specific block, although the software reset implemented in

each block can also be used. After a general hardware reset, the control block will be setting the reset register bits to a high

level following a certain reset sequence. If a block is powered down and it is desired to power it up, a hardware reset is nec-

essary.

Register 01h contains the software override bit which must be set to low prior to any write operation. If bit 01h(0) is high, the

control block will not write any register except for 01h itself. This register is initialized to all ones, although bits 01h[15:1] are

not used, so right after initialization no write process is allowed. Bit 01h(0) must be set low.

15.2 Input Clock Block Registers

The loss of clock block monitors the input clock CLK and the 38.88 MHz clock generated by the external VCXO.

are active-low level, so register 20h is initialized to all ones if bit 20h(1) is low, the input clock block will be operating in soft-

ware mode, enabling all the programming capabilities and allowing access to the full flexibility of the block.

Table 15-3. Software Override

Address

(Hex)

Bit Name Description Reset

0x01 15:1 — Unused: program to one. 111111111111111

0 OVERRIDE Software override bit.

1 = Software programming disabled (hardware mode).

0 = Software programming enabled (software mode).

Table 15-4. Loss of Clock Block Software Override and Reset

Address

(Hex)

Bit Name Description Reset

20 15:2 — Unused: program to one. 11111111111111

1 SWOVRDN Reserved. 1

0 SWRSTN Input clock block powerdown.

1 = Block active.

0 = Block powered down.

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

4444 Agere Systems Inc.

must indicate the input clock frequency (FINSEL for CLK). This register is initialized to all ones. It can be written at any time

via serial interface (even in hardware mode). Only in hardware mode will any change in these registers reprogram the frac-

tional dividers by rewriting registers 24h—2Dh.

Register 23h is used to program the threshold time, which is the number of absent input cycles needed to raise the loss of

clock interrupt. This values is shared by all the loss of clock detectors. Register 23h can be written at any time (even in

hardware mode). The minimum value for this register is a value of 2. If a lower value is written, the threshold will be set to a

values of 2.

Register 2Eh is used to program the hysteresis time, which is the number of input clock cycles needed to erase the loss of

clock flag once the clock is back. This values is shared by all the loss of clock detectors. Register 2Eh can be written at any

time (even in hardware mode). The minimum value for this register is a value of 4. If a lower value is written, the hysteresis

will be set to a values of 4.

Table 15-5. FINSEL[3:0] Register

Address

(Hex)

Bit Name Description Reset

21 15:4 — Unused: program to one. 111111111111

3:0 FINSEL[3:0] Clock A and clock B input frequency select.

(Bit 3 is a don’t care).

1111, 0111 = 51.84 MHz.

1110, 0110 = 38.88 MHz.

1101, 0101 = 19.44 MHz.

1100, 0100 = 8.192 MHz.

1011, 0011 = 6.480 MHz.

1010, 0010 = 2.048 MHz.

1001, 0001 = 1.544 MHz.

1000, 0000 = 8 kHz.

1111

Table 15-6. Loss of Clock Threshold

Address (Hex) Bit Name Description Reset

23 15:0 THRESHOLD Loss of clock threshold value (number of missing consec-

utive clock cycles needed to trigger loss of clock interrupt).

0000000000000010

Table 15-7. Loss of Clock Hysteresis

Address (Hex) Bit Name Description Reset

2E 15:0 HYSTERESIS Loss of clock hysteresis value (number of consecutive clock

cycles needed to erase loss of clock interrupt, once clock is back).

00000000

00000100

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 45

15.3 State Machine Block Registers

The address space for the state machine control circuit is 30h—34h.

Bits 30h[8:3] are used for test purposes, and they must be high in normal operation mode, specially bit 30h[3], which is the

test mode bit.

Register 31h is initialized to all ones. Positions [15:8] will always read as zeros. This register is updated by the TSYN con-

trol block based on the input pins state, although they can also be modified via serial interface. This register will therefore

reflect the input pins with the same name given that the TSYN control block updates register 31h via internal bus. The

TSYN03622 will use the respective external balls for control when register 01h bit 0 is high, and it will use the configuration

from register 31h when register 01h bit 0 is low. All bits in register 31h are active-low.

Bit 31h[7] is the squelch enable ENSQLN. Setting this bit low, the SDH and PDH output clocks will be squelched if one of

the next conditions, in the table below, are met.

Table 15-8. State Machine Block Control Register

Address (Hex) Bit Name Description Reset

30 15:9 — Unused: program to ones. 1111111

8 Reserved For test purposes, set to 1. 1

7 Reserved For test purposes, set to 1. 1

6 LOCN For test purposes, set to 1. 1

5 Reserved For test purposes, set to 1. 1

4 BUSYN For test purposes, set to 1. 1

3 TESTN For test purposes, set to 1. 1

2 Reserved — 1

1 SWOVRDN Software override bit.

1 = Hardware mode (registers 32, 33, and 34 use their default values).

0 = Software mode (user can overwrite registers 32, 33, and 34).

0 SWRSTN State machine block software powerdown.

1 = Block active.

0 = State machine control circuits powered down except for micropro-

cessor interface.

Table 15-9. State Machine Block State Machine Register

Address (Hex) Bit Name Description Reset

31 15:8 — Unused. 00000000

7 ENSQLN Squelch enable.

1 = Squelch disabled.

0 = Squelch enabled. (Squelch active conditions are listed in

Table 15-10).

6 Reserved Reserved, set to 1. 1

5 Reserved Reserved, set to 1. 1

4 SWCONTN Software control. Used with ENSQLN for output squelch control.

See ENSQLN.

0 = Software control is enabled.

1 = Software control is disabled.

3 Reserved Reserved, set to 1. 1

2 Reserved Reserved, set to 1. 1

1 Reserved Reserved, set to 1. 1

0 Reserved Reserved, set to 1. 1

Conditions for use of this register: 01h(0) = 0.

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

4646 Agere Systems Inc.

As indicated in the previous table, when operating with SWCONTN = 0, the squelch enable is used to squelch the output

clocks, whereas for the other operation mode the squelch enable allows squelching when the special conditions are met.

15.4 PDH Output Block Registers

15.4.1 Fractional Dividers Registers: 40h—66h

The PDH fractional dividers enable each of the five PDH CMOS output clocks to be fully programmable. Registers

40h—66h contain the parameters to set the respective frequencies, setting the frequencies is enable in registers 80h—83h.

Each fractional divider includes seven registers. Those registers are located at consecutive addresses. The address of

each register can be specified by the base address of the corresponding fractional divider and the relative offset.

Base Address

Fractional divider 1 40h

Fractional divider 2 48h

Fractional divider 3 50h

Fractional divider 4 58h

Fractional divider 5 60h

To calculate the values for the respective dividers, a software program is available to automate the process. Please contact

your Agere Systems representative to get a copy of the program. All registers are initialized to all zeros at reset.

15.5 General Configuration Registers 80h—83h

Registers 80h—83h are the general configuration registers, which control the operation mode of the PDH block. The first

two registers 80h and 81h control the general behavior of the PDH block, whereas registers 82h and 83h control the five

fractional dividers used to generate the PDH rates.

Register 80h contains the software reset bit 80h(0) and the four PDHSEL[3:0] bits used to select one of the sixteen preset

configurations when 81h[4:3] = 10 (basic software control) generating the most needed PDH rates. Bit 80h[0] is the soft-

ware reset used to power down the PDH block except for the microprocessor used to read and write registers. The micro-

processor can only be reset by hardware reset. Register 80h is initialized with all bits low except for 80h(0), which is high.

Bits [10:1] can be written and read as they were written, but they are not used by the PDH block.

Table 15-10. Squelch

Mode of Operation Conditions Needed to Squelch the Output Clocks when ENSQLN = 0

SWCONTN = 1 The output clocks will be squelched if the input clock reference is lost (LOC = 1).

SWCONTN = 0 The output clocks will be squelched always if ENSQLN is low, no matter the conditions of the

input clocks are.

Table 15-11. PDH Control Register 1

Address

(Hex)

Bit Name Description Reset

80 15:12 PDHSEL Software PDH output clock select. See Table 15-12 for preset configura-

tions. To use this register, 81h(4:3) must be set to 10.

0000

11:1 — Reserved. 00000000000

0 SWRSTN PDH block software powerdown.

1 = Block active.

0 = PDH output block powered down except for microprocessor interface.

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 47

Table 15-12. PDH Clock Outputs for the 16 Preset Configurations (Bit 81h[3] = 0)

PDHSEL Clock 1 Clock 2 Clock 3 Clock 4 Clock 5

0000 Disabled

0001 44.736 MHz Disabled

0010 34.368 MHz Disabled

0011 Disabled 32.768 MHz Disabled

0100 24.704 MHz Disabled

0101 Disabled 16.384 MHz Disabled

0110 Disabled 8.192 MHz Disabled

0111 Disabled 4.096 MHz Disabled

1000 Disabled 2.43 MHz

1001 Disabled 2.048 MHz Disabled

1010 Disabled 1.544 MHz Disabled

1011 Disabled 2.048 MHz 1.544 MHz Disabled

1100 44.736 MHz 32.768 MHz 24.704 MHz 2.048 MHz 1.544 MHz

1101 34.368 MHz 32.768 MHz 24.704 MHz 2.048 MHz 1.544 MHz

1110 Disabled

1111 44.736 MHz 32.768 MHz 2.048 MHz 1.544 MHz 2.43 MHz

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

4848 Agere Systems Inc.

Registers 82h and 83h indicate the operation mode of each fractional divider when bit 81h[3] is high. There are 4 bits for

each fractional divider. These registers are reset to all zeros. Each fractional divider can be operated in sixteen different

modes. These modes are described in Table 15-15.

Table 15-13. PDH Control Register 2

Address

(Hex)

Bit Name Description Reset

81 15:10 — Reserved. 000000

9:8 DIV2N For Test Purposes Only. Program to 00. 00

7:5 CKMXSEL For Test Purposes Only. Program to 000. 000

4:3 MODESEL 00—Hardware control. This mode allows to control the PDH block through the

external PDHSEL[3:0] pins in case the TSYN control block fails. These pins

reach the PDH block, so the PDH block behavior is independent of the TSYN

control block. This mode offers 16 presets, which generate the most needed

PDH frequencies. Every one of those configurations programs each fractional

divider to work in one of the 16 modes listed in Table 15-15.

10—Basic software control. This mode is intended to be used in conjunction

with the TSYN control block. The PDH block operates in the same way as in

hardware control offering the same 16 presets, but this time instead of reading

the external pins directly, the four PDHSEL[3:0] bits are read from register 80h

(four most significant bits). This register is written by the control block at initial-

ization or when any change is made on the external pins, as the control block

monitors the external pins in a continuous basis. Register 80h can also be writ-

ten via serial interface (software override).

X1—Enhanced software control. This mode can only be used by program-

ming the PDH block via serial interface. This third alternative allows individual

selection of the operating mode for each fractional divider. Registers 82h and

83h contain the 20 bits needed to specify the operating mode for each of the

five fractional dividers (4 bits per fractional divider).

2:0 DELAY For Test Purpose Only. Program to 00. 000

Table 15-14. Enhanced Software Mode Fractional Divider Selection

Address

(Hex)

Bit Name Description Reset

82 15:12 FD 1 MODE PDH1 fractional divider mode, see text below and Table 15-15 to pro-

gram value.

0000

11:8 FD 2 MODE PDH2 fractional divider mode, see text below and Table 15-15 to pro-

gram value.

0000

7:4 FD 3 MODE PDH3 fractional divider mode, see text below and Table 15-15 to pro-

gram value.

0000

3:0 FD 4 MODE PDH4 fractional divider mode, see text below and Table 15-15 to pro-

gram value.

0000

83 15:12 FD 5 MODE PDH5 fractional divider mode, see text below and Table 15-15 to pro-

gram value.

0000

11:0 — Reserved. 000000000000

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 49

In mode 14, the fractional divider can be programmed through the registers located inside the fractional divider.

Fractional dividers 1—3 use the 622.08 MHz clock as input, where fractional dividers four and five use the 155.52 MHz

clock. Based on the previous table, the input frequency to each fractional divider and the division factor indicated in

Table 15-16, the sixteen presets will generate the output clocks (each clock is generated by the fractional divider with the

same number) shown in Table 15-12.

Table 15-16 summarizes the operation mode for the five fractional dividers when bit 80[3] is low. In that case, the PDH

block offers sixteen preset configurations that can be selected by the external pins (when 81h[4] = 0) or writing

Table 15-15. Software Mode Fractional Divider Selection

Mode Mode Bits [3:0] Divides By

0 0000 13 + 211/233

1 0001 18 + 18/179

2 0010 18 + 63/64

3 0011 25 + 35/193

4 0100 37 + 31/32

5 0101 75 + 15/16

6 0110 100 + 140/193

70111 64

8 1000 151 + 7/8

9 1001 303 + 3/4

10 1010 256

11 1011 402 + 174/193

12 1100 32

13 1101 Reserved

14 1110 Programmable

15 1111 Power down

Table 15-16. Fractional Dividers Operation Mode

This table shows the fractional dividers operation mode as a function of the external pins PDHSEL[3:0] or bits 80h[15:12]

(bit 81h[3] must be low).

PDHSEL[3:0] or Bits 80h[15:12] FD 1 FD 2 FD 3 FD 4 FD 5

0000 15 15 15 15 15

0001 0 15 15 15 15

0010 1 15 15 15 15

0011 15 2 15 15 15

0100 3 15 15 15 15

0101 15 4 15 15 15

0110 15 5 15 15 15

0111 15 15 8 15 15

1000 15 15 15 15 7

1001 15 15 9 15 15

1010 15 15 15 6 15

1011 15 15 9 6 15

1100 02356

1101 12356

1110 15 15 15 15 15

1111 0 2 9 6 7

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

5050 Agere Systems Inc.

15.6 SDH/Sync Generation Block Registers

Bit 0 is the software reset used to reset the SDH/sync block.

Bits 1, 2, and 3 are overrides (active-low level). When the SDH_HW pin is high, the values used as SDHSEL, DUTY, and

SYNCOFFSET are read from the external pins. When that pin is low, those values will be set via serial interface. If bits 1, 2,

and 3 are high, the values will be read from the same registers as if the TSYN was in pin control; that is, SDHSEL is stored

in register A1h, DUTY is in register A2h, and SYNCOFFSET is in register A3h.

When bit A0h(1) is low (SDH_HW = 0), the enables for the output clocks will be taken from register A5, which is a bit-to-

enable register.

If bit A0h(2) is low (SDH_HW = 0), the duty cycle is specified by register A6h, which allows different duty cycles for the

three kinds of output syncs.

Setting bit A0h(3) to a low level and SDH_HW = 0 allows the user to specify the offset in the output sync with registers A8h

and A9h. Those registers give a wider range to position the output sync than the external pins or register A3h. By using

these registers, the user may be able to place the output sync in any position of the 8 kHz cycle.

Table 15-17. SDH/Sync Control Register

Address

(Hex)

Bit Name Description Reset

A0 15:4 — Reserved. 000000000000

3 SYNC OFFSET OVERRIDE Sync offset override.

1 = Sync offset read from register A3h.

0 = Sync offset read from registers A8h and A9h (which

has a wider range than external pins, covering a

complete 8 kHz cycle).

Conditions for use of this feature: SDH_HW pin low.

2 DUTY CYCLE OVERRIDE Duty cycle override.

1 = Duty cycle read from register A2h.

0 = Duty cycle read from A6h (which allows for different

duty cycles for the three kinds of output syncs).

Conditions for use of this feature: SDH_HW pin low.

1 SDHSEL OVERRIDE SDHSEL override.

1 = Output clocks enables read from SDHSEL, read

from register A1h.

0 = Output clocks enables read from register A5h.

Conditions for use of this feature: SDH_HW pin low.

0 SRESETN SDH/Sync block software powerdown.

1 = Active.

0 = Powered down except for microprocessor interface.

Conditions for use of this feature: SDH_HW pin low.

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 51

This is the SDHSEL[3:0] register used to select one of the sixteen presets when the SDH_HW pin is low and bit A0h(1) is

high (basic software enables configuration). Each of the sixteen presets controls the clock and sync enables as the SDH-

SEL[3:0] external pins do when the SDH_HW pin is high. This register is initialized at 0000, selecting the preset number

zero, which disables all clock and sync outputs.

Register A2h is the duty cycle register, where bit A2h(0) is the duty cycle bit. A2h(0) is used to select the duty cycle of the

output syncs only when the SDH_HW pin is low and the duty cycle override bit A0h(2) is high (basic software duty cycle

configuration). It works as the external pin SYDU when pin SDH_HW is high. If the duty cycle bit is high, the duty cycle of

all output syncs will be 50%, although it can be programmed to take a different value through the algorithm control registers

B0h, B1h, and B2h. If the duty cycle bit is zero, each output sync will have the default pulse width, depending on the

selected sync for each output.

The duty cycle bit is initialized to one, so the output syncs will have 50% duty cycle.

This is the sync offset and direction register used in the same way as the external pins SYOFF[9:0] and SYOFFPOS. This

A3h[9:0] are the sync offset and bit A3h(10) is the direction. In order to get a positive delay, that is, to delay the output sync

with respect to the negative edge of the input sync, that bit, A3h(10), must be high. Register A3h is reset to all zero.

Table 15-18. SDHSEL Register

Address (Hex) Bit Name Description Reset

A1 15:4 — Reserved. 000000000000

3:0 SDHSEL SDH clock and sync selection.

See Table 7-1 on page 20.

Conditions for use of this feature: A0h(1) = 1 and SDH_HW pin low.

0000

Table 15-19. Sync Duty Cycle

Address (Hex) Bit Name Description Reset

A2 15:1 — Reserved. 000000000000000

0 Duty Cycle Sync duty cycle.

1 = 50%.

0 = Pulse width per conditions for use of this feature:

A0h(2) = 1 and SDH_HW pin low.

Table 15-20. Output Syncs Duty Cycle

Sync Output Pulse Width

PECL0/PECL1, LVDS0/LVDS1 One cycle of the 155 MHz or 622 MHz clock.

CMOS One cycle of the 77.76 MHz, 51.84 MHz, 38.88 MHz, or 19.44 MHz.

Table 15-21. Sync Offset

Address (Hex) Bit Name Description Reset

A3 15:11 — Reserved. 00000

10 SYOFFPOS Positive of negative offset bit.

1 = Positive.

0 = Negative.

Conditions for use of this feature: A0h(3) = 1 and SDH_HW pin low.

9:0 SYOFF Sync offset.

Value of this offset indicates number of 1/622.08 (~1.6) ns increments.

Conditions for use of this feature: A0h(3) = 1 and SDH_HW pin low.

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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5252 Agere Systems Inc.

* In Version 1.0 and 1.1 of the TSYN03622, there is an errata with bit 11 of register A4h. This register can be written, but does not respond correctly to a

read. When this bit is read, it will return a 0, regardless of the true value in the register.

This register is used with register A5h for enhanced software enables configuration, it will only be used when the SDH_HW

pin is low and bit A0h(1) is low (override enables). It controls the output sync enables, so it selects the output sync pulse

width when the duty cycle bit is low (not 50%). This register is initialized to zero.

Table 15-22. Sync Source

Address

(Hex)

Bit Name Description Reset

A4 15:12 — Reserved. 0000

11* SYPCL6221 LVPECL Sync Enable.

These registers [11:8] control the enables and sources of the LVPECL syncs. Bits

10 and 8 control SYPCLP/N[0] and bits 11 and 9 control

SYPCLP/N[1] as follows:

SYPCLP/N[0]

X0X0 = Disabled.

X0X1 = Enabled, pulse width based on SYNC155, as defined in A6h(1).

X1X0 = Enabled, pulse width based on SYNC622, as defined in A6h(0).

X1X1 = Disabled.

SYPCLP/N[0]

0X0X = Disabled.

0X1X = Enabled, pulse width based on SYNC155, as defined in A6h(1).

1X0X = Enabled, pulse width based on SYNC622, as defined in A6h(0).

1X1X = SYPCLP/N[1] disabled.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

10 SYPCL6220 0

9 SYPCL1551 0

8 SYPCL1550 0

7 SYNC8K78 CMOS Sync Enable.

These registers [7:4] control the enable and source of the CMOS sync. The pulse

width is based on A6h(2).

If A6h(2) is high, the pulse width is based on the configuration below.

0001, 0010, 0100, or 1000: pulse width is 50% of sync period.

Other = Disabled.

If A6h(2) is low, the pulse width is based on the configuration below.

0001 = One cycle of the 19.44 MHz clock.

0010 = One cycle of the 38.88 MHz clock.

0100 = One cycle of the 51.84 MHz clock.

1000 = One cycle of the 77.76 MHz clock.

Other = Disabled.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

6 SYNC8K51 0

5 SYNC8K38 0

4 SYNC8K19 0

3 SYLVS6221 LVDS sync enable.

These registers [3:0] control the enables and sources of the LVDS syncs. Bits 2

and 0 control SYLVSP/N[0], and bits 3 and 1 control SYLVSP/N[1] as follows:

SYLVSP/N[0]

X0X0 = Disabled.

X0X1 = Enabled, pulse width based on SYNC155, as defined in A6h(1).

X1X0 = Enabled, pulse width based on SYNC622, as defined in A6h(0).

X1X1 = Disabled.

SYLVSP/N[1]

0X0X = Disabled.

0X1X = Enabled, pulse width based on SYNC155, as defined in A6h(1).

1X0X = Enabled. pulse width based on SYNC622, as defined in A6h(0).

1X1X = Disabled.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

2 SYLVS6220 0

1 SYLVS1551 0

0 SYLVS1550 0

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

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This register controls the individual SDH clock enables when the SDH_HW pin is low and bit A0h(1) = 0 (enhanced soft-

ware enables configuration). A low-zero means that the corresponding output clock will be disabled.

Recall that regarding the 155.52 MHz and 622.08 MHz clocks, only the enable signals are generated by the SDH block.

The clocks are generated by other circuits external to the SDH block. Register A5h is initialized to zero (all clocks disabled).

When A0h[2] is low, the sync outputs (SYNC8K, SYPCL[1:0], and SYLVS[0:1]) duty cycles will be programmed from regis-

ters A4h and A6h. In register A6h, if any of the used bits are set low, then the pulse widths for the selected syncs will be set

by the respective control in register A4h. If a respective sync output is programmed to have a duty cycle less then 50% per

the previous conditions, then the clock outputs per Table 15-24 through Table 15-26 will be active, regardless of the clock

enable status in register A5h.

Table 15-23. SONET/SDH Clock Enable

Address

(Hex)

Bit Name Description Reset

A5 15:10 — Reserved. 000000

9 PECL622 Enable for the 622.08 MHz PECL differential output (PECL622).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

8 PECL1551 Enable for the 155.52 MHz PECL differential output (PECL1551).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

7 PECL1550 Enable for the 155.52 MHz PECL differential output (PECL1550).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

6 CK78 Enable for the 77.76 MHz single-ended CMOS output.

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

5 CK51 Enable for the 51.84 MHz single-ended CMOS output.

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

4 CK38 Enable for the 38.88 MHz single-ended CMOS output.

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

3 CK19 Enable for the 19.44 MHz single-ended CMOS output.

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

2 LVDS622 Enable for the 622.08 MHz LVDS differential output (LVDS622).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

1 LVDS1551 Enable for the 155.52 MHz LVDS differential output (LVDS1551).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

0 LVDS1550 Enable for the 155.52 MHz LVDS differential output (LVDS1550).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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5454 Agere Systems Inc.

15.7 LVPECL Output Syncs and Clocks

15.8 CMOS Output Syncs and Clocks

Table 15-24. LVPECL Output Clock Status when Influenced by Programmable Duty Cycle on Syncs

Setting in

Hex

Setting in Binary PCK155P/N0 PCK155P/N1 PCK622P/N

Bit 11 Bit 10 Bit 9 Bit 8

0 0 0 0 0 Set by A5h[7] Set by A5h[8] Set by A5h[8]

1 0 0 0 1 Active Set by A5h[8] Set by A5h[8]

2 0 0 1 0 Set by A5h[7] Active Set by A5h[8]

3 0 0 1 1 Active Active Set by A5h[8]

4 0 1 0 0 Set by A5h[7] Set by A5h[8] Active

5 0 1 0 1 Active Set by A5h[8] Active

6 0 1 1 0 Set by A5h[7] Active Active

7 0 1 1 1 Active Active Active

8 1 0 0 0 Set by A5h[7] Set by A5h[8] Active

9 1 0 0 1 Active Set by A5h[8] Active

A 1 0 1 0 Set by A5h[7] Active Active

B 1 0 1 1 Active Active Active

C 1 1 0 0 Set by A5h[7] Set by A5h[8] Active

D 1 1 0 1 Active Set by A5h[8] Active

E 1 1 1 0 Set by A5h[7] Active Active

F 1 1 1 1 Active Active Active

Table 15-25. LVPECL Output Clock Status when Influenced by Programmable Duty Cycle on Syncs

Setting

in Hex

Setting in Binary CK19 CK38 CK51 CK77

Bit 7 Bit 6 Bit 5 Bit 4

0 0 0 0 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

1 0 0 0 1 Active Set by A5h[4] Set by A5h[5] Set by A5h[6]

2 0 0 1 0 Set by A5h[3] Active Set by A5h[5] Set by A5h[6]

3 0 0 1 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

4 0 1 0 0 Set by A5h[3] Set by A5h[4] Active Set by A5h[6]

5 0 1 0 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

6 0 1 1 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

7 0 1 1 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

8 1 0 0 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Active

9 1 0 0 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

A 1 0 1 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

B 1 0 1 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

C 1 1 0 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

D 1 1 0 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

E 1 1 1 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

F 1 1 1 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

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15.9 LVDS Output Syncs and Clocks

This register is used to control the individual syncs duty cycle when the SDH_HW pin is low and bit A0h(2) = 0 (enhanced

software duty cycle configuration). Only the three least significant bits are used as there are only three types of output

syncs (SYC155, SYNC622, and CMOS). A high-duty cycle bit selects the duty cycle of the corresponding sync to be 50%.

If the bit is low, the sync pulse width will be equal to one 622.08 MHz clock cycle for SYNC622, and one 155.52 MHz clock

cycle for SYNC155; and for the CMOS sync, the pulse width can be programmed to be one clock cycle of the 77.76 MHz,

51.84 MHz, 38.88 MHz, or 19.44 MHZ clock. Register A6 is initialized to 111; that is, all 50% duty cycle.

Table 15-26. LVDS Output Clock Status when Influenced by Programmable Duty Cycle on Syncs

Setting in

Hex

Setting in Binary CK155P/N0 CK155P/N1 CK622P/N

Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 Set by A5h[0] Set by A5h[1] Set by A5h[2]

1 0 0 0 1 Active Set by A5h[1] Set by A5h[2]

2 0 0 1 0 Set by A5h[0] Active Set by A5h[2]

3 0 0 1 1 Active Active Set by A5h[2]

4 0 1 0 0 Set by A5h[0] Set by A5h[1] Active

5 0 1 0 1 Active Set by A5h[1] Active

6 0 1 1 0 Set by A5h[0] Active Active

7 0 1 1 1 Active Active Active

8 1 0 0 0 Set by A5h[0] Set by A5h[1] Active

9 1 0 0 1 Active Set by A5h[1] Active

A 1 0 1 0 Set by A5h[0] Active Active

B 1 0 1 1 Active Active Active

C 1 1 0 0 Set by A5h[0] Set by A5h[1] Active

D 1 1 0 1 Active Set by A5h[1] Active

E 1 1 1 0 Set by A5h[0] Active Active

F 1 1 1 1 Active Active Active

Table 15-27. Sync Duty Cycle

Address

(Hex)

Bit Name Description Reset

A6 15:3 — Reserved. 0000000000000

2 DUTY CYCLE SYNCCMOS Set duty cycle for the CMOS sync.

1 = 50%.

0 = Pulse width as set by A4h(7:4).

Conditions for use of this feature: A0h(2) = 0 and

SDH_HW pin low.

1 DUTY CYCLE SYNC155 Set duty cycle for the SYNC155.

1 = 50%.

0 = One 155.52 MHz clock cycle.

Conditions for use of this feature: A0h(2) = 0 and

SDH_HW pin low.

0 DUTY CYCLE SYNC622 Set duty cycle for the SYNC622.

1 = 50%.

0 = One 622.08 MHz clock cycle.

Conditions for use of this feature: A0h(2) = 0 and

SDH_HW pin low.

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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5656 Agere Systems Inc.

This is the edge selection for the four SDH clocks generated by the SDH block. A high bit means that the corresponding

clock’s rising edge will be synchronized to the negative edge of the input sync (actually it will lead the sync by 1—2 cycles

of a 622 MHz clock). If the edge selection bit is low, the falling edge of the corresponding clock will be aligned to the input

sync. This register is set to 1111 at reset, aligning the rising edges of the clocks to the input sync.

These registers are used to increase the possible offset between the input and output syncs. They will be used in enhanced

software offset configuration (pin SDH_HW = 0 and bit A0h(3) = 0), giving 17 bits for the absolute value of the offset as

opposed to the 10 bits available in hardware and basic software offset configuration. Those 17 bits are the 16 bits of regis-

ter A8h and bit A9h(0), which is the most significant bit of the offset. Bit A9h(1) is the direction of the offset (1 means that

the output sync will be delayed from the input sync). These registers are initialized to zero. In order to write registers A8h

and A9h, first A8h must be written. However, register A8h will not be actually written until register A9h is also written.

Table 15-28. CMOS SONET Clock Edge Selection

Address (Hex) Bit Name Description Reset

A7 15:4 — Reserved. 000000000000

3 CK78 Edge selection for the 77.76 MHz clock.

1 = Rising edge of corresponding clock aligned to input sync.

0 = Falling edge of corresponding clock aligned to input sync.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

2 CK51 Edge selection for the 51.84 MHz clock.

1 = Rising edge of corresponding clock aligned to input sync.

0 = Falling edge of corresponding clock aligned to input sync.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

1 CK38 Edge selection for the 38.88 MHz clock.

1 = Rising edge of corresponding clock aligned to input sync.

0 = Falling edge of corresponding clock aligned to input sync.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

0 CK19 Edge selection for the 19.44 MHz clock.

1 = Rising edge of corresponding clock aligned to input sync.

0 = Falling edge of corresponding clock aligned to input sync.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

Table 15-29. Enhanced Sync Offset

Address (Hex) Bit Name Description Reset

A8 15:0 SSYNCOFFSET Enhanced sync offset.

Bits A9h(0) (MSB) and A8h(15:0) contain the sync

offset value, calculated in increments of

1/622.08 (~1.6) ns. To be used with A9h[1:0]

SSYOFFPOS.

Bit A9h(1): Denotes whether enhanced offset is pos-

itive or negative:

1 = Positive.

0 = Negative.

Bits A9h(15:2): Reserved.

Conditions for use of this feature: A0h(3) = 0 and

SDH_HW pin low.

0000000000000000

A9 15:2 — 00000000000000

1 SYOFFPOS 0

0 SSYNCOFFSET(16) 0

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 57

These registers contain the value RISE used by the algorithm to calculate the position of the rising edge of the output sync.

These two registers together offer 17 bits to define the value of RISE. Bit B1h(0) is the most significant bit. At initialization,

these registers have the value B1h(0) and Bh0 = 1001011111100000 = 77,760.

These registers are also used in conjunction with register B6h to generate the parameter tcnt, used by the high-speed sync

generation block. It is not recommended that rise position of the sync outputs be adjusted in this fashion, as the frequency

of the sync outputs may be affected. It is recommended instead to use the offset functionality in registers A8h and A9h to

control the rise of the sync outputs and then use register B2h to control the fall position.

Register B2h is used to store the value of the parameter FALL used by the sync generation algorithm. This register can be

modified to obtain any desired duty cycle on the output syncs. It is initialized at 1001011111100000 = 38,880. Given that

value, with the initial value of registers B0h and B1h, the output syncs will have 50% duty cycle when the corresponding

duty cycle bit is high.

Table 15-30. Sync Rising Edge Position

Address

(Hex)

Bit Name Description Reset

B0 15:0 RISE Sync rising edge position.

Bits B1h(0) (MSB) and B0h(15:0) contain the sync rising edge position,

calculated in increments of 1/622.08 (~1.6) ns.

Bits B1h(15:1): reserved.

by the internal state machine after one of the following actions occur:

■The SDH_HW pin is high and the user changes the SYOFF or

SYOFFPOS pins.

■SDH_HW is low, A0(3) is high and the user writes to register A3.

■SDH_HW is low, A0(3) is low and the user changes A8h or A9h.

0x2FC0

B1 15:1 — 000000000000000

0RISE(16) 1

Table 15-31. Sync Falling Edge Position

Address

(Hex)

Bit Name Description Reset

B2 15:0 FALL Sync falling edge position.

Contains the sync falling edge position, calculated in increments of

1/622.08 (~1.6) ns.

Sync outputs must be set to 50% duty cycle for this feature. This can be set by the fol-

lowing: with A0h(2) high, set A2h(0) high; with A0h(2) low, set respective bits of A6h

high, for CMOS specifically, A4h[7:4] must be set either to 0001, 0010, 0100 or 1000.

nal state machine after one of the following actions occur:

■The SDH_HW pin is high and the user changes the SYOFF or SYOFFPOS pins.

■SDH_HW is low, A0(3) is high, and the user writes to register A3.

■SDH_HW is low, A0(3) is low, and the user changes A8h or A9h.

0x97E0

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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5858 Agere Systems Inc.

This register gives an extra offset to compensate the delay due to the circuits. This offset is always negative, as opposed to

the regular offset defined by registers A3h or A8h/A9h, which can be positive or negative (positive offset increases the

delay of the output sync in relation to the negative edge of the input sync. This register is initialized to 10110 = 22. That

value compensates the delay between the negative edge of the input sync and the positive edge of the output sync when

the regular offset is zero. Without this extra offset, the output sync would be delayed 22 622 MHz clock cycles. Register

B3h is therefore parameter DELTA used by the sync generation algorithm.

The 5 bits of register B6h are used in conjunction with registers B0h/B1h to calculate the value of the parameter tcnt used

by the sync generation algorithm (tcnt = RISE – B6h). The value of B6h will be subtracted form the value of registers

B0h/B1h to calculate tcnt. The initial value at reset is 01011 = 11. As it can be seen in the previous algorithm description,

this value is needed to generate the proper value for tcnt.

It is not recommended that rise position of the sync outputs be adjusted in this fashion, since the frequency of the sync out-

puts may be affected. It is recommended instead to use the offset functionality in registers A8h and A9h to control the rise

of the sync outputs and then use register B2h to control the fall position.

Table 15-32. Sync Delta

Address

(Hex)

Bit Name Description Reset

B3 15:5 — Reserved. 00000000000

4:0 DELTA Compensation for the delay between the negative edge of the input sync and

the positive edge of the output sync when the regular offset is zero.

Value of this offset indicates number of 1/622.08 (~1.6) ns increments.

internal state machine after one of the following actions occur:

■The SDH_HW pin is high and the user changes the SYOFF or SYOFFPOS

pins.

■SDH_HW is low, A0(3) is high and the user writes to register A3.

■SDH_HW is low, A0(3) is low and the user changes A8h or A9h.

10110

Table 15-33. Sync Delta Rise

Address

(Hex)

Bit Name Description Reset

B6 15:5 — Reserved. 00000000000

4:0 DELTARISE The five bits of register B6h are used in conjunction with registers B0h/B1h

to calculate the value of the parameter tcnt used by the sync generation al-

gorithm (tcnt = RISE – B6h). The value of B6h will be subtracted from the

value of registers B0h/B1h to calculate tcnt.

by the internal state machine after one of the following actions occur:

■The SDH_HW pin is high and the user changes the SYOFF or

SYOFFPOS pins.

■SDH_HW is low, A0(3) is high and the user writes to register A3.

■SDH_HW is low, A0(3) is low and the user changes A8h or A9h.

01011

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 59

The interrupt register E0h is a read-only and clear-on-read register, which reflects the status of the TSYN interrupts. When-

ever there is an interrupt, the corresponding bit will be set high and will remain high until the register is read, even if the

event which generated the interrupt is over. However, the interrupt external pins reflect the interrupts only while they are

active, so the corresponding pin goes low as soon as the event has finished.

Table 15-34. Interrupt Status Register

Address

(Hex)

Bit Name Description Reset

E0 15:10 — Reserved. 111111

9 SQUELCH The output clocks have been squelched due to a problem.

1 = Squelch inactive.

0 = Squelch active.

8 Reserved Reserved. 1

7 Reserved Reserved. 1

6 HSLOL Loss of lock—high-speed PLL.

1 = Loss of lock.

0 = In lock.

5 LSLOL Loss of lock—low-speed PLL.

1 = Loss of lock.

0 = In lock.

4 Reserved Reserved. 1

3 LOCLS Loss of external 38.88 MHz VCXO clock.

1 = Loss of clock.

0 = No loss of clock.

2 Reserved Reserved. 1

1 Reserved Reserved. 1

0 LOCA Loss of clock A.

1 = Loss of clock.

0 = No loss of clock.

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

6060 Agere Systems Inc.

16 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those

given in the operational sections of this device specification. Exposure to absolute maximum ratings for extended periods

can adversely affect device reliability.

16.1 Handling Precautions

Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be

taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere

employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to deter-

mine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit

parameters used in each of the models, as defined by JEDEC’s JESD22-A114 (HBM) and JESD22-C101 (CDM) stan-

dards.

16.2 Operating Conditions

Note: For conditions of SDHSEL[3:0] = 1111 and PDHSEL[3:0] = 1100, power dissipation will vary based on specific device

configuration and customer applications. For further information, contact the Agere Systems representative.

16.3 Powerup Conditions

No special powerup sequence is necessary; however, the device needs to be reset on powerup. The output clocks will be

active, i.e., free running, based on the pin configurations. CKPDHx clocks will not be active until the high-speed PLL is

locked.

Table 16-1. Absolute Maximum Ratings

Parameter Min Max Unit

Power Supply Voltage (VDD)–0.50 4.2 V

Storage Temperature –40 125 °C

Ball Voltage GND – 0.5 VDD + 0.5 V

Table 16-2. Handling Precautions

Device Minimum HBM Threshold Minimum CDM Threshold

TSYN03622 1500 V 200 V

Table 16-3. Recommended Operation Conditions

Parameter Symbol Min Typ Max Unit

Power Supply (dc voltage) VDD 3.135 3.3 3.465 V

Temperature:

Ambient — –40 25 85 °C

Power Dissipation PD—1.0 TBD W

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 61

17 Electrical Characteristics

17.1 LVPECL, LVDS, CMOS, Input, and Output Balls

Note: For Table 17-1 through Table 17-5, VDD = 3.3 V ± 5%, TAMBIENT = –40 °C to +85 °C.

* Looser than IEEE® specification of ±10 Ω.

Table 17-1. LVDS Output dc Characteristics

Applicable Balls Parameter Symbol Conditions Min Typ Max Unit

CK622P/N,

CK155P/N[1:0],

SYLVSP/N[1:0]

Output Voltage High, VOA or VOB VOH RLOAD = 100 Ω ± 1% 1350 — 1475 mV

Output Voltage Low, VOA or VOB VOL RLOAD = 100 Ω ± 1% 925 — 1100 mV

Output Differential Voltage |VOD| RLOAD = 100 Ω ± 1% 250 — 400 mV

Output Offset Voltage VOS R

LOAD = 100 Ω ± 1% 1125 — 1275 mV

Differential Output Impedance ROVCM = 1.0 V and 1.4 V 80 100 120 Ω

RO Mismatch Between A and B ∆Ro VCM = 1.0 V and 1.4 V — — 20 %

Change in |VOD| Between Logic 0

and Logic 1

|∆VOD|R

LOAD = 100 Ω ± 1% — — 25 mV

Change in |VOS| Between Logic 0

and Logic 1

|∆VOS|R

LOAD = 100 Ω ± 1% — — 25 mV

Output Current ISA, ISB Driver shorted to GND — — 24 mA

Output Current ISAB Drivers shorted

together

—— 12mA

Table 17-2. LVDS Input dc Characteristics

Applicable

Balls

Parameter Symbol Conditions Min Typ Max Unit

CLKP/N Input Common-mode Voltage Range VCM Avg (VIA, VIB) 0 1200 2400 mV

Input Peak Differential Voltage VDIFF |VIA –VIB| 100 — 800 mV

Input Differential Threshold VIDTH VIA –VIB –100 — 100 mV

Differential Input Impedance* RIN Measure at dc 80 100 120 Ω

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

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6262 Agere Systems Inc.

Table 17-3. CMOS Input dc Characteristics

Applicable

Balls

Parameter Symbol Conditions Min Max Unit

LSVCO Input Voltage High VIH — VDD – 1.0 VDD V

Input Voltage Low VIL —GND 0.8 V

Input Current High Leakage IIH VIN = VDD —10 µA

Input Current Low Leakage IIL VIN = GND –10 —µA

CLK, SYCLK,

SDHSEL[3:0]

SYOFF[9:0],

PDHSEL[3:0],

SDH_HW, TSTMODE

Input Voltage High VIH — VDD – 1.0 VDD V

Input Voltage Low VIL —GND 0.8 V

Input Current High Leakage IIH VIN = VDD —225 µA

Input Current Low Leakage IIL VIN = GND –10 —µA

SELLVDS,

FINSEL[3:0], INLOSN,

SYOFFPOS,

SYDU, SWCONTN,

ENSQLN, RESETN,

LF0Z, SERCLK,

SERENBLN, SERDAT

Input Voltage High VIH — VDD –1.0 VDD V

Input Voltage Low VIL —GND 0.8 V

Input Current High Leakage IIH VIN = VDD —10 µA

Input Current Low Leakage IIL VIN = GND –225 —µA

Table 17-4. CMOS Output dc Characteristics

Applicable

Balls

Parameter Symbol Conditions Min Max Unit

CK77,CK51, CK38,

CK19, SYNC8K,

CKPDH5, CKPDH4,

CKPDH3, CKPDH2,

CKPDH1, MON8K,

SERDAT

Output Voltage High VOH IOH = –4.0 mA VDD – 0.5 VDD V

Output Voltage Low VOL IOL = 4.0 mA GND 0.5 V

Output Load Capacitance CL— — 15 pF

INT[6, 5, 3, 0] Output Voltage High VOH IOH = –1.0 mA VDD – 0.5 VDD V

Output Voltage Low VOL IOL = 1.0 mA GND 0.5 V

Output Load Capacitance CL— — 15 pF

Table 17-5. LVPECL Output dc Characteristics

Applicable

Balls

Parameter Symbol Conditions Min Typ Max Unit

PCK622P/N,

PCK155P/N[1:0],

SYPCLP/N[1:0]

Output Voltage High VOH Load = 50 Ω

connected to

VDD – 2.0 V

VDD – 1.21 VDD – 1.135 VDD – 1.06 V

Output Voltage Low VOL VDD – 2.01 VDD – 1.935 VDD – 1.86 V

Output Differential

Voltage

|VOD| 0.650 0.800 0.950 V

Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 63

18 Timing Characteristics

*As defined in the IEEE standard 1596.3 -1996.

Table 18-1. LVDS Input ac Timing Characteristics

Applicable

Balls

Symbol Parameter Conditions Min Typ Max Unit

CLKP/N tPW Pulse Width Input frequencies greater than 8 kHz 8 — — ns

—Duty Cycle Input frequency of 8 kHz 45 50 55 %

Table 18-2. LVDS Output ac Timing Characteristics

Applicable

Balls

Symbol Parameter Conditions Min Typ Max Unit

CK622P/N,

CK155P/N[1:0]

SYLVSP/N[1:0]

tRISE

tFALL

Rise Time, 20% to 80%

Fall Time, 20% to 80%

ZLOAD = 100 Ω ± 1%

200

—

300

tSKEW1* Differential Skew — — — 50 ps

Table 18-3. CMOS Input ac Timing Characteristics

Applicable

Balls

Symbol Parameter Conditions Min Typ Max Unit

CLK,

SYCLK

tPW Pulse Width Input frequencies greater than 8 kHz 8 — — ns

—Duty Cycle Input frequency of 8 kHz 45 50 55 %

Table 18-4. CMOS Output ac Timing Characteristics

Applicable

Balls

Symbol Parameter Conditions Min Typ Max Unit

CK77,CK51, CK38, CK19,

SYNC8K, CKPDH5,

CKPDH4, CKPDH3,

CKPDH2, CKPDH1,

INT[6, 5, 3, 0]

tRISE

tFALL

Rise Time, 20% to 80%

Fall Time, 20% to 80%

Load = 15 pF, 1kΩ—

—

Table 18-5. LVPECL Output ac Timing Characteristics

Applicable

Balls

Symbol Parameter Conditions Min Typ Max Unit

PCK622P/N,

PCK155P/N[1:0]

SYPCLP/N[1:0]

tRISE

tFALL

Rise Time, 20% to 80%

Fall Time, 20% to 80%

Load = 50 Ω connected

to VDD – 2.0 V

—

TSYN03622 SONET/SDH/PDH/ATM Data Sheet, Revision 1

Clock Synthesizer August 26, 2003

6464 Agere Systems Inc.

19 Packaging Diagram

19.1 208-Plastic Ball Grid Array (17 x 17), 0.63 mm Ball Size (4-Layer—Bottom View)

Dimensions are in millimeters.

5-7809.b (F)

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Data Sheet, Revision 1 TSYN03622 SONET/SDH/PDH/ATM

August 26, 2003 Clock Synthesizer

Agere Systems Inc. 65

20 Ordering Information

21 Revision History

21.1 Navigating Through an Adobe Acrobat ® Document

If the reader displays this document in Adobe Acrobat Reader ®, clicking on any blue entry in the text will bring the reader

to that reference point. Clicking on the back arrow in Acrobat Reader, will bring the reader back to the starting point.

21.2 Changes

Changes that were made to this document (since the June 20, 2003 issue) are listed below.

■On page 8: Figure 3-1 was updated to reflect LF0Z, LF[0:2]. SYCLKA was changed to SYCLK.

■On page 10: The entries for Table 4-1, Ball Assignments for 208-Ball PBGA by Ball Number Order, were reordered.

Names for pins A2, A3, A14, and A15 were corrected. Pin name for H1 was changed from PCK622N to PCK622N1.

■On page 12: In Table 4-2, Physical Ball Orientation (Bumps Down), pin name for H1 was changed from PCK622N to the

correct name: PCK622N1.

■On page 37: The first paragraph under Section 13.5, Interrupt Generation (INT[6, 5, 3, 0]), was updated.

■On page 57 Table 15-31, Sync Falling Edge Position, was updated.

■On page 63: In Table 18-3, CMOS Input ac Timing Characteristics, pin SYCLKA was changed to SYCLK.

Table 20-1. Ordering Information

Device Code Package Temperature Comcode

(Ordering Number)

TSYN03622 208 PBGAM1 –40 °C to +85 °C 700034203

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere is a registered trademark of Agere Systems Inc. Agere Systems, the Agere logo, Ultramapper, Hypermapper, and Supermapper are trademarks of Agere Systems Inc.

August 26, 2003

DS03-130HSPL-1 (Replaces DS03-130HSPL)

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

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