KMPC8245ARVV400D - Freescale Semiconductor

Freescale Semiconductor

Technical Data

Specifications provided in this document supersede those in

the MPC8245 Integrated Pr ocessor Har dw are

Specifications, Rev. 3 or later, for the part numbers listed in

Table A only.

Specifications not addressed in this document are

unchanged. Because this document is frequently updated,

refer to http:/ /www.f reescale.com or to your Fr eescale sales

office for the latest version.

Note that headings and table numbers in this document are

not consecutively numbered. They are intended to

correspond to the heading or table aff ected in the general

hardware specification.

Part numbers addressed in this document are listed in

Table A. For more detailed ordering information, see

Sectio n 9, “Ord erin g In formation .”

Document Number: MPC8245ECS02AD

Rev. 3, 12/2005

Freescale Part Numbers Affected:

MPC8245ARZU400D

MPC8245ARVV400D

MPC8245 Hardware Specifications

Addendum for the

MPC

8245ARXXnnnx

Series

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

2Freescale Semiconductor

Electrical and Thermal Characteristics

4 Electrical and Thermal Characteristics

This section provides th e AC and DC electrical speci f icat ions and the rmal char acter i stics f or the

MPC8245.

4.1.1 Absolute Maximum Ratings

The tables in this section describe the MPC8245 DC electrical characteristics. Table 1 provides the

absolute maximum ratings.

Table A. Part Numbers Addressed in this Data Sheet

Freescale

Part No.1

Operating Conditions

Significant Differences from

Hardware Specification

Processor

Version

Value

CPU

Frequency

(MHz)

VDD

(°C)

MPC8245ARZU400D

400 2.1 ± 100 mV 0 to 85 Modified voltage and temperature

specifications to achieve 400 MHz 0x80811014

MPC8245ARVV400D

Note:

The ‘A’ in the part number represents parts that are manufactured under a 29-angstrom process instead of the original

35-angstrom process. Package Options: ZU - TBGA, V V- Lead Free TBGA

Table 1. Absolute Maximum Ratings

Characteristic 1Symbol Range Unit

Supply voltage—CPU core and peripheral logic VDD –0.3 to 2.2 V

Supply voltage—memory bus drivers GVDD –0.3 to 3.6 V

Supply voltage—PCI and standard I/O buffers OVDD –0.3 to 3.6 V

Supply voltage—PLLs AVDD/AVDD2 –0.3 to 2.2 V

Supply voltage—PCI reference LVDD –0.3 to 5.4 V

Input voltage 2Vin –0.3 to 3.6 V

Operational die-junction temperature range Tj0 to 85 °C

Storage temperature range Tstg –55 to 150 °C

Notes:

1. Table 2 shows functional and tested operating conditions. Absolute maximum ratings are stress ratings only, and functional

operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent

damage to the device.

2. PCI inputs with LVDD = 5 V ± 5% V DC may undergo corresponding stress at voltages exceeding LVDD +0.5VDC.

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

Freescale Semiconductor 3

Electrical and Thermal Characteristics

4.1.2 Recommended Operating Conditions

Table 2 provides the recommended operating conditions for the MPC8245 part numbers described herein.

4.1.5 Power Characteristics

The AC electrical characteristics and AC timing for the parts described in this document are unaffected,

and comply with the MPC8245 Integrated Processor Hardware Specifications. Table 5 provides the power

consumption for the MPC8245 part numbers described herein.

Table 2. Recommended Operating Conditions (1)

Notes:

1. Freescale tested these operating conditions and recommends them. Proper device operation outside of these conditions is

not guaranteed.

Characteristic Symbol

Recommended

Value for

400 MHz CPU

Unit

Supply voltage VDD 2.1 V ± 100 mV V

CPU PLL supply voltage AVDD 2.1 V ± 100 mV V

PLL supply voltage—peripheral logic AVDD2 2.1 V ± 100 mV V

Die-junction temperature(2)

2. For information about the thermal characteristics of this part, refer to the

MPC8245 Integrated Processor Hardware

Specifications

. Note that the lower die-junction temperature creates a greater need to use a heat sink with this part.

Tj0 to 85 °C

Table 5. Power Consumption

Mode

PCI Bus Clock/Memory

Bus Clock

CPU Clock Frequency

(MHz) Unit Notes

66/133/399

Typi cal 2.8 W 1, 5

Max—CFP 3.3 W 1, 2

Max—INT 2.8 W 1, 3

Doze 1.9 W 1, 4, 6

Nap 0.7 W 1, 4, 6

Sleep 0.4 W 1, 4, 6

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

4Freescale Semiconductor

Electrical and Thermal Characteristics

4.3.1 Clock AC Specifications

Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation for

29 angstrom parts. These graphs define the areas of DLL locking for various modes. The gray areas show

where the DLL will lock.

I/O Power Supplies10

Mode Range Unit Notes

Typ — OV DD 140–360 mW 7, 8

Typ — GV DD 340–920 mW 7, 9

Notes:

1. The values include VDD, AVDD, and AVDD2, but do not include I/O supply power.

2. Maximum—FP power is measured at VDD = 2.1 V with dynamic power management enabled while running an entirely

cache-resident, looping, floating point multiplication instruction.

3. Maximum—INT power is measured at VDD = 2.1 V with dynamic power management enabled while running entirely

cache-resident, looping, integer instructions.

4. Power saving mode maximums are measured at VDD = 2.1 V while the device is in doze, nap, or sleep mode.

5. Typical power is measured at VDD = AVDD = 2.1 V, OVDD = 3.3 V where a nominal FP value, a nominal INT value, and a

value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory

are averaged.

6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.

7. The typical minimum I/O power values was the result of the MPC8245 performing cache resident integer operations at the

slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz.

8. The typical maximum OVDD value resulted from the MPC8245 operating at the fastest frequency combination of 66:133:399

(PCI:Mem:CPU) MHz for the 400-MHz part, and performing continuous flushes of cache lines with alternating ones and

zeros to PCI memory.

9. The typical maximum GVDD value resulted from the MPC8245 operating at the fastest frequency combination of

66:133:399 (PCI:Mem:CPU) MHz for the 400-MHz part, and performing continuous flushes of cache lines with alternating

ones and zeros on 64-bit boundaries to local memory.

10. Power consumption of PLL supply pins (AVDD and AVDD2) < 15 mW that the design guarantees but were not tested.

Table 5. Power Consumption (continued)

Mode

PCI Bus Clock/Memory

Bus Clock

CPU Clock Frequency

(MHz) Unit Notes

66/133/399

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

Freescale Semiconductor 5

Electrical and Thermal Characteristics

The DLL_MAX_DELA Y bit can lengthen the amount of time through the delay line. This is accomplished

by increasing the time between each of the 128 tap points in the delay line. Although this increased time

makes it easier to guarantee that the reference clock will be within the DLL lock range, it also means there

may be slightly more jitter in the output clock of the DLL, should the phase comparator shift the clock

between adjacent tap points. Refer to Freescale application note AN2164, MPC8245/MPC8241 Memory

Clock Design Guideli nes:Part 1, for details about DLL modes and memory design.

The value of the current tap point once the DLL has locked can be determined by reading bits 6–0

(DLL_TAP_COUNT) of the DLL tap count register (DTCR, located at offset 0xE3). These bits store the

value (binary 0 through 127) of the current tap point and can indicate whether the DLL advances or

decrements as it maintains the DLL lock. Therefore, for evaluation purposes, DTCR can be read for all

DLL modes that support the Tloop value th at is used for the trace length of SDRAM_SYNC_OUT to

SDRAM_SYNC_IN. The DLL mode that provides the smallest tap point value seen in DTCR should be

used. T his is becaus e the bigger the tap point value, the more jitte r tha t ca n be e xpected f or c lock s igna ls.

Note that keeping a DL L mode that is locked be low tap point 12 is not recommende d.

Table 9. DLL Mode Definition

DLL Mode Value of Bit 2 of Config

Value of Bit 7 of Config

Normal tap delay,

No DLL extend

Normal tap delay,

DLL extend

Max tap delay,

No DLL extend

Max tap delay,

DLL extend

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

6Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 7. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 0

and Normal Tap Delay

Tloop Propagation Delay Time (ns)

Tclk SDRAM_SYNC_OUT Period (ns)

N = 1

N = 2

7.5

4 5

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

Freescale Semiconductor 7

Electrical and Thermal Characteristics

Figure 8. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1

and Normal Tap Delay

Tloop Propagation Delay Time (ns)

Tclk SDRAM_SYNC_OUT Period (ns)

N = 1

N = 2

7.5

4 5

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

8Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 0

and Max Tap Delay

Tloop Propagation Delay Time (ns)

Tclk SDRAM_SYNC_OUT Period (ns)

N = 1

N = 2

7.5

4 5

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

Freescale Semiconductor 9

Electrical and Thermal Characteristics

Figure 10. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1

and Max Tap Delay

Tloop Propagation Delay Time (ns)

Tclk SDRAM_SYNC_OUT Period (ns)

N = 1

N = 2

7.5

4 5

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

10 Freescale Semiconductor

PLL Configuration

6 PLL Configuration

The MPC8245 internal PLLs are configured by the PL L_C FG[0:4] signals. For a given PCI_SYNC_IN

(PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO)

frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO)

frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations for the

400-MHz parts are shown in Table 18.

Table 18. PLL Configurations for the 400-MHz Part Offering

Ref PLL_CFG

[0:4]11,14,15

400-MHz Part 9Multipliers

PCI Clock Input

(PCI_SYNC_IN)

Range 1

(MHz)

Periph

Logic/Mem

Bus Clock

Range

(MHz)

CPU Clock

Range

(MHz)

PCI-to-Mem

(Mem VCO)

Mem-to-CPU

(CPU VCO)

0 00000 25–44275–132 188–330 3 (2) 2.5 (2)

1 00001 25–44575–132 225–396 3 (2) 3 (2)

2 0001013 509–66150–66 225–297 1 (4) 4.5 (2)

3 0001116 508–66150–66 100–133 1 (Bypass) 2 (4)

4 00100 25–46450–92 100–184 2 (4) 2 (4)

6 0011017 Bypass Bypass Bypass

7 (Rev. B) 00111 606–66160–66 180–198 1 (Bypass) 3 (2)

7 (Rev. D) 0011113 25–285100–112 350–392 4 (2) 3.5 (2)

8 01000 606–66160–66 180–198 1 (4) 3 (2)

9 01001 456–66190–132 180–264 2 (2) 2 (2)

A 01010 25–44550–88 225–396 2 (4) 4.5 (2)

B 01011 453–66168–99 204–297 1.5 (2) 3 (2)

C 01100 366–46472–92 180–230 2 (4) 2.5 (2)

D 01101 453–66168–99 238–347 1.5 (2) 3.5 (2)

E 01110 306–46460–92 180–276 2 (4) 3 (2)

F 01111 25–385 75–114 263–399 3 (2) 3.5 (2)

10 10000 30–44260–132 180–264 3 (2) 2 (2)

11 10001 25–332100–132 250–330 4 (2) 2.5 (2)

12 10010 606–66190–99 180–198 1.5 (2) 2 (2)

13 10011 25–335100–132 300–396 4 (2) 3 (2)

14 10100 266–47452–94 182–329 2 (4) 3.5 (2)

15 10101 273–40568–100 272–400 2.5 (2) 4 (2)

16 10110 25–46450–92 200–368 2 (4) 4 (2)

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

Freescale Semiconductor 11

PLL Configuration

17 10111 25–332100–132 200–264 4 (2) 2 (2)

18 11000 273–53568–132 204–396 2.5 (2) 3 (2)

19 11001 366–66172–132 180–330 2 (2) 2.5 (2)

1A 11010 509–66150–66 200–264 1 (4) 4 (2)

1B 1101113 343–66168–132 204–396 2 (2) 3 (2)

1C 11100 446–66166–99 198–297 1.5 (2) 3 (2)

1D 11101 486–66172–99 180–248 1.5 (2) 2.5 (2)

1E (Rev. B) 1111010 Not usable Off Off

1E (Rev. D) 11110 333–57566–114 231–399 2 (2) 3.5 (2)

1F 1111110 Not usable Off Off

Notes:

1. Limited by maximum PCI input frequency (66 MHz).

2. Limited by maximum system memory interface operating frequency (133 MHz).

3. Limited by minimum memory VCO frequency (132 MHz).

4. Limited due to maximum memory VCO frequency (372 MHz).

5. Limited by maximum CPU operating frequency (400 MHz).

6. Limited by minimum CPU VCO frequency (360 MHz).

7. Limited by maximum CPU VCO frequency (800 MHz).

8. Limited by minimum CPU operating frequency (100 MHz).

9. Limited by minimum memory bus frequency (50 MHz).

10. In clock off mode, no clocking occurs inside the MPC8245, regardless of the PCI_SYNC_IN input.

11. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for

clarity.

12. PLL_CFG[0:4] settings that are not listed are reserved.

13. Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not

backwards-compatible.

14. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully

backwards-compatible.

15. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.

16. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral

logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for

hardware modeling support. The AC timing specifications given in this document do not apply in the PLL

bypass mode.

17. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the

peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In

this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode

operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be

externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications

given in this document do not apply in the dual PLL bypass mode.

Table 18. PLL Configurations for the 400-MHz Part Offering (continued)

Ref PLL_CFG

[0:4]11,14,15

400-MHz Part 9Multipliers

PCI Clock Input

(PCI_SYNC_IN)

Range 1

(MHz)

Periph

Logic/Mem

Bus Clock

Range

(MHz)

CPU Clock

Range

(MHz)

PCI-to-Mem

(Mem VCO)

Mem-to-CPU

(CPU VCO)

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

12 Freescale Semiconductor

Ordering Information

9 Ordering Information

Ordering information for the parts covered in this document is provided in Secti on 9.1 , “Part Numb er s

Fully Addressed by This Document.” Se ction 9.3, “Part Marking,” addr ess es th e marking speci f icat ions.

9.1 Part Numbers Fully Addressed by This Document

Table 21 provides the ordering information for the MPC8245 parts described herein. Note that the

individual part numbers correspond to a maximum proce ssor core frequency.

Table 23. Part Numbers Addressed by This Document.

MPC

nnnn X

xx nnn x

Product

Code

Part

Identifier

Process 3

Identifier

Process

Descriptor Package 1Processor

Frequency 2Revision Level

Processor

Version

Value

MPC 8245 A R: 0° to 85°CZU=TBGA

V V= Lead-free

TBGA

400 MHz

2.1 V ± 100 mV

D:1.4 Rev ID:0x14 0x80811014

Notes:

1. See Section 5, “Package Description,” for more information on available package types.

2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this

specification support all core frequencies. Additionally, parts addressed by part number specifications may support other

maximum core frequencies.

3. Process identifier ‘A’ represents parts that are manufactured under a 29-angstrom process verses the original

35-angstrom process.

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

Freescale Semiconductor 13

Document Revision History

9.3 Part Marking

Parts are marked as in the example shown in Figure 33.

Figure 33. Freescale Part Marking for TBGA Device

2 Document Revision History

Table B provides a revision history for this part number specification.

Table B Document Revision History

Rev. No. Date Substantive Change(s)

3 12/05 • Changed Document ID from MPC8245ARUPNS to MPC8245ECS02AD.

• Changed title of document from

MPC8245 Part Number Specification for the MPC8245ARZUnnnX

Series

” to the “

MPC8245 Hardware Specification Addendum for the MPC8245ARXXnnnx Series

.”

• Table A and Ta ble 23 were updated to reflect current part offerings for the part.

• Removed Section 2, “Features” and Section 3, “.General Parameters.”

• Added Section 4, “Electrical and Thermal Characteristics.” heading and introduction.

• Remove all 466 MHz specific information as this part is not available for new orders. Section 4.3.3

was removed because it was specific to the 466 MHz part.

• Figure 33 was updated to reflect current part marking format.

2 07/12/04 • Updated to Freescale template.

• Updated section numbers to accurately reflect hardware specifications sections.

• Changed junction temperature range in Table 1 to reflect range depicted in Table A (0° to 85°C).

• Added Section 4.3.1 to illustrate DLL locking graphs for 29 angstrom parts (400- and 466-MHz parts).

1.0 • Added to list of parts covered by this document, including the non-A process identifier parts. Updated

Table A and Table 20.

• Nontechnical reformatting.

0.1 Minor edit to part number.

0 Original release.

Notes:

MMMMMM is the 6-digit mask number.

ATWLYYWW is Test traceability code.

MPC8245ARXXnnnx

MMMMMM

ATW LY Y WW

CCCCC

YWWLAZ

YWWLAZ is the Assembly traceability code.

CCCCC is the country code.

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

14 Freescale Semiconductor

Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3

Freescale Semiconductor 15

Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

Document Number: MPC8245ECS02AD

Rev. 3

12/2005

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