2010 Microchip Technology Inc. Preliminary DS30480C-page 1
PIC18FXX39
1.0 DEVICE OVERVIEW
This document includes the programming
specifications for the following devices:
• PIC18F2439
• PIC18F2539
• PIC18F4439
• PIC18F4539
2.0 PROGRAMMING OVERVIEW
OF THE PIC18FXX 39
The PIC18FXX39 can be programmed using the high
voltage In-Circuit Serial ProgrammingTM (ICSPTM)
method, or the low voltage ICSP method; both while in
the users’ system. The low voltage ICSP method is
slightly different than the high voltage method, and
these differences are noted where applicable. This
programming specification applies to PIC18FXX39
devices in all package types.
2.1 Hardware Requirements
In High Voltage IC SP mode , the PIC 18 FXX39 requ ire s
two programmable power supplies: one for VDD and
one for MCLR/VPP. Both supplies should have a
minimum resolution of 0.25V. Refer to Section 6.0 for
additional hardware parameters.
2.1.1 LOW VOLTAGE ICSP
PROGRAMMING
In Low Voltage ICSP mode, the PIC18FXX39 can be
programmed using a VDD source in the operating
range. This only means that MCLR/VPP does not have
to be brought to a different voltage, but can instead be
left at the normal operating voltage. Refer to
Section 6.0 for additional hardware parameters.
2.2 Pin Diagrams
The pin diagrams for the PIC18FXX39 family are
shown in Figure 2-1. The pin descriptions of these
diagram s do not represent the co mplete functio nality of
the device types. One should refer to the appropriate
device data sheet for complete pin descriptions.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXX39
Pin Name During Programming
Pin Name Pin Type Pin Description
MCLR/VPP VPP P Program mi ng Enab le
VDD VDD P Power Su pply
Vss VSS P Ground
RB5 PGM I Low Voltage ICSP™ Input w hen LVP Co nfigura tion bi t equal s ‘1’(1)
RB6 SCLK I Serial Clock
RB7 SDATA I/O Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: See Section 5.3 for more detail.
Pr ogramming for PI C18FXX39 F lash MCUs
PIC18FXX39
DS30480C-page 2 Preliminary 2010 Microchip Technology Inc.
FIGURE 2-1: PIC18FXX39 FAMILY PIN DIAGRAMS
Note: Not all multiplexed pin definitions are shown. Refer to the appropriate data sheet for complete
pin descriptions.
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
VDD
VSS
OSC1
OSC2
RC0
PWM1
PWM2
RC3
RD0
RD1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18FXX39
9
MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
VSS
OSC1
OSC2
RC0
PWM1
PWM2
RC3
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
1
2
3
4
5
6
7
8
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
9
PIC18FXX39
28-Pin DIP, SOIC 40-Pin DIP
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3
RA2
RA1
RA0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
PWM2
PWM1
NC
NC
RC0
OSC2
OSC1
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
PIC18FXX39
44-Pin TQFP
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3
RA2
RA1
RA0
MCLR/VPP
RB3
RB7
RB6
RB5
RB4
NC
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
PWM2
PWM1
RC0
OSC2
OSC1
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
PIC18FXX39
44-Pin QFN
AVSS
VDD
AVDD
2010 Microchip Technology Inc. Preliminary DS30480C-page 3
PIC18FXX39
2.3 Memory Map
The code memory sp ace extend s from 0000h to 5FFFh
(24 Kbytes) in three 8-Kbyte panels in PIC18FX539
parts. In PIC18FX439 parts, program space is from
0000h to 2FFFh (12 Kbytes). Addresses 0000h
through 01FFh, however, define a “Boot Block” region
that is treated separately from Panel 1. All code
memory is on-chip.
A user may sto re ide ntif ic atio n inf orm atio n (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000 h through 200007h. Th e ID locations
read out normally , even after code protection is applied.
Locations 300001h through 30000Dh are reserved for
the configuration bits. These bits may be set to select
various device options, and are described in
Section 5.0 . These configu ration bit s read out n ormally,
even after code protected.
Locatio ns 3FFFF Eh and 3FFF FFh ar e reserved for the
device ID bits. These bits may be used by the
programmer to identify what device type is being
prog ram med, an d ar e desc ribe d in S ect ion 5 .0. The se
configuration bits read out normally, even after code
protection.
TABLE 2-2: IMPLEMENTATION OF CODE
MEMORY
2.3.1 MEMOR Y ADDRESS POINTER
Memory in the address space 000000h to 3FFFFFh is
addressed via the Table Pointer, which is comprised of
three pointe r regis ters :
• TBLPTRU, at address 0FF8h
• TBLPTRH, at address 0FF7h
• TBLPTRL, at address 0FF6h
FIGURE 2-2: MEMORY MAP FOR PIC18FXX39
Device Code Memory Size
PIC18F2439 0000h - 2FFFh (12 Kbytes)
PIC18F2539 0000h - 5FFFh (24 Kbytes)
PIC18F4439 0000h - 2FFFh (12 Kbytes)
PIC18F4539 0000h - 5FFFh (24 Kbytes)
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]
200000h ID Location 1
200001h ID Location 2
200002h ID Location 3
200003h ID Location 4
200004h ID Location 5
200005h ID Location 6
200006h ID Location 7
200007h ID Location 8
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
3FFFFEh Device ID1
3FFFFFh Device ID2
0000h
5FFFh
200000h
3FFFFFh
3FFFh
Unimplemented Unimplemented
Read as 0’sRead as 0’s
24 Kbytes
200h
1FFFh
Boot Block Boot Block
Panel 1
Panel 2
Panel 3
Panel 1
Panel 2
12 Kbytes
2FFFh
PIC18FXX39
DS30480C-page 4 Preliminary 2010 Microchip Technology Inc.
2.4 High Level Overview of the
Programming Process
Figure 2-3 shows the high level overview of the
programming process. The device is first checked to
see if it is blank; if it is not, a bulk erase is performed.
Next, the code memory, ID locations, and data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the configuration bits are then
programmed and verified.
FIGURE 2-3: HIGH LEVEL PROGRAMMING FLOW
Start
Program Me mory
Program IDs
Program Data
Verify Program
Verify IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Is part blank
?No Perform Bulk
Erase
Yes
Blank Check
2010 Microchip Technology Inc. Preliminary DS30480C-page 5
PIC18FXX39
2.5 Entering High Voltage ICSP
Program/Verify Mode
The High Voltage ICSP Program/Verify mode is
entered by holding SCLK and SDATA low, and then
raising MCLR/VPP to VIHH (high voltage). Once in this
mode, the code memory, data EEPROM, ID locations,
and configuration bits can be accessed and
programmed in serial fashion.
The sequence that enters the device into the
Programm ing/V erify mo de places al l unused I/Os i n the
high impedance state.
FIGURE 2-4: ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
2.5.1 ENTERING LOW VOLTAG E ICSP
PROGRAM/VERIFY MODE
When the LVP conf igu rati on bit is ‘1’ (s ee Sec tion 5.3),
the Low Voltage ICSP mode is enabled. Low Voltage
ICSP Progra m/V erify mod e is entered b y holding SCLK
and SDATA low , p lacin g a lo gic h igh on PGM, and the n
raising MCLR/VPP to VIH. In this mode, the RB5/PGM
pin is dedicated to the programming function and
ceases to be a general purpose I/O pin.
The sequence that enters the device into the
Programming/Verify mode places all unused I/O’s in
the high impedance state.
FIGURE 2-5: ENTERING LOW
VOLTAGE PROGRAM/
VERIFY MODE
2.6 Serial Program/Verify Operation
The SCLK pin is used as a clock input pin and the
SDATA pin is us ed for ente ring co mman d bit s and data
input/output during serial operation. Commands and
data are transmitted on the rising edge of SCLK,
latched on the falling edge of SCLK, and are Least
Significant bit (LSb) first.
2.6.1 4-BIT COMMANDS
All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit op erand, which depend s
on the type of command being executed. To input a
comman d, SCL K is cycled four tim es. The co mmands
needed for programming and verification are shown in
Table 2-3.
TABLE 2-3: COMMANDS FOR
PROGRAMMING
MCLR/VPP
P12
SDATA
SDATA = Input
SCLK
VDD
D110
P13
Description 4-bit
Command
Core Instruction
(Shift in16-bit instruction) 0000
Shift out TABLAT register 0010
Table Read 1000
Table Read, post-i nc rem en t 1001
Table Read , post-d ecrem ent 1010
Table Read , pre-in cre men t 1011
Table Write 1100
Table Write, post-increment by 2 1101
Table Wri te, pos t-de crement by 2 1110
Table Write, start programming 1111
MCLR/VPP
P12
SDATA
SDATA = Input
SCLK
PGM
P15
VDD
VIH
VIH
PIC18FXX39
DS30480C-page 6 Preliminary 2010 Microchip Technology Inc.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data, or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Table 2-4. The 4-bit
command is shown MSb first. The command operand,
or “Data Payload”, is shown <MSB><LSB>. Figure 2-6
demonstrates how to serially present a 20-bit
command/operand to the device.
TABLE 2-4: SAMPLE COMMAND
SEQUENCE
2.6.2 CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to setup
registers as approp riate for us e with other co mmand s.
FIGURE 2-6: TABLE WRITE, POST-INCREMENT TIMING (1101)
4-bit
Command Data
Payload Core Instruction
1101 3C 40 Table Write,
post-increment by 2
1234
SCLK P5
SDATA
SDATA = Input
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-bit Command
1011
1234
nnnn
P3
P2 P2A
000000 010001111 0
04C3
P4
4-bit Command 16- bit D ata Pa yload
P2B
2010 Microchip Technology Inc. Preliminary DS30480C-page 7
PIC18FXX39
3.0 DEVICE PROGRAMMING
3.1 Blank Check
The term, “Blank Check”, means to verify that the
device has no programmed memory cells. All
memories must be verified: code memory, data
EEPROM, ID locations, and configuration bits. The
Device ID registers (3FFFFEh:3FFFFFh) should be
ignored.
A “blank” or “erased” memory cell will read as a ‘1’. So,
“Blank Checking” a device merely means to verify that
all bytes read as FFh, except the configuration bits.
Unused (reserved) configuration bits will read ‘0’
(programmed). Refer to Table 5-2 for blank
configuration expect data for the various PIC18FXX39
devices.
If it is determined that the device is not blank, then the
device should be Bulk Erased (see Section 3.2) before
any attempt to program is made.
Given that “Blank Checking” is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.1 and Sect ion 4.3 for i mplemen tati on det ails .
FIGURE 3-1: BLANK CHECK FLOW
3.2 High Voltage ICSP Bulk Erase
Erasing code or data EEPROM is accomplished by
writing an “erase option” to address 3C0004h. Code
memory may be erased portions at a time, or the user
may era se the entire devi ce in one a ction. “Bulk Erase”
operations will also clear any code protect settings
associated with the memory block erased. Erase
options are detailed in Table 3-1.
TABLE 3-1: BULK ERASE OPTIONS
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th SCLK after the WRITE command), serial
execution will cease until the erase completes
(param et er P11). During this time, SC LK may c ont inu e
to toggle, but SDATA must be held low.
The code s equence to eras e the entire devic e is shown
in Table 3-2 and Table 3-3. The corresponding
flowcharts are shown in Figure 3-2 and Figure 3-3.
Is
Yes
No
Start
Blank Check Device
device
blank?
Bulk Erase Device
Blank Check Device
Is
device
blank? Continue
Abort
No
Yes Continue
Description Data
Erase Data EEPROM 81h
Erase Boot Block 83h
Erase Panel 1 88h
Erase Panel 2 (PIC18FX539 only) 89h
Erase Panel 3 (PIC18FX539 only) 8Ah
Note: A Bulk Erase is the only way to reprogram
code protect bits from an on state to an off
state.
PIC18FXX39
DS30480C-page 8 Preliminary 2010 Microchip Technology Inc.
TABLE 3-2: CHIP ERASE COMMAND SEQUENCE FOR PIC18FX439
4-bit Command Data Payload Core Instruction
Step 1: Load 3C0004h to Address Pointer.
0000
0000
0000
0000
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Step 2: Erase boot block.
0000
0000
0000
00 83
00 00
00 00
Write 83h to 3C0004h to erase the boot block
NOP
Hold SDATA low until erase complete
Step 3: Erase Panel 1.
0000
0000
0000
00 88
00 00
00 00
Write 88h to 3C0004h to erase the panel 1
NOP
Hold SDATA low until erase complete
Step 4: Configure device for single panel write.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes
Step 5: Direct access to code memory.
0000
0000
8E A6
9C A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 6: Set the Table Pointer to point to the first 64-byte block of Panel 2.
0000
0000
0000
0000
0000
0000
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Step 7: Enable memory writes and setup an erase.
0000
0000
84 A6
88 A6
BSF EECON1, WREN
BSF EECON1, FREE
Step 8: Perform Dat a EEPROM unlock sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 55h
MOVWF EECON2
MOVLW AAh
MOVWF EECON2
Step 9: Initiate erase.
0000
0000
82 A6
00 00
BSF EECON1, WR
NOP
Step 10: Wait for P11+P10 and then disable writes.
0000 94 A6 BCF EECON1, WREN
Step 11: Increment Table Pointer by 64 and repeat from step 7 to step 10, 40 times.
2010 Microchip Technology Inc. Preliminary DS30480C-page 9
PIC18FXX39
FIGURE 3-2: CHIP ERASE FLOW FOR PIC18FX439
No
Yes
END
Increment Address
by 64
Address =
2FFFh?
Delay
P11 + P10 Time
Enable Memory Write
Unlock Sequence
and Data EEPROM
and Erase the
Locations
Load 2000h to
Starting Address)
Table Pointer
(Panel 2
Set Code Memory
Access to EE
Control Regis ters
Load 00h
(Sing le Pane l)
to 3C0006h
Delay
P11 + P10 Time
Write 88h to
Erase Panel 1
Delay
P11 + P10 Time
Write 83h to
Erase Boot Block
Load 300004h
to Address Pointer
START
PIC18FXX39
DS30480C-page 10 Preliminary 2010 Microchip Technology Inc.
TABLE 3-3: CHIP ERASE COMMAND SEQUENCE FOR PIC18FX539
4-bit Command Data Payload Core Instruction
Step 1: Load 3C0004h to Address Pointer.
0000
0000
0000
0000
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Step 2: Erase boot block.
0000
0000
0000
00 83
00 00
00 00
Write 83h to 3C0004h to erase the boot block
NOP
Hold SDATA low until erase complete (P11+P10)
Step 3: Erase Panel 1.
0000
0000
0000
00 88
00 00
00 00
Write 88h to 3C0004h to erase the panel 1
NOP
Hold SDATA low until erase complete (P11+P10)
Step 4: Erase Panel 2.
0000
0000
0000
00 89
00 00
00 00
Write 89h to 3C0004h to erase the panel 2
NOP
Hold SDATA low until erase complete (P11+P10)
Step 5: Erase Panel 3.
0000
0000
0000
00 8A
00 00
00 00
Write 8Ah to 3C0004h to erase the panel 3
NOP
Hold SDATA low until erase complete (P11+P10)
2010 Microchip Technology Inc. Preliminary DS30480C-page 11
PIC18FXX39
FIGURE 3-3: CHIP ERASE FLOW FOR PIC18FX539
FIGURE 3-4: BULK ERASE TIMING
END
Delay
P11 + P10 Time
Write 8Ah to
Erase Panel 3
Write 89h to
Erase Panel 2
Delay
P11 + P10 Time
Write 88h to
Erase Panel 1
Delay
P11 + P10 Time
Write 83h to
Erase Boot Block
Load 300004h
to Address Pointer
START
Delay
P11 + P10 Time
n
1234 121516 123
SCLK
P5 P5A
SDATA
SDATA = Input
00011
P11
P10
Erase Time
00 0 000 0 0
12
00
4
0
12 1516
P5
123
P5A
4
0000 n
4-bit Command 4-bit Command 4-bit CommandNOP
16-bit
Data Payload 16-bit
Data Payload
PIC18FXX39
DS30480C-page 12 Preliminary 2010 Microchip Technology Inc.
3.2.1 LOW VOLTAGE ICSP BULK ERASE
When using low voltage ICSP, the part must be
supplied by the voltage specified in parameter D111, if
a bulk erase is to be executed. All other bulk erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the bulk erase
limit, refer to the erase methodology described in
Section 3.3.1.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the bulk erase
limit, follow the methodology described in Section 3.4
and write zeroes to the array.
3.3 Code Memory Programming
Programming code memory is accomplished by first
loading dat a int o the appro priate wr ite bu ffe rs an d then
initiating a programming sequence. Each panel in the
code memory space (see Figure 2-2) has an 8-byte
deep w rite buffer that must be load ed pri or to init iat ing
a write sequence. The actual memory write sequence
takes the contents of these buffers and programs the
associated EEPROM code memory.
The programming duration is externally timed and is
controlled by SCLK. After a “Start Programming”
command is issued (4-bit command, ‘1111’), a NOP is
issued where t he 4th SCLK is held high for t he duratio n
of the programming time, P9.
Aft er SCLK i s b roug ht l ow, the progra mm ing se quence
is terminated. SCLK must be held low for the time
specified by parameter P10 to allow high voltage
discharge of the memory array.
The code sequence to program a PIC18FXX39 device
is shown in Table 3-4. The flowchart shown in
Figure 3-7 depicts the logic necessary to completely
wri te a PIC18FXX 39 device.
FIGURE 3-5: ERASE AND WRITE BOUNDARIES
Note: The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3> Offset = TBLPTR<12:6>
Panel n
Erase Region
(64 bytes)
8-byte Write Buffer
Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.
2010 Microchip Technology Inc. Preliminary DS30480C-page 13
PIC18FXX39
TABLE 3-4: WRITE CODE MEMORY CODE SEQUENCE
FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)
4-bit Command Data Payload Core Instruction
Step 1: Configure device for multi-panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 40
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes.
Step 2: Direct access to code memory.
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 3: Load write buffer.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP – Hold SCLK high for Time P9
Step 4: Delay of P10.
To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented by 8 at each iteration of the loop.
1234 12 1516 123 4
SCLK P5A
SDATA
SDATA = Input
n
1111
34 65
P9
P10
Progra mm i ng Time
nnn nn n n 0 0
12
000
16-bit
Data Payload
0
3
0
P5
4-bit Command 16-bit Data Payload 4-bit Command
PIC18FXX39
DS30480C-page 14 Preliminary 2010 Microchip Technology Inc.
3.3.1 MODIFYING CODE MEMORY
All of the programming examples up to this point have
assum ed that the device i s blank p rior to progra mming.
In fact, if the de vice is no t blan k, the direc tion h as been
to completely erase the device via a Bulk Erase
operation (see Section 3.2).
It may be the case, however, that the user wishes to
modify only a section of an already programmed
device. In such a situation, erasing the entire device is
not a realistic option.
The minim um am ount of dat a that c an be wri tten to the
device is 8 bytes. This is accomplished by placing the
dev ice in Si ngle P anel Writ e mode , loadi ng the 8-byt e
write buffer for the panel, and then initiating a write
sequence, as shown in Table 3-4. In this case,
however, it is assumed that the address space to be
written already has data in it (i.e., it is not blank).
The minimum amount of code memory that may be
erased at a given time is 64 bytes. Again, the device
must be placed in Single Panel Write mode. The
EECON1 register must then be used to erase the
64-byte target space prior to writing the data.
When using the EECON1 register to act on code
memory, the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).
The WREN bit must be se t (EECON1<2> = 1) to enable
writes of an y s ort (e. g., erases), and this mu st b e done
prior to initiating a write sequence. The FREE bit must
be set (EECO N1<4> = 1) i n order to e rase the pro gram
spa ce bei ng pointed t o by the Table Pointer. The e ras e
sequence is initiated by the setting the WR bit
(EECON1< 1> = 1). It is stron gly recomm ended tha t the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 re gister , EECON2 i s used to “enable ” the WR
bit. This register must be sequentially loaded with 55h
and then, AAh, immediately prior to asserting the WR
bit in order for the write to occur.
The erase wil l begin on the falling edge of the 4th SCLK
after the WR bit is set.
After the erase sequence terminates, SCLK must still
be hel d lo w f or t h e t i me sp ec if i ed by par a me t er P 10 t o
allow high voltage discharge of the memory array.
FIGURE 3-7: PROGRAM CODE
MEMORY FLOW
Start Write Sequence
All
locations
done?
No
End
Start
Yes
Delay P9 and
Pull SCLK Low
Load 8 Bytes
to Write Buffer
at <Addr>
and Hold SCLK
High Until Done
Configure
Device for
Single Panel Write
Delay P10
Increment Address
by 8
2010 Microchip Technology Inc. Preliminary DS30480C-page 15
PIC18FXX39
TABLE 3-5: MODIFYING CODE MEMORY
4-bit Command Data Payload Core Instruction
Step 1: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes.
S t ep 2: Direct access to code memory.
0000
0000
8E A6
9C A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
S tep 3: Set the Table Pointer for the block to be erased.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 4: Enable memory writes and setup an erase.
0000
0000
84 A6
88 A6
BSF EECON1, WREN
BSF EECON1, FREE
Step 5: Perform Data EEPROM unlock sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 0X55
MOVWF EECON2
MOVLW 0XAA
MOVWF EECON2
Step 6: Initiate erase.
0000
0000
82 A6
00 00
BSF EECON1, WR
NOP
Step 7: Wait for P11+P 10 and then disable writes.
0000 94 A6 BCF EECON1, WREN
Step 8: Load write buffer for panel. Correct panel will be selected based on the Table Pointer.
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold SCLK high for time P9
To continue writing data, repeat step 8, where the Address Pointer is incremented by 8 at each iteration of the loop.
PIC18FXX39
DS30480C-page 16 Preliminary 2010 Microchip Technology Inc.
3.4 Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a data latch, EEDATA.
Data EEPROM is written by loading EEADR with the
desired memory location, EEDATA with the data to be
writ ten, an d initi ating a m emory w rite by approp riately
configuring the EECON1 and EECON2 registers. A
byte write automatically erases the location and writes
the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, the EEPGD bit must be cleared
(EECON1<7> = 0) and the CFGS bit must be cleared
(EECON1<6> = 0). The WREN bit must be set
(EECON1< 2> = 1) to enable writes o f any s ort, and this
must be done prior to initiating a write sequence. The
write sequence is initiated by the setting the WR bit
(EECON1< 1> = 1). It is stron gly recomm ended tha t the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 re gister , EECON2 i s used to “enable ” the WR
bit. This register must be sequentially loaded with 55h
and then, AAh, immediately prior to asserting the WR
bit in order for the write to occur.
The writ e wil l begin on the fa lling e dge of th e 4th SCLK
after the WR bit is set.
After the programming sequence terminates, SCLK
must still be held low for the time specified by
parameter P10 to allow high voltage discharge of the
memory array.
FIGURE 3-8: PROGRAM DATA FLOW
FIGURE 3-9: DATA EEPROM WRITE TIMING
Start
St art Write
Set D a ta
Done
No
Yes
Done?
Delay P11+P10
Enable Write
Unlock Sequence
55h - EECON2
AAh - EECON2
Sequence
Set Address
for Write to Occur
n
SCLK
SDATA
SDATA = Input
0000
Data EEPROM
0000
BSF EECON1, WR
4-bit Command
1234 121516 123
P5 P5A P11
P10 12
412 1516
P5
123
P5A
4
0000 0000 n
4-bit Command 4-bit Command
16-bit
Data Payload Write Time 16-bit
Data Payload
2010 Microchip Technology Inc. Preliminary DS30480C-page 17
PIC18FXX39
TABLE 3-6: PROGRAMMING DATA MEMORY
4-bit Command Data Payload Core Instruction
Step 1: Direct access to Data EEPROM.
0000
0000 9E A6
9C A6 BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the Data EEPROM Address Pointer.
0000
0000 0E <Addr>
6E A9 MOVLW <Addr>
MOVWF EEADR
Step 3: Load the data to be written.
0000
0000 0E <Data>
6E A8 MOVLW <Data>
MOVWF EEDATA
Step 4: Enable memory writes.
0000 84 A6 BSF EECON1, WREN
Step 5: Perform Dat a EEPROM unlock sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 0X55
MOVWF EECON2
MOVLW 0XAA
MOVWF EECON2
Step 6: Initiate write.
0000
0000
0000
82 A6
00 00
00 00
BSF EECON1, WR
NOP
Hold SDATA low until write completes
Step 7: Wait for P11 and then disable writes.
0000 94 A6 BCF EECON1, WREN
Repeat steps 2 through 7 to write more data.
PIC18FXX39
DS30480C-page 18 Preliminary 2010 Microchip Technology Inc.
3.5 ID Location Programming
The ID locations are programmed much like the code
memory, except that multi-panel writes must be
disabled. The single panel that will be written will
automatically be enabled, based on the value of the
Table Pointer. The ID registers are mapped in
address es 20 0000h throug h 2000 07h. T hese locat ions
read out normal ly, even after code prote ct ion .
Table 3-7 demon strates the code seque nce required to
write the ID locations.
TABLE 3-7: WRITE ID SEQUENCE
Note: For single panel programming, the user
must still fill the 8-byte data buffer for the
panel.
4-bit Command Data Payload Core Instruction
Step 1: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes.
Step 2: Direct access to code memory.
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 3: Load write buffer. Panel will be automatically determined by address.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold SCLK high for time P9
2010 Microchip Technology Inc. Preliminary DS30480C-page 19
PIC18FXX39
3.6 Boot Block Programming
The Boot Block segment is programmed in exactly the
same manner as the ID locations (see Section 3.5).
Multi-panel writes must be disabled so that only
address es in the rang e 000 0h to 01 FFh wil l be wr itte n.
The code sequence detailed in Table 3-7 should be
used, ex cept t hat the addres s dat a use d in “Step 3” will
be in the range 000000h to 0001FFh.
3.7 Configuration Bits Programming
Unlike code memory, the configuration bits are
programmed a byte at a time. The “Table Write, Begin
Programming” 4-bit command (1111) is use d, bu t onl y
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses,
and the MSB will be written to odd addresses. The
code sequence to program two consecutive
configuration locations is shown in Figure 3-8.
TABLE 3-8: SET ADDRESS POINTER TO CONFIGURATION LOCATION
FIGURE 3-10: CONFIGURATION PROGRAMMING FLOW
4-bit Command Data Payload Core Instruction
Step 1: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes.
Step 2: Direct access to configuration memory.
0000
0000 8E A6
8C A6 BSF EECON1, EEPGD
BSF EECON1, CFGS
Step 3: Set Table Pointer for configuration word to be written. Write even/odd addresses.
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
INCF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
Load Even
Configuration
Start
Program Program
MSB
Done
Delay P9 Time
for Writ e
Delay P9 Time
for Wr i te
LSB
Load Odd
Configuration
Address Address
Done
Start
PIC18FXX39
DS30480C-page 20 Preliminary 2010 Microchip Technology Inc.
4.0 READING THE DEVICE
4.1 Read Data EEPROM Memory
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a data latch, EEDATA.
Data EEPROM is read by loading EEADR with the
desir ed memor y locat ion and in itiat ing a memor y read
by appropriately configuring the EECON1 register . The
data will be loaded into EEDATA, where it may be
serially output on SDA TA via the 4-bit command, ‘0010’
(shift out data holding register). A delay of P6 must be
introduc ed af ter th e fal li ng ed ge o f the 8th SCLK of th e
operand to allow SDATA to transition from an input to
an output. During this time, SCLK must be held low
(see Figure 4-2).
The command sequence to read a single byte of data
is shown in Table 4-1.
FIGURE 4-1: READ DATA E EPROM
FLOW
TABLE 4-1: READ DATA EEPROM MEMORY
FIGURE 4-2: SHIFT OUT DATA HOLDING REGISTER TIMING (0010)
Start
Set
Address
Read
Byte
Done
No
Yes
Done?
Move to TABLAT
Shift O ut D a ta
4-bit Command Data Payload Core Instruction
Step 1: Direct access to Data EEPROM.
0000
0000 9E A6
9C A6 BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the Data EEPROM Address Pointer.
0000
0000 0E <Addr>
6E A9 MOVLW <Addr>
MOVWF EEADR
Step 3: Initiate a memory read.
0000 80 A6 BSF EECON1, RD
Step 4: Load data into the serial data holding register.
0000
0000
0010
50 A8
6E F5
<LSB><MSB>
MOVF EEDATA, W, 0
MOVWF TABLAT
Shift Out Data(1)
Note 1: The <LSB> is undefined; the <MSB> is the data.
1234
SCLK P5
SDATA
SDATA = Input
Shift Data Out
P6
SDATA = Output
5678 1234
P5A
91011 13 15161412
Fetch Next 4-bit Command
0100
SDATA = Input
LSb MSb
123456
1234
nnnn
P14
2010 Microchip Technology Inc. Preliminary DS30480C-page 21
PIC18FXX39
4.2 Read Code Memory, ID Locations,
and Configurati on Bits
Code memory is accessed one byte at a time, via the
4-bit command, ‘1001’ (Table Read, post-increment).
The co ntents of memory p ointed to by the Table Poin ter
(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the
Table Latch an d then serially output on SDATA.
The 4-bit command is shifted in LSb first. The Table
Read is execu ted duri ng the nex t 8 cloc ks, the n shif ted
out on SDATA during the last 8 clocks, LSb to MSb. A
delay of P6 mu st be introduc ed af ter the fall ing edg e of
the 8th SCLK of the operand to allow SDATA to
transition from an input to an output. During this time,
SCLK mu st be he ld low (s ee Table 4-2). This opera tion
also increments the Table Pointer by one, pointing to
the next byte in code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh addre ss s p a ce, s o i t a ls o a ppl ie s
to the reading of the ID and configuration registers.
TABLE 4-2: READ CODE MEMORY SEQUENCE
FIGURE 4-3: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
4-bit Command Data Payload Core Instruction
Step 1: Set Table Pointer.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 2: Read memory into Table Latch and then shift out on SDATA, LSb to MSb.
1001 00 00 TBLRD *+
1234
SCLK P5
SDATA
SDATA = Input
Shift Data Out
P6
SDATA = Output
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-bit Command
1001
SDATA = Input
LSb MSb
123456
1234
nnnn
P14
PIC18FXX39
DS30480C-page 22 Preliminary 2010 Microchip Technology Inc.
4.3 Verify Code Memory and ID
Locations
The veri fy step invo lves read ing back the code memo ry
space and comparing against the copy held in the
programmer’s buffer. Memory reads occur a single byte
at a time, so two bytes must be read to compare
against the word in the programmer’s buffer. Refer to
Section 4.2 for implementation details of reading code
memory.
The Table Pointer must be manually set to 200000h
(base address of the ID locations) once the code
memory has been verified. The post-increment feature
of the Table Read 4-bit command may not be used to
increme nt the Table Pointer bey on d 1FFFFF h.
FIGURE 4-4: VERIFY CODE MEMORY FLOW
4.4 Verify Configuration Bits
A configuration address may be read and output on
SDATA via the 4-bit command, ‘1001’. Configuration
data is read and written in a byte-wise fashion, so it is
not nec essary t o merg e two by tes into a word p rior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.2 for implementation details of reading
configu r ati on data.
4.5 Verify Data EEPROM
A data EEPROM add ress may b e re ad vi a a seque nc e
of core instructions (4-bit command, ‘0000’) and then
output on SDATA via the 4-bit command, ‘0010’ (shift
out data holding register). The result may then be
immediately compared to the appropriate data in the
programmer’s memory for verification. Refer to
Section 4.1 for implementation details of reading data
EEPROM.
Read Low Byte
Read High Byte
Does
word = expect
data? Failure,
Report
Error
All
code memory
verified?
No
Yes
No
Set Pointer = 0
Start
Set Pointer = 200000h
Yes
Read Low Byte
Read High Byte
Does
word = expect
data? Failure,
Report
Error
All
ID locations
verified?
No
Yes
Done
Yes
No
2010 Microchip Technology Inc. Preliminary DS30480C-page 23
PIC18FXX39
5.0 CONFIGURATION WORD
The PIC18FXX39 has several configuration words.
These bits can be set or cleared to select various
device configurations. All other memory areas should
be programmed and verified prior to setting
configuration words. These bits may be read out
normally, even after read or code protected.
5.1 ID Locations
A user may sto re ide ntif ic atio n inf orm atio n (ID) in eight
ID locations mapped in 200000h:200007h. It is
recommended that the Most Significant nibble of each
ID be 0Fh. In doing so, if the user code inadvertently
tries to execute from the ID space, the ID data will
execute as a NOP.
5.2 Device ID W ord
The device ID word for the PIC18FXX39 is located at
3FFFFEh:3FFFFFh. These bits may be used by the
programmer to identify what device type is being
progra mmed an d re ad out norm al ly, even af te r co de or
read protect ed.
5.3 Low Voltage Programming
(LVP) Bit
The LVP bit in configuration register, CONFIG4L,
enables low voltage ICSP programming. The LVP bit
defaults to a ‘1’ from the factory.
If Low V ol tage Program ming mode is no t used, the L V P
bit can be pro grammed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be
progra mmed b y ent erin g the H ig h Voltag e I C SP mod e,
where M CLR/VPP is raised to VIHH. On ce the LVP bit i s
progra mmed to a ‘0’, only t he Hi gh Voltage ICSP mod e
is available and only the High Voltage ICSP mode can
be used to program the device.
TABLE 5-1: DEVICE ID VALUE
Note 1: The normal ICSP mode is always avail-
able, re gardless of the state o f the LVP bit,
by applying VIHH to the MCLR/VPP pin.
2: While in Low Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purp os e I/O.
Device Device ID Value
DEVID2 DEVID1
PIC18F2439 04h 100x xxxx
PIC18F2539 04h 000x xxxx
PIC18F4439 04h 101x xxxx
PIC18F4539 04h 001x xxxx
PIC18FXX39
DS30480C-page 24 Preliminary 2010 Microchip Technology Inc.
TABLE 5-2: PIC18FXX39 CONFIGURATION BITS AND DEVICE IDs
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Erased or
“Blank” Value
300000h CONFIG1L — — — — — — — — 0000 0000
300001h CONFIG1H ———
(1) —— FOSC2 FOSC1 FOSC0 0010 0111
300002h CONFIG2L — — — — BORV1 BORV2 BOREN PWRTEN 0000 1111
300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN 0000 1111
300004h CONFIG3L — — — — — — — — 0000 0000
300005h CONFIG3H — — — — — — — —(1) 0000 0001
300006h CONFIG4L BKBUG ————LVP—STVREN1000 0101
300007h CONFIG4H — — — — — — — — 0000 0000
300008h CONFIG5L — — — — —(1) CP2 CP1 CP0 0000 1111
300009h CONFIG5H CPD CPB — — — — — — 1100 0000
30000Ah CONFIG6L — — — — —(1) WRT2 WRT1 WRT0 0000 1111
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 1110 0000
30000Ch CONFIG7L — — — — —(1) EBTR2 EBTR1 EBTR0 0000 1111
30000Dh CONFIG7H —EBTRB— — — — — — 0100 0000
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1
Note 1: Unimplemented, but reserved; maintain this bit set.
2: Shaded cells are unimplemented, read as ‘0’.
2010 Microchip Technology Inc. Preliminary DS30480C-page 25
PIC18FXX39
TABLE 5-3: PIC18FXX39 BIT DESCRIPTION
Bit Name Configuration
Words Description
FOSC2:FOSC0 CONFIG1H Oscillator Selection bits
111 = Reserved
110 = HS oscillator w/ PLL enabled
101 = EC oscillator w/ OSC2 configured as RA6
100 = EC oscillator w/ OSC2 configured as “divide by 4 clock output”
011 = Reserved
010 = HS oscillator
001 = Reserved
000 = Reserved
BORV1:BORV0 CONFIG2L Brown-out Reset Voltage bits
11 =V
BOR set to 2.0V
10 =V
BOR set to 2.7V
01 =V
BOR set to 4.2V
00 =V
BOR set to 4.5V
BOREN CONFIG2L Brown-out Reset Enable bit
1 = Brown-out Rese t enabl ed
0 = Brown-out Re se t disa ble d
PWRTEN CONFIG2L Power-up Ti mer Enable bit
1 = PWRT disabl ed
0 = PWRT enabled
WDTPS2:WDTPS0 CONFIG2H Watchdog Timer Postscaler Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
WDTEN CONFIG2H Watchdog Timer Enable bit
1 = WDT enable d
0 = WDT disabled (control is placed on SWDTEN bit)
BKBUG CONFIG4L Background Debugger Enable bit
1 = Back ground debugg er dis abl ed
0 = Back ground debugg er enab led
LVP CONFIG4L Low Voltage Programming Enable bit
1 = Low volt age program mi ng ena ble d
0 = Low volt age program mi ng dis ab led
STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit
1 = Stack overflow/un derf low will cause RESET
0 = Stack overflow/un derflow will not cause RESET
CP0 CONFIG5L Code Protection bits (code memory area 0200h - 1FFFh)
1 = Code memo ry not co de pr ote cte d
0 = Code memory code protected
CP1 CONFIG5L Code Protection bits (code memory area 2000h - 3FFFh)
1 = Code memo ry not co de pr ote cte d
0 = Code memory code protected
CP2 CONFIG5L Code Protection bits (code memory area 4000h - 5FFFh)
1 = Code memo ry not co de pr ote cte d
0 = Code memory code protected
PIC18FXX39
DS30480C-page 26 Preliminary 2010 Microchip Technology Inc.
CPD CONFIG5H Code Protection bits (data EEPROM)
1 = Data EEPROM not code protected
0 = Data EEPROM code protected
CPB CONFIG5H Code Protection bits (boot block, memory area 0000h - 01FFh)
1 = Boot block not code protected
0 = Boot block code protected
WRT0 CONFIG6L Table Write Protection bit (code memory area 0200h - 1FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT1 CONFIG6L Table Write Protection bit (code memory area 2000h - 3FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT2 CONFIG6L Table Write Protection bit (code memory area 4000h - 5FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRTD CONFIG6H Ta ble Write Protection bit (data EEPROM)
1 = Data EEPROM not write protected
0 = Data EEPROM write protected
WRTB CONFIG6H Table Write Protection bit (boot block, memory area 0000h - 01FFh)
1 = Boo t bloc k not write protected
0 = Boo t bloc k wr ite prot ect ed
WRTC CONFIG6H Table Write Protection bit (Configuration registers)
1 = Configuration registers not write protected
0 = Configuration registers write protected
EBTR0 CONFIG7L Table Read Protection bit (code memory area 0200h - 01FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTR1 CONFIG7L Table Read Protection bit (code memory area 2000h - 3FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTR2 CONFIG7L Table Read Protection bit (code memory area 4000h - 5FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTRB CONFIG7H Table Read Protection bit (boot block, memory area 0000h - 01FFh)
1 = Boot block not protected from table reads executed in other blocks
0 = Boot block protected from table reads executed in other blocks
DEV10:DEV3 DEVID2 Device ID bits are used with the DEV2:DEV0 bits in the DEVID1 register to
identify part number.
DEV2:DEV0 DEVID1 Device ID bits are used with the DEV10:DEV3 bits in the DEVID2 register to
identify part number.
REV4:REV0 DEVID1 These bits are used to indicate the revision of the device.
TABLE 5-3: PIC18FXX39 BIT DESCRIPTION (CONTINUED)
Bit Name Configuration
Words Description
2010 Microchip Technology Inc. Preliminary DS30480C-page 27
PIC18FXX39
5.4 Embedding Configuration Word
Info rmation in th e H E X Fi le
To allow portability of code, a PIC18FXX39
prog r am mer is r e qui r ed to r e ad th e c o nf i gur a ti on w ord
locations from the HEX file. If configuration word
informa tion is not prese nt in the HEX file, then a sim ple
warning message should be issued. Similarly, while
saving a HEX file, all configuration word information
must be included. An option to not include the
configu ration word informatio n may be provided. Whe n
embedding configuration word information in the HEX
file, it should start at address 300000h.
Microchip Technology Inc. feels strongly that this
featur e is imp orta nt for th e bene fit of t he end cu stome r.
5.5 Checksum Comput ation
The check s um is cal cu lat ed by sum mi ng the foll owing:
• The conte nts of all code me mory locations
• The configuration word, appropriately masked
• ID locations
The Least Significant 16 bits of this sum are the
checksum.
Table 5-4 describes how to calculate the checksum for
each device.
Note 1: The checksum calculation differs depend-
ing on the c ode pro tect settin g. Sin ce the
code memory locations read out differ-
ently depending on the code protect set-
ting, the table describes how to
manipulate the actual code memory val-
ues to simulate the values that would be
read from a protected device. When cal-
culating a checksum by reading a device,
the entire code memory can simply be
read and summed. The configuration
word and ID locations can always be read.
PIC18FXX39
DS30480C-page 28 Preliminary 2010 Microchip Technology Inc.
TABLE 5-4: CHECKSUM COMPUTATION
Device Code Protect
or Mode Checksum Calculation Method Blank
Checksum Seed
at 0 Seed at 0
and Max
PIC18F2439 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+
SUM(4000:5FFF)+(CONFI G0 & 0000)+(CONFI G1 & 0027)+
(CONFIG2 & 000F)+(CONFIG3 & 000F)+(CONFIG4 & 0000)+
(CONFIG5 & 0000)+(CONFIG6 & 0085)+(CO NFI G7 & 0000)+
(CONFIG8 & 0007)+(CONFIG9 & 00C0)+(CO NFI G1 0 & 0007)+
(CONFIG11 & 00E0)+(CONFIG12 & 0007)+(CONFIG13 & 0040)
A2BF A26A A215
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+
(CONFIG0 & 0000)+(CONFIG1 & 0027)+(CO NFI G2 & 000F)+
(CONFIG3 & 000F)+(CONF IG4 & 0000)+(CO NFIG5 & 0000)+
(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CO NFI G8 & 0007)+
(CONFIG9 & 00C0)+(CONFIG10 & 0007)+(CONF I G11 & 00E0)+
(CONFIG12 & 0007)+(CONFIG13 & 0040)+S UM(I Ds)
A4A5 A49B A43C
Boot/Panel 1/
Panel 2 SUM(4000:5FFF)+(CONFIG0 & 0000)+(CONFIG 1 & 0027)+
(CONFIG2 & 000F)+(CONFIG3 & 000F)+(CONFIG4 & 0000)+
(CONFIG5 & 0000)+(CONFIG6 & 0085)+(CO NFI G7 & 0000)+
(CONFIG8 & 0007)+(CONFIG9 & 00C0)+(CO NFI G1 0 & 0007)+
(CONFIG11 & 00E0)+(CONFIG12 & 0007)+(CONFIG13 & 0040)+
SUM(IDs)
E2A2 E298 E239
All (CONFIG0 & 0000)+(CONFIG1 & 0027)+(CONF IG2 & 000F)+
(CONFIG3 & 000F)+(CONF IG4 & 0000)+(CO NFIG5 & 0000)+
(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CO NFI G8 & 0007)+
(CONFIG9 & 00C0)+(CONFIG10 & 0007)+(CONF I G11 & 00E0)+
(CONFIG12 & 0007)+(CONFIG13 & 0040)+S UM(I Ds)
029E 0294 028A
PIC18F2539 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+
SUM(4000:5FFF)+(CONFI G0 & 0000)+(CONFI G1 & 0027)+
(CONFIG2 & 000F)+(CONFIG3 & 000F)+(CONFIG4 & 0000)+
(CONFIG5 & 0000)+(CONFIG6 & 0085)+(CO NFI G7 & 0000)+
(CONFIG8 & 0007)+(CONFIG9 & 00C0)+(CO NFI G1 0 & 0007)+
(CONFIG11 & 00E0)+(CONFIG12 & 0007)+(CONFIG13 & 0040)
A2BF A26A A215
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+
(CONFIG0 & 0000)+(CONFIG1 & 0027)+(CO NFI G2 & 000F)+
(CONFIG3 & 000F)+(CONF IG4 & 0000)+(CO NFIG5 & 0000)+
(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CO NFI G8 & 0007)+
(CONFIG9 & 00C0)+(CONFIG10 & 0007)+(CONF I G11 & 00E0)+
(CONFIG12 & 0007)+(CONFIG13 & 0040)+S UM(I Ds)
A4A5 A49B A43C
Boot/Panel 1/
Panel 2 SUM(4000:5FFF)+(CONFIG0 & 0000)+(CONFIG 1 & 0027)+
(CONFIG2 & 000F)+(CONFIG3 & 000F)+(CONFIG4 & 0000)+
(CONFIG5 & 0000)+(CONFIG6 & 0085)+(CO NFI G7 & 0000)+
(CONFIG8 & 0007)+(CONFIG9 & 00C0)+(CO NFI G1 0 & 0007)+
(CONFIG11 & 00E0)+(CONFIG12 & 0007)+(CONFIG13 & 0040)+
SUM(IDs)
E2A2 E298 E239
All (CONFIG0 & 0000)+(CONFIG1 & 0027)+(CONF IG2 & 000F)+
(CONFIG3 & 000F)+(CONF IG4 & 0000)+(CO NFIG5 & 0000)+
(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CO NFI G8 & 0007)+
(CONFIG9 & 00C0)+(CONFIG10 & 0007)+(CONF I G11 & 00E0)+
(CONFIG12 & 0007)+(CONFIG13 & 0040)+S UM(I Ds)
029E 0294 028A
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND
2010 Microchip Technology Inc. Preliminary DS30480C-page 29
PIC18FXX39
PIC18F4439 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+
SUM(4000:5FFF)+(CONFI G0 & 0000)+(CONFI G1 & 0027)+
(CONFIG2 & 000F)+(CONFIG3 & 000F)+(CONFIG4 & 0000)+
(CONFIG5 & 0000)+(CONFIG6 & 0085)+(CO NFI G7 & 0000)+
(CONFIG8 & 0007)+(CONFIG9 & 00C0)+(CO NFI G1 0 & 0007)+
(CONFIG11 & 00E0)+(CONFIG12 & 0007)+(CONFIG13 & 0040)
A2BF A26A A215
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+
(CONFIG0 & 0000)+(CONFIG1 & 0027)+(CO NFI G2 & 000F)+
(CONFIG3 & 000F)+(CONF IG4 & 0000)+(CO NFIG5 & 0000)+
(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CO NFI G8 & 0007)+
(CONFIG9 & 00C0)+(CONFIG10 & 0007)+(CONF I G11 & 00E0)+
(CONFIG12 & 0007)+(CONFIG13 & 0040)+S UM(I Ds)
A4A5 A49B A43C
Boot/Panel 1/
Panel 2 SUM(4000:5FFF)+(CONFIG0 & 0000)+(CONFIG 1 & 0027)+
(CONFIG2 & 000F)+(CONFIG3 & 000F)+(CONFIG4 & 0000)+
(CONFIG5 & 0000)+(CONFIG6 & 0085)+(CO NFI G7 & 0000)+
(CONFIG8 & 0007)+(CONFIG9 & 00C0)+(CO NFI G1 0 & 0007)+
(CONFIG11 & 00E0)+(CONFIG12 & 0007)+(CONFIG13 & 0040)+
SUM(IDs)
E2A2 E298 E239
All (CONFIG0 & 0000)+(CONFIG1 & 0027)+(CONF IG2 & 000F)+
(CONFIG3 & 000F)+(CONF IG4 & 0000)+(CO NFIG5 & 0000)+
(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CO NFI G8 & 0007)+
(CONFIG9 & 00C0)+(CONFIG10 & 0007)+(CONF I G11 & 00E0)+
(CONFIG12 & 0007)+(CONFIG13 & 0040)+S UM(I Ds)
029E 0294 028A
PIC18F4539 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+
SUM(4000:5FFF)+(CONFI G0 & 0000)+(CONFI G1 & 0027)+
(CONFIG2 & 000F)+(CONFIG3 & 000F)+(CONFIG4 & 0000)+
(CONFIG5 & 0000)+(CONFIG6 & 0085)+(CO NFI G7 & 0000)+
(CONFIG8 & 0007)+(CONFIG9 & 00C0)+(CO NFI G1 0 & 0007)+
(CONFIG11 & 00E0)+(CONFIG12 & 0007)+(CONFIG13 & 0040)
A2BF A26A A215
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+
(CONFIG0 & 0000)+(CONFIG1 & 0027)+(CO NFI G2 & 000F)+
(CONFIG3 & 000F)+(CONF IG4 & 0000)+(CO NFIG5 & 0000)+
(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CO NFI G8 & 0007)+
(CONFIG9 & 00C0)+(CONFIG10 & 0007)+(CONF I G11 & 00E0)+
(CONFIG12 & 0007)+(CONFIG13 & 0040)+S UM(I Ds)
A4A5 A49B A43C
Boot/Panel 1/
Panel 2 SUM(4000:5FFF)+(CONFIG0 & 0000)+(CONFIG 1 & 0027)+
(CONFIG2 & 000F)+(CONFIG3 & 000F)+(CONFIG4 & 0000)+
(CONFIG5 & 0000)+(CONFIG6 & 0085)+(CO NFI G7 & 0000)+
(CONFIG8 & 0007)+(CONFIG9 & 00C0)+(CO NFI G1 0 & 0007)+
(CONFIG11 & 00E0)+(CONFIG12 & 0007)+(CONFIG13 & 0040)+
SUM(IDs)
E2A2 E298 E239
All (CONFIG0 & 0000)+(CONFIG1 & 0027)+(CONF IG2 & 000F)+
(CONFIG3 & 000F)+(CONF IG4 & 0000)+(CO NFIG5 & 0000)+
(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CO NFI G8 & 0007)+
(CONFIG9 & 00C0)+(CONFIG10 & 0007)+(CONF I G11 & 00E0)+
(CONFIG12 & 0007)+(CONFIG13 & 0040)+S UM(I Ds)
029E 0294 028A
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
Device Code Protect
or Mode Checksum Calculation Method Blank
Checksum Seed
at 0 Seed at 0
and Max
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND
PIC18FXX39
DS30480C-page 30 Preliminary 2010 Microchip Technology Inc.
5.6 Embedding Data EEPROM
Info rmation In th e H E X Fi le
To allow portability of code, a PIC18FXX39
programmer is required to read the data EEPROM
information from the HEX file. If data EEPROM
info rmatio n is not present , a simpl e warnin g messa ge
should be issu ed. Sim ila rly, when sa vi ng a HEX file, all
data EEPROM inform ation must be inc luded. An optio n
to not include the data EEPROM information may be
provide d. When embeddi ng data EEPROM information
in the HEX file, it should start at address F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.
2010 Microchip Technology Inc. Preliminary DS30480C-page 31
PIC18FXX39
6.0 AC/DC CHA RACTERISTICS TIMING REQUIREMENTS FOR
PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operati ng Temperature: 25C is recommended
Param
No. Sym Characteristic Min Max Units Conditions
D110 VIHH High Voltage Programming Voltage on
MCLR/VPP 9.00 13.25 V
D110A VIHLLow Voltage Programming Voltage on
MCLR/VPP 2.00 5.50 V
D111 VDD Supply Voltage during Programming 2.00 5.50 V Normal
programming
4.50 5.50 V Bulk erase
operations
D112 IPP Programming Current on MCLR/VPP —300µA
D113 IDDP Supply Current during Programming — 1 mA
D031 VIL Input Low Voltage VSS 0.2 VSS V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA
D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA
D012 CIO Capacitive Loading on I/O pin
(SDATA) — 50 pF To meet AC
specifications
P2 Tsclk Serial Clock (SCLK) Period 100 — ns VDD = 5.0V
1—µsV
DD = 2.0V
P2A TsclkL Serial Clock (SCLK) Low Time 40 — ns VDD = 5.0V
400 — ns VDD = 2.0V
P2B TsclkH Serial Cl oc k (SCLK) High Time 40 — ns VDD = 5.0V
400 — ns VDD = 2.0V
P3 Tset1 Input Data Setup Time to Serial Clock 15 — ns
P4 Thld1 Input Data Hold Time from SCLK 15 — ns
P5 Tdly1 Delay between 4-bit Command and
Command Operand 20 — ns
P5A Tdly1a Delay between 4-bit Command
Operand and next 4-bit Command 20 — ns
P6 Tdly2 Delay between Last SCLK of
Command Byte to First SCLK of
Read of Data Word
20 — ns
P9 Tdly5 SCLK High Time
(minimum programming time) 1—ms
P10 Tdly6 S CLK Low Time after Programming
(high voltage discharge time) 5—µs
P11 Td ly7 Delay to allow Sel f-T im ed Dat a W rite or
Bulk Erase to occur 10 — ms
P12 Thld2 Input D a t a Hold Time from MCLR /VPP 2—µs
P13 Tset2 VDD Setup Ti me to MCLR/VPP 100 — ns
P14 Tvalid Data Out Val id from SCLK 10 — ns
P15 Tset3 PGM Setup Time to MCLR/VPP 2—µs
PIC18FXX39
DS30480C-page 32 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS30480C-page 33
Information contained in this publication regarding device
applications a nd t he lik e is provided only for yo ur conve nience
and may be superseded by updates . It is y our respo n s ibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PI CSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor ,
MXDEV, MXLAB, SEEVAL and The Em bedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Cert ified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Inc orporated, Pr inted in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of t he most secure famili es of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Mill ennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCU s and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS30480C-page 34 Preliminary 2010 Microchip Technology Inc.
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