LT3800EFE#PBF - LINEAR TECHNOLOGY

LT3800

3800fc

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

High-Voltage Synchronous

Current Mode Step-Down

Controller

The LT

3800 is a 200kHz ﬁ xed frequency high voltage

synchronous current mode step-down switching regulator

controller. The IC drives standard gate N-channel power

MOSFETs and can operate with input voltages from 4V to

60V. An onboard regulator provides IC power directly from

VIN and provides for output-derived power to minimize

VIN quiescent current. MOSFET drivers employ an internal

dynamic bootstrap feature, maximizing gate-source “ON”

voltages during normal operation for improved operating

efﬁ ciencies. The LT3800 incorporates Burst Mode

opera-

tion, which reduces no load quiescent current to under

100µA. Light load efﬁ ciencies are also improved through

a reverse inductor current inhibit, allowing the controller

to support discontinuous operation. Both Burst Mode

operation and the reverse-current inhibit features can be

disabled if desired. The LT3800 incorporates a program-

mable soft-start that directly controls the voltage slew rate

of the converter output for reduced startup surge currents

and overshoot errors. The LT3800 is available in a 16-lead

thermally enhanced TSSOP package.

12V 75W DC/DC Converter with Reverse Current Inhibit and Input UVLO

n Wide 4V to 60V Input Voltage Range

n Output Voltages up to 36V

n Adaptive Nonoverlap Circuitry Prevents Switch

Shoot-Through

n Reverse Inductor Current Inhibit for Discontinuous

Operation Improves Efﬁ ciency with Light Loads

n Output Slew Rate Controlled Soft-Start with

Auto-Reset

n 100µA No Load Quiescent Current

n Low 10µA Current Shutdown

n 1% Regulation Accuracy

n 200kHz Operating Frequency

n Standard Gate N-Channel Power MOSFETs

n Current Limit Unaffected by Duty Cycle

n Reverse Overcurrent Protection

n 16-Lead Thermally Enhanced TSSOP Package

n 12V and 42V Automotive and Heavy Equipment

n 48V Telecom Power Supplies

n Avionics and Industrial Control Systems

n Distributed Power Converters

Efﬁ ciency and Power Loss

VIN

SHDN

CSS

BURST_EN

VFB

SENSE–

BOOST

VCC

PGND

SENSE+

LT3800

SGND

1.5nF 200k

100pF

680pF

174k

20k

82.5k

0.015Ω

BAS19

1N4148

1µF

×3

56µF

×2

10µF 270µF

Si7850DP

Si7370DP B160

15µH

VIN

20V TO 55V

VOUT

12V AT 75W

3800 TA01a

ILOAD (A)

EFFICIENCY (%)

POWER LOSS (W)

100

3800 TA01b

0.1 1

VIN = 24V

LOSS (48V)

VIN = 48V

VIN = 60V

VIN = 36V

L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks

and No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U.S. Patents including

5481178, 6611131, 6304066, 6498466, 6580258.

LT3800

3800fc

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

Supply Voltages

Input Supply Pin (VIN) ............................... –0.3V to 65V

Boosted Supply Pin (BOOST) .................... –0.3V to 80V

Boosted Supply Voltage (BOOST – SW) ... –0.3V to 24V

Boosted Supply Reference Pin (SW) ............ –2V to 65V

Local Supply Pin (VCC) .............................. –0.3V to 24V

Input Voltages

SENSE+, SENSE– ...................................... –0.3V to 40V

SENSE+ – SENSE– ......................................... –1V to 1V

BURST_EN Pin .......................................... –0.3V to 24V

Other Inputs (SHDN, CSS, VFB, VC) .......... –0.3V to 5.0V

Input Currents

SHDN, CSS ............................................... –1mA to 1mA

Maximum Temperatures

Operating Junction Temperature Range (Note 2)

LT3800E (Note 3) .............................. –40°C to 125°C

LT3800I ............................................. –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................. 300°C

(Note 1)

FE PACKAGE

16-LEAD PLASTIC TSSOP

TOP VIEW

VIN

SHDN

CSS

BURST_EN

VFB

SENSE–

BOOST

VCC

PGND

SENSE+

TJMAX = 125°C, θJA = 40°C/W, θJC = 10°C/W

EXPOSED PAD (PIN 17) IS SGND

MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3800EFE#PBF LT3800EFE#TRPBF 3800EFE 16-Lead Plastic TSSOP –40°C to 125°C

LT3800IFE#PBF LT3800IFE#TRPBF 3800IFE 16-Lead Plastic TSSOP –40°C to 125°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Operating Voltage Range (Note 4)

Minimum Start Voltage

UVLO Threshold (Falling)

UVLO Hysteresis

●

7.5

3.65 3.80

670

3.95

IVIN VIN Supply Current

VIN Burst Mode Current

VIN Shutdown Current

VCC > 9V

VBURST_EN = 0V, VFB = 1.35V

VSHDN = 0V

●20

815

µA

VBOOST Operating Voltage

Operating Voltage Range (Note 5)

UVLO Threshold (Rising)

UVLO Hysteresis

VBOOST – VSW

●

0.4

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,

SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted.

LT3800

3800fc

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,

SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IBOOST BOOST Supply Current (Note 6)

BOOST Burst Mode Current

BOOST Shutdown Current

VBURST_EN = 0V

VSHDN = 0V

1.4

0.1

µA

VCC Operating Voltage (Note 5)

Output Voltage

UVLO Threshold (Rising)

UVLO Hysteresis

●

●8.0

6.25

500

8.3

IVCC VCC Supply Current (Note 6)

VCC Burst Mode Current

VCC Shutdown Current

Short-Circuit Current

VBURST_EN = 0V

VSHDN = 0V

●

●–40

–120

3.6 mA

µA

VSHDN Enable Threshold (Rising)

Threshold Hysteresis

● 1.30 1.35

120

1.40 V

VSENSE Common Mode Range

Current Limit Sense Voltage

Reverse Protect Sense Voltage

Reverse Current Offset

VSENSE+ – VSENSE–

VSENSE+ – VSENSE–, VBURST_EN = VCC

VBURST_EN = 0V or VBURST_EN = VFB

●

140 150

–150

175 mV

ISENSE Input Current

(ISENSE+ + ISENSE–)

VSENSE(CM) = 0V

VSENSE(CM) = 2.75V

VSENSE(CM) > 4V

0.8

–20

–0.3

µA

fOOperating Frequency

●

190

175

200 210

220

kHz

VFB Error Amp Reference Voltage Measured at VFB Pin

●

1.224

1.215

1.231 1.238

1.245

IFB Feedback Input Current 25 nA

VFB(SS) Soft-Start Disable Voltage

Soft-Start Disable Hysteresis

VFB Rising 1.185

300

ICSS Soft-Start Capacitor Control Current 2 µA

gmError Amp Transconductance ● 275 350 400 µmhos

AVError Amp DC Voltage Gain 62 dB

VCError Amp Output Range Zero Current to Current Limit 1.2 V

IVC Error Amp Sink/Source Current ±30 µA

VTG,BG Gate Drive Output On Voltage (Note 7)

Gate Drive Output Off Voltage

9.8

0.1

tTG,BG Gate Drive Rise/Fall Time 10% to 90% or 90% to 10% 50 ns

tTG(OFF) Minimum Off Time 450 ns

tTG(ON) Minimum On Time ●300 500 ns

tNOL Gate Drive Nonoverlap Time TG Fall to BG Rise

BG Fall to TG Rise

200

150

LT3800

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ELECTRICAL CHARACTERISTICS

Shutdown Threshold (Rising)

vs Temperature

Shutdown Threshold (Falling)

vs Temperature VCC vs Temperature

VCC vs ICC(LOAD) VCC vs VIN ICC Current Limit vs Temperature

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the speciﬁ ed maximum operating junction

temperature may impair device reliability.

Note 3: The LT3800E is guaranteed to meet performance speciﬁ cations

from 0°C to 125°C junction temperature. Speciﬁ cations over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

TYPICAL PERFORMANCE CHARACTERISTICS

LT3800I is guaranteed over the full –40°C to 125°C operating junction

temperature range.

Note 4: VIN voltages below the start-up threshold (7.5V) are only

supported when VCC is externally driven above 6.5V.

Note 5: Operating range dictated by MOSFET absolute maximum gate-

source voltage ratings.

Note 6: Supply current speciﬁ cation does not include switch drive

currents. Actual supply currents will be higher.

Note 7: DC measurement of gate drive output “ON” voltage is typically

8.6V. Internal dynamic bootstrap operation yields typical gate “ON”

voltages of 9.8V during standard switching operation. Standard operation

gate “ON” voltage is not tested but guaranteed by design.

TEMPERATURE (°C)

–50 –25

1.37

1.36

1.35

1.34

1.33 100

3800 G01

0 50 12525 75

SHUTDOWN THRESHOLD, RISING (V)

–50 –25 1000 50 12525 75

TEMPERATURE (°C)

1.240

1.235

1.230

1.225

1.220

3800 G02

SHUTDOWN THRESHOLD, FALLING (V)

TEMPERATURE (°C)

–50 –25

VCC (V)

8.0

8.1

7.8

7.9

125

3800 G03

050

25 75 100

ICC = 0mA

ICC = 20mA

ICC(LOAD) (mA)

VCC (V)

3800 G04

10 20 30

8.05

8.00

7.95

7.90

7.85 51525

TA = 25°C

VIN (V)

VCC (V)

379 12

3800 G05

56 810 11

ICC = 20mA

TA = 25°C

–50 –25 1000 50 12525 75

TEMPERATURE (°C)

200

175

150

125

100

3800 G06

ICC CURRENT LIMIT (mA)

LT3800

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TYPICAL PERFORMANCE CHARACTERISTICS

VCC UVLO Threshold (Rising)

vs Temperature ICC vs VCC (SHDN = 0V)

Error Amp Transconductance

vs Temperature

I(SENSE+ + SENSE–) vs VSENSE(CM)

Operating Frequency

vs Temperature

Error Amp Reference

vs Temperature

PIN FUNCTIONS

TEMPERATURE (°C)

–50 –25 100

3800 G07

0 50 12525 75

6.30

6.25

6.20

6.15

VCC UVLO THRESHOLD, RISING (V)

VCC (V)

ICC (µA)

3800 G12

0246810

12 14 18 20

TA = 25°C

TEMPERATURE (°C)

–50 –25 1000 50 12525 75

380

360

340

320

3800 G08

ERROR AMP TRANSCONDUCTANCE (µmho)

VSENSE(CM) (V)

0 0.5 1.5 2.5 3.5 4.5

I(SENSE+ + SENSE–) (µA)

800

600

400

200

–200

–400 1.0 2.0 3.0 4.0

3800 G09

5.0

TA = 25°C

TEMPERATURE (°C)

3800 G10

–50

220

210

200

190

180

–25

OPERATING FREQUENCY (kHz)

1000 50 12525 75 –50 –25 1000 50 12525 75

TEMPERATURE (°C)

ERROR AMP REFERENCE (V)

1.232

1.231

1.230

1.229

1.228

1.227

3800 G11

VIN (Pin 1): Converter Input Supply.

NC (Pin 2): No Connection.

SHDN (Pin 3): Precision Shutdown Pin. Enable threshold

is 1.35V (rising) with 120mV of input hysteresis. When

in shutdown mode, all internal IC functions are disabled.

The precision threshold allows use of the SHDN pin to

incorporate UVLO functions. If the SHDN pin is pulled

below 0.7V, the IC enters a low current shutdown mode

with IVIN < 10µA. In low-current shutdown, the IC will

sink 20µA from the VCC pin until that local supply has

collapsed. Typical pin input bias current is <10nA and the

pin is internally clamped to 6V.

CSS (Pin 4): Soft-Start AC Coupling Capacitor Input.

Connect capacitor (CSS) in series with a 200k resistor

from pin to converter output (VOUT). Controls converter

start-up output voltage slew rate (∆VOUT/∆t). Slew rate

corresponds to 2µA average current through the soft-start

coupling capacitor. The capacitor value for a desired output

startup slew rate follows the relation:

SS = 2µA/(∆VOUT/∆t)

Shorting this pin to SGND disables the soft-start function

BURST_EN (Pin 5): Burst Mode Operation Enable Pin.

This pin also controls reverse-inhibit mode of operation.

When the pin voltage is below 0.5V, Burst Mode operation

LT3800

3800fc

PIN FUNCTIONS

and reverse-current inhibit functions are enabled. When

the pin voltage is above 0.5V, Burst Mode operation is dis-

abled, but reverse-current inhibit operation is maintained.

DC/DC converters operating with reverse-current inhibit

operation (BURST_EN = VFB) have a 1mA minimum load

requirement. Reverse-current inhibit is disabled when the

pin voltage is above 2.5V. This pin is typically shorted to

ground to enable Burst Mode operation and reverse-current

inhibit, shorted to VFB to disable Burst Mode operation

while enabling reverse-current inhibit, and connected

to VCC pin to disable both functions. See Applications

Information section.

VFB (Pin 6): Error Ampliﬁ er Inverting Input. The noninvert-

ing input of the error ampliﬁ er is connected to an internal

1.231V reference. Desired converter output voltage (VOUT)

is programmed by connecting a resistive divider from the

converter output to the VFB pin. Values for the resistor

connected from VOUT to VFB (R2) and the resistor con-

nected from VFB to ground (R1) can be calculated via the

following relationship:

R2 =R1• VOUT

1.231–1











The VFB pin input bias current is 25nA, so use of extremely

high value feedback resistors could cause a converter

output that is slightly higher than expected. Bias current

error at the output can be estimated as:

∆VOUT(BIAS) = 25nA • R2

VC (Pin 7): Error Ampliﬁ er Output. The voltage on the VC

pin corresponds to the maximum (peak) switch current per

oscillator cycle. The error ampliﬁ er is typically conﬁ gured

as an integrator by connecting an RC network from this

pin to ground. This network creates the dominant pole for

the converter voltage regulation feedback loop. Speciﬁ c

integrator characteristics can be conﬁ gured to optimize

transient response. Connecting a 100pF or greater high

frequency bypass capacitor from this pin to ground is also

recommended. When Burst Mode operation is enabled (see

Pin 5 description), an internal low impedance clamp on the

VC pin is set at 100mV below the burst threshold, which

limits the negative excursion of the pin voltage. There-

fore, this pin cannot be pulled low with a low-impedance

source. If the VC pin must be externally manipulated, do

so through a 1k series resistance.

SENSE– (Pin 8): Negative Input for Current Sense Ampli-

ﬁ er. Sensed inductor current limit set at ±150mV across

SENSE inputs.

SENSE+ (Pin 9): Positive Input for Current Sense Ampli-

ﬁ er. Sensed inductor current limit set at ±150mV across

SENSE inputs.

PGND (Pin 10): High Current Ground Reference for Syn-

chronous Switch. Current path from pin to negative terminal

of VCC decoupling capacitor must not corrupt SGND.

BG (Pin 11): Synchronous Switch Gate Drive Output.

VCC (Pin 12): Internal Regulator Output. Most IC func-

tions are powered from this pin. Driving this pin from

an external source reduces VIN pin current to 20µA.

This pin is decoupled with a low ESR 1µF capacitor to

PGND. In shutdown mode, this pin sinks 20µA until the

pin voltage is discharged to 0V. See Typical Performance

Characteristics.

NC (Pin 13): No Connection.

SW (Pin 14): Reference for VBOOST Supply and High Cur-

rent Return for Bootstrapped Switch.

TG (Pin 15): Bootstrapped Switch Gate Drive Output.

BOOST (Pin 16): Bootstrapped Supply – Maximum Operat-

ing Voltage (Ground Referred) to 75V. This pin is decoupled

with a low ESR 1µF capacitor to pin SW. The voltage on

the decoupling capacitor is refreshed through a rectiﬁ er

from either VCC or an external source.

Exposed Package Backside (SGND) (Pin 17): Low Noise

Ground Reference. SGND connection is made through

the exposed lead frame on back of TSSOP package which

must be soldered to the PCB ground.

LT3800

3800fc

FUNCTIONAL DIAGRAM

–+

–

VIN

UVLO

(<4V)

BST

UVLO

REG

FEEDBACK

REFERENCE

–

1.231V

3.8V

REG

INTERNAL

SUPPLY RAIL

116

VIN

VCC

UVLO

(<6V)

SHDN

DRIVE

CONTROL

DRIVE

CONTROL

NOL

SWITCH

LOGIC

DRIVE

CONTROL

BURST_EN

CSS

SENSE–

VFB

–

1.185V

0.5V

ERROR

AMP

2µA

Burst Mode

OPERATION

SOFT-START

DISABLE/BURST

ENABLE

OSCILLATOR

SLOPE COMP

GENERATOR

BOOST

VCC

11 BG

PGND

SENSE+

GND

3800 FD

BOOSTED

SWITCH

DRIVER

CURRENT

SENSE

COMPARATOR

–+ R

–+

160mV

SYNCHRONOUS

SWITCH DRIVER

REVERSE

CURRENT

INHIBIT

10mV

–

LT3800

3800fc

Overview

The LT3800 is a high input voltage range step-down

synchronous DC/DC converter controller IC that uses a

200kHz constant frequency, current mode architecture

with external N-channel MOSFET switches.

The LT3800 has provisions for high efﬁ ciency, low load

operation for battery-powered applications. Burst Mode

operation reduces total average input quiescent currents to

100µA during no load conditions. A low current shutdown

mode can also be activated, reducing quiescent current to

<10µA. Burst Mode operation can be disabled if desired.

The LT3800 also employs a reverse-current inhibit feature,

allowing increased efﬁ ciencies during light loads through

nonsynchronous operation. This feature disables the

synchronous switch if inductor current approaches zero.

If full time synchronous operation is desired, this feature

can be disabled.

Much of the LT3800’s internal circuitry is biased from an

internal linear regulator. The output of this regulator is

the VCC pin, allowing bypassing of the internal regulator.

The associated internal circuitry can be powered from

the output of the converter, increasing overall converter

efﬁ ciency. Using externally derived power also eliminates

the IC’s power dissipation associated with the internal VIN

to VCC regulator.

Theory of Operation (See Block Diagram)

The LT3800 senses converter output voltage via the VFB

pin. The difference between the voltage on this pin and

an internal 1.231V reference is ampliﬁ ed to generate an

error voltage on the VC pin which is, in turn, used as a

threshold for the current sense comparator.

During normal operation, the LT3800 internal oscilla-

tor runs at 200kHz. At the beginning of each oscillator

cycle, the switch drive is enabled. The switch drive stays

enabled until the sensed switch current exceeds the VC

derived threshold for the current sense comparator and, in

turn, disables the switch driver. If the current comparator

threshold is not obtained for the entire oscillator cycle,

the switch driver is disabled at the end of the cycle for

450ns. This minimum off-time mode of operation assures

regeneration of the BOOST bootstrapped supply.

Power Requirements

The LT3800 is biased using a local linear regulator to

generate internal operational voltages from the VIN pin.

Virtually all of the circuitry in the LT3800 is biased via an

internal linear regulator output (VCC). This pin is decoupled

with a low ESR 1µF capacitor to PGND.

The VCC regulator generates an 8V output provided there

is ample voltage on the VIN pin. The VCC regulator has

approximately 1V of dropout, and will follow the VIN pin

with voltages below the dropout threshold.

The LT3800 has a start-up requirement of VIN > 7.5V. This

assures that the onboard regulator has ample headroom

to bring the VCC pin above its UVLO threshold. The VCC

regulator can only source current, so forcing the VCC pin

above its 8V regulated voltage allows use of externally

derived power for the IC, minimizing power dissipation

in the IC. Using the onboard regulator for start-up, then

deriving power for VCC from the converter output maxi-

mizes conversion efﬁ ciencies and is common practice. If

VCC is maintained above 6.5V using an external source,

the LT3800 can continue to operate with VIN as low as 4V.

The LT3800 operates with 3mA quiescent current from

the VCC supply. This current is a fraction of the actual VCC

quiescent currents during normal operation. Additional

current is produced from the MOSFET switching currents

for both the boosted and synchronous switches and are

typically derived from the VCC supply.

Because the LT3800 uses a linear regulator to generate

VCC, power dissipation can become a concern with high

VIN voltages. Gate drive currents are typically in the range

of 5mA to 15mA per MOSFET, so gate drive currents can

create substantial power dissipation. It is advisable to

derive VCC and VBOOST power from an external source

whenever possible.

APPLICATIONS INFORMATION

LT3800

3800fc

APPLICATIONS INFORMATION

Figure 1. VCC Regulator Continuous Operating Conditions

The onboard VCC regulator will provide gate drive power

for start-up under all conditions with total MOSFET gate

charge loads up to 180nC. The regulator can operate the

LT3800 continuously, provided the VIN voltage and/or

MOSFET gate charge currents do not create excessive

power dissipation in the IC. Safe operating conditions

for continuous regulator use are shown in Figure 1. In

applications where these conditions are exceeded, VCC

must be derived from an external source after start-up.

In LT3800 converter applications with output voltages in

the 9V to 20V range, back-feeding VCC and VBOOST from

the converter output is trivial, accomplished by connect-

ing diodes from the output to these supply pins. Deriving

these supplies from output voltages greater than 20V will

require additional regulation to reduce the feedback voltage.

Outputs lower than 9V will require step-up techniques to

increase the feedback voltage to something greater than

the 8V VCC regulated output. Low power boost switchers

are sometimes used to provide the step-up function, but

a simple charge-pump can perform this function in many

instances.

Charge Pump Doubler

TOTAL FET GATE CHARGE (nC)

VIN (V)

50 100 150 200

3800 F01

SAFE

OPERATING

CONDITIONS

Charge Pump Tripler

VOUT

1µF

B0520 B0520

1µF

Si1555DL

LT3800

VCC

VOUT

1µF

B0520

1µF

Si1555DLSi1555DL

LT3800

VCC

B0520

3800 AI01

Inductor Auxiliary Winding

VOUT

3800 AI04

VCC

•

LT3800

3800fc

APPLICATIONS INFORMATION

Burst Mode

The LT3800 employs low current Burst Mode functional-

ity to maximize efﬁ ciency during no load and low load

conditions. Burst Mode operation is enabled by shorting

the BURST_EN pin to SGND. Burst Mode operation can

be disabled by shorting BURST_EN to either VFB or VCC.

When the required switch current, sensed via the VC

pin voltage, is below 15% of maximum, the Burst Mode

operation is employed and that level of sense current is

latched onto the IC control path. If the output load requires

less than this latched current level, the converter will

overdrive the output slightly during each switch cycle.

This overdrive condition is sensed internally and forces

the voltage on the VC pin to continue to drop. When the

voltage on VC drops 150mV below the 15% load level,

switching is disabled and the LT3800 shuts down most

of its internal circuitry, reducing total quiescent current

to 100µA. When the converter output begins to fall, the

VC pin voltage begins to climb. When the voltage on the

VC pin climbs back to the 15% load level, the IC returns

to normal operation and switching resumes. An internal

clamp on the VC pin is set at 100mV below the switch

disable threshold, which limits the negative excursion of

the pin voltage, minimizing the converter output ripple

during Burst Mode operation.

During Burst Mode operation, VIN pin current is 20µA

and VCC current is reduced to 80µA. If no external drive is

provided for VCC, all VCC bias currents originate from the

VIN pin, giving a total VIN current of 100µA. Burst current

can be reduced further when VCC is driven using an output

derived source, as the VCC component of VIN current is

then reduced by the converter buck ratio.

Reverse-Current Inhibit

The LT3800 contains a reverse-current inhibit feature to

maximize efﬁ ciency during light load conditions. This

mode of operation allows discontinuous operation, and

is sometimes referred to as “pulse-skipping” mode. Refer

to Figure 2.

This feature is enabled with Burst Mode operation, and can

also be enabled while Burst Mode operation is disabled

by shorting the BURST_EN pin to VFB.

When reverse-current inhibit is enabled, the LT3800 sense

ampliﬁ er detects inductor currents approaching zero and

disables the synchronous switch for the remainder of

the switch cycle. If the inductor current is allowed to go

negative before the synchronous switch is disabled, the

switch node could inductively kick positive with a high

dv/dt. The LT3800 prevents this by incorporating a 10mV

positive offset at the sense inputs.

Figure 2. Inductor Current vs Mode

PULSE SKIP MODE

ILILFORCED CONTINUOUS

DECREASING

LOAD

CURRENT

3800 F02

LT3800

3800fc

APPLICATIONS INFORMATION

With the reverse-current inhibit feature enabled, an LT3800

converter will operate much like a nonsynchronous

converter during light loads. Reverse-current inhibit

reduces resistive losses associated with inductor ripple

currents, which improves operating efﬁ ciencies during

light-load conditions.

An LT3800 DC/DC converter that is operating in reverse-

inhibit mode has a minimum load requirement of 1mA

(BURST_EN = VFB). Since most applications use output-

generated power for the LT3800, this requirement is met

by the bias currents of the IC, however, for applications

that do not derive power from the output, this require-

ment is easily accomplished by using a 1.2k resistor

connected from VFB to ground as one of the converter

output voltage programming resistors (R1). There are no

minimum load restrictions when in Burst Mode operation

(BURST_EN < 0.5V) or continuous conduction mode

(BURST_EN > 2.5V).

Soft-Start

The LT3800 incorporates a programmable soft-start

function to control start-up surge currents, limit output

overshoot and for use in supply sequencing. The soft-start

function directly monitors and controls output voltage slew

rate during converter start-up.

As the output voltage of the converter rises, the soft-start

circuit monitors δV/δt current through a coupling capaci-

tor and adjusts the voltage on the VC pin to maintain an

average value of 2µA. The soft-start function forces the

programmed slew rate while the converter output rises to

95% regulation, which corresponds to 1.185V on the VFB

pin. Once 95% regulation is achieved, the soft-start circuit

is disabled. The soft-start circuit will re-enable when the

VFB pin drops below 70% regulation, which corresponds to

300mV of control hysteresis on the VFB pin, which allows

for a controlled recovery from a ‘brown-out’ condition.

The desired soft-start rise time (tSS) is programmed via

a programming capacitor CSS1, using a value that cor-

responds to 2µA average current during the soft-start

interval. This capacitor value follows the relation:

CSS1 =2E –6 •t

VOUT

RSS is typically set to 200k for most applications.

Considerations for Low Voltage Output Applications

The LT3800 CSS pin biases to 220mV during the soft-start

cycle, and this voltage is increased at network node “A” by

the 2µA signal current through RSS, so the output has to

reach this value before the soft-start function is engaged.

The value of this output soft-start start-up voltage offset

(VOUT(SS)) follows the relation:

OUT(SS) = 220mV + RSS • 2E–6

which is typically 0.64V for RSS = 200k.

In some low voltage output applications, it may be desir-

able to reduce the value of this soft-start start-up voltage

offset. This is possible by reducing the value of RSS. With

reduced values of RSS, the signal component caused by

voltage ripple on the output must be minimized for proper

soft-start operation.

Peak-to-peak output voltage ripple (∆VOUT) will be imposed

on node “A” through the capacitor CSS1. The value of RSS

can be set using the following equation:

RSS =

VOUT

1.3E–6

It is important to use low ESR output capacitors for LT3800

voltage converter designs to minimize this ripple voltage

component. A design with an excessive ripple component

can be evidenced by observing the VC pin during the start

cycle.

CSS

VOUT

CSS1 RSS

3800 AI06

LT3800

3800fc

APPLICATIONS INFORMATION

The soft-start cycle should be evaluated to verify that the

reduced RSS value allows operation without excessive

modulation of the VC pin before ﬁ nalizing the design.

If the VC pin has an excessive ripple component during the

soft-start cycle, converter output ripple should be reduced

or RSS increased. Reduction in converter output ripple is

typically accomplished by increasing output capacitance

and/or reducing output capacitor ESR.

External Current Limit Foldback Circuit

An additional start-up voltage offset can occur during the

period before the LT3800 soft-start circuit becomes active.

Before the soft-start circuit throttles back the VC pin in

response to the rising output voltage, current as high as

the peak programmed current limit (IMAX) can ﬂ ow in the

inductor. Switching will stop once the soft-start circuit takes

hold and reduces the voltage on the VC pin, but the output

voltage will continue to increase as the stored energy in

the inductor is transferred to the output capacitor. With

IMAX ﬂ owing in the inductor, the resulting leading-edge

rise on VOUT due to energy stored in the inductor follows

the relationship:

VOUT =IMAX •L

COUT











1/ 2

Inductor current typically doesn’t reach IMAX in the few

cycles that occur before soft-start becomes active, but can

with high input voltages or small inductors, so the above

relation is useful as a worst-case scenario.

This energy transfer increase in output voltage is typically

small, but for some low voltage applications with relatively

small output capacitors, it can become signiﬁ cant. The volt-

age rise can be reduced by increasing output capacitance,

which puts additional limitations on COUT for these low

voltage supplies. Another approach is to add an external

current limit foldback circuit which reduces the value of

IMAX during start-up.

An external current limit foldback circuit can be easily

incorporated into an LT3800 DC/DC converter application

by placing a 1N4148 diode and a 47k resistor from the

converter output (VOUT) to the LT3800’s VC pin. This limits

the peak current to 0.25 • IMAX when VOUT = 0V. A current

limit foldback circuit also has the added advantage of

providing a reduced output current in the DC/DC converter

during short-circuit fault conditions, so a foldback circuit

may be useful even if the soft-start function is disabled.

If the soft-start circuit is disabled by shorting the CSS pin

to ground, the external current limit fold-back circuit must

be modiﬁ ed by adding an additional diode and resistor.

The 2-diode, 2-resistor network shown also provides

0.25 • IMAX when VOUT = 0V.

Soft-Start Characteristic Showing Excessive Ripple Component Desirable Soft-Start Characteristic

VOUT

VOUT(SS)

V(VC)

250µs/DIV 3800 AI07

VOUT

VOUT(SS)

V(VC)

250µs/DIV 3800 AI08

LT3800

3800fc

APPLICATIONS INFORMATION

Adaptive Nonoverlap (NOL) Output Stage

The FET driver output stages implement adaptive nonover-

lap control. This feature maintains a constant dead time,

preventing shoot-through switch currents, independent

of the type, size or operating conditions of the external

switch elements.

Each of the two switch drivers contains a NOL control

circuit, which monitors the output gate drive signal of the

other switch driver. The NOL control circuits interrupt the

“turn on” command to their associated switch driver until

the other switch gate is fully discharged.

Antislope Compensation

Most current mode switching controllers use slope com-

pensation to prevent current mode instability. The LT3800

is no exception. A slope-compensation circuit imposes an

artiﬁ cial ramp on the sensed current to increase the rising

slope as duty cycle increases. Unfortunately, this additional

ramp corrupts the sensed current value, reducing the

achievable current limit value by the same amount as the

added ramp represents. As such, current limit is typically

reduced as duty cycles increase. The LT3800 contains

circuitry to eliminate the current limit reduction typically

associated with slope compensation. As the slope-com-

pensation ramp is added to the sensed current, a similar

ramp is added to the current limit threshold reference.

The end result is that current limit is not compromised,

so a LT3800 converter can provide full power regardless

of required duty cycle.

Shutdown

The LT3800 SHDN pin uses a bandgap generated reference

threshold of 1.35V. This precision threshold allows use of

the SHDN pin for both logic-level controlled applications

and analog monitoring applications such as power supply

sequencing.

The LT3800 operational status is primarily controlled by

a UVLO circuit on the VCC regulator pin. When the IC is

enabled via the SHDN pin, only the VCC regulator is enabled.

Switching remains disabled until the UVLO threshold is

achieved at the VCC pin, when the remainder of the IC is

enabled and switching commences.

Because an LT3800 controlled converter is a power

transfer device, a voltage that is lower than expected on

the input supply could require currents that exceed the

sourcing capabilities of that supply, causing the system

to lock up in an undervoltage state. Input supply start-up

protection can be achieved by enabling the SHDN pin

using a resistive divider from the VIN supply to ground.

Setting the divider output to 1.35V when that supply is at

an adequate voltage prevents an LT3800 converter from

drawing large currents until the input supply is able to

provide the required power. 120mV of input hysteresis

on the SHDN pin allows for almost 10% of input supply

droop before disabling the converter.

Current Limit Foldback Circuit for

Applications That Use Soft-Start

Alternative Current Limit Foldback Circuit for Applications That

Have Soft-Start Disabled

VOUT

1N4148

3800 AI09

47k

VOUT

1N4148

3800 AI10

39k

27k

LT3800

3800fc

APPLICATIONS INFORMATION

The UVLO voltage, VIN(UVLO), is set using the following

relation:

RA=RB•VIN(UVLO) – 1.35V

1.35V

If additional hysteresis is desired for the enable function,

an external positive feedback resistor can be used from

the LT3800 regulator output.

The shutdown function can be disabled by connecting the

SHDN pin to VIN through a large value pull-up resistor. This

pin contains a low impedance clamp at 6V, so the SHDN

pin will sink current from the pull-up resistor (RPU):

ISHDN =VIN –6V

RPU

Because this arrangement will pull the SHDN pin to the

6V clamp voltage, it will violate the 5V absolute maximum

voltage rating of the pin. This is permitted, however, as

long as the absolute maximum input current rating of

1mA is not exceeded. Input SHDN pin currents of <100µA

are recommended; a 1M or greater pull-up resistor is

typically used for this conﬁ guration.

Inductor Selection

The primary criterion for inductor value selection in LT3800

applications is ripple current created in that inductor. Basic

design considerations for ripple current are output voltage

ripple, and the ability of the internal slope compensation

waveform to prevent current mode instability. Once the

value is determined, an inductor must also have a satu-

ration current equal to or exceeding the maximum peak

current in the inductor.

Ripple current (∆IL) in an inductor for a given value (L)

can be approximated using the relation:

IL=1– VOUT

VIN









•VOUT

fO•L

The typical range of values for ∆I is 20% to 40% of

IOUT(MAX), where IOUT(MAX) is the maximum converter

output load current. Ripple currents in this range typically

yield a good design compromise between inductor perfor-

mance versus inductor size and cost, and values in this

range are generally a good starting point. A starting point

inductor value can thus be determined using the relation:

L=VOUT •

1– VOUT

VIN











fO• 0.3 •IOUT(MAX)

Use of smaller inductors increase output ripple currents,

requiring more capacitance on the converter output. Also,

with converter operation with duty cycles greater than

50%, the slope compensation criterion, described later,

must be met. Designing for smaller ripple currents requires

larger inductor values, which can increase converter cost

and/or footprint.

Programming LT3800 VIN UVLO

3800 AI02

LT3800

VIN

SHDN

SGND

LT3800

3800fc

APPLICATIONS INFORMATION

Some magnetics vendors specify a volt-second product

in their data sheet. If they do not, consult the vendor to

make sure the speciﬁ cation is not being exceeded by your

design. The required volt-second product is calculated as

follows:

Volt-SecondVOUT

•1–

VOUT

VIN











Magnetics vendors specify either the saturation current, the

RMS current, or both. When selecting an inductor based

on inductor saturation current, the peak current through

the inductor, IOUT(MAX) + (∆I/2), is used. When selecting

an inductor based on RMS current the maximum load

current, IOUT(MAX), is used.

The requirement for avoiding current mode instability is

keeping the rising slope of sensed inductor ripple current

(S1) greater than the falling slope (S2). During continuous-

current switcher operation, the rising slope of the current

waveform in the switched inductor is less than the falling

slope when operating at duty cycles (DC) greater than 50%.

To avoid the instability condition during this operation, a

false signal is added to the sensed current, increasing the

perceived rising slope. To prevent current mode instability,

the slope of this false signal (Sx) must be sufﬁ cient such

that the sensed rising slope exceeds the falling slope, or

S1 + Sx ≥ S2. This leads to the following relations:

Sx ≥ S2 (2DC – 1)/DC

where:

S2 ~ VOUT/L

Solving for L yields a relation for the minimum inductance

that will satisfy slope compensation requirements:

LMIN =VOUT •2DC – 1

DC • Sx

The LT3800 maximizes available dynamic range using a

slope compensation generator that continuously increases

the additional signal slope as duty cycle increases. The

slope compensation waveform is calibrated at an 80%

duty cycle, to generate an equivalent slope of at least

1E5 • ILIMIT A/sec, where ILIMIT is the programmed con-

verter current limit. Current limit is programmed by using

a sense resistor (RS) such that ILIMIT = 150mV/RS, so the

equation for the minimum inductance to meet the current

mode instability criterion can be reduced to:

MIN = (5E–5)(VOUT)(RS)

For example, with VOUT = 5V and RS = 20m:

MIN = (5E–5)(5)(0.02) = 5µH

After calculating the minimum inductance value, the volt-

second product, the saturation current and the RMS current

for your design, an off the shelf inductor can be selected

from a magnetics vendor. A list of magnetics vendors

can be found at http://www.linear.com/ezone/vlinks or by

contacting the Linear Technology Applications department.

Output Voltage Programming

Output voltage is programmed through a resistor feedback

network to VFB (Pin 6) on the LT3800. This pin is the inverting

input of the error ampliﬁ er, which is internally referenced

to 1.231V. The divider is ratioed to provide 1.231V at the

VFB pin when the output is at its desired value. The output

voltage is thus set following the relation:

R2 =R1• VOUT

1.231–1











when an external resistor divider is connected to the

output as shown.

Programming LT3800 Output Voltage

3800 AI03

LT3800

VOUT

VFB

SGND

LT3800

3800fc

APPLICATIONS INFORMATION

Power MOSFET Selection

External N-channel MOSFET switches are used with the

LT3800. The positive gate-source drive voltage of the

LT3800 for both switches is roughly equivalent to the VCC

supply voltage, for use of standard threshold MOSFETs.

Selection criteria for the power MOSFETs include the

“ON” resistance (RDS(ON)), total gate charge (QG), reverse

transfer capacitance (CRSS), maximum drain-source volt-

age (VDSS) and maximum current.

The power FETs selected must have a maximum operating

VDSS exceeding the maximum VIN. VGS voltage maximum

must exceed the VCC supply voltage.

Total gate charge (QG) is used to determine the FET gate

drive currents required. QG increases with applied gate

voltage, so the QG for the maximum applied gate voltage

must be used. A graph of QG vs. VGS is typically provided

in MOSFET data sheets.

In a conﬁ guration where the LT3800 linear regulator is

providing VCC and VBOOST currents, the VCC 8V output

voltage can be used to determine QG. Required drive cur-

rent for a given FET follows the simple relation:

GATE = QG(8V) • fO

QG(8V) is the total FET gate charge for VGS = 8V, and f0 =

operating frequency. If these currents are externally derived

by backdriving VCC, use the backfeed voltage to determine

QG. Be aware, however, that even in a backfeed conﬁ gura-

tion, the drive currents for both boosted and synchronous

FETs are still typically supplied by the LT3800 internal VCC

regulator during start-up. The LT3800 can start using FETs

with a combined QG(8V) up to 180nC.

Once voltage requirements have been determined, RDS(ON)

can be selected based on allowable power dissipation and

required output current.

In an LT3800 buck converter, the average inductor cur-

rent is equal to the DC load current. The average cur-

rents through the main (bootstrapped) and synchronous

(ground-referred) switches are:

MAIN = (ILOAD)(DC)

SYNC = (ILOAD)(1 – DC)

The RDS(ON) required for a given conduction loss can be

calculated using the relation:

LOSS = ISWITCH2 • RDS(ON)

In high voltage applications (VIN > 20V), the main switch

is required to slew very large voltages. MOSFET transition

losses are proportional to VIN2 and can become the domi-

nant power loss term in the main switch. This transition

loss takes the form:

TR ≈ (k)(VIN)2(ISWITCH)(CRSS)(fO)

where k is a constant inversely related to the gate drive

current, approximated by k = 2 in LT3800 applications,

and ISWITCH is the converter output current. The power

loss terms for the switches are thus:

MAIN = (DC)(ISWITCH)2(1 + d)(RDS(ON)) +

2(VIN)2(ISWITCH)(CRSS)(fO)

SYNC = (1 – DC)(ISWITCH)2(1 + d)(RDS(ON))

The (1 + d) term in the above relations is the temperature

dependency of RDS(ON), typically given in the form of a

normalized RDS(ON) vs Temperature curve in a MOSFET

data sheet.

The CRSS term is typically smaller for higher voltage FETs,

and it is often advantageous to use a FET with a higher

VDS rating to minimize transition losses at the expense of

additional RDS(ON) losses.

In some applications, parasitic FET capacitances couple

the negative going switch node transient onto the bottom

gate drive pin of the LT3800, causing a negative voltage

in excess of the Absolute Maximum Rating to be imposed

on that pin. Connection of a catch Schottky diode from

this pin to ground will eliminate this effect. A 1A current

rating is typically sufﬁ cient for the diode.

Input Capacitor Selection

The large currents typical of LT3800 applications require

special consideration for the converter input and output

supply decoupling capacitors. Under normal steady state

buck operation, the source current of the main switch

MOSFET is a square wave of duty cycle VOUT/VIN. Most

of this current is provided by the input bypass capacitor.

LT3800

3800fc

APPLICATIONS INFORMATION

To prevent large input voltage transients and avoid bypass

capacitor heating, a low ESR input capacitor sized for the

maximum RMS current must be used. This maximum

capacitor RMS current follows the relation:

IRMS =

IMAX VOUT VIN –V

OUT

()

VIN

which peaks at a 50% duty cycle, when IRMS = IMAX/2.

The bulk capacitance is calculated based on an accept-

able maximum input ripple voltage, ∆VIN, which follows

the relation:

CIN(BULK) =IOUT(MAX) •

VOUT

VIN

VIN •f

∆V is typically on the order of 100mV to 200mV. Aluminum

electrolytic capacitors are a good choice for high voltage,

bulk capacitance due to their high capacitance per unit area.

The capacitor voltage rating must be rated greater than

VIN(MAX). The combination of aluminum electrolytic ca-

pacitors and ceramic capacitors is a common approach

to meeting supply input capacitor requirements. Multiple

capacitors are also commonly paralleled to meet size or

height requirements in a design.

Capacitor ripple current ratings are often based on only

2000 hours (three months) lifetime; it is advisable to derate

either the ESR or temperature rating of the capacitor for

increased MTBF of the regulator.

Output Capacitor Selection

The output capacitor in a buck converter generally has

much less ripple current than the input capacitor. Peak-to-

peak ripple current is equal to that in the inductor (∆IL),

typically a fraction of the load current. COUT is selected

to reduce output voltage ripple to a desirable value given

an expected output ripple current. Output ripple (∆VOUT)

is approximated by:

∆VOUT ≈ ∆IL(ESR + [(8)(fO) • COUT]–1)

where fO = operating frequency.

∆VOUT increases with input voltage, so the maximum

operating input voltage should be used for worst-case

calculations. Multiple capacitors are often paralleled to

meet ESR requirements. Typically, once the ESR require-

ment is satisﬁ ed, the capacitance is adequate for ﬁ ltering

and has the required RMS current rating. An additional

ceramic capacitor in parallel is commonly used to reduce

the effect of parasitic inductance in the output capacitor,

which reduces high frequency switching noise on the

converter output.

Increasing inductance is an option to reduce ESR require-

ments. For extremely low

∆

VOUT, an additional LC ﬁ lter

stage can be added to the output of the supply. Application

Note 44 has information on sizing an additional output

LC ﬁ lter.

Layout Considerations

The LT3800 is typically used in DC/DC converter designs

that involve substantial switching transients. The switch

drivers on the IC are designed to drive large capacitances

and, as such, generate signiﬁ cant transient currents them-

selves. Careful consideration must be made regarding

supply bypass capacitor locations to avoid corrupting the

ground reference used by IC.

Typically, high current paths and transients from the input

supply and any local drive supplies must be kept isolated

from SGND, to which sensitive circuits such as the error

amp reference and the current sense circuits are referred.

Effective grounding can be achieved by considering switch

current in the ground plane, and the return current paths of

each respective bypass capacitor. The VIN bypass return,

VCC bypass return, and the source of the synchronous

FET carry PGND currents. SGND originates at the negative

terminal of the VOUT bypass capacitor, and is the small

signal reference for the LT3800.

Don’t be tempted to run small traces to separate ground

paths. A good ground plane is important as always, but

PGND referred bypass elements must be oriented such

that transient currents in these return paths do not corrupt

the SGND reference.

During the dead-time between switch conduction, the

body diode of the synchronous FET conducts inductor

LT3800

3800fc

APPLICATIONS INFORMATION

current. Commutating this diode requires a signiﬁ cant

charge contribution from the main switch. At the instant

the body diode commutates, a current discontinuity is

created and parasitic inductance causes the switch node

to ﬂ y up in response to this discontinuity. High cur-

rents and excessive parasitic inductance can generate

extremely fast dV/dt rise times. This phenomenon can

cause avalanche breakdown in the synchronous FET

body diode, signiﬁ cant inductive overshoot on the switch

node, and shoot-through currents via parasitic turn-on of

the synchronous FET. Layout practices and component

orientations that minimize parasitic inductance on this

node is critical for reducing these effects.

Ringing waveforms in a converter circuit can lead to device

failure, excessive EMI, or instability. In many cases, you

can damp a ringing waveform with a series RC network

across the offending device. In LT3800 applications, any

ringing will typically occur on the switch node, which

can usually be reduced by placing a snubber across the

synchronous FET. Use of a snubber network, however,

should be considered a last resort. Effective layout practices

typically reduce ringing and overshoot, and will eliminate

the need for such solutions.

Effective grounding techniques are critical for successful

DC/DC converter layouts. Orient power path components

such that current paths in the ground plane do not cross

through signal ground areas. Signal ground refers to the

Exposed Pad on the backside of the LT3800 IC. SGND

is referenced to the (–) terminal of the VOUT decoupling

capacitor and is used as the converter voltage feedback

reference. Power ground currents are controlled on the

LT3800 via the PGND pin, and this ground references

the high current synchronous switch drive components,

as well as the local VCC supply. It is important to keep

PGND and SGND voltages consistent with each other, so

separating these grounds with thin traces is not recom-

mended. When the synchronous FET is turned on, gate

drive surge currents return to the LT3800 PGND pin from

the FET source. The BOOST supply refresh surge currents

also return through this same path. The synchronous FET

must be oriented such that these PGND return currents do

not corrupt the SGND reference. Problems caused by the

PGND return path are generally recognized during heavy

load conditions, and are typically evidenced as multiple

switch pulses occurring during a single 5µs switch cycle.

This behavior indicates that SGND is being corrupted and

grounding should be improved. SGND corruption can

often be eliminated, however, by adding a small capacitor

(100pF-200pF) across the synchronous switch FET from

drain to source.

The high di/dt loop formed by the switch MOSFETs and

the input capacitor (CIN) should have short wide traces

to minimize high frequency noise and voltage stress from

inductive ringing. Surface mount components are preferred

to reduce parasitic inductances from component leads.

Connect the drain of the main switch MOSFET directly to

the (+) plate of CIN, and connect the source of the syn-

chronous switch MOSFET directly to the (–) terminal of

CIN. This capacitor provides the AC current to the switch

MOSFETs. Switch path currents can be controlled by

orienting switch FETs, the switched inductor, and input

and output decoupling capacitors in close proximity to

each other.

Locate the VCC and BOOST decoupling capacitors in close

proximity to the IC. These capacitors carry the MOSFET

drivers’ high peak currents. Locate the small-signal

components away from high frequency switching nodes

(BOOST, SW, TG, VCC and BG). Small-signal nodes are

oriented on the left side of the LT3800, while high current

switching nodes are oriented on the right side of the IC

to simplify layout. This also helps prevent corruption of

the SGND reference.

Connect the VFB pin directly to the feedback resistors

independent of any other nodes, such as the SENSE– pin.

The feedback resistors should be connected between the

(+) and (–) terminals of the output capacitor (COUT).

Locate the feedback resistors in close proximity to the

LT3800 to minimize the length of the high impedance

VFB node.

The SENSE– and SENSE+ traces should be routed together

and kept as short as possible.

LT3800

3800fc

APPLICATIONS INFORMATION

The LT3800 packaging has been designed to efﬁ ciently

remove heat from the IC via the Exposed Pad on the

backside of the package. The Exposed Pad is soldered to

a copper footprint on the PCB. This footprint should be

made as large as possible to reduce the thermal resistance

of the IC case to ambient air.

Orientation of Components Isolates Power Path and PGND

Currents, Preventing Corruption of SGND Reference

BOOST

VCC

PGNDSGND

LT3800

SGND

REFERRED

COMPONENTS

VOUT

3800 AI05

VIN

ISENSE

TYPICAL APPLICATIONS

6.5V-55V to 5V 10A DC/DC Converter with Charge Pump Doubler VCC Refresh and Current Limit Foldback

VIN

SHDN

CSS

BURST_EN

VFB

SENSE–

BOOST

VCC

PGND

SENSE+

LT3800

SGND

1.5nF

62k R5

47k

1N4148

R4 75k

470pF

C10

100pF

309k

100k

0.01Ω

BAS19

C1 1µF

16V X7R

C3 1µF

16V X7R

1µF

100V

X7R ×3

56µF

63V

×2

10µF

6.3V

X7R

220µF

×2

Si7850DP

×2

Si7370DP

×2

1/2 Si1555DL

DS3

B160

×2

DS1

MBRO520L

1µF

DS2

MBRO520L

5.6µH

VIN

6.5V TO 55V

VOUT

5V AT 10A

3800 TA02a

C5: SANYO POSCAP 6TP220M

L1: IHLP-5050FD-01

Efﬁ ciency and Power Loss

IOUT (A)

EFFICIENCY (%)

POWER LOSS (W)

100

2468

3800 TA02b

VIN = 13.8V

VIN = 55V

VIN = 24V

VIN = 48V

POWER LOSS

VIN = 48V

POWER LOSS

VIN = 13.8V

LT3800

3800fc

TYPICAL APPLICATIONS

9V-38V to 3.3V 10A DC/DC Converter with Input UVLO and Burst Mode Operation

No Load I(VIN) = 100μA

Efﬁ ciency and Power Loss

VIN

SHDN

CSS

BURST_EN

VFB

SENSE–

BOOST

VCC

PGND

SENSE+

LT3800

SGND

C1 1nF

100pF

330pF

C10

100pF

169k

100k

R4 39k

82k

187k

0.01Ω

MBR520

C5 1µF

16V X7R

C4 1µF

16V X7R

4.7µF

50V

X7R ×3

100µF

50V

×2

10µF

6.3V

X7R

470µF

×2

Si7884DP

DS1

SS14

×2

3.3μH

VIN

9V TO 38V

VOUT

3.3V AT 10A

3800 TA03a

C6: SANYO POSCAP 4TPD470M

L1: IHLP-5050FD-01

ILOAD (A)

3800 TA03b

EFFICIENCY (%)

POWER LOSS (W)

0.1 10

VIN = 13.8V

LT3800

3800fc

TYPICAL APPLICATIONS

9V-38V to 5V 6A DC/DC Converter with All Ceramic Capacitors, Input UVLO,

Burst Mode Operation and Current Limit Foldback

Efﬁ ciency and Power Loss

VIN

SHDN

CSS

BURST_EN

VFB

SENSE–

BOOST

VCC

PGND

SENSE+

LT3800

SGND

C1 3.9nF

C9 1nF

100pF

1nF

47pF

154k

49.9k

47k

1N4148

R4 51k

27k

RB 187k

0.02Ω

BAS19

C5 1µF

10V X7R

C4 1µF

10V X7R

22µF

×3

100µF

×2

Si7884DP

DS1

SS14

10μH

VIN

9V TO 38V

VOUT

5V AT 6A

3800 TA05a

C7: TDK C4532X5R0J107MT

C8: TDK C5750X7R1E226MT

L1: IHLP-5050FD-01

ILOAD (A)

EFFICIENCY (%)

POWER LOSS (W)

100

0.001 0.1 1 10

3800 TA05b

0.01

0.80

1.60

2.00

2.80

3.20

2.40

1.20

0.40

VIN = 13.8V

LT3800

3800fc

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev I)

Exposed Pad Variation BC

FE16 (BC) TSSOP REV I 1210

0.09 – 0.20

(.0035 – .0079)

0s – 8s

0.25

REF

0.50 – 0.75

(.020 – .030)

4.30 – 4.50*

(.169 – .177)

134

5678

DETAIL B IS THE PART OF

THE LEAD FRAME FEATURE

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

4.90 – 5.10*

(.193 – .201)

16 1514 13 12 11

1.10

(.0433)

MAX

0.05 – 0.15

(.002 – .006)

0.65

(.0256)

BSC

2.94

(.116)

0.48

(.019)

REF

0.51

(.020)

REF

0.195 – 0.30

(.0077 – .0118)

TYP

RECOMMENDED SOLDER PAD LAYOUT

0.45 t0.05

0.65 BSC

4.50 t0.10

6.60 t0.10

1.05 t0.10

2.94

(.116)

3.58

(.141)

3.58

(.141)

MILLIMETERS

(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

6.40

(.252)

BSC

DETAIL B

LT3800

3800fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

C 9/11 Minor correction to TA04a schematic 24

(Revision history begins at Rev C)

LT3800

3800fc

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0911 REV C • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

24V-48V to –12V 75W Inverting DC/DC Converter with VIN UVLO

Efﬁ ciency and Power Loss

ILOAD (A)

0.1

EFFICIENCY (%)

POWER LOSS (W)

100

110

3800 TA04b

VIN = 24V

VIN = 48V

VIN = 36V LOSS

VIN = 36V

PART NUMBER DESCRIPTION COMMENTS

LTC1735 Synchronous Step-Down Controller 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 6V, IOUT ≤ 20A

LTC1778 No RSENSE™ Synchronous Step-Down Controller Current Mode Without Using Sense Resistor, 4V ≤ VIN ≤ 36V

1934 Micropower Step-Down Switching Regulator 3.2V ≤ VIN ≤ 34V, 300mA Switch, ThinSOT™ Package

LT1952 Synchronous Single Switch Forward Converter 25W to 500W Isolated Power Supplies, Small Size, High Efﬁ ciency

LT1976 60V Switching Regulator 3.2V ≤ VIN ≤ 60V, 1.5A Switch, 16-Lead TSSOP

LT3010 3V to 80V LDO 50mA Output Current, 1.275V ≤ VOUT ≤ 60V

LT3430/LT3431 3A, 60V Switching Regulators 5.5V ≤ VIN ≤ 60V, 200kHz, 16-Lead TSSOP

LTC3703 100V Synchronous Step-Down Controller Large 1 Gate Drivers, No RSENSE

LTC3703-5 60V Synchronous Step-Down Controller Large 1 Gate Drivers, No RSENSE

LTC3727-1 High VOUT 2-Phase Dual Step-Down Controller 0.8V ≤ VOUT ≤ 14V, PLL: 250kHz to 550kHz

LTC3728L 2-Phase, Dual Synchronous Step-Down Controller 550kHz, PLL: 250kHz to 550kHz, 4V ≤ VIN ≤ 36V

VIN

SHDN

CSS

BURST_EN

VFB

SENSE–

BOOST

VCC

PGND

SENSE+

LT3800

SGND

C1 1nF R1 200k

470pF

130k

39k

20k

174k

C2 1µF

16V X7R

100pF

4.7µF

16V

X7R

270µF

16V

SPRAGUE SP

150pF

100V

1N4148

BAS19

56µF

63V

C10

1µF

100V

X7R

1µF

16V

X7R

FDD3570

L1: COEV MGPWL-00099

VIN

24V TO 48V

VOUT

–12V

75W

0.01Ω

15µH

DS1

B180

2N3906

3800 TA04a