Rev. 1.1 September 2010 www.aosmd.com Page 1 of 14
AOZ1037
EZBuck™ 5A Synchronous Buck Regulator
General Description
The AOZ1037 is a high efficiency, simple to use, 5A
synchronous buck regulator. The AOZ1037 works from a
4.5V to 18V input voltage range, and provides up to 5A
of continuous output current with an output voltage
adjustable down to 0.8V.
The AOZ1037 comes in an exposed p ad SO-8 p acka ges
and is rated over a -40 °C to +85° C am b ien t tem p er a tur e
range.
Features
z4.5 to 18V operating input voltage range
zSynchronous rectification: 55m internal high-side
switch and 19m Internal low-side switch
zHigh efficiency: up to 95%
zInternal soft start
zActive high power good state
zOutput voltage adjustable to 0.8V
z5A continuous output current
zFixed 500kHz PWM operatio n
zCycle-by-cycle current limit
zPre-bias start-up
zShort-circuit protection
zThermal shutdown
zExposed pad SO-8 package
Applications
zPoint of load DC/DC conversion
zLCD TVs
zSet top boxes
zDVD / Blu-ray players/recorders
zCable modems
zPCIe graphics cards
zTelecom/Networking/Datacom equipment
Typical Application
Figure 1. 3.3V/5A Synchronous Buck Regulator
LX
VIN
VIN
VOUT
FB
PGND
EN
COMP
AGND
C2, C3
22µF
R1
R2
CC
RC
C1
22µF
L1 4.7µH
AOZ1037
PGOOD
R3
5V
AOZ1037
Rev. 1.1 September 2010 www.aosmd.com Page 2 of 14
Ordering Information
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
Pin Description
Part Number Ambient Temperature Range Package Environmental
AOZ1037PI -40°C to +85°C EPAD SO-8 Green Product
1
2
3
4
PGND
VIN
A
GND
FB
Exposed Pad SO-8
(Top View)
PAD
(LX)
NC
PGOOD
EN
COMP
8
7
6
5
Pin Number Pin Name Pin Function
1 PGND Power ground. PGND need s to be electrically connected to AGND.
2V
IN Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high, the device
starts up.
3 AGND Analog ground. AGND is the reference point fo r controller section. AGND needs to be electricall y
connected to PGND.
4 FB Feedback input. The FB pin is used to set the output voltage via a resistor divider between the out-
put and AGND.
5 COMP External loop compensation pin. Connect a RC network between COMP and AGND to compen-
sate the control loop.
6 EN Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the device. if
on/off control is not needed, connect it to VIN and do not leave it open.
7 PGOOD Power Good Output. PGOOD is an open-drain output that indicates the status of output voltage.
PGOOD is pulled low when output is below 90% of the normal regulation.
8 NC No Connect. Pin 8 is not internally connected.
Pad LX S witching node. LX is the drain of the internal PFET. LX is used as the thermal pad of the power
stage.
AOZ1037
Rev. 1.1 September 2010 www.aosmd.com Page 3 of 14
Block Diagram
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage th e
device.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5k in series with 100pF.
Recommended Operating Conditions
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Note:
2. The value of ΘJA is measured with the device mounted on 1-in2 FR-4
board with 2oz. Copper, in a still air environment with TA = 25°C. The
value in any given application depends on the user's specific board
design.
500kHz
Oscillator
AGND PGND
VIN
EN
FB
COMP
LX
OTP
Internal
+5V
ILimit
PWM
Control
Logic
5V LDO
Regulator
UVLO
& POR
Softstart
Reference
& Bias
0.8V
Q1
Q2
PWM
Comp
Level
Shifter
+
FET
Driver
ISen
EAmp
0.2V
+
+
+
+
+
Short Circuit
Detection
Comparator
0.72V
+
PGOOD
Parameter Rating
Supply Voltage (VIN) 20V
LX to AGND -0.7V to VIN+0.3V
LX to AGND 23V (<50ns)
EN to AGND -0.3V to VIN+0.3V
FB to AGND -0.3V to 6V
COMP to AGND -0.3V to 6V
PGND to AGND -0.3V to +0.3V
Junction Temperature (TJ) +150°C
Storage Temperature (TS) -65°C to +150°C
ESD Rating(1) 2.0kV
Parameter Rating
Supply Voltage (VIN) 4.5V to 18V
Output Voltage Range 0.8V to VIN
Ambient Temperature (TA) -40°C to +85°C
Package Thermal Resistance
Exposed Pad SO-8 (ΘJA)(2) 50°C/W
AOZ1037
Rev. 1.1 September 2010 www.aosmd.com Page 4 of 14
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specifi ed(3)
Note:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Symbol Parameter Conditions Min. Typ. Max. Units
VIN Supply Voltage 4.5 18 V
VUVLO Input Under-Voltage Lockout Threshold VIN Rising
VIN Falling 4.1
3.7 V
IIN Supply Current (Quiescent) IOUT = 0, VFB = 1.2V, VEN > 1.2V 1.6 2.5 mA
IOFF Shutdown Supply Current VEN = 0V 1.0 10 µA
VFB Feedback Voltage TA = 25°C 0.788 0.8 0.812 V
Load Regulation 0.5 %
Line Regulation 1.0 %
IFB Feedback Voltage Input Current 200 nA
ENABLE
VEN EN Input Threshold Off Threshold
On Threshold 20.6 V
VHYS EN Input Hysteresis 100 mV
MODULATOR
fOFrequency 400 500 600 kHz
DMAX Maximum Duty Cycle 100 %
Ton_min Minimum On Time 150 ns
GVEA Error Amplifier Voltage Gain 500 V / V
GEA Error Amplifier T r ansconductance 200 µA / V
PROTECTION
ILIM Current Limit 5.8 6.5 A
Over-Temperature Shutdown Limit TJ Rising
TJ Falling 150
100 °C
tSS Soft Start Interval 3ms
POWER GOOD
VOLPG PG LOW Voltage IOL = 1mA 0.6 V
PG Leakage A
VPGL PG Threshold Voltage 87 90 92 %Vo
PG Threshold Voltage Hysteresis 3 %
tPG PG Delay Time 128 µs
PWM OUTPUT STAGE
High-Side Switch On-Resistance VIN = 12V
VIN = 5V 55
75 m
Low-Side Switch On-Resistance V IN = 12V
VIN = 5V 19
23 m
Rev. 1.1 September 2010 www.aosmd.com Page 5 of 14
AOZ1037
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light Load Operation
2ms/div
Start Up to Full Load
1ms/div
Full Load (CCM) Operation
1µs/div
Short Circuit Protection
50µs/div
Short Circuit Recovery
1ms/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
IL
1A/div
VLX
10V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
IL
1A/div
VLX
10V/div
Vin
10V/div
Vo
2V/div
lin
1A/div
LX
10V/div
Vo
2V/div
IL
2A/div
LX
10V/div
Vo
2V/div
IL
2A/div
Rev. 1.1 September 2010 www.aosmd.com Page 6 of 14
AOZ1037
Efficiency
Efficiency (VIN = 12V) vs. Load Current
40%
50%
60%
70%
80%
90%
100%
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Load Current (A)
Efficiency (%)
5V OUTPUT
3.3V OUTPUT
1.8V OUTPUT
1.2V OUTPUT
Efficiency (VIN = 5V) vs. Load Current
40%
50%
60%
70%
80%
90%
100%
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Load Current (A)
Efficiency (%)
3.3V OUTPUT
1.8V OUTPUT
1.2V OUTPUT
Rev. 1.1 September 2010 www.aosmd.com Page 7 of 14
AOZ1037
Detailed Description
The AOZ1037 is a current-mode step down regulator with
integrated high-side PMOS switch and a low-side NMOS
switch. It operates from a 4.5V to 18V input volt age range
and supplies up to 5A of load current.
Features include
enable control, Power-On
Reset, input under voltage
lockout, output over voltage protection, active high power
good state, fixed internal soft-start and thermal shut
down.
The AOZ1037 is available in exposed pad SO-8
package.
Enable and Soft Start
The AOZ1037 has an internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In the soft start process, the output
voltage is typically ramped to regulation voltage in 3ms.
The 3ms soft start time is set internally.
The EN pin of the AOZ1037 is active HIGH. Connect the
EN pin to VIN if the enable function is not used. Pulling
EN to ground will disable the AOZ1037. Do not leave it
open. The voltage on the EN pin must be above 2V to
enable the AOZ1037. When voltage on the EN pin falls
below 0.6V, the AOZ1037 is disabled. If an application
circuit requires the AOZ1037 to be disabled, an open
drain or open collector cir cuit should be used to interface
to the EN pin.
Power Good
The output of Power-Good is an open drain N-channel
MOSFET, which supplie s an activ e high po wer go od
stage. A pull-up resisto r (R3) sho uld connect this p in to a
DC poer trail with maximum voltage no higher than 6V.
The AOZ1037 monitors the FB voltage: when FB pin
voltage is lower than 90% of the normal voltage, N-
channel MOSFET turns on and the Power-Good pin is
pulled low, which indicates the power is abnormal.
Steady-State Operation
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1037 integrates an internal P-MOSFET as the
high-side switch. In ductor current is sensed by amplifying
the voltage drop acro ss the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal tran sconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
against the current signal, which is sum of indu ctor
current signal and ramp compensation signal, at the
PWM comparator input. If the current signal is less than
the error voltage, the internal high-side switch is on. The
inductor current fl ows from the input thro ugh the in ductor
to the output. When the current signal exceeds the error
voltage, the high-side switch is off. The inductor current
is freewheeling through the inter nal low-side N-M OSFET
switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both high-side and
low-side switch.
Comparing with regulators using freewheeling Schottky
diodes, the AOZ1037 uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficien cy and reduces power loss in the
low-side switch.
The AOZ1037 uses a P-Channel MOSFET as the high-
side switch. It saves the bootstrap capacitor normally
seen in a circuit which is using an NMOS switch.
Switching Frequency
The AOZ1037 switching fr eq uen cy is fixed and set by an
internal oscillator. The practical switching frequency
could range from 400 kHz to 600 kHz due to device
variation.
Light Load Mode
The AOZ1037 includes is a Pulse-Skip architecture for
Light Load operation, enabling increased efficiency
during standby. Under Heavy Loads, the controller
operates in a standard Synchr onous Mode using the
high-side PMOS as control FET and low-side NMOS as
synchronous rectifier NMOS. During Light Loads, the
controller automatically switches to a Non-Synchronous
mode using the high-side PMOS as control FET and the
integrated diode as freewheeling rectifier diode.
Output Volt age Programming
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider networ k. In the
application circuit shown in Figure 1, the resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below:
VO0.8 1 R1
R2
-------
+
⎝⎠
⎜⎟
⎛⎞
×=
AOZ1037
Rev. 1.1 September 2010 www.aosmd.com Page 8 of 14
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1.
Table 1.
The combination of R1 a nd R2 sho uld be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
Protection Features
The AOZ1037 has multiple pr otection features to prevent
system circuit damage under abnormal conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current prot ection. Since the AOZ 1 03 7 em p l oy s pea k
current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
When the output is shorted to ground under fault
conditions, the inductor current decays very slow during
a switching cycle because of VO = 0V. To prevent
catastroph ic failure, a secondary current limit is designed
inside the AOZ1037. The me asured inductor current is
compared against a preset voltage which represents the
current limit. When the output current is more than
current limit, the high side switch will be turned off and
EN pin will be pulled down. The converter will initiate a
soft start once the over-current condition disappears.
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage. When
the input voltage exceeds 4.1V, the converter starts
operation. When input voltage falls below 3.7V, the
converter will be shut down.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shut s down the inte rnal control circuit and
high side PMOS if the junction temperature exceeds
150°C. The regulator will restart automatically under the
control of soft- start circuit when the junction temperature
decreases to 100°C.
Application Information
The basic AOZ1037 application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
The input ca pacitor must be connected to the VIN pin and
PGND pin of AOZ1037 to maintain steady input voltage
and filter out the pulsing input cur re nt. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
Since the input current is discontinu ous in a buck
converter, the curren t stre ss on the input capacitor is
another concern when selectin g the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
if we let m equal the conversion ratio:
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2 below. It can be seen that when VO is
half of VIN, CIN is under the worst current stress. The
worst current stress on CIN is 0.5 x IO.
VO (V) R1 (k) R2 (k)
0.8 1.0 Open
1.2 4.99 10
1.5 10 11.5
1.8 12.7 10.2
2.5 21.5 10
3.3 31.1 10
5.0 52.3 10
ΔVIN IO
fC
IN
×
----------------- 1VO
VIN
---------
⎝⎠
⎜⎟
⎛⎞
VO
VIN
---------
××=
ICIN_RMS IOVO
VIN
---------1VO
VIN
---------
⎝⎠
⎜⎟
⎛⎞
×=
VO
VIN
---------m=
AOZ1037
Rev. 1.1 September 2010 www.aosmd.com Page 9 of 14
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input
capacitors must have cur rent ratin g highe r than ICIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics.
Note that the ripple current rating from capacitor
manufactures are based on certain amount of life time.
Further de-rating may be necessary in practical design.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
The peak inductor current is:
High inductance gives low inductor ripple current but
requires larger size indu ct or to avo id sa tur a tion . Lo w
ripple current reduces inductor core losses. It also
reduces RMS curr en t thr o ug h ind u cto r an d swit ch es,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20%
to 30% of output current.
When selecting the ind ucto r, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be ch ecked for
thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating , output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-ratin g ne ed s to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
If the impedance of ESR at switching frequency
dominates, the output ripple volt a ge is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
0
0.1
0.2
0.3
0.4
0.5
0 0.5 1
m
I
CIN_RMS
(m)
I
O
ΔILVO
fL×
-----------1VO
VIN
---------
⎝⎠
⎜⎟
⎛⎞
×=
ILpeak IO
ΔIL
2
--------
+=
ΔVOΔILESRCO 1
8fC
O
××
-------------------------
+
⎝⎠
⎛⎞
×=
ΔVOΔIL1
8fC
O
××
-------------------------
×=
ΔVOΔILESRCO
×=
AOZ1037
Rev. 1.1 September 2010 www.aosmd.com Page 10 of 14
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR t antalu m are recommended
to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It
can be calculated by:
Usually, the ripple current rating of the output cap acitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
External Schottky Diode for High Input Operation
When VIN is higher than 16V, an external 1A schottky
diode is required between LX and PGND for proper
operation.
Loop Compensation
The AOZ1037 employs peak current mode control for
easy use and fast tr ansient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape th e
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ1037. For most cases, a
series capacitor and resistor network connected to the
COMP pin set s the pole-zero an d is adequate for a st able
high-bandwidth control loop.
In the AOZ1037, FB pin and COMP pin are the inverting
input and the output of internal erro r amplifier. A series
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
C2 is the compensation capacitor in Figure 1.
The zero given by the external compensation network,
capacitor C2 and resistor R3, is located at:
To design the compensation circuit, a target crossover
frequency fC for close loop must be se lected. The system
crossover frequency is wher e control loop has unity gain .
The crossover is the also called the con verter bandwid th.
Generally a hig her bandwidth means faster response to
load transient. Howe ver, the bandwidth sho uld not be too
high because of system stability concern. When
designing the compensation loop, converter stability
under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1037 operates at a frequency range from 400kHz to
600kHz. It is recommended to choose a crossover
frequency equal or less than 40kHz.
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the comp ensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
ICO_RMS
ΔIL
12
----------
=
fP11
2πCORL
××
-----------------------------------
=
fZ11
2πCOESRCO
××
------------------------------------------------
=
fP2GEA
2πC2GVEA
××
------------------------------------------
=
fZ21
2πC2R3
××
----------------------------------
=
fC40kHz=
RCfCVO
VFB
---------- 2πC2
×
GEA GCS
×
------------------------------
××=
AOZ1037
Rev. 1.1 September 2010 www.aosmd.com Page 11 of 14
where;
fC is the desired crossover frequency. For best performance,
fC is set to be about 1/10 of the switching frequency;
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V, and
GCS is the current sense circuit transconductance, which is 6.68
A/V
The compensation capacitor CC and resistor RC to gether
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. C2 can is selected by:
The above equation can be simplified to:
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Consideration
In the AOZ1037 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX
pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output cap acitors and load, to the low-side NMOSFET.
Current flows in the second loop when the low-side
NMOSFET is on.
In PCB layout, minimizing the two loops area redu ces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input
capacitor, output capacitor, and PGND pin of the
AOZ1037.
In the AOZ1037 buck regulato r circuit, the major power
dissip ating compo nent s are the AOZ1 037 an d the outp ut
inductor. The total power dissip ation of converter circuit
can be measured by input power minus output power.
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
The actual junction temperature can be calculated with
power dissipation in the AOZ1037 and thermal
impedance from junction to ambient.
The maximum junction temperature of AOZ1037 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1037 under different ambient
temperature.
The thermal performance of the AOZ1037 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
The AOZ1037 is an expo se d pad SO-8 package. La yo ut
tips are listed below for the best electric and thermal
performance.
1. The exposed p ad LX pins are connected to internal
PFET and NFET drains. Connect a large copper
plane to the LX pins to help thermal dissipation.
2. Do not use thermal relief connection to the VIN
and the PGND pin. Pour a maximized copper ar ea
to the PGND pin and the VIN pin to help thermal
dissipation.
3. Input capacitor should be connected as close as
possible to the VIN pin and the PGN D pin to red uc e
the LX voltage over-shoot. This is especially impor-
tant for VIN >16V.
4. A ground plane is suggested. If a ground plane is
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
5. Make the current tr ace from the LX pin s to L to CO to
the PGND as short as possible.
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or VOUT.
CC1.5
2πR3fP1
××
-----------------------------------
=
CCCORL
×
R3
---------------------
=
Ptotal_loss VIN IIN VOIO
××=
Pinductor_loss IO2Rinductor 1.1××=
Tjunction Ptotal_loss Pinductor_loss
()Θ×JA
=
AOZ1037
Rev. 1.1 September 2010 www.aosmd.com Page 12 of 14
Package Dimensions, SO-8 EP1
Notes:
1. Package body sizes exclude mold flash and gate burrs.
2. Dimension L is measured in gauge plane.
3. Tolerance 0.10mm unless otherwise specified.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Followed from JEDEC MS-012
Symbols
A
A1
A2
B
C
D
D0
D1
E
e
E1
E2
E3
L
y
θ
|
L1–L1'
|
L1
Dimensions in millimeters
RECOMMENDED LAND PATTERN
Min.
1.40
0.00
1.40
0.31
0.17
4.80
3.20
3.10
5.80
3.80
2.21
0.40
0
D0
UNIT: mm
θ
Nom.
1.55
0.05
1.50
0.406
4.96
3.40
3.30
6.00
1.27
3.90
2.41
0.40 REF
0.95
3
0.04
1.04 REF
Max.
1.70
0.10
1.60
0.51
0.25
5.00
3.60
3.50
6.20
4.00
2.61
1.27
0.10
8
0.12
Dimensions in inches
D1
E1 E
E3E2
Note 5
L1'
L1
L
Gauge plane
0.2500 C
D
7 (4x)
B
3.70
2.20
2.87
2.71
5.74
1.27 0.80
0.635
eA1
A2 A
Symbols
A
A1
A2
B
C
D
D0
D1
E
e
E1
E2
E3
L
y
θ
|
L1–L1'
|
L1
Min.
0.055
0.000
0.055
0.012
0.007
0.189
0.126
0.122
0.228
0.150
0.087
0.016
0
Nom.
0.061
0.002
0.059
0.016
0.195
0.134
0.130
0.236
0.050
0.153
0.095
0.016 REF
0.037
3
0.002
0.041 REF
Max.
0.067
0.004
0.063
0.020
0.010
0.197
0.142
0.138
0.244
0.157
0.103
0.050
0.004
8
0.005
AOZ1037
Rev. 1.1 September 2010 www.aosmd.com Page 13 of 14
Tape and Reel Dimensions
SO-8 Carrier Tape
SO-8 Reel
SO-8 Tape
Leader/Trailer
& Orientation
Tape Size
12mm
Reel Size
ø330
M
ø330.00
±0.50
Package
SO-8
(12mm)
A0
6.40
±0.10
B0
5.20
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.10
T
0.25
±0.10
N
ø97.00
±0.10
K0
Unit: mm
B0
G
M
W1
S
K
H
N
W
V
R
Trailer Tape
300mm min. or
75 empty pockets
Components Tape
Orientation in Pocket
Leader Tape
500mm min. or
125 empty pockets
A0
P1
P2
See Note 5
See Note 3
See Note 3
Feeding Direction
P0
E2
E1
E
D0
T
D1
W
13.00
±0.30
W1
17.40
±1.00
H
ø13.00
+0.50/-0.20
K
10.60
S
2.00
±0.50
G
R
V
AOZ1037
Rev. 1.1 September 2010 www.aosmd.com Page 14 of 14
Part Marking
Z1037PI
FAY Part Number Code
Assembly Lot Code
Year & Week Code
WLT
Fab & Assembly Location
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.