Product Folder Order Now Technical Documents Support & Community Tools & Software Reference Design TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 TPS62125 3-V to 17-V, 300-mA Step-Down Converter With Adjustable Enable Threshold and Hysteresis 1 Features 3 Description * * The TPS62125 device is a high-efficiency synchronous step-down converter optimized for low and ultralow power applications providing up to 300mA output current. The wide input voltage range of 3 V to 17 V supports 4-cell alkaline and 1- to 4-cell LiIon batteries in series configuration as well as 9-V to 15-V powered applications. The device includes a precise low-power enable comparator which can be used as an input supply voltage supervisor (SVS) to address system specific power-up and power-down requirements. The enable comparator consumes only 6-A quiescent current and features an accurate threshold of 1.2 V typical as well as an adjustable hysteresis. With this feature, the converter can generate a power supply rail by extracting energy from a storage capacitor fed from high impedance sources such as solar panels or current loops. With its DCS-Control scheme the converter provides power-save mode operation to maintain highest efficiency over the entire load current range. At light loads the converter operates in pulse frequency modulation (PFM) mode and transitions seamlessly and automatically in pulse width modulation (PWM) mode at higher load currents. The DCS-ControlTM scheme is optimized for low-output ripple voltage in PFM mode in order to reduce output noise to a minimum and features excellent AC load regulation. An open-drain power good output indicates once the output voltage is in regulation. 1 * * * * * * * * * * * * * Wide Input Voltage Range 3 V to 17 V Input Supply Voltage Supervisor (SVS) With Adjustable Threshold and Hysteresis Consuming Typical 6-A Quiescent Current Wide Output Voltage Range 1.2 V to 10 V Typical 13-A Quiescent Current 350-nA Typical Shutdown Current Seamless Power Save Mode Transition DCS-ControlTM Scheme Low Output Ripple Voltage Up to 1-MHz Switching Frequency Highest Efficiency over Wide VIN and VOUT Range Pin to Pin Compatible with TPS62160/70 100% Duty Cycle Mode Power Good Open Drain Output Output Discharge Function Small 2-mm x 2-mm 8-pin WSON Package 2 Applications * * * * * Embedded Processing 4-Cell Alkaline, 1- to 4-Cell Li-Ion Battery-Powered Applications 9-V to 15-V Standby Power Supply Energy Harvesting Inverter (Negative VOUT) Device Information(1) PART NUMBER PACKAGE TPS62125 BODY SIZE (NOM) WSON (8) 2.00 mm x 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Schematic TPS62125 VIN L 15H SW R1 1.8M VOS CIN 10F EN FB R2 576k EN_hys Rpullup GND PG 10mA 100mA 90 PWR GOOD COUT 10F 85 250mA 1.0mA 80 Efficiency (%) VIN = 4V to 17V Efficiency vs Input Voltage 95 VOUT = 3.3V up to 300mA 75 70 0.25mA 65 VOUT = 3.3V L = 15mH VLF302515 COUT = 10mF 60 0.1mA 55 50 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage VIN(V) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 7.2 7.3 7.4 Overview ................................................................... 9 Functional Block Diagram ......................................... 9 Feature Description................................................. 10 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application .................................................. 13 8.3 System Examples .................................................. 26 9 Power Supply Recommendations...................... 28 10 Layout................................................................... 28 10.1 Layout Guidelines ................................................. 28 10.2 Layout Example .................................................... 28 11 Device and Documentation Support ................. 29 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 29 29 29 29 29 29 12 Mechanical, Packaging, and Orderable Information ........................................................... 29 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (July 2015) to Revision E * Added SW node AC abs max ratings .................................................................................................................................... 4 Changes from Revision C (December 2013) to Revision D * 2 Page Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 5 Pin Configuration and Functions DSG Package 8-Pin WSON Top View 8 1 2 3 TH E ER XP M OS A ED L PA D GND VIN EN EN_hys 4 7 6 5 PG SW VOS FB Pin Functions PIN NAME EN NO. 3 I/O IN DESCRIPTION Input pin for the enable comparator. Pulling this pin to GND turns the device into shutdown mode. The DC/DC converter is enabled once the rising voltage on this pin trips the enable comparator threshold, VTH EN ON of typ. 1.2 V. The DC/DC converter is turned off once a falling voltage on this pin trips the threshold, VTH EN OFF of typ. 1.15 V. The comparator threshold can be increased by connecting an external resistor to pin EN_hys. See also application section. This pin must be terminated. EN_hys 4 OUT Enable hysteresis open-drain output. This pin is pulled to GND when the voltage on the EN pin is below the comparator threshold VTH EN ON of typ. 1.2 V and the comparator has not yet tripped. The pin is high impedance once the enable comparator has tripped and the voltage at the pin EN is above the threshold VTH EN ON. The pin is pulled to GND once the falling voltage on the EN pin trips the threshold VTH EN OFF (1.15 V typical). This pin can be used to increase the hysteresis of the enable comparator. If not used, tie this pin to GND, or leave it open. FB 5 IN This is the feedback pin for the regulator. An external resistor divider network connected to this pin sets the output voltage. In case of fixed output voltage option, the resistor divider is integrated and the pin need to be connected directly to the output voltage. GND 1 PWR GND supply pin. PG 8 OUT Open drain power good output. This pin is internally pulled to GND when the device is disabled or the output voltage is below the PG threshold. The pin is floating when the output voltage is in regulation and above the PG threshold. For power good indication, the pin can be connected via a pull up resistor to a voltage rail up to 10 . The pin can sink a current up to 0.4 mA and maintain the specified high/low voltage levels. It can be used to discharge the output capacitor with up to 10 mA. In this case the current into the pin must be limited with an appropriate pull up resistor. More details can be found in the application section. If not used, leave the pin open, or connect to GND. SW 7 OUT This is the switch pin and is connected to the internal MOSFET switches. Connect the inductor to this pin. Do not tie this pin to VIN, VOUT or GND. VIN 2 PWR VIN power supply pin. VOS 6 IN This is the output voltage sense pin for the DCS-Control circuitry. This pin must be connected to the output voltage of the DC/DC converter. Exposed Thermal PAD - - This pad must be connected to GND. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 3 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings Pin voltage (2) MIN MAX UNIT VIN -0.3 20 V SW (DC) -0.3 VIN + 0.3V V SW (AC, less than 10ns) (3) -3.0 23.5 V EN -0.3 VIN + 0.3 V FB -0.3 3.6 V VOS, PG -0.3 12 V EN_hys -0.3 7 V 10 mA Power good sink current IPG EN_hys sink current IEN_hys 3 mA Maximum operating junction temperature, TJ -40 125 C Storage temperature, Tstg -65 150 C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal GND. While switching 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN NOM MAX VIN Supply voltage 3 Output current capability TA Operating ambient temperature TJ Operating junction temperature, (1) (1) 3 V VIN < 6 V 200 6 V VIN 17 V 300 (Unless Otherwise Noted) UNIT 17 V mA -40 85 C -40 125 C In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)) and the maximum power dissipation of the device in the application (PD(max)); for more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.4 Thermal Information TPS62125 THERMAL METRIC (1) DSG (WSON) UNIT 8 PINS RJA Junction-to-ambient thermal resistance 65.2 C/W RJC(top) Junction-to-case (top) thermal resistance 93.3 C/W RJB Junction-to-board thermal resistance 30.1 C/W JT Junction-to-top characterization parameter 0.5 C/W JB Junction-to-board characterization parameter 47.4 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 7.2 C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 6.5 Electrical Characteristics TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted), VIN = 12 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input voltage range (1) 3 17 V VOUT Output voltage range 1.2 10 V 23 A IQ Quiescent current IOUT = 0 mA, device not switching, EN = VIN, regulator sleeps 13 IOUT = 0 mA, device switching, VIN = 7.2 V, VOUT = 1.2 V, L = 22 H 14 A VIN = 5 V, EN = 1.1 V, enable comparator active, device DC/DC converter off 6 11 A IActive Active mode current consumption VIN = 5 V = VOUT, TA = 25C, high-side MOSFET switch fully turned on (100% mode) 230 275 A ISD Shutdown current (2) Enable comparator off, EN < 0.4 V, VOUT = SW = 0 V, VIN = 5 V 0.35 2.4 A VUVLO Undervoltage lockout threshold Falling VIN 2.8 2.85 V Rising VIN 2.9 2.95 V 1.16 1.20 1.24 V 1.12 1.15 1.19 ENABLE COMPARATOR THRESHOLD AND HYSTERESIS (EN, EN_hys) VTH EN ON EN pin threshold rising edge VTH EN OFF EN pin threshold falling edge VTH EN Hys EN pin hysteresis IN IIN EN Input bias current into EN pin EN = 1.3 V VEN_hyst EN_hys pin output low IEN_hyst = 1 mA, EN = 1.1 V IIN EN_hyst Input bias current into EN_hyst pin EN_hyst = 1.3 V 3 V V 17 V 50 0 0 V mV 50 nA 0.4 V 50 nA POWER SWITCH High-side MOSFET ON-resistance RDS(ON) Low-side MOSFET ON-resistance ILIMF TSD VIN = 3 V, I = 100 mA 2.4 4 VIN = 12 V, I = 100 mA 1.5 2.6 VIN = 3 V, I = 100 mA 0.75 1.3 VIN = 12 V, I = 100 mA 0.6 1 750 900 Switch current limit high-side MOSFET VIN = 12 V Thermal shutdown Increasing junction temperature 150 C Thermal shutdown hysteresis Decreasing junction temperature 20 C 500 ns 60 ns 0.808 V 600 mA OUTPUT tONmin Minimum ON-time VIN = 5 V, VOUT = 2.5 V tOFFmin Minimum OFF-time VIN = 5 V VREF_FB Internal reference voltage of error amplifier VFB Feedback voltage accuracy Referred to internal reference (VREF_FB) Feedback voltage line regulation IOUT = 100 mA, 5 V VIN 17 V, VOUT = 3.3 V (3) -2.5% (3) 0% 2.5% -0.05 %/V -0.00 4 %/mA Feedback voltage load regulation VOUT = 3.3 V; IOUT = 1 mA to 300 mA, VIN = 12 V Input bias current into FB pin VFB = 0.8 V tStart Regulator start-up time Time from EN high to device starts switching, VIN = 5 V tRamp Output voltage ramp time Time to ramp up VOUT = 1.8 V, no load 200 ILK_SW Leakage current into SW pin (4) 2.85 A Bias current into VOS pin VOS = VIN = VSW = 1.8 V, EN = GND, device in shutdown mode 1.8 IIN_VOS 0 50 nA IIN_FB (1) (2) (3) (4) 0 50 50 nA s The part is functional down to the falling UVLO (Undervoltage Lockout) threshold Current into VIN pin VOUT = 3.3 V, L = 15 H, COUT = 10 F An internal resistor divider network with typ. 1 M total resistance is connected between SW pin and GND. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 5 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com Electrical Characteristics (continued) TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted), VIN = 12 V PARAMETER TEST CONDITIONS MIN TYP MAX Rising VFB feedback voltage 93% 95% 97% Falling VFB feedback voltage 87% 90% 93% UNIT POWER GOOD OUTPUT (PG) VTH_PG Power good threshold voltage VOL PG pin output low voltage Current into PG pin IPG= 0.4 mA 0.3 VOH PG pin output high voltage Open drain output, external pullup resistor 10 V IIN_PG Bias current into PG pin V(PG) = 3 V, EN = 1.3 V, FB = 0.85 V 50 nA 6 Submit Documentation Feedback 0 V Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 6.6 Typical Characteristics 25 1.5 1.4 1.3 TA = 85C 1.2 20 Quiescent Current IQ (mA) Shutdown Current - ISD [mA] 1.1 TA = 60C 1.0 0.9 TA = 25C 0.8 TA = 0C 0.7 0.6 TA = -40C 0.5 IQ no switching: TA= 85C IQ no switching: TA= 60C 15 IQ no switching: TA= 25C 10 IQ no switching: TA= -40C 0.4 IQ device switching: TA= 25C, VOUT = 1.8V, IOUT = 0mA no load, EN = VIN 5 0.3 0.2 0.1 0 3 4 5 6 7 0 8 9 10 11 12 13 14 15 16 17 Input Voltage - VIN [V] Figure 1. Shutdown Current vs. Input Voltage 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) Figure 2. Quiescent Current vs. Input Voltage 1000 25 VIN = 6V TA = 85C 20 Quiescent Current (mA) Quiescent Current (mA) 100 VIN = 6V TA = 25C VIN = 6V TA = 85C VIN = 6V TA = -40C VIN = 12V TA = 25C VIN = 12V TA = 85C VIN = 12V TA = -40C 10 VIN = 12V TA = 85C VIN = 6V TA = 25C 15 VIN = 12V TA = 25C VIN = 6V TA = -40C VIN = 12V TA = -40C 10 1 5 0.1 0 200 400 600 800 1000 Voltage VEN (mV) 1200 0 200 400 600 800 1000 Voltage VEN (mV) 1200 1400 Figure 4. Quiescent Current vs. VEN Voltage, Falling VEN 3 2.8 2.6 2.4 VTH EN ON TA = 25C VTH EN ON TA = -40C 2.2 VTH EN ON TA = 85C TA = 85C 2 RDSON (W) EN Comparator Threshold - VTH EN (V) Figure 3. Quiescent Current vs. EN Voltage, Rising VEN 1.25 1.245 1.24 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 1.18 1.175 1.17 1.165 1.16 1.155 1.15 0 1400 TA = 60C 1.8 1.6 1.4 1.2 1 VTH EN OFF TA = 25C VTH EN OFF TA = -40C VTH EN OFF TA = 85C TA = 0C TA = -40C 0.8 TA = 25C 0.6 0.4 0.2 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage VIN (V) Figure 5. EN Comparator Thresholds vs. Input Voltage 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage VIN [V] Figure 6. RDSON High-Side Switch Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 7 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com Typical Characteristics (continued) 1.0 0.9 TA = 85C 0.8 TA = 60C 0.7 RDSON (W) 0.6 0.5 0.4 TA = 0C 0.3 TA = 25C TA = -40C 0.2 0.1 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage - VIN [V] Figure 7. RDSON Low-Side Switch (Rectifier) 8 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 7 Detailed Description 7.1 Overview The TPS62125 high-efficiency synchronous switch mode buck converter includes TI's DCS-Control (Direct Control with Seamless Transition into Power-Save Mode), an advanced regulation topology, which combines the advantages of hysteretic and voltage mode control. Characteristics of DCS-Control are excellent AC load regulation and transient response, low-output ripple voltage and a seamless transition between PFM and PWM mode operation. DCS-Control includes an AC loop which senses the output voltage (VOS pin) and directly feeds the information to a fast comparator stage. This comparator sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. In order to achieve accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. The DCS-Control topology supports pulse width modulation (PWM) mode for medium and high load conditions and a power-save mode at light loads. During PWM mode, it operates in continuous conduction. The switch frequency is up to 1 MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter seamless enters power-save mode to maintain high efficiency down to very light loads. In power-save mode the switching frequency varies linearly with the load current. Because DCS-Control supports both operation modes within one single building block, the transition from PWM to power-save mode is seamless without effects on the output voltage. The TPS62125 offers both excellent DC voltage and superior load transient regulation, combined with very low-output voltage ripple, minimizing interference with RF circuits. At high load currents the converter operates in quasi fixed frequency PWM mode operation and at light loads in pulse frequency modulation (PFM) mode to maintain highest efficiency over the full load current range. In PFM mode, the device generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a sleep period where most of the internal circuits are shutdown to achieve a quiescent current of typically 13 A. During this time, the load current is supported by the output capacitor. The duration of the sleep period depends on the load current and the inductor peak current. 7.2 Functional Block Diagram ON/ SD VREF EN 1.2V VREF_FB 0.808V Softstart Softstart PG Comparator EN VREF PG VTH_PG UVLO Comparator FB VIN EN Comparator VUVLO EN_hys EN_comp DC-DC ON/OFF Peak Current Limit Comparator GND Limit High Side Timer DCS Control VOS VIN VOS Min. On Control Logic VIN PMOS Min. OFF Direct Control & Compensation Gate Driver Anti Shoot-Through SW VREF_FB FB Error amplifier fixed VOUT NMOS Comparator GND Thermal Shutdown Zero Current Comparator Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 9 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com 7.3 Feature Description 7.3.1 Undervoltage Lockout In addition to the EN comparator, the device includes an under-voltage lockout circuit which prevents the device from misoperation at low input voltages. Both circuits are fed to an AND gate and prevents the converter from turning on the high-side MOSFET switch or low-side MOSFET under undefined conditions. The UVLO threshold is set to 2.9 V typical for rising VIN and 2.8 V typical for falling VIN. The hysteresis between rising and falling UVLO threshold ensures proper start-up. Fully functional operation is permitted for an input voltage down to the falling UVLO threshold level. The converter starts operation again once the input voltage trips the rising UVLO threshold level and the voltage at the EN pin trips VTH_EN_ON. 7.3.2 Enable Comparator (EN / EN_hys) The EN pin is connected to an on/shutdown detector (ON/SD) and an input of the enable comparator. With a voltage level of 0.4 V or less at the EN pin, the ON/SD detector turns the device into Shutdown mode and the quiescent current is reduced to typically 350 nA. In this mode the EN comparator as well the entire internalcontrol circuitry are switched off. A voltage level of typical 900 mV (rising) at the EN pin triggers the on/shutdown detector and activates the internal reference VREF (typical 1.2 V), the EN comparator and the UVLO comparator. In applications with slow rising voltage levels at the EN pin, the quiescent current profile before this trip point needs to be considered, see Figure 3. Once the ON/SD detector has tripped, the quiescent current consumption of the device is typical 6 A. The TPS62125 starts regulation once the voltage at the EN pin trips the threshold VEN_TH ON (typical 1.2 V) and the input voltage is above the UVLO threshold. It enters softstart and ramps up the output voltage. For proper operation, the EN pin must be terminated and must not be left floating. The quiescent current consumption of the TPS62125 is typical 13 A under no load condition (not switching). See Figure 1. The DC/DC regulator stops operation once the voltage on the EN pin falls below the threshold VEN_TH OFF (typical 1.15 V) or the input voltage falls below UVLO threshold. The enable comparator features a built in hysteresis of typical 50 mV. This hysteresis can be increased with an external resistor connected to pin EN_hys. 7.3.3 Power Good Output and Output Discharge (PG) The power good output (PG pin) is an open drain output. The circuit is active once the device is enabled. It is driven by an internal comparator connected to the FB pin voltage and an internal reference. The PG output provides a high level (open drain high impedance) once the feedback voltage exceeds typical 95% of its nominal value. The PG output is driven to low level once the FB pin voltage falls below typical 90% of its nominal value VREF_FB. The PG output goes high (high impedance) with a delay of typically 2 s. A pull up resistor is needed to generate a high level. The PG pin can be connected via a pull up resistors to a voltage up to 10 V. This pin can also be used to discharge the output capacitor. See section Application Information for more details. The PG output is pulled low if the voltage on the EN pin falls below the threshold VEN_TH is below the undervoltage lockout threshold UVLO. OFF or the input voltage 7.3.4 Thermal Shutdown As soon as the junction temperature, TJ, exceeds 150C (typical) the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis. 7.4 Device Functional Modes 7.4.1 Pulse Width Modulation (PWM) Operation The TPS62125 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal switching frequency of about 1 MHz. The frequency variation in PWM mode is controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device enters power-save mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than half the inductor's ripple current. 10 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 Device Functional Modes (continued) 7.4.2 Power-Save Mode With decreasing load current, the TPS62125 transitions seamlessly from PWM mode to power-save mode once the inductor current becomes discontinuous. This ensures a high efficiency at light loads. In power-save mode the converter operates in pulse frequency modulation (PFM) mode and the switching frequency decreases linearly with the load current. DCS-Control features a small and predictable output voltage ripple in power-save mode. The transition between PWM mode and power-save mode occurs seamlessly in both directions. The minimum ON-time TONmin for a single pulse can be estimated by: TON = VOUT 1ms VIN (1) Therefore the peak inductor current in PFM mode is approximately: (VIN - VOUT ) T ILPFMpeak = ON L where * * * * * TON: High-side MOSFET switch on time [s] VIN: Input voltage [V] VOUT: Output voltage [V] L : Inductance [H] ILPFMpeak : PFM inductor peak current [mA] (2) The transition from PFM mode to PWM mode operation and back occurs at a load current of approximately 0.5 x ILPFMpeak. The maximum switching frequency can be estimated by: f SW max 1 = 1MHz 1ms (3) 7.4.3 100% Duty Cycle Low Dropout Operation The device increases the ON-time of the high-side MOSFET switch as the input voltage comes close to the output voltage in order to keep the output voltage in regulation. This reduces the switching frequency. With further decreasing input voltage VIN, the high-side MOSFET switch is turned on completely. In this case, the converter provides a low input-to-output voltage difference. This is particularly useful in applications with a widely variable supply voltage to achieve longest operation time by taking full advantage of the whole supply voltage span. The minimum input voltage to maintain output voltage regulation depends on the load current and output voltage, and can be calculated as: VIm in = VOUT min + I OUT ( RDSON max + RL ) where * * * * IOUT: Output current RDS(ON)max: Maximum high-side switch RDS(ON) RL: DC resistance of the inductor VOUTmin: Minimum output voltage the load can accept (4) 7.4.4 Soft-Start The TPS62125 has an internal soft-start circuit which controls the ramp up of the output voltage and limits the inrush current during start-up. This limits input voltage drop. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 11 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com Device Functional Modes (continued) The soft-start system generates a monotonic ramp up of the output voltage and reaches an output voltage of 1.8 V typical within 240 s after the EN pin was pulled high. For higher output voltages, the ramp up time of the output voltage can be estimated with a ramp up slew rate of about 12 mV/us. TPS62125 is able to start into a prebiased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its nominal value. In case the output voltage is higher than the nominal value, the device starts switching once the output has been discharged by an external load or leakage current to its nominal output voltage value. During start-up the device can provide an output current of half of the high-side MOSFET switch current limit ILIMF. Large output capacitors and high load currents may exceed the current capability of the device during startup. In this case the start-up ramp of the output voltage will be slower. 7.4.5 Short-Circuit Protection The TPS62125 integrates a high-side MOSFET switch current limit, ILIMF, to protect the device against a short circuit. The current in the high-side MOSFET switch is monitored by a current limit comparator and once the current reaches the limit of ILIMF , the high-side MOSFET switch is turned off and the low-side MOSFET switch is turned on to ramp down the inductor current. The high-side MOSFET switch is turned on again once the zero current comparator trips and the inductor current has become zero. In this case, the output current is limited to half of the high-side MOSFET switch current limit, 0.5 x ILIMF, typ. 300mA. 12 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS62125 is a high-efficiency synchronous step-down converter providing a wide output voltage range from 1.2 V to 10 V. 8.2 Typical Application TPS62125 VIN = 4V to 17V VIN SW R1 1.8M VOS EN CIN 10F VOUT = 3.3V up to 300mA L 15H FB COUT 10F R2 576k EN_hys Rpullup GND PG PWR GOOD Figure 8. TPS62125 3.3-V Output Voltage Configuration 8.2.1 Design Requirements The device operates over an input voltage range from 3 V to 17 V. The output voltage is adjustable using an external feedback divider. 8.2.2 Detailed Design Procedure 8.2.2.1 Output Voltage Setting The output voltage can be calculated by: ae R o VOUT = VREF _ FB cc1 + 1 // e R2 o ae R VOUT = 0.8V cc1 + 1 e R2 o aeV R1 = R2 c OUT - 1/ o e 0.8V o // o (5) Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 13 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com Typical Application (continued) The internal reference voltage for the error amplifier, VREF_FB, is nominal 0.808 V. However for the feedback resistor divider selection, it is recommended to use the value 0.800 V as the reference. Using this value, the output voltage sets 1% higher and provides more headroom for load transients as well for line and load regulation. The current through the feedback resistors R1 and R2 should be higher than 1 A. In applications operating over full temperature range or in noisy environments, this current may be increased for robust operation. However, higher currents through the feedback resistors impact the light load efficiency of the converter. Table 1 shows a selection of suggested values for the feedback divider network for most common output voltages. Table 1. Suggested Values for Feedback Divider Network OUTPUT VOLTAGE 1.2 V 1.8 V 3.3 V 5V 6.7 V 8V R1 [k] 180 300 1800 1100 1475 1800 R2 [k] 360 240 576 210 200 200 8.2.2.2 Enable Threshold and Hysteresis Setting ON/SD VREF 1.2V VIN VIN REN1 EN EN Comparator VTH_EN REN2 EN_hys REN HYS GND Figure 9. Using the Enable Comparator Threshold and Hysteresis for an Input SVS (Supply Voltage Supervisor) The enable comparator can be used as an adjustable input supply voltage supervisor (SVS) to start and stop the DC/DC converter depending on the input voltage level. The input voltage level, VIN_startup, at which the device starts up is set by the resistors REN1 and REN2 and can be calculated by : ae R V IN _ startup = V EN _ TH _ ON cc1 + EN 1 REN 2 e o ae R // = 1.2V cc1 + EN 1 REN 2 o e o // o (6) The resistor values REN1 and REN2 can be calculated by: ae V o aeV o R E N 1 = R E N 2 c IN _ startup - 1 / = R E N 2 cc IN _ startup - 1 // cV / e 1 . 2V o e E N _ TH _ O N o R EN 2 = 14 R EN 1 o ae V IN _ startup c - 1/ / cV o e EN _ TH _ O N = (7) R EN 1 o ae V IN _ startup cc - 1 // o e 1 . 2V (8) Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 The input voltage level VIN_stop at which the device will stop operation is set by REN1, REN2 and REN be calculated by: ae R EN 1 V IN _ stop = V EN _ TH _ OFF c 1 + c R EN 2 + R EN _ hys e o ae R EN 1 / = 1 . 15V c 1 + / c R EN 2 + R EN _ hys o e HYS and can o / / o (9) The resistor value REN_hys can be calculated according to: R EN _ hys = R EN 1 ae V IN _ stop o c - 1/ cV / e EN _ TH _ OFF o - R EN 2 = R EN 1 o ae V IN _ stop cc - 1 // o e 1 .15V - R EN 2 (10) The current through the resistors REN1, REN2, and REN HYS should be higher than 1 A. In applications operating over the full temperature range and in noisy environments, the resistor values can be reduced to smaller values. VIN DC/DC start VIN_startup Hysteresis VIN_stop DC/DC stop VOUT Proper VOUT ramp up Figure 10. Using the EN Comparator as Input SVS for Proper VOUT Ramp Up 8.2.2.3 Power Good (PG) Pullup and Output Discharge Resistor The power good open collector output needs an external pull up resistor to indicate a high level. The pull up resistor can be connected to a voltage level up to 10 V. The output can sink current up to 0.4 mA with specified output low level of less than 0.3 V. The lowest value for the pull up resistor can be calculated by: R Pullup min = VOUT - 0.3V 0.0004 A (11) VOUT TPS62125 COUT RPullup RIPG PG Comparator VTH_PG FB PG VPG Power Good max 10V Figure 11. PG Open Collector Output Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 15 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com The PG pin can be used to discharge the output capacitor. The PG output has an internal resistance RIPG of typical 600 and minimum 400 . The maximum sink current into the PG pin is 10 mA. In order to limit the discharge current to the maximum allowable sink current into the PG pin, the external pull up resistor RPull up can be calculated to: RPullup min = VOUT I PG _ max - RIPG _ min = VOUT - 400W 0.01A (12) In case a negative value is calculated, the external pull up resistor can be removed and the PG pin can be directly connected to the output. 8.2.2.4 Output Filter Design (Inductor and Output Capacitor) The external components have to fulfill the needs of the application, but also the stability criteria of the devices control loop. The TPS62125 is optimized to work within a range of L and C combinations. The LC output filter inductance and capacitance have to be considered together, creating a double pole, responsible for the corner frequency of the converter. Table 2 can be used to simplify the output filter component selection. Table 2. Recommended LC Output Filter Combinations INDUCTOR VALUE [H] (1) OUTPUT CAPACITOR VALUE [F] (2) 10 F 2 x 10 F 22 F 47 F 15 22 (3) 15 (3) 22 (3) VOUT 1.2 V - 1.8 V VOUT 1.8 V - 3.3 V VOUT 3.3 V - 5 V 10 15 (3) (3) 10 (3) (3) 15 22 22 VOUT 5 V - 10 V (1) (2) (3) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by 20% and -30%. Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by 20% and -50%. This LC combination is the standard value and recommended for most applications. More detailed information on further LC combinations can be found in application note SLVA515. 8.2.2.5 Inductor Selection The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage ripple and the efficiency. The selected inductor has to be rated for its DC resistance and saturation current. The inductor ripple current (IL) decreases with higher inductance and increases with higher VIN or VOUT and can be estimated according to Equation 13. Equation 14 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 14. This is recommended because during heavy load transient the inductor current will rise above the calculated value. A more conservative way is to select the inductor saturation current according to the high-side MOSFET switch current limit ILIMF. (VIN - VOUT ) DIL = TON L (13) 16 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 ILmax = Ioutmax + IL 2 where * * * * TON: See Equation 1 L: Inductance IL: Peak to Peak inductor ripple current ILmax: Maximum Inductor current (14) In DC/DC converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e. quality factor) and by the inductor DCR value. To achieve high-efficiency operation, take care in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. The total losses of the coil consist of both the losses in the DC resistance (RDC) and the following frequencydependent components: * The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) * Additional losses in the conductor from the skin effect (current displacement at high frequencies) * Magnetic field losses of the neighboring windings (proximity effect) * Radiation losses The following inductor series from different suppliers have been used with the TPS62125. Table 3. List of Inductors INDUCTANCE [H] DCR [] DIMENSIONS [mm3] INDUCTOR TYPE SUPPLIER 10 / 15 0.33 max / 0.44 max. 3.3 x 3.3 x 1.4 LPS3314 Coilcraft 22 0.36 max. 3.9 x 3.9 x 1.8 LPS4018 Coilcraft 15 0.33 max. 3.0 x 2.5 x 1.5 VLF302515 TDK 10/15 0.44 max / 0.7 max. 3.0 x 3.0 x 1.5 LPS3015 Coilcraft 10 0.38 typ. 3.2 x 2.5 x 1.7 LQH32PN Murata 8.2.2.6 Output Capacitor Selection Ceramic capacitors with low ESR values provide the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At light load currents the converter operates in power-save mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in PFM mode. In order to achieve specified regulation performance and low-output voltage ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic capacitors drops with increasing DC-bias voltage. Due to this effect, it is recommended for output voltages above 3.3 V to use at least 1 x 22-F or 2 x 10-F ceramic capacitors on the output. 8.2.2.7 Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications, a 10-F ceramic capacitor is recommended. The voltage rating and DC bias characteristic of ceramic capacitors need to be considered. The input capacitor can be increased without any limit for better input voltage filtering. For applications powered from high impedance sources, a tantalum polymer capacitor should be used to buffer the input voltage for the TPS62125. Tantalum polymer capacitors provide a constant capacitance vs. DC bias characteristic compared to ceramic capacitors. In this case, a 10-F ceramic capacitor should be used in parallel to the tantalum polymer capacitor to provide low ESR. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 17 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on the input can induce large ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings. In case the power is supplied via a connector e.g. from a wall adapter, a hot-plug event can cause voltage overshoots on the VIN pin exceeding the absolute maximum ratings and can damage the device, too. In this case a tantalum polymer capacitor or overvoltage protection circuit reduces the voltage overshoot, see Figure 45. Table 4 shows a list of input/output capacitors. Table 4. List of Capacitors CAPACITANCE [F] SIZE CAPACITOR TYPE USAGE SUPPLIER 10 0805 GRM21B 25V X5R CIN /COUT Murata 10 0805 GRM21B 16V X5R COUT Murata 22 1206 GRM31CR61 16V X5R COUT Murata 22 B2 (3.5x2.8x1.9) 20TQC22MYFB CIN / input protection Sanyo . 8.2.3 Application Curves 95 95 90 90 85 85 80 80 VIN = 3V VIN = 5V VIN = 7.5V VIN = 9V VIN = 12V VIN = 15V 75 70 65 60 0.1 1 10 Output Current IOUT (mA) 100 100mA 250mA 1.0mA 75 VOUT = 1.8V L = 15mH LPS3314 COUT = 10mF 70 0.25mA 65 60 VOUT = 1.8V L = 15mH LPS3314 COUT = 10mF 55 50 0.01 Efficiency (%) Efficiency (%) 10mA 0.1mA 55 50 1000 Figure 12. Efficiency vs. Output Current VOUT = 1.8 V 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage VIN (V) Figure 13. Efficiency vs. Input Voltage, VOUT = 1.8 V 100 95 95 90 10mA 90 85 80 VIN = 4.0V VIN = 5V VIN = 7.5V VIN = 9V VIN = 12V VIN = 15V 75 70 65 55 0.1 1 10 Output Current (mA) 100 70 0.25mA VOUT = 3.3V L = 15mH VLF302515 COUT = 10mF 60 0.1mA 55 1000 50 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage VIN(V) Figure 14. Efficiency vs. Output current, VOUT = 3.3 V 18 1.0mA 75 65 VOUT = 3.3V L = 15mH VLF302515 COUT = 10mF 60 50 0.01 250mA 80 Efficiency (%) Efficiency (%) 85 100mA Figure 15. Efficiency vs. Input voltage, VOUT = 3.3 V Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 100 100 95 95 90 90 VIN = 6.0V VIN = 7.5V VIN = 9.0V VIN = 12V VIN = 15V 80 75 Efficiency (%) Efficiency (%) 10mA 250mA 85 85 70 70 65 60 55 55 1 10 100 Output Current IOUT (mA) 0.25mA 75 60 0.1 1.0mA 80 VOUT = 5V L = 10mH LPS3314 COUT = 2x10mF 65 50 0.01 100mA 50 1000 Figure 16. Efficiency vs. Output Current, VOUT = 5 V VOUT = 5V L = 10mH LPS3314 COUT = 2x10mF 6 7 8 9 10 11 12 13 14 Input Voltage VIN (V) 100 95 95 90 90 10mA 75 70 VOUT = 6.7V L = 10mH LPS3314 COUT = 2x10mF 65 50 1000 Figure 18. Efficiency vs. Output current, VOUT = 6.8 V 100 95 95 90 90 7 8 9 10 0.1mA 11 12 13 14 Input Voltage VIN (V) 15 100mA 10mA Efficiency (%) VIN = 9.0V VIN = 12V VIN = 15V 80 75 VOUT = 8V L = 10mH LPS3314 COUT = 10mF+22mF 70 65 1.0mA 0.25mA 75 70 VOUT = 8V L = 10mH LPS3314 COUT = 10mF + 22mF 65 60 55 55 1 10 100 Output Current IOUT (mA) 50 1000 Figure 20. Efficiency vs. Output Current, VOUT = 8 V 17 80 60 0.1 16 250mA 85 85 Efficiency (%) VOUT = 6.7V L = 10mH LPS3314 COUT = 2x10mF Figure 19. Efficiency vs. Input Voltage, VOUT = 6.8 V 100 50 0.01 0.25mA 65 55 100 250mA 70 55 1 10 Output Currernt IOUT (mA) 17 1.0mA 75 60 0.1 16 80 60 50 0.01 100mA 85 Efficiency (%) Efficiency (%) 85 VIN = 7.5V VIN = 9V VIN = 12V VIN = 15V 15 Figure 17. Efficiency vs. Input Voltage, VOUT = 5 V 100 80 0.1mA 9 10 11 12 13 14 Input Voltage VIN (V) 0.1mA 15 16 17 Figure 21. Efficiency vs. Input Voltage, VOUT = 8 V Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 19 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com 100 100 95 95 90 90 85 85 10mA 100mA 250mA 80 Efficiency (%) Efficiency (%) 1.0mA VIN = 12V VIN = 15V 75 VOUT = 10V L = 10mH LPS3314 COUT = 10mF + 22mF 70 65 60 55 55 1 10 100 Output Currernt IOUT (mA) 50 1000 Figure 22. Efficiency vs. Output Current, VOUT = 10 V VOUT 3.3V L = 15mH, COUT = 10mF 13 14 15 Input Voltage VIN (V) 16 17 3.35 3.333 VIN = 5V, TA= 25C VIN = 7.5V, TA = 25C VIN = 12V, TA = 25C VIN = 5V, TA = 85C VIN = 7.5V, TA = 85 VIN = 12V, TA = 85 3.300 3.267 3.234 0.01 0.1 1 10 Output Current [mA] 3.3 IOUT = 1mA IOUT = 25mA IOUT = 100mA IOUT = 150mA 3.25 100 3.2 1000 Figure 24. Output Voltage vs. Output Current, VOUT = 3.3 V 5 6 7 8 9 10 11 12 13 Input Voltage (V) 14 15 16 17 Figure 25. Output Voltage vs. Input Voltage, VOUT = 3.3 V 5.15 5.20 VIN = 7.5V, TA = 25C VIN = 12V, TA = 25C VIN = 7.5V, TA = -40C VIN = 12V, TA = -40C VIN = 7.5V, TA = 85 VIN = 12V, TA = 85 5.05 5.05 5 5.00 4.95 4.95 4.9 0.1 1 10 Output Current [mA] 100 VOUT 5.0V L = 10mH, COUT = 2x10mF 5.1 Output Voltage (V) VOUT 5.0V L = 10mH, COUT = 2x10mF 5.10 4.90 0.01 12 VOUT 3.3V L = 15mH, COUT = 10mF VIN = 5V, TA = -40C VIN = 7.5V, TA = -40C VIN = 12V, TA = -40C 3.366 5.15 11 3.4 Output Voltage (V) Output Voltage [V] 3.399 0.1mA VOUT = 10V L = 10mH LPS3314 COUT = 10mF+22mF Figure 23. Efficiency vs. Input Voltage, VOUT = 10 V 3.432 Output Voltage [V] 70 60 0.1 0.25mA 75 65 50 0.01 1000 4.85 IOUT = 1mA IOUT = 25mA IOUT = 100mA IOUT = 250mA 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) Figure 26. Output Voltage vs. Output current, VOUT = 5 V 20 80 Figure 27. Output Voltage vs. Input Voltage, VOUT = 5 V Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 6.968 6.9 VOUT 6.7V L = 10mH, COUT = 2x10mF 6.85 6.901 VIN = 12V, TA = 25C VIN = 9V, TA = -40C Output Voltage [V] 6.8 VIN = 9V, TA = 25C Output Voltage [V] VIN = 12V, TA = -40C 6.834 6.767 VIN = 9V, TA = 85 6.700 6.75 6.7 6.65 VIN = 12V, TA = 85 6.633 6.55 6.5 6.566 0.01 0.1 IOUT = 1mA IOUT = 25mA IOUT = 100mA IOUT = 250mA 6.6 VOUT 6.7V L = 10mH, COUT = 2x10mF 1 10 Output Current [mA] 100 1000 Figure 28. Output Voltage vs. Output Current, VOUT = 6.7 V 8 11 12 13 14 Input Voltage [V] 15 16 17 8.24 VOUT 8.0V L = 10mH, COUT = 10mF + 22mF 8.24 VOUT 8.0V L = 10mH, COUT = 10mF + 22mF 8.16 VIN = 15V, TA = -40C 8.16 VIN = 15V, TA = 25C 8.08 Output Voltage [V] Output Voltage [V] 10 Figure 29. Output voltage vs. Input voltage, VOUT = 6.7 V 8.32 VIN = 12V, TA = -40C 8.08 8 7.92 8.00 VIN = 12V, TA = 25C 7.84 0.01 7.84 7.76 0.1 IOUT = 1mA IOUT = 25mA IOUT = 100mA IOUT = 250mA VIN = 12V, TA = 85 VIN = 15V, TA = 85 7.92 1 10 Output Current [mA] 100 1000 9 10 11 12 13 14 15 16 17 Input Voltage [V] Figure 30. Output Voltage vs. Output Current, VOUT = 8 V 50 Figure 31. Output Voltage vs. Input Voltage, VOUT = 8 V 1000 40 VIN = 12V 900 VOUT = 3.3V L = 15mH COUT = 10mF Switch Frequency fSW( kHz) Output Ripple Voltage (mVpp) 9 30 20 VIN = 15V 800 700 VIN = 7.5V 600 500 VIN = 5V 400 300 VIN = 5.0V VIN = 7.5V VIN = 12V VIN = 15V 10 0 0 50 100 150 200 Output Current (mA) 250 VOUT = 3.3V L = 15mH COUT = 10mF 200 100 0 300 Figure 32. Output Ripple Voltage vs. Output Current, VOUT = 3.3 V 0 50 100 150 200 Output Current (mA) 250 300 Figure 33. Switch Frequency vs. Output Current, VOUT = 3.3 V Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 21 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com 1200 1200 1100 VIN = 12V VIN = 7.5V 900 800 700 600 500 900 800 VIN = 10V 700 600 500 400 400 VOUT = 5.0V L = 10mH COUT = 2x10mF 300 200 300 VOUT = 8.0V L = 10mH COUT = 10mF + 22mF 200 100 100 0 0 50 100 150 200 Output Current (mA) 250 VOUT = 3.3 V 3.3V offset, 50mV/Div ILoad = 1mA 0 300 Figure 34. Switch Frequency vs. Output Current, VOUT 5 V VIN = 12V L = 15 mH COUT = 10 mF SW pin 10V/Div 0 50 100 150 200 Output Current (mA) 250 300 Figure 35. Switch Frequency vs. Output Current, VOUT = 8 V VOUT = 3.3 V 3.3V offset, 50mV/Div ILoad = 100mA VIN = 12V L = 15 mH COUT = 10 mF SW pin 10V/Div Inductor current 200mA/Div Inductor current 200mA/Div Figure 36. Power-Save Mode VOUT= 3.3 V, IOUT = 1 mA VOUT = 3.3 V 3.3V offset, 50mV/Div VIN = 12V L = 15 mH COUT = 10 mF SW pin 10V/Div Figure 37. PWM Mode VOUT= 3.3 V, IOUT = 100 mA VOUT = 3.3 V 3.3V offset, 50mV/Div VIN = 12V L = 15 mH COUT = 10 mF SW pin 10V/Div IOUT 5mA to 200mA 200mA/Div Inductor current 200mA/Div Inductor current 200mA/Div Figure 38. Load Transient 5 mA to 200 mA, VOUT = 3.3 V 22 VIN = 15V VIN = 12V 1000 Switch Frequency FSW ( kHz) 1000 Frequency ( kHz) 1100 VIN = 15V IOUT AC 10kHz 5mA to 200mA 200mA/Div Figure 39. AC Load Regulation, VOUT = 3.3 V Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 VIN = 12V L = 10 mH COUT = 2x 10 mF VOUT = 5.0 V 5V offset, 50mV/Div Inductor current 200mA/Div Inductor current 200mA/Div ILoad = 1mA to 50mA 50mA / Div ILoad = 10mA to 200mA 200mA / Div Figure 40. Load Transient 1 mA to 50 mA, VOUT = 5 V VOUT = 5.0 V 5V offset, 50mV/Div VIN = 12V L = 10 mH COUT = 2x 10 mF VOUT = 5.0 V 5V offset, 50mV/Div Figure 41. Load Transient 10 mA to 200 mA, VOUT = 5 V VIN = 9V to 12V IOUT = 100mA L = 15 mH COUT = 10 mF VIN = 12V L = 10 mH COUT = 2x 10 mF VOUT = 3.3 V, 50mV/Div Inductor current 200mA/Div ILoad = AC 5kHz 1mA to 250mA 200mA / Div Figure 43. Line Transient Response VIN = 9 V to 12 V Figure 42. AC Load Regulation VOUT = 5 V VIN overshoot 25V IIN VIN = 12V, Hotplug CIN = 10mF ceramic capacitor Current into input capacitor 20A/div VIN overshoot reduction to 15V Current into input capacitors 20A/div IIN Figure 44. VIN Hotplug Overshoot VIN = 12V, Hotplug CIN = 10mF additional 22mF tantalum-polymer input capacitor type Poscap 20TQC22MYFB Figure 45. VIN Hotplug Overshoot Reduction With Poscap Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 23 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 VOUT = 5.0 V 2V/Div www.ti.com VIN = 12V CIN = 10uF ceramic + 22uF Poscap VOUT Startup L = 10 mH COUT = 2x 10 mF IIN 200mA/Div VIN : ramped up/down 0V to 12V, 175mV/ms 2.5V/Div REN1 = 820kW REN2 = 110kW REN2 = 82kW VOUT = 5.0 V L = 10 mH COUT = 2x10 mF Load = 100W VIN_Start = 10V VIN_Stop = 6V Current into CIN VOUT 2.5V/Div IL 1A/Div PG 5V/Div Short IOUT 1A/Div IOUT = 10mA Short IIN 200mA/Div Figure 47. Input Supply Voltage Supervisor (SVS), VOUT = 5 V Figure 46. Short Circuit and Overcurrent Protection VIN : ramped up/down 0V to 12V, 175mV/ms 2.5V/Div EN = VIN UVLO VOUT = 5.0 V L = 10 mH COUT = 2x10 mF Load = 100W VIN tracks VOUT VIN: 0.5mA current source 2.5V/Div REN1 = 680kW REN2 = 110kW REN2 = 120kW VIN_startup = 6.82V VIN_stop = 4.55V CIN = 10mF ceramic + 22mF Poscap VOUT = 3.3 V L = 15 mH, COUT = 10 mF UVLO 7ms/20mA Pulse Load VOUT 2.5V/Div VOUT 2.0V/Div PG 5V/Div IOUT 20mA/Div Startup in 20mA Load 0.5mA Source Current IIN 200mA/Div IIN: 0.5mA/Div Figure 48. Operation With EN = VIN, VIN Tracks VOUT VIN = 12V VOUT = 1.8 V L = 15 mH COUT = 10 mF Load = 180W Figure 49. 0.5 mA Current Source, 20 mA Pulse Load VIN = 12V VOUT = 3.3 V L = 15 mH COUT = 10 mF Load = 330W Figure 50. Start-Up 1.8 V VOUT 24 Figure 51. Start-Up 3.3 V VOUT Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 VIN = 12V VOUT = 8.0 V L = 10 mH COUT = 2x10 mF Load = 800W VIN = 12V VOUT = 5.0 V L = 10 mH COUT = 2x10 mF Load = 500W Figure 52. Start-Up 5 V VOUT Figure 53. Start-Up 8 V VOUT VIN = 12V VOUT = 3.3 V COUT = 10uF L = 15mH RLoad = 100 W RPullup PG = 100kW to VOUT VIN 1V/Div VIN_stop = 4.55V REN1 = 680kW REN2 = 110kW REN_hys = 120kW VIN = 12V to 0V VOUT = 3.3 V COUT = 10uF L = 15mH IOUT = 0mA RPullup PG = 0W to VOUT 1V/Div VOUT 1V/Div 2V/Div 1V/Div Figure 54. VOUT Ramp Up/Down With EN On/Off VIN 2V/Div VIN_stop = 4.55V REN1 = 680kW REN2 = 110kW REN_hys = 120kW Figure 55. Output Discharge Using PG Pin, Triggered by EN Comparator VIN = 12V to 0V VOUT = 3.3 V COUT = 10uF L = 15mH IOUT = 0mA RPullup PG = 100kW to VOUT VOUT 1V/Div PG 1V/Div Figure 56. VOUT Ramp Down With Falling VIN, See Schematic Figure 59 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 25 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com 8.3 System Examples 8.3.1 TPS62125 5-V Output Voltage Configuration TPS62125 VIN = 6V to 17V VOUT = 5V up to 300mA L 10H SW VIN R1 1.1M VOS EN CIN 10F FB R2 210k EN_hys COUT 2 x 10F or 1 x 22F Rpullup GND PG PWR GOOD Figure 57. TPS62125 5-V Output Voltage Configuration 8.3.2 TPS62125 5-V VOUT VIN_Start = 10V VIN_Stop = 6V TPS62125 SW VIN REN1 820k CIN 10F VOUT = 5V up to 300mA L 10H R1 1.1M VOS R2 REN2 110k FB EN R2 210k COUT 2 x 10F or 1 x 22F EN_hys REN_hys 82k Rpullup GND PG PWR GOOD Figure 58. TPS62125 5-V VOUT, Start-up Voltage VIN_Start = 10 V, Stop Voltage VIN_Stop = 6 V, See Figure 47 8.3.3 TPS62125 Operation From a Storage Capacitor Charged From a 0.5 mA Current Source VIN_Start = 6.82V VIN_Stop = 4.55V TPS62125 VIN Current Source 0.5mA 10V max REN1 610k CIN 22F Poscap CIN 10F REN2 110k SW R1 1.8M VOS R2 EN VOUT = 3.3V up to 300mA L 15H FB COUT 10F R2 576k EN_hys REN_hys 120k Rpullup 100k GND PG PWR Good Figure 59. TPS62125 Operation From a Storage Capacitor Charged From a 0.5 mA Current Source, VOUT = 3.3 V, See Figure 49 26 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 System Examples (continued) 8.3.4 5 V to -5 V Inverter Configuration CIN 10F VIN = 5V TPS62125 VOS EN GND R1 1.1M FB Cbypass 10F R2 210k EN_hys GND L 10H SW VIN PG COUT 2 x 10F or 1 x 22F VOUT = - 5V up to 150mA Figure 60. 5 V to -5 V Inverter Configuration, See SLVA514 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 27 TPS62125 SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 www.ti.com 9 Power Supply Recommendations The TPS62125 has no special requirements for its input power supply. The input power supply's output current needs to be rated according to the supply voltage, output voltage, and output current of the TPS62125. 10 Layout 10.1 Layout Guidelines As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Take care in the board layout to get the specified performance. If the layout is not carefully done, the regulator could show frequency variations, poor line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low-inductance, low-impedance ground path. Therefore, use wide and short traces for the paths conducting AC current of the DC/DC converter. The area of the AC current loop (input capacitor - TPS62125 - inductor - output capacitor) should be routed as small as possible to avoid magnetic field radiation. Therefore the input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Use a common power GND node and a different node for the signal GND to minimize the effects of ground noise. Keep the common path to the GND pin, which returns both the small signal components and the high current of the output capacitors as short as possible to avoid ground noise. A well proven practice is to merge small signal GND and power GND path at the exposed thermal pad. The FB divider network and the FB line should be routed away from the inductor and the SW node to avoid noise coupling. The VOS line should be connected as short as possible to the output, ideally to the VOUT terminal of the inductor. Keep the area of the loop VOS node - inductor - SW node small. The exposed thermal pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation. 10.2 Layout Example COUT L PG GND Approximate circuit area 2 2 = 51mm (0.079in ) VOUT CIN VIN REN1 REN2 U1 GND R1 R2 REN_hys Figure 61. EVM Board Layout 28 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 TPS62125 www.ti.com SLVSAQ5E - MARCH 2012 - REVISED MAY 2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks DCS-Control, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPS62125 29 PACKAGE OPTION ADDENDUM www.ti.com 12-May-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS62125DSGR ACTIVE WSON DSG 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 SAQ TPS62125DSGT ACTIVE WSON DSG 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 SAQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-May-2017 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS62125DSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS62125DSGT WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62125DSGR WSON DSG 8 3000 210.0 185.0 35.0 TPS62125DSGT WSON DSG 8 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DSG0008A WSON - 0.8 mm max height SCALE 5.500 PLASTIC SMALL OUTLINE - NO LEAD 2.1 1.9 A B PIN 1 INDEX AREA 2.1 1.9 0.3 0.2 0.4 0.2 OPTIONAL TERMINAL TYPICAL C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C EXPOSED THERMAL PAD (0.2) TYP 0.9 0.1 5 4 6X 0.5 2X 1.5 SEE OPTIONAL TERMINAL 9 8 1 PIN 1 ID 1.6 0.1 8X 0.4 8X 0.2 0.3 0.2 0.1 0.05 C A B C 4218900/B 09/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DSG0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.9) 8X (0.5) ( 0.2) VIA TYP 1 8 8X (0.25) (0.55) SYMM 9 (1.6) 6X (0.5) 5 4 SYMM (R0.05) TYP (1.9) LAND PATTERN EXAMPLE SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4218900/B 09/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN DSG0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 8X (0.5) SYMM METAL 1 8 8X (0.25) (0.45) SYMM 9 (0.7) 6X (0.5) 5 4 (R0.05) TYP (0.9) (1.9) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X 4218900/B 09/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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