DATASHEET ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Description Features/Benefits The ICS9FG104E is a frequency generator that provides 4 differential HCSL output pairs. It can be used to drive PCIe Gen1/2, SATA and USB3.0 devices. The part can use either a 14.31818 MHz or 25 MHz crystal. The 9FG104E can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 50 ps and output-to-output skew of less than 35 ps. * Generates common frequencies from 14.318MHz or Recommended Application * Frequency Generator for CPU, PCIe Gen1/2, SATA and USB3.0 * Output Features * * 4 - HCSL differential outputs * 1 - 3.3V REF output (either 14.318M or 25M depending on XTAL) * * * * 25MHz Crystal or reference input 4 - 0.7V current-mode HCSL output pairs Supports Serial-ATA at 100MHz Two spread spectrum modes: -0.5% down spread and +/-0.25% center spread; Lower EMI 31.5KHz spread modulation rate; passes USB3 compliance testing Unused outputs may be disabled in either driven or Hi-Z state for power manangement I-temp version available; supports embedded applications Key Specifications * * * * * Cycle to cycle jitter: < 50ps Phase jitter: PCIe Gen1/2 <3ps rms Output to output skew <35ps +/-300 ppm frequency accuracy on output clocks +/-50ppm on all output frequencies with Spread Off Block Diagram XIN/CLKIN REFOUT OSC X2 2 PROGRAMMABLE SPREAD PLL SPREAD SEL14M_25M# DIF_STOP# FS(2:0) STOP LOGIC 4 DIF(3:0) CONTROL LOGIC SDATA SCLK IREF IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 1 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 9FG104E XIN/CLKIN X2 VDD GND REFOUT vFS2 DIF_3 DIF_3# VDD GND DIF_2 DIF_2# SDATA SCLK VDDA GNDA IREF vFS0 vFS1 DIF_0 DIF_0# VDD GND DIF_1 DIF_1# ^SEL14M_25M# vSPREAD DIF_STOP# ^ Pin has internal 120K pull up v Pin has internal 120K pull down Power Groups Pin Number VDD GND 3 4 9,21 10,20 28 27 Description REFOUT, Digital Inputs DIF Outputs IREF, Analog VDD, GND for PLL Core Frequency Select Table SEL14M_25M# FS2 FS1 FS0 OUTPUT(MHz) (FS3) 0 0 0 0 100.00 0 0 0 1 125.00 0 0 1 0 133.33 0 0 1 1 166.67 0 1 0 0 200.00 0 1 0 1 266.00 0 1 1 0 333.00 0 1 1 1 400.00 1 0 0 0 100.00 1 0 0 1 125.00 1 0 1 0 133.33 1 0 1 1 166.67 1 1 0 0 200.00 1 1 0 1 266.00 1 1 1 0 333.00 1 1 1 1 400.00 IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 2 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Pin Descriptions PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIN NAME XIN/CLKIN X2 VDD GND REFOUT vFS2 DIF_3 DIF_3# VDD GND DIF_2 DIF_2# SDATA SCLK DIF_STOP# PIN TYPE IN OUT PWR PWR OUT IN OUT OUT PWR PWR OUT OUT I/O IN IN 16 vSPREAD IN 17 ^SEL14M_25M# IN 18 19 20 21 22 23 24 25 DIF_1# DIF_1 GND VDD DIF_0# DIF_0 vFS1 vFS0 OUT OUT PWR PWR OUT OUT IN IN 26 IREF OUT 27 28 GNDA VDDA PWR PWR DESCRIPTION Crystal input or Reference Clock input Crystal output, Nominally 14.318MHz Power supply, nominal 3.3V Ground pin. Reference Clock output Frequency select pin. This pin has an internal 120k pull down resistor 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output Data pin for SMBus circuitry, 3.3V tolerant. Clock pin of SMBus circuitry, 5V tolerant. Active low input to stop differential output clocks. Asynchronous, active high input to enable spread spectrum functionality. This pin has a 120Kohm pull down resistor. Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm pull up resistor. 1 = 14.31818 MHz, 0 = 25 MHz 0.7V differential Complementary clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output 3.3V Frequency select latched input pin with internal 120kohm pull down resistor. 3.3V Frequency select latched input pin with internal 120kohm pull down resistor. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 3 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS9FG104E. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Symbol Parameter VDDxx 3.3V Supply Voltage Ts Storage Temperature Tambient Ambient Operating Temp*(Commerical Grade) Tambient Ambient Operating Temp*(Industrial Grade) Tcase Case Temperature ESD prot Input ESD protection*human body model Min Max 4.6 150 +70 +85 115 -65 0 -40 Units V C C C C V 2000 Electrical Characteristics-REF-14.318/25 MHz TA = TA M B IENT ; VDD = 3.3 V +/-5%;RS=33, CL = 5 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX Output High Voltage Output Low Voltage Rise Time Fall Time VOH VOL tr1 tf1 IOH = -1 mA IOL = 1 mA VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V 2.4 Duty Cycle dt1 VT = 1.5 V Jitter tjcyc-cycCOM Jitter tjcyc-cycIND UNITS Notes 1 1 1.4 1.4 0.4 2.5 2.5 V V ns ns 1 1 1 1 45 53 55 % 1 VT = 1.5 V (commercial) 87 200 ps 1 VT = 1.5 V (industrial) 87 250 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Trim capacitors must be used to tune the REF to the exact Crystal Frequency. Electrical Characteristics-Differential Phase Jitter Parameters PARAMETER SYMBOL CONDITIONS tjphasePLL PCIe Gen 1 PCIe Gen 1/2 10kHz < f < 1.5MHz PCIe Gen 1/2 1.5MHz < f < Nyquist (50MHz) tjphaseLo tjphaseHigh Jitter, Phase tjphQPI MIN QPI 133MHz 4.8G/6.4Gb,12UI tjphFBD3.2G tjphFBD4.8G FBD specs (11 to 33MHz) FBD specs (11 to 33MHz) TYP MAX 25 86 0.8 3 1.8 3.1 0.2 0.5 1.4 3 1.1 2.5 UNITS Notes ps (p-p) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) 1,2 1,2 1,2 1,3 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 See http://www.pcisig.com for compelte specs 3 First number is 4.8G link speed, second number is 6.4G link speed. From Intel Clock Jit tool IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 4 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Electrical Characteristics-Input/Supply/Common Output Parameters TA = TA M B IENT ; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Tambient Tambient TCOM TIND Commericial Temperature Industrial Temperature 0 -40 70 85 C C Input High Voltage Input Low Voltage Input High Current VIH VIL IIH 3.3 V +/-5% 3.3 V +/-5% VIN = VDD 2 VDD + 0.3 VSS - 0.3 0.8 5 V V uA 1 1 1 IIL1 VIN = 0 V; Inputs with no pullup resistors -5 uA 1 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA 1 Input Low Current Operating Supply Current (TA = Commercial) DIF_STOP# Current (TA = Commercial) Operating Supply Current (TA = Industrial) IDDVDD IDDVDDA IDDVDD IDDVDDA IDDVDDPD IDDVDDAPD IDDVDDPD IDDVDDAPD IDDVDD IDDVDDA IDDVDD IDDVDDA IDDVDDPD CL=Full load; fout = 100 MHz All DIF pairs stopped in driven mode All DIF pairs stopped in Hi-Z mode CL=Full load; fout = 400 MHz CL=Full load; fout = 100 MHz DIF_STOP# Current (TA = Industrial) IDDVDDAPD IDDVDDPD IDDVDDAPD All DIF pairs stopped in Hi-Z mode Input Frequency 3 Fi SEL14M_25M# = 0 SEL14M_25M# = 1 Pin Inductance1 Input/Output Capacitance1 Lpin CIN COUT TSTABcom Clk Stabilization TSTABind Modulation Frequency Modulation Frequency f MOD f MOD DIF output enable t DIFOE Input Rise and Fall times tR/tF -5 CL=Full load; fout = 400 MHz All DIF pairs stopped in driven mode 1,2 TYP Logic Inputs Output pin capacitance From VDD Power-Up to 1st clock (Commercial) From VDD Power-Up to 1st clock (Industrial) SEL14M_25M# = 0 SEL14M_25M# = 1 DIF output enable after DIF_Stop# de-assertion 125 25 100 25 100 25 35 25 mA mA mA mA mA mA mA mA 1 1 1 1 1 1 1 1 109 21 90 20 87 125 25 100 25 100 mA mA mA mA mA 1 1 1 1 1 20 25 mA 1 35 25 27.5 15.75 7 5 6 mA mA MHz MHz nH pF pF 1 1 3 3 1 1 1 1.2 1.8 ms 1,2 1.8 3 ms 1,2 31.4 31.6 33 33 kHz kHz 1,3,4 1,3,4 15 ns 1 5 ns 1 1.5 20% to 80% of VDD UNITS NOTES 106 22 87 22 86 20 28 19 27 20 22.5 25.00 12.886 14.31818 30 30 MAX 1 Guaranteed by design, not 100% tested in production. See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF pin and tuned to 0 PPM to meet ppm frequency accuracy on PLL outputs. 2 4 These values assume 25MHz or 14.31818MHz inputs respectively. Using a higher or lower frequency will scale these frequencies accordingly. The output frequecy selected by the FS inputs will also scale. For example, 27MHz input with an FS selection of 100MHz will yield an output frequency of 27/25 x 100 = 108MHz. IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 5 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Electrical Characteristics-DIF 0.7V Current Mode Differential Pair TA = TA M B IENT ; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, IREF = 475 PARAMETER SYMBOL CONDITIONS MIN TYP MAX Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. 660 750 850 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Measurement on single ended signal using absolute value. Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf Notes 1 mV -150 3 150 336 550 mV Crossing variation over all edges 40 140 mV 1 14.3M input, SS OFF 14.3M input, SS ON 25M input SS OFF 25M input, SS ON 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V -300 300 -300 300 -50 50 -300 300 2.49988 2.5000 2.50013 2.4993 2.5133 2.99985 3.0000 3.00015 2.9991 3.016 3.74981 3.7500 3.75019 3.7489 3.77 4.9998 5.0000 5.0003 4.9985 5.0266 5.9997 6.0000 6.0003 5.9982 6.0320 7.4996 7.5000 7.5004 7.4978 5.4000 9.9995 10.0000 10.0005 9.9970 10.0533 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 241 700 175 260 700 18 125 19 125 ppm ppm ppm ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2,5 1,2,5 1,2,5 1,2,5 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 Duty Cycle dt3 Measured Differentially tsk3 VT = 50% Measured Differentially 1150 1 1 1 1 Skew, output to output Jitter, Cycle to cycle tjcyc-cyc UNITS -300 250 45 mV 50.0 55 % 1 21 17 35 50 ps ps 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is tuned to 0 PPM. 3 Figures are for down spread. 4 This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit http://www.pcisig.com for additional details 5 +/- 50 ppm at any frequency with spread off IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 6 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA General SMBus Serial Interface Information for ICS9FG104E How to Write How to Read * * * * * * * * * * * * * * * * * * * * * Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write Operation Controller (Host) T Index Block Read Operation IDT (Slave/Receiver) Controller (Host) starT bit T Slave Address WR * * * Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit IDT (Slave/Receiver) starT bit Slave Address WRite ACK WR WRite ACK Beginning Byte = N ACK Beginning Byte = N ACK Data Byte Count = X ACK RT Slave Address Beginning Byte N ACK O O RD ReaD ACK X Byte O Repeat starT O Data Byte Count=X O O ACK ACK ACK Beginning Byte N Byte N + X - 1 stoP bit O X Byte P O O O O O Read Address Write Address DD(H) DC(H) IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Byte N + X - 1 N Not acknowledge P stoP bit 7 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) Byte 0 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 17 6 24 25 16 Bit 2 - Bit 1 Bit 0 Name Control Function FS31 FS21 FS11 FS01 Spread Enable1 Enable Software Control of Frequency, Spread Enable (Spread Type always Software DIF_STOP# drive mode SPREAD TYPE Type RW RW RW RW RW RW RW RW 0 1 See Frequency Selection Table, Page 1 Off Hardware Select Driven Down On Software Select Hi-Z Center Default Pin 17 Pin 6 Pin 24 Pin 25 Pin 16 0 0 0 Notes: 1. These bits reflect the state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin. SMBus Table: Output Enable Register Byte 1 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name Control Function Reserved Output Enable Output Enable Reserved Reserved Output Enable Output Enable Reserved DIF_3 EN DIF_2 EN DIF_1 EN DIF_0 EN Type 0 1 RW RW Disable Disable Enable Enable RW RW Disable Disable Enable Enable Type 0 1 Default 1 1 1 1 1 1 1 1 SMBus Table: Output Stop Control Register Byte 2 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name Control Function DIF_3 STOP EN DIF_2 STOP EN Free Run/ Free Run/ DIF_1 STOP EN DIF_0 STOP EN Free Run/ Free Run/ Reserved Stop Enable Stop Enable Reserved Reserved Stop Enable Stop Enable Reserved IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA RW RW Free-run Free-run Stop-able Stop-able RW RW Free-run Free-run Stop-able Stop-able 8 ICS9FG104E Default 0 0 0 0 0 0 0 0 REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA SMBus Table: Frequency Select Readback Register Byte 3 Pin # Bit 7 27 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 44 45 16 Name Control Function Type State of pin 17 R State of pin 6 State of pin 24 State of pin 25 State of pin 26 Reserved Reserved Reserved R R R R SEL14M_25M#1 (FS3) FS21 FS11 FS01 SPREAD1 0 1 Default Pin 17 See Frequency Selection Table, Page 1 Off On Pin 6 Pin 24 Pin 25 Pin 16 0 0 0 1 Default Notes: 1. These bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not. SMBus Table: Vendor & Revision ID Register Byte 4 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function Type 0 R R R R R R R R - - X X X X 0 0 0 1 Control Function Type 0 1 Default Device ID = 08 hex R R R R R R R R - - 0 0 0 0 1 0 0 0 Control Function Type 0 1 Default Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. RW RW RW RW RW RW RW RW - - 0 0 0 0 0 1 1 1 REVISION ID VENDOR ID Rev E = 1000 SMBus Table: DEVICE ID Byte 5 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0 SMBus Table: Byte Count Register Byte 6 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 9 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA SMBus Table: Reserved Register Byte 7 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name Control Function Type 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 SMBus Table: Reserved Register Byte 8 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name Control Function Type 0 1 Default 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SMBus Table: M/N Programming Enable Byte 9 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 - M/N_Enable REFOUT_En Control Function Type M/N Prog. Enable RW Reserved REFOUT Enable RW Reserved Reserved Reserved Reserved Reserved 0 1 Default Disable Enable Disable Enable 0 1 1 0 0 0 0 0 0 1 SMBus Table: PLL Frequency Control Register Byte 10 Pin # Name Control Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - PLL N Div8 PLL N Div9 PLL M Div5 PLL M Div4 PLL M Div3 PLL M Div2 PLL M Div1 PLL M Div0 N Divider Prog bit 8 N Divider Prog bit 9 M Divider Programming bit (5:0) IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Type RW The decimal representation RW of M and N Divider in Byte RW 11 and 12 will configure the RW PLL VCO frequency. Default at power up = latch-in or RW RW Byte 0 Rom table. VCO Frequency = fXTAL x RW RW [NDiv(9:0)+8] / [MDiv(5:0)+2] 10 ICS9FG104E Default X X X X X X X X REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA SMBus Table: PLL Frequency Control Register Byte 11 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - PLL N Div7 PLL N Div6 PLL N Div5 PLL N Div4 PLL N Div3 PLL N Div2 PLL N Div1 PLL N Div0 Control Function N Divider Programming Byte11 bit(7:0) and Byte10 bit(7:6) Type 0 1 RW The decimal representation RW of M and N Divider in Byte RW 11 and 12 will configure the RW PLL VCO frequency. Default at power up = latch-in or RW RW Byte 0 Rom table. VCO Frequency = fXTAL x RW RW [NDiv(9:0)+8] / [MDiv(5:0)+2] Default X X X X X X X X SMBus Table: PLL Spread Spectrum Control Register Byte 12 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - PLL SSP7 PLL SSP6 PLL SSP5 PLL SSP4 PLL SSP3 PLL SSP2 PLL SSP1 PLL SSP0 Control Function Spread Spectrum Programming bit(7:0) Type 0 1 RW RW RW These Spread Spectrum bits in Byte 13 and 14 will RW RW program the spread pecentage of PLL RW RW RW Default X X X X X X X X SMBus Table: PLL Spread Spectrum Control Register Byte 13 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - PLL SSP14 PLL SSP13 PLL SSP12 PLL SSP11 PLL SSP10 PLL SSP9 PLL SSP8 Control Function Type 0 1 Reserved Spread Spectrum Programming bit(14:8) RW RW These Spread Spectrum bits RW in Byte 13 and 14 will RW program the spread RW pecentage of PLL RW RW Default 0 X X X X X X X SMBus Table: Reserved Test Register Byte 14 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name Control Function Type 0 1 Reserved Test Register. Do not write to this register, erratic device operation may occur. IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 11 ICS9FG104E Default 1 0 0 0 0 0 0 0 REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA DIF_STOP# - Assertion (transition from '1' to '0') Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True = HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '1', DIF outputs will be tri-stated. DIF_STOP# - De-assertion (transition from '0' to '1') With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a voltage greater than 200mV. IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 12 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA DIF Reference Clock Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs HCSL Output Buffer Rt Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' HCSL Output Buffer Rs Rt Rt L3' IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA PCI Express Add-in Board REF_CLK Input L3 13 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b HCSL Output Buffer R2a R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 F Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA PCIe Device REF_CLK Input 14 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Package Outline and Package Dimensions (28-SSOP) 28 E1 209 mil SSOP In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -2.00 -.079 A1 0.05 -.002 -A2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 D SEE VARIATIONS SEE VARIATIONS E 7.40 8.20 .291 .323 E1 5.00 5.60 .197 .220 e 0.65 BASIC 0.0256 BASIC L 0.55 0.95 .022 .037 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 E INDEX AREA 1 2 VARIATIONS D D mm. N MIN 9.90 28 D (inch) MAX 10.50 MIN .390 MAX .413 Reference Doc.: JEDEC Publication 95, MO-150 A A2 A1 c -Ce b SEATING PLANE L .10 (.004) C IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 15 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Package Outline and Package Dimensions (28-TSSOP) Millimeters 28 Symbol E1 INDEX AREA Min A A1 A2 b C D E E1 e L aaa E 1 2 D Inches Max Min -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 9.60 9.80 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.378 0.386 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A A2 A1 c - Ce SEATING PLANE b L aaa C Ordering Information Part/Order Number Shipping Packaging Package Temperature 9FG104EFLF 9FG104EFLFT 9FG104EFILF 9FG104EFILFT 9FG104EGLF 9FG104EGLFT 9FG104EGILF 9FG104EGILFT Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 0 to +70C 0 to +70C -40 to +85C -40 to +85C 0 to +70C 0 to +70C -40 to +85C -40 to +85C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. "E" is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 16 ICS9FG104E REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA Revision History Rev. A B Issue Date 6/21/2012 10/11/2012 Issuer RDW RDW C 10/23/2012 AT D 10/29/2012 AT Description Moved from Advance to final Electrical Tables updated to harmonize with the 9FG108E Correct typo on front page for output-to-output skew. Should be 35ps, not 65ps. Electrical table spec is correct and shows the 35ps value. Update the Jitter parameters in the table "Electrical Characteristics - REF 14.318/25MHz" to distinguish between commercial and industrial conditions. Added a separate line for each condition. For commercial, values were changed from 87ps Min & 250ps Max to 87ps Min & 200ps Max. For industrial, values are kept the same - 87ps Min & 250ps Max. IDT(R) FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 17 ICS9FG104E Page # 1 4 REV D 102912 ICS9FG104E FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA SYNTHESIZERS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA