PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS841S01I is a PLL-based clock generator specifically designed for PCI_ExpressTMClock HiPerClockSTM Generation applications. This device generates a 100MHz HCSL clock. The device offers a HCSL (Host Clock Signal Level) clock output from a clock input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. * One 0.7V current mode differential HCSL output pair ICS * Crystal oscillator interface, 25MHz * Output frequency: 100MHz * Period jitter: TBD * Output skew: 150ps (maximum) * Cycle-to-cyle jitter: 50ps (maximum) * I2C support with readback capabilities up to 400kHz * Spread Spectrum for electromagnetic interference (EMI) reduction The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -.5%. * 3.3V operating supply mode * -40C to 85C ambient operating temperature The ICS841S01I is available in both standard and lead-free 16-Lead TSSOP packages. * Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT XTAL_IN OSC PLL XTAL_OUT SDATA Pullup SCLK Pullup Divider Network SRCT0 SRCC0 I2C Logic V SS _ SRC VDD _SRC SRCT0 SRCC0 VDD _SRC V SS _ SRC IREF V SSA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD _SRC SDATA SCLK XTAL_OUT XTAL_IN VDD _REF V SS _REF V DDA ICS841S01I IREF 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 6 VSS_SRC Type Description Power Ground for SRC outputs. 2, 5, 16 VDD_SRC Power Power supply for SRC outputs. 3, 4 SRCT0, SRCC0 Output 7 IREF Input 8 VSSA Power Differential output pair. HCSL interface levels. A fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode SRCC0, SRCT0 clock outputs. Analog ground pin. 9 VDDA Power Power supply for PLL. 10 VSS_REF Power Ground for crystal interface 11 12, 13 VDD_REF Power Power supply for crystal interface. Crystal oscillator interface. XTAL_IN is the input. XTAL_IN, XTAL_OUT Input XTAL_OUT is the output. SMBus compatible SCLK. This pin has an internal pullup resistor, but 14 SCLK Input Pullup is in high impedance in powerdown mode. LVCMOS/LVTTL interface levels. SMBus compatible SDATA. This pin has an internal pullup resistor, 15 SDATA Pullup but is in high impedance in powerdown mode. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k COUT Output Pin Capacitance LIN Pin Inductance 841S01BGI 3 www.icst.com/products/hiperclocks.html 2 5 pF 7 nH JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR SERIAL DATA INTERFACE DATA PROTOCOL To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). TABLE 3A. COMMAND CODE DEFINITION BIT 7 6:5 4:0 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation. Chip select address, set to "00" to access device. Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be "00000". TABLE 3B. BLOCK READ AND BLOCK WRITE PROTOCOL BIT 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 841S01BGI Description = Block Write Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop BIT 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 Description = Block Read Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat star t Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data Byte 1 from slave - 8 bits Acknowledge Data Byte 2 from slave - 8 bits Acknowledge Data Bytes from Slave / Acknowledges Data Byte N from slave - 8 bits Not Acknowledge www.icst.com/products/hiperclocks.html 3 JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR TABLE 3C. BYTE READ AND BYTE WRITE PROTOCOL BIT 1 2:8 9 10 11:18 19 20:27 28 29 Description = Byte Write Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop BIT 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39 Description = Byte Read Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat star t Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits Not Acknowledge Stop CONTROL REGISTERS TABLE 4A. BYTE 0:CONTROL REGISTER 0 BIT 7 6 5 4 3 @Pup 0 1 1 1 1 Name Reser ved Reser ved Reser ved Reser ved Reser ved 2 1 SRC[T/C]0 1 0 0 0 Reser ved Reser ved 841S01BGI Description Reser ved Reser ved Reser ved Reser ved Reser ved SRC[T/C]0 Output Enable 0 = Disable (Hi-Z) 1 = Enable Reser ved Reser ved www.icst.com/products/hiperclocks.html 4 JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. PCI EXPRESSTMCLOCK GENERATOR TABLE 4B. BYTE 1:CONTROL REGISTER 1 BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved TABLE 4C. BYTE 2:CONTROL REGISTER 2 Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved TABLE 4D. BYTE 3:CONTROL REGISTER 3 BIT 7 6 5 4 3 2 1 0 @Pup 1 0 1 0 1 1 1 1 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved ICS841S01I BIT @Pup Name 7 1 SRCT/C 6 5 4 3 1 1 0 1 Reser ved Reser ved Reser ved Reser ved 2 0 SRC 1 0 1 1 Reser ved Reser ved Description Spread Spectrum Selection 0 = -0.35%, 1 = -0.50% Reser ved Reser ved Reser ved Reser ved SRC Spread Spectrum Enable 0 = Spread Off, 1 = Spread On Reser ved Reser ved TABLE 4E. BYTE 4:CONTROL REGISTER 4 Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 1 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved TABLE 4F. BYTE 5:CONTROL REGISTER 5 BIT 7 6 5 4 3 2 1 0 841S01BGI @Pup 0 0 0 0 0 0 0 0 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved www.icst.com/products/hiperclocks.html 5 JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR TABLE 4G. BYTE 6:CONTROL REGISTER 6 BIT @Pup Name 7 0 TEST_SEL 6 0 TEST_MODE 5 4 3 2 1 0 0 1 0 0 1 1 Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description REF/N or Tri-state Select 0 = Hi-Z, 1 = REF/N TEST Clock Mode Entr y Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode Reser ved Reser ved Reser ved Reser ved Reserved Reser ved TABLE 4H. BYTE 7:CONTROL REGISTER 7 BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 1 Name Description Revision Code Bit Revision Code Bit Revision Code Bit Revision Code Bit Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 3 2 1 0 OUTPUT DRIVER CURRENT The ICS841S01I outputs are HCSL current drive with the current being set with a resistor from IREF to ground. For a 50 pc board trace, the drive current would typically be set with a RREF of 475 which products an IREF of 2.32mA. The IREF is multiplied by a current mirror to an output drive of 6*2.32mA or 13.92mA. See Figure 1 for current mirror and output drive details. IREF RREF RL RL FIGURE 1. HCSL CURRENT MIRROR AND OUTPUT DRIVE 841S01BGI www.icst.com/products/hiperclocks.html 6 JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD_REF + 0.5 V Outputs, VO -0.5V to VDD_SRC + 0.5V Package Thermal Impedance, JA 89C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V5%, TA = -40C TO 85C Symbol Parameter Minimum Typical Maximum Units VDD_REF Power Supply Voltage Test Conditions 3.135 3. 3 3.465 V VDDA Analog Supply Voltage VDD_REF - IDDA*10 3.3 VDD_REF V VDD_SRC Output Supply Voltage 3.135 3.3 3.465 V IDD Dynamic Supply Current 400 mA IDDA Analog Supply Current At Max. Load and Frequency TBD mA TABLE 5B. DC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V5%, TA = -40C TO 85C Symbol Parameter VIHSMBUS Input High Voltage SDATA, SCLK VILSMBUS Input Low Voltage SDATA, SCLK IIH Input High Current SDATA, SCLK VDD = VIN = 3.465V IIL Input Low Current SDATA, SCLK VDD = 3.465V, VIN = 0V IOH Output Current IOZ High Impedance Leakage Current 841S01BGI Test Conditions Minimum Typical 2.2 Maximum Units V 1.0 V 5 A -150 A 14 -10 www.icst.com/products/hiperclocks.html 7 mA 10 A JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR TABLE 6. AC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V5%, TA = -40C TO 85C Symbol Parameter fref Frequency sclk SCLK Frequency Test Conditions XTAL External Reference odc SRCT/SRCC Duty Cycle; NOTE 2 tsk(o) SRCT/C to SRCT/C Clock Skew; NOTE 2 tPERIOD Average Period; NOTE 3 SRCT/C Cycle-to-Cycle Jitter ; NOTE 2 tjit(per) Period Jitter, RMS tR / tF SRCT/SRCC Rise/Fall Time; NOTE 4 tRFM Rise/Fall Time Matching; NOTE 5 tDC XTAL_IN Duty Cycle; NOTE 6 tR / tF Rise/Fall Time Variation VHIGH Voltage High Voltage Low Output Crossover Voltage VOVS Maximum Overshoot Voltage VUDS Minimum Undershoot Voltage 45 9.9970 tjit(cc) VLOW Typical Maximum 25 Frequency Tolerance; NOTE 1 VOX Minimum 20% to 80% MHz 400 kHz 50 ppm 0 ppm 55 % 150 ps 10.0533 ns 50 ps TBD ps 700 ps 20 % 47.5 52.5 % 125 ps 660 850 mv 550 mV VHIGH + 0.3 V 175 -150 @ 0.7V Swing Units 250 -0.3 mv V VRB Ring Back Voltage 0.2 V NOTE 1: With recommended cr ystal. NOTE 2: Measured at crossing point VOX. NOTE 3: Measured at crossing point VOX at 100MHz. NOTE 4: Measured from VOL = 0.175V to VOH = 0.525V. NOTE 5: Determined as a fraction of 2*(tR - tF) / (tR + tF). NOTE 6: The device will operate reliably with input duty cycles up to 30/70% but the REF clock duty cycle will not be within specification 841S01BGI www.icst.com/products/hiperclocks.html 8 JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 3.3V5% 3.3V5% Measurement Point 33 VDDA 49.9 HSCL SRCC0 SRCT0 100 Differential Measurement Point 33 tcycle n VDD_REF, VDD_SRC tcycle n+1 GND t jit(cc) = tcycle n -tcycle n+1 49.9 475 1000 Cycles 0V 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT CYCLE-TO-CYCLE JITTER VOH nSRCx VREF SRCx VOL 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements nSRCy SRCy tsk(o) Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) OUTPUT SKEW PERIOD JITTER SRCC0 80% 80% SRCT0 VSW I N G t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 841S01BGI HCSL OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 9 JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. HCSL OUTPUT All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS841S01I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD_REF, VDDA, and VDD_SRC should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA. The 10 resistor can also be replaced by a ferrite bead. 3.3V VDD_REF .01F 10 VDDA .01F 10F FIGURE 2. POWER SUPPLY FILTERING USING THE ON-BOARD CRYSTAL OSCILLATOR The ICS841S01I features a fully integrated Pierce oscillator to minimize system implementation costs. The ICS841S01I may be operated with a 25MHz crystal and without additional components. Recommended operation for the crystal should be of a parallel resonant type and a load specification of CL = 18pF. See Table 7 for complete crystal specifications. The crystal and optional trim capacitors should be located as close to the ICS841S01I XTAL_IN and XTAL_OUT pins as possible to avoid any board level parasitic. XT AL_IN If more precise frequency control is desired, the addition of capacitors from each of the XTAL_IN and XTAL_OUT pins to ground may be used to trim the frequency as shown in Figure 3. TBD 25MHz TABLE 7. RECOMMENDED CRYSTAL SPECIFICATIONS Parameter Value Crystal Cut Fundamental AT Cut Resonance Parallel Resonance Shunt Capacitance (CL) 5-7pF Load Capacitance (CO) 18pF Equivalent Series Resistance (ESR) 20-50 841S01BGI XTAL_OUT TBD FIGURE3. CRYSTAL OSCILLATOR WITH TRIM CAPACITOR www.icst.com/products/hiperclocks.html 10 JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR RELIABILITY INFORMATION TABLE 8. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1C/W 89.0C/W 118.2C/W 81.8C/W 106.8C/W 78.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS841S01I is: 1874 841S01BGI www.icst.com/products/hiperclocks.html 11 JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS841S01I PCI EXPRESSTMCLOCK GENERATOR 16 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 16 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 E E1 5.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0 8 aaa -- 0.10 0.75 Reference Document: JEDEC Publication 95, MO-153 841S01BGI www.icst.com/products/hiperclocks.html 12 JUNE 12, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS841S01I PCI EXPRESSTMCLOCK GENERATOR TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS841S01BGI ICS841S01BI 16 Lead TSSOP tube -40C to 85C ICS841S01BGIT ICS841S01BI 16 Lead TSSOP 2500 tape & reel -40C to 85C ICS841S01BGILF 41S01BIL 16 Lead "Lead-Free" TSSOP tube -40C to 85C ICS841S01BGILFT 41S01BIL 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an"LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 841S01BGI www.icst.com/products/hiperclocks.html 13 JUNE 12, 2006