6033A–I NTA P–03/04
Features
•ARM7TDMI® ARM® Thumb® Pr ocess or Core
– In-Circuit Emulator, 40 MHz operation
•16-bit Fixed-point OakDSPCore®
– Up t o 60 MHz oper ations
– 104K bytes of Integrated Fast RAM, Codec Interface
•Ethernet Bridge
– Dual Ethernet 10/100 Mbps MAC Interface
– 16-Kbyte Frame Buffer
•1 K-Byte Boot ROM, Embedding a Boot Program
– Enable Application Download from DataFlash®
•External Bus Interface
– On-chip 32-bit SDRAM Controller
– 4 Chip Select Static Memory Controller
•Multi-level Priority, Individually Maskable, Vectored Interrupt Controller
•Three 16-b it Timer/Co u nter s
•Two UARTs with Modem Control Lines
•Serial Periph eral Inter fa ce (SPI)
•Two PIO Controllers, Managing up to 48 General-purpose I/O Pins
•Supported by a Wide Range of Ready-to-u se Applic ation Software,
– Multi-tasking Operating System, Networking
– Voice-processing Functions
•Available in a 208-lead PQFP Package and 256-ball BGA Package
•Power Supplies
– VDDIO 3.3V Nominal
– VDDCORE and VDDOSC 1.8V Nominal
•0°C to + 70°C Operating Temperature Range
Description
The AT75C221, Atmel’s latest device in the family of smart inter ne t appli ance p roces-
sors (SIAP™) , is a high-perform ance processor designed for professional inter net
appli ance ap plicat ions suc h as the Ether ne t IP phon e. The AT75C2 21 is built aro und
an ARM7TDMI microcontroller core running at 40 MHz with an OakDSPCore copro-
cessor running at 60 MHz and a dual Ethernet 10/100 Mbits/sec MAC interface.
In a typical standalone IP phone, the DSP handles the voice processing functions
(voice compression, acoustic echo canc ellation, etc.) while the dual-por t Ether net
10/100 Mbits/sec MAC interface establishes the connection to the Ether net physical
layer (PHY) that links the network and the PC. In such an application, the power of the
ARM7TDMI allows it to run a VoIP protocol stack as well as all the system control
tasks.
Atmel provides the AT75C221 with several software modules, including:
• A set of drivers for a Linux® kernel capable of driving the embedded peripherals.
• A comprehensive set of tunable DSP algorithms for voice processing, tailored to
be run by the DSP subsystem.
Smart Internet
Appliance
Processor
(SIAP™)
AT75C221
Preliminary
2AT75C221 Preliminary 6033A–INTAP–03/04
Bloc k Diagram
Figure 1. AT75C221 Bl ock D iag ram
SPI
Peripheral Bridge
Peripheral Data
Controller
OakDSPCore
DSP Subsystem
ARM7TDMI Core
External Bus
Interface
SDRAMC
System
Controller
Boot ROM
Ethernet
10/100 Mbps
MAC Interface
ICE
Ethernet
10/100 Mbps
MAC Interface
16kBytes
SRAM
ASB/ASB
Bridge
SMC
16- or 32-bit dat
a
Memory Bus
JTAG Debug
Interface
Audio Codec
a
nd I/O Lines
MII PHY
Interface
MII PHY
Interface
OSC
PLL
Interrupt and
F
ast Interrupt
Advanced
Interrupt
Controller
I/O LInes PIO Controller A
I/O LInes PIO Controller B
Serial Periphera
ls
Boot DataFlash
UART A Serial Port
UART B Serial Port
PWM SignalsTimer/Counter 0
PWM SignalsTimer/Counter 1
PWM SignalsTimer/Counter 2
Note: Unidirectional arrows indicate Master to Slave
3
AT75C221 Preliminary
6033A–INTAP–03/04
Typical Application
Figure 2. Typical Application Overview
Pinout The AT75C221 ships in two packages:
• 208-lead PQFP
• 256-ball BGA
The produ ct f eatures of the 25 6-ball BGA pack age are i ncreas ed com pared to t he 2 08-
lead PQFP package.
The features av ail abl e onl y with the BGA pack age ar e:
• The 32-bit wide data bus. (In PQFP, only a 16-bit wide data bus is supported.)
• The Parallel I/O lines PA13 to PA18 and PA20 to PA31(1)
• The Parallel I/O lines PB10 to PB16
Note: 1. PA22 also exists in the 208-lead PQFP package.
VolP
Protocol
Stack
ARM7TDMI Core
External Bus
Interface
SDRAM
Controller
SRAM
Controller
SDRAM
Flash
Speaker
Phone
Interface
Voice
Codec Voice
Processing
DSP Subsystem
Analog Front End
AT75C221
Keyboard Screen
Speaker
M
icrophone
Handset
Dual-port
Ethernet
10/100 Mbps
MAC
Interface
Ethernet
10/100 Mbps PHY
Ethernet
10/100 Mbps PHY
Network
PC
4AT75C221 Preliminary 6033A–INTAP–03/04
208-lead PQFP Package Pinout
Table 1. Pinout for 208-lead PQFP Package
Pin
Number Signal Name Pin
Number Signal Name Pin
Number Signal Name Pin
Number Signal Name
1GND 37 MB_TXD0 73 A15 109 RAS
2SCLKA 38 MB_TXD1 74 A16 110 CAS
3VDDIO 39 MB_TXD2 75 A17 111 NC(1)
4FSA 40 GND 76 A18 112 WE
5STXA 41 MB_TXD3 77 A19B/A0 113 DQM0
6SRXA 42 MB_TXEN 78 A20/BA1 114 DQM1
7NTRST 43 MB_TXCLK 79 A21 115 NC(1)
8MA_COL 44 MB_RXD0 80 D0 116 GND
9MA_CRS 45 MB_RXD1 81 D1 117 NC(1)
10 MA_TXER 46 MB_RXD2 82 D2 118 VDDCORE
11 MA_TXD0 47 MB_RXD3 83 D3 119 GND
12 MA_TXD1 48 MB_RXER 84 GND 120 VDDOSC
13 MA_TXD2 49 MB_RXCLK 85 D4 121 PLLRC
14 MA_TXD3 50 MB_RXDV 86 VDDIO 122 GND
15 MA_TXEN 51 MB_MDC 87 D5 123 GND
16 VDDIO 52 VDDIO 88 D6 124 XTALOUT
17 MA_TXCLK 53 GND 89 D7 125 XTALIN
18 GND 54 MB_MDIO 90 D8 126 VDDCORE
19 MA_RXD0 55 MB_LINK 91 D9 127 NCE0
20 MA_RXD1 56 A0 92 D10 128 NCE1
21 MA_RXD2 57 A1 93 D11 129 NCE2
22 MA_RXD3 58 A2 94 D12 130 VDDIO
23 MA_RXER 59 A3 95 D13 131 NCE3
24 MA_RXCLK 60 A4 96 D14 132 NWE0
25 GND 61 A5 97 VDDCORE 133 NWE1
26 VDDCORE 62 A6 98 GND 134 NC(1)
27 MA_RXDV 63 A7 99 D15 135 VDDIO
28 MA_MDC 64 A8 100 VDDIO 136 GND
29 MA_MDIO 65 A9 101 GND 137 NC(1)
30 MA_LINK 66 A10 102 VDDIO 138 NWR
31 MB_COL 67 A11 103 NC(1) 139 NSOE
32 MB_CRS 68 A12 104 VDDIO 140 GND
33 GND 69 VDDIO 105 GND 141 VDDCORE
34 VDDCORE 70 GND 106 SDCK 142 V DDIO
35 VDDIO 71 A13 107 SDCS 143 MISO
36 MB_TXER 72 A14 108 SDA10 144 MOSI
5
AT75C221 Preliminary
6033A–INTAP–03/04
Note: 1. NC pins should be left unconnected.
Mec hanic al Ove rview of
the 208-lead PQFP
Package
Figure 3 below shows the orientation of the 208-lead PQFP Package.
For a d etaile d mech anica l des criptio n, see “Mec hanic al Charac terist ics a nd Pa ckagi ng”
on page 164.
Figure 3. 208-lead PQFP Package Orientation (Top View)
145 SPCK 161 TMS 177 PA5 193 GND
146 PA22 162 TCK 178 PA4 194 PB0
147 VDDIO 163 PA19 179 PA3 195 PB1
148 GND 164 VDDCORE 180 PA2 196 PB2
149 NRST 165 GND 181 PA1 197 PB3
150 FIQ 166 PA12 182 PA0 198 PB4
151 IRQ0 167 GND 183 GND 199 PB5
152 TST 168 VDDIO 184 RXDA 200 PB6
153 GND 169 PA11 185 TXDA 201 PB7
154 VDDCORE 170 PA10 186 NRSTA 202 PB8
155 NC(1) 171 PA9 187 NCTSA 203 PB9
156 VDDIO 172 PA8 188 NDTRA 204 VDDIO
157 GND 173 PA7 189 NDSRA 205 DBW32
158 VDDIO 174 PA6 190 NDCDA 206 GND
159 TDO 175 VDDIO 191 RXDB 207 BO256
160 TDI 176 NC(1) 192 TXDB 208 VDDIO
Table 1. Pinout for 208-lead PQFP Package (Continued)
Pin
Number Signal Name Pin
Number Signal Name Pin
Number Signal Name Pin
Number Signal Name
152
53
104
105156
157
208
6AT75C221 Preliminary 6033A–INTAP–03/04
256-ball BGA Package Pinout
Table 2. Pinout for 256-ball BGA Package
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 GND B18 TDI D15 VDDIO H20 NSOE
A2 PB9 B19 NC(1) D16 PA24 J1 MA_TXEN
A3 PB4 B20 NC(1) D17 GND J2 MA_TXD3
A4 PB1 C1 PB10 D18 PA29 J3 MA_TXD2
A5 NDSRB C2 PA28 D19 VDDCORE J4 MA_TXD1
A6 NRSTB C3 DBW32 D20 IRQ1 J17 NWR
A7 RXDB C4 PB6 E1 STXA J18 NWE3
A8 NDSRA C5 PB2 E2 FSA J19 NC(1)
A9 TXDA C6 NRIB E3 SCLKA J20 NWE2
A10 PA2 C7 NCTSB E4 PA25 K1 MA_RXD0
A11 PA3 C8 NRIA E17 PA30 K2 MA_TXCLK
A12 PA6 C9 NCTSA E18 TST K3 NC(1)
A13 PA10 C10 PA0 E19 IRQ0 K4 VDDIO
A14 PA13 C11 PA4 E20 NC(1) K17 NWE1
A15 PA15 C12 PA8 F1 PB13 K18 NWE0
A16 PA19 C13 PA12 F2 PB12 K19 NCE3
A17 NC(1) C14 PA14 F3 SRXA K20 NCE2
A18 PA23 C15 PA18 F4 VDDIO L1 MA_RXD1
A19 TDO C16 PA21 F17 VDDIO L2 MA_RXD2
A20 NC(1) C17 TCK F18 FIQ L3 MA_RXD3
B1 BO256 C18 NC(1) F19 NC(1) L4 MA_RXER
B2 PB8 C19 NC(1) F20 SPCK L17 VDDIO
B3 PB7 C20 PA31 G1 MA_COL L18 NCE0
B4 PB3 D1 PB11 G2 PB15 L19 NC(1)
B5 PB0 D2 PA27 G3 PB14 L20 NCE1
B6 NDTRB D3 PA26 G4 NTRST M1 MA_RXCLK
B7 TXDB D4 GND G17 NRST M2 VDDCORE
B8 NDCDA D5 PB5 G18 PA22 M3 MA_RXDV
B9 NRSTA D6 VDDIO G19 MOSI M4 MA_MDC
B10 PA1 D7 NDCDB G20 MISO M17 PLLRC
B11 PA5 D8 GND H1 MA_TXD0 M18 NC(1)
B12 PA7 D9 NDTRA H2 MA_TXER M19 XTALOUT
B13 PA11 D10 RXDA H3 MA_CRS M20 XTALIN
B14 VDDCORE D11 VDDIO H4 GND N1 MA_MDIO
B15 PA16 D12 PA9 H17 GND N2 MA_LINK
B16 PA20 D13 GND H18 VDDIO N3 MB_COL
B17 TMS D14 PA17 H19 VDDCORE N4 GND
7
AT75C221 Preliminary
6033A–INTAP–03/04
Note: 1. NC Balls should be left unconnected.
N17 GND T20 SDCS V7 A11 W14 D12
N18 DQM3 U1 MB_RXD0 V8 A14 W15 VDDCORE
N19 VDDCORE U2 MB_RXD2 V9 A18 W16 D17
N20 VDDOSC U3 MB_RXCLK V10 A22 W17 D20
P1 MB_CRS U4 GND V11 D2 W18 D24
P2 VDDCORE U5 A1 V12 D6 W19 VDDIO
P3 MB_TXD0 U6 VDDIO V13 D10 W20 NC(1)
P4 MB_TXD3 U7 A8 V14 D14 Y1 NC(1)
P17 RAS U8 GND V15 NC(1) Y2 MB_MDIO
P18 DQM0 U9 A17 V16 D19 Y3 A2
P19 DQM1 U10 VDDIO V17 D23 Y4 A3
P20 DQM2 U11 D3 V18 D26 Y5 A6
R1 MB_TXER U12 D7 V19 NC(1) Y6 A10
R2 MB_TXD1 U13 GND V20 D29 Y7 A13
R3 MB_TXEN U14 D16 W1 MB_MDC Y8 A16
R4 VDDIO U15 VDDIO W2 NC(1) Y9 A20/BA1
R17 VDDIO U16 D22 W3 NC(1) Y10 A23
R18 SDA10 U17 GND W4 MB_LINK Y11 D0
R19 CAS U18 D27 W5 A5 Y12 D4
R20 WE U19 NC(1) W6 A9 Y13 D8
T1 MB_TXD2 U20 D30 W7 A12 Y14 D11
T2 MB_TXCLK V1 MB_RXD3 W8 A15 Y15 D13
T3 MB_RXD1 V2 MB_RXDV W9 A19/BA0 Y16 D15
T4 MB_RXER V3 NC(1) W10 A21 Y17 D18
T17 D28 V4 A0 W11 D1 Y18 D21
T18 D31 V5 A4 W12 D5 Y19 D25
T19 SDCK V6 A7 W13 D9 Y20 NC(1)
Table 2. Pinout for 256-ball BGA Package (Continued)
Pin Sig na l Name Pin Sig nal Nam e P in Sig nal Nam e Pin Sig nal Nam e
8AT75C221 Preliminary 6033A–INTAP–03/04
Mec hanic al Ove rview of
the 256-ball BGA
Package
Figure 4 below shows the orientation of the 256-ball BGA Package.
For a d etaile d mech anica l des criptio n, see “Mec hanic al Charac terist ics a nd Pa ckagi ng”
on page 164.
Figure 4. 256-ball BGA Package Orientation (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
9
AT75C221 Preliminary
6033A–INTAP–03/04
Periphe ra l Mu ltiplexing on PIO Lines
The A T75C2 21 feat ures two PI O Contr oller s, PIOA and PIO B, mu ltiple xing I/O lin es of
the peripheral set.
The PI O Con troller A m anages 32 I/O lin es, PA0 to P A31, b ut onl y the I/O li nes PA0 to
PA12, PA19 and PA22 are available in the 208-lead package.
The PIO Controller B manages only 16 I/O lines, PB0 to PB15, but only the I/O lines
PB0 to PB9 are available in the 208-lead package.
Each I/O line of a PIO Controller can be multiplexed with a peripheral I/O. Multiplexing of
the PIO Controller A is given in Table 3 on page 10. Multiplexing of the PIO Controller B
is given in Table 4 on page 11.
10 AT75C221 Preliminary 6033A–INTAP–03/04
PIO Controller A Multiplexing
Table 3. Multiplexing on PIO Controller A
I/O Line Peripheral
Name QFP 208 Signal Name Description Type
PA0 Yes OAKAIN0 DSP Subsystem User Input 0 Input
PA1 Yes OAKAIN1 DSP Subsystem User Input 1 Input
PA2 Yes OAKAOUT0 DSP Subsystem User Output 0 Output
PA3 Yes OAKAOUT1 DSP Subsystem User Output 1 Output
PA4 Yes
PA5 Yes
PA6 Yes
PA7 Yes
PA8 Yes TCLK0 Timer Counter Clock Input 0 Input
PA9 Yes TIOA0 Timer Counter I/O LIne A 0 I/O
PA10 Yes TIOB0 Timer Counter I/O LIne B 0 I/O
PA11 Yes SCKA UART A Serial Clock I/O
PA12 Yes NPCS1 Serial Peripehral Chip Select 1 Output
PA13 No
PA14 No NPCS2 Serial Peripheral Chip Select 2 Output
PA15 No NPCS3 Serial Peripheral Chip Select 3 Output
PA16 No TCLK2 Timer Counter Clock 2 Input
PA17 No TIOA2 Timer Counter I/O Line A 2 I/O
PA18 No TIOB2 Timer Counter I/O Line B 2 I/O
PA19 Yes ACLKO ARM System Clock Output
PA20 No
PA21 No
PA22 Yes NPCS0 Serial Peripheral Chip Select 0 I/O
PA23 No
PA24 No
PA25 No
PA26 No
PA27 No
PA28 No
PA29 No
PA30 No
PA31 No
11
AT75C221 Preliminary
6033A–INTAP–03/04
PIO Controller B Multiplexing
Table 4. Multiplexing on PIO Controller B
I/O Line Peripheral
Name QFP 208 Signal Name Description Type
PB0 Yes TCLK1 Timer Counter Clock Input 1 Input
PB1 Yes TIOA1 Timer Counter I/O LIne A 1 I/O
PB2 Yes TIOB1 Timer Counter I/O LIne B 1 I/O
PB3 Yes
PB4 Yes
PB5 Yes NRIA UART A Ring Indicator Input
PB6 Yes
PB7 Yes
PB8 Yes
PB9 Yes
PB10 No
PB11 No
PB12 No
PA13 No
PA14 No
PA15 No
12 AT75C221 Preliminary 6033A–INTAP–03/04
Signal Descri ption
Table 5. Signal Description
Block Signal Name Function Type
Power Supplies
VDDIO I/O Line s Power Supply
VDDCORE Device Core Power Supply
VDDOSC PLL and Oscillator Powe r Supply
GND Ground
External Bus Interface [A21:0] Address Bus Output
[D31:0] Data Bus Input/Output
Synchronous Dynamic
Memory Controll er
SDCK SDRAM Clock Output
DQM0-DQM3 SDRAM Byte Masks Output
SDCS SDRAM Chip Select Output
SDA10 SDRAM Address Line 10 Output
RAS Row Address Strobes Output
CAS Column Addre ss Strobes Out put
WE Write Enable Output
BA0-BA1 Bank Address Line Output
Static Me mory Controller
NCE0-NCE3 Ch ip Selects Output
NWE0-NWE3 Byte Select/Write Enable Output
NSOE Output Enable Output
NWR Memory Block Write Enable Output
PIO Controller A PA0-PA31 PIO Controller A I/O Lines Input/Output
PIO Controller B PB0-PB15 PIO Controller B I/O Lines Input/Output
Timer Counter
TCLK0-TCLK2 Timer Counter Clock 0 to 2 Input
TIOA0-TIOA2 Timer Counter I/O Line A 0 to 2 Input/Output
TIOB0-TIOA2 Timer Counter I/O Line B 0 to 2 Input/Output
Serial Peripheral Interface
MISO Master In/Slave Out Input/Output
MOSI Master Out/Slave In Input/Output
SPCK Serial Clock Input/Output
NPCS0/NSS Peripheral Chip Select 0/Slave Select Input/Output
NPCS1-NPCS3 Perip heral Chip Select 1 to 3 Output
13
AT75C221 Preliminary
6033A–INTAP–03/04
UART A and UART B
RXDA-RXDB Receive Data Input
TXDA-TXDB Transmit Data Output
NRTSA-NRSTB Ready to Send Output
NCTSA-NCTSB Clear to Send Input
NDTRA-NDTRB Data Terminal Ready Output
NDSRA-NDSRB Data Set Ready Input
NDCDA-NDCDB Data Carrier Detect Input
MAC A Interface
MA_COL MAC A Collision Detect Input
MA_CRS MAC A Ca rrier Sense Input
MA_TXER MAC A Transmit Error Output
MA_TXD0-MA_TXD3 MAC A Transmit Data Bus Output
MA_TXEN MAC A Transmit Enable Output
MA_TXCLK MAC A Transmit Clock Input
MA_RXD0-MA_RXD3 MAC A Receive Data Bus Input
MA_RXER MAC A Receive Error Input
MA_RXCLK MAC A Receive Clock Input
MA_RXDV MAC A Receive Data Valid Input
MA_MDC MAC A Management Data Clock Output
MA_MDIO MAC A Management Data Bus Input/Output
MA_LINK MAC A Link Interrupt Input
MAC B Interface
MB_COL MAC B Collision Detect Input
MB_CRS MAC B Ca rrier Sense Input
MB_TXER MAC B Transmit Error Output
MB_TXD0-MB_TXD3 MAC B Transmit Data Bus Output
MB_TXEN MAC B Transmit Enable Output
MB_TXCLK MAC B Transmit Clock Input
MB_RXD0-MB_RXD3 MAC B Receive Data Bus Input
MB_RXER MAC B Receive Error Input
MB_RXCLK MAC B Receive Clock Input
MB_RXDV MAC B Receive Data Valid Input
MB_MDC MAC B Management Data Clock Output
MB_MDIO MAC B Management Data Bus Input/Output
MB_LINK MAC B Link Interrupt Input
Table 5. Signal Description (Continued)
Block Signal Name Function Type
14 AT75C221 Preliminary 6033A–INTAP–03/04
In-Circuit Emulator
NTRST Test Reset Input
TCK Test Clock Input
TMS Test Mode Select Input
TDI Test Data Input Input
TDO Test Data Output Output
Codec Interface
SCLKA Serial Clock Input/Output
FSA Frame Pulse Input/Output
STXA Transmit Data to Codec Input
SRXA Receive Data to Codec Output
DSP Subsystem OAKAIN0-OAKAIN1 OakDSPCore User Input Input
OAKAOUT0-OAKAOUT1 OakDSPCore User Output Output
Miscellaneous
NRST Reset Input
FIQ Fast Interrupt Input
IRQ0-IR Q1 Inter rupt Lines Input
PLLRC PLL RC Filter Analog
XTALIN Crystal Input Analog
XTALOUT External Crystal Analog
TST Test Mode Input
B0256 Package Size Option (1 = 256 pins) Input
DBW32 External Data Bus Width for CS0 (1 = 32 bits) Input
ACLKO ARM Clock Output Output
Table 5. Signal Description (Continued)
Block Signal Name Function Type
15
AT75C221 Preliminary
6033A–INTAP–03/04
Power Supplies The AT75C221 has three types of power supply pins:
• VDDCORE pins power the core, including the ARM7TDMI processor, the DSP
subsystem, the memories and the peripherals; voltage is between 1.65V and 1.95V,
1.8V nominal.
• VDDIO pins power the I/O lines, including those of the External Bus Interface and
those of the peripherals; voltage is between 3V and 3.6V, 3.3V nominal.
• VDDOSC pins power the PLL and oscillator cells; voltage is between 1.65V and
1.95V, 1.8V nominal.
Ground pins are common to all power supplies.
System Controller The AT75C221 features a System Controller, which takes care of and controls:
• The Test Mode
•The Reset
• The System Clocks
• The Chip Identifier
The Syste m Controll er manages the reset of all the syst em and integrate s a clock gen-
erator, made up of an oscillator and a PLL.
Test The AT75C221 features a test pi n (TST). This pin must be tied low for normal opera-
tions. Using the A T75C221 wi th the TST pi n at a high le vel mig ht lead to unp redict able
results.
Reset Controller
NRST Pin The AT75C22 1 is rese t by asserti ng the NRST p in low . It shoul d be asse rted f or a tim e
adequate to ensure the startup of the oscillator on a power on, and at least 1 ACLK
cycle for a warm reset. A s the ACLK swi tches on the 31 ,25kHz (assum ing the cr ystal is
at 16 MHz) as soon as the reset is asserted, it must remain low for at least 32 µs. The
first instruction fetch happens 10 ACLK cycles after the reset releases.
System Reset A reset initializes the user interface registers to their default states as defined in the
peripheral sections of this datasheet and forces the ARM7TDMI to perform the next
instruction fetch from address zero. Except for the program counter and the Current Pro-
gram S tatus Regis ter, the ARM process or register s do not h ave defi ned reset states.
When NRST is active, the inputs of the AT75C221 mu st be held at valid logic levels to
reduce the power consumption to a minimum.
Boot Memory and Remap
Command When NRST is released, the PA0 pin is sampled to determine if the ARM processor
should boot from internal ROM or from external memory connected to NCE0. The
details of the boot operation s are descr ibed in “Memo ry Controller ( MC)” on page 20.
The Boot Program is described in “Boot Program” on page 28.
After a reset, the RM bit in the Mode Regis ter reflects the state of the P A0 pin. Then,
writing this bit at 1 removes the RO M from the address 0. Writing it at 0 remaps the
ROM at address 0x0.
DSP Subsystem Reset The DSPRST bit in the Mode Register controls the reset of the DSP Subsystem. Writing
this bit at 0 asserts the reset of the DSP Subsystem. Writing it at 1 releases it.
16 AT75C221 Preliminary 6033A–INTAP–03/04
When NRST is asserted, the DSPRST bit is cleared, so that the DSP Subsystem is held
in reset.
Codec Reset The CRST in the Mode Register controls the reset of the Codec Interface. Writing this bit
at 0 asserts the reset of the Codec Interface. Writing at 1 releases it.
When the NRST is asserted, the CRST bit is cleared, so that the Codec Interface is held
in reset.
Clock Generator The AT75C221 features a Clock Generator, which is based on a 16 MHz oscillator and a
PLL. It provides all the clocks of the system, including:
• A clock signal named ACLK, to the ARM processor, to the memory controller and to
the External Bus Interface and to all the embedded peripherals
• A 60 MHz clock signal named DSPCLK, to the D SP Subsystem
The ACLK signal is also provided on the ACLKO pin, through PIO Controller A.
Figure 5 below shows the architecture of the Clock Generator.
Figure 5. Clock Generator
After the reset, the DSPCLK clock is disabled and the ACLK clock is running at
31.25 kHz. The user can program the LPCS field to speed the boot sequence.
The ACLKST (ARM Clock Status) bit reflects the clock being used for the ARM. When
read at 0, ACLK is 40 MHz if SA is 0 and 34.3 MHz if SA is 1. When re ad at 1, ACLK is
at a f req uenc y ac cordi ng to t he v alu e pro gra mmed in the LPC S fiel d i n th e S IAP M ode
Register (SIAP_MR).
Chip ID The System Controller features a Chip ID Register. The SIAP ID Register reads a value
giving:
• The IDENT field, which is always 0x0221, like the name of the device
XTALOUT
1
6 MHz
C
rystal
XTALIN
16MHz
Oscillator
PLL
x15 DIV4
ACLK
DSPCLK
240 MHz 60 MHz
DIV6
LP
DIV
LPCS
0
1
PLLRC
IDSPCLK
LP
SA
0
1
DIV7
ACLKO
Counter and Control Logic RDY
17
AT75C221 Preliminary
6033A–INTAP–03/04
• the PKG bit, which gives the level of the BO256 pin sampled at reset. This bit
permits to identify whether the data bus is 32-bit wide, as on the BGA256 package,
or 16-bit wide, as the QFP208 package. Note that the QFP208 package can be
emulated with a BGA256 device by tying the pin DBW32 low.
System Controller User Interface
Base Address: 0xFF00 0000.
Table 6. System Controller Register Mapping
Offset Register Name Register Description Access Reset Value
0x0 SIAP_MD SIAP Mode Register Read/Write 0x0000 034x
0x4 SIAP_ID SIAP ID Register Read-only 0x000x 0221
0x8 Reserved
0xC SIAP_CLKF SIAP Clock Status Register Read-only 0x0000001
18 AT75C221 Preliminary 6033A–INTAP–03/04
SIAP-E Mode Register
Register Name: SIAP_MD
Access: Read/Wr ite
•RM: Remap
0 =The ROM is mapped only at its normal address.
1 =The ROM is mapped at its address and at address 0x0.
• DSPRST: DSP Subsystem Reset
0 =The DSP Subsystem reset is asserted.
1 =The DSP Subsystem reset is released.
• IDSPCLK: Inhibit DSP Subsystem Clock
0 =The DSP Subsystem clock is stopped.
1 =The DSP Subsystem is running at 60MHz.
• LP: Low Power Mode
0 =The PLL is enabled and ACLK is the output of the PLL divided by 6 or 7.
1 =The PLL is disabled and ACLK is defined by LPCS.
• SA: Slow ARM
0 =The ARM divider is 6.
1 =The ARM divider is 7.
• LPCS: Low P ower Clock Select
• CRST: Codec Interface Reset
0 =The Codec Interface reset is asserted.
1 =The Codec Interface reset is released.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–CRST– 0 – – LPCS
76543210
SA LP – – IDSPCLK – DSPRST RM
LPCS Divisor ACLK
0 0 2 8 MHz
0 1 16 1 MHz
1 0 64 250 kHz
1 1 512 31,25 kHz
19
AT75C221 Preliminary
6033A–INTAP–03/04
SIAP-E ID Register
Register Name: SIAP_ID
Access: Read-only
• IDENT: Identifier
This field indicates the device identifier 0x0221.
•PKG: Package
0 = BO256 has been sampled low at reset. The package is a QFP208, or a BGA256 and the user configured BO256 to sim-
ulate a QFP208 package.
1 = BO256 has been sampled high at reset. The package is a BGA256.
SIAP-E Clock Status Register
Register Name: SIAP_CLKF
Access: Read-only
• ACLKST: ARM Clock Status
0 = ARM Clock currently using the 240 MHz source (PLL).
1 = ARM Clock currently using the 16 MHz source (oscillator).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––PKG
15 14 13 12 11 10 9 8
IDENT
76543210
IDENT
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––ACLKST
20 AT75C221 Preliminary 6033A–INTAP–03/04
Memory Controller (MC)
Architecture The AT75C221 architecture is made up of two Advanced System Buses, the ARM ASB
and the MAC ASB. Both handle a single memory space.
The ARM ASB handles the ac cess requests of the ARM7TDMI and the PDC. It also
handles the access requests coming from the MAC ASB. It connects with the External
Bus Interface, the Per ipheral Bridge and the Internal Memories, including the m ailbox
with the DSP Subsystem. It also connects with the MAC ASB.
The MAC ASB handles the access requests of the DMAs of both Ethernet MACs. It also
handles the access requests coming from the the ARM ASB. It connects essentially with
the Frame Buffer, but also connects with the ARM ASB.
The major advantage of this double-ASB architecture is that the Ethernet traffic does not
occupy the main ASB bandwidth, ensuring that the ARM7TDMI can perform at its maxi-
mum speed while the Ethernet traffic goes through the Frame Buffer.
The AT75C221 architecture is shown in Figure 6.
Figure 6. AT75C221 Mem or y Contro lle r Architecture
ARM7TDMI
Processor
Main
Bus
Arbiter
Peripheral
Data
Controller
Memory Controller
ARM ASB Internal
ROM
From Master
to Slave
MAC ASB
APB
External
Bus
Interface
MACA
DMA
MACB
DMA
PA0
DSP
SubSystem
Secondary
Bus
Arbiter
ASB-ASB
Bridge
Peripheral
Bridge
Frame
Buffer
21
AT75C221 Preliminary
6033A–INTAP–03/04
Memory Map The AT75C221 memory map is divided into regions of 256 megabytes. The top memory
region (0xF00 0_0000) is reserve d and subdivid ed for the internal m emories, the DSP
Subsystem mailbox and shared memory and the embedded peripherals.
The dev ice can defin e up to five ot her active ex ternal me mory regions by means of the
static memory controller and SDRAM memory controller.
The memory map is divided between both ASBs, as shown in Figure 7. All regions
except the 16 megabytes between 0xFC00 0000 and 0xFCFF FFFF are located on the
Main ASB. Accesses to locations between 0xFC00 0000 and 0xFCFF FFFF are routed
to the MAC ASB.
The memo ry map assume s default valu es on reset. Ext ernal memory reg ions can be
reprogrammed to other base addresses in the Static Memory Controller or in the
SDRAM Controller. Note that the internal memory regions have fixed locations that can-
not be reprogrammed.
There are no hardware locks to prevent incorrect programming of the regions. Program-
ming two or more regions to have the same base address or overlapping two memory
regions res ul ts in unde fin ed beha vi or .
The ARM processor reset vector at address 0x00000000 is mapped into the internal
ROM or extern al me mory c onnec ted o n NCE0 . Thi s sel ectio n depe nds o n the PA0 sig-
nal pin. After booting, the ROM region can be disabled and any external memory can be
mapped to the bottom of the memory map by programming SMC_CSRx or
SDRAMC_ADDR.
Figure 7. AT75C221 Mem or y Map
0x0000 0000
0x0FFF FFFF
0x1000 0000
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
0x3000 0000
0x3FFF FFFF
0x4000 0000
0x4FFF FFFF
0x5000 0000
0xEFFF FFFF
0xF000 0000
0xFFFF FFFF
256M bytes
256M bytes
256M bytes
256M bytes
256M bytes
256M bytes
10 x 256M bytes
External Static Memory
connected on NCE0
Unused
Internal Memories
and Peripherals
External Static Memory
connected on NCE1
External Static Memory
connected on NCE2
External Static Memory
connected on NCE3
SMC
External Static Memory
connected on SDCS SDRAMC
22 AT75C221 Preliminary 6033A–INTAP–03/04
Figure 8 below shows the mapping of the internal memories and the address space
reserved for the Peripheral Bridge.
Figure 8. Internal Memory Mapping
ARM ASB Arbitration The ARM ASB is arbitrated with the following priorities:
• The PDC has the highest priority.
• The Bridge from the MAC ASB has the middle priority.
• The ARM processor has the lowest priority.
MAC ASB Arbitration The MAC ASB is arbitrated with the following priorities:
• The Bridge from the ARM ASB has the highest priority.
• The MAC A has the middle priority.
• The MAC B has the lowest priority.
ASB-ASB Bridge
Arbitration The MAC ASB has two priority levels; the two MACs share low priority access and the
ASB-ASB Bridge has high priority. The MACs do not burst more than four words per
access and release the bus request between accesses so the MACs share a priority
level with a simple round-robin arbitration scheme.
The A RM is likely to be the only mast er accessin g the MAC bus via the bridge and
should not perfor m more than a couple o f cycles before r eleasing the MAC bus. Car e
should be taken to prevent other masters o n the ARM bus holding the MAC bus for
more than a few cycles. Otherwise , the MACs drop frames due to FIFO overflow or
underflow.
When a ma ster on o ne bus ac ce ss es a slave o n t he oth er bu s, th e foll owi ng op er ati ons
occur:
• The local b us arbit er arbi trat es th e maste r’ s r equest f or th e local A SB b us if i t does not
already have access to the bus.
• When the local bus arbiter grants the local bus to the master, the master initiates a
cycle with an address corresponding to a slave on the remote bus.
• The bridge is selected as the slave on the local bus and responds by inserting wait
cycles. The bridge also requests the remote bus from the remote bus arbiter.
0xF8FF FFFF
0xFA00 0000
0xFAFF FFFF
0xFB00 0000
0xFBFF FFFF
0xFC00 0000
0xFCFF FFFF
0xFD00 0000
0xFDFF FFFF
0xFD00 0000
0xEFFF FFFF
0xFF00 0000
0xFFFF FFFF
144M bytes
16M bytes
16M bytes
16M bytes
16M bytes
16M bytes
Reserved
Unused
Peripherals
OAKA Dual Port Mail Box
Reserved
Frame Buffer
OAKA Program RAM
0xF900 0000
0xF9FF FFFF ROM
Actual Siz
e
1K byte
512 bytes
0xFF00 0000
16M bytes
16M bytes
16K byte
s
64K byte
s
23
AT75C221 Preliminary
6033A–INTAP–03/04
• When the bridge is granted the remote bus, the two ASB buses are coupled and the
transfer completes.
The ASB pe rfor ms pip eline d arbitr ation. T he AS B-ASB Brid ge can onl y req uest the bus
when the address of the slave is available. For this reason, the ASB-ASB Bridge inserts
a wait cycle during the arbitration cycle on the remote bus because it cannot request the
bus early.
Boot Mode The AT75C221 ha s an inte grated 1- Kby te ROM to sup port the boot software. When th e
device is released from reset, the pin PA0 is sampled by the Memory Controller. If sam-
pled low, the intern al ROM be comes access ible from the ad dress 0x 0, so tha t the AR M
processo r st ar ts ex ecu tio n o f the Bo ot P r ogram. Note th at th e ROM r ema ins a cce ssi bl e
at its normal address. If the pin PA0 is sampled high at reset, the mapping does not
change and the external memory connected on NCE0 should contain a valid boot
sequence.
The level of the pin PA0 at resets is indicated by the RM flag in the SIAP-E Mode Regis-
ter (SIAP_MD). Then, the RM bit c an be written at any value to map to or remove the
ROM from address 0x0.
If PA0 is asserted on reset, the Boot Program in ROM is executed. The Boot Program is
described in “Boot Program” on page 28.
Figure 9 below shows the mapping of the ROM depending on the Boot Mode.
Figure 9. ROM Mapping Depending on the Boot Mode
Endianness The AT75 C221 Memor y Control ler opera tes in lit tle-end ian mode on ly. The us er has to
make sure that the data structures used by the ARM7TDMI, the Ethernet DMAs and the
PDC are compliant with this mode of byte arrangement.
OakA Program RAM During normal operation, internal 64K x 8 RAM contains the program executed by the
OakDSPCore. However, when the OakDSPCore is held in reset, this RAM is mapped in
the ARM ad dress space to al low f or DSP cod e upl oad. Th is m echa nism is ex plained in
details in the DSP Subsystem datasheet.
The ARM processor can also use the DSP program RAM as a general purpose mem-
ory. It can access it for code or for data. The access times are summarized below.
0x0000 0000
0x0FFF FFFF
256M bytes
ROM
RM = 0
1K byte
External Memory
Connected on
NCE0
External Memory
Connected on
NCE0
0x0000 03FF
0x0000 0400
RM = 1
24 AT75C221 Preliminary 6033A–INTAP–03/04
• Data Wr i te
– byte: 1 wait state
– half word (aligned): 1 wait state
– word (aligned): 3 wait states
• Data Read
– byte: 1 wait state
– half word: 1 wait state
– word: 3 wait states
• Code Fetch:
– Thumb: 1 wait state
– ARM: 3 wait states
Unaligned 16- or 32-bit acc ess es are not suppor ted and might lead to unpredictable
results.
Dual -Port Mailbox This block of memory is described in the documentation of the DSP Subsystem.
25
AT75C221 Preliminary
6033A–INTAP–03/04
Peripherals T he Peripheral Bridge allows access to the embedded per ipheral user interfaces. It is
optimized for low power consumption, as it is built without usage of any clock. However,
any access on the peripheral is performed in two cycles.
The AT75C22 1 peripher als are design ed to be progra mmed with a minimu m number of
instructions. Each peripheral has 16K bytes of address space allocated in the upper part
of the address space.
Peripheral Registers All of the peripheral registers are 32-bits wide and support only aligned accesses. When
a misaligned access is performed within the peripheral address space, the access is
automatically performed at the lower aligned address.
All the register bits which are unde fined or unused (marked “-”) read 0. It is recom-
mended to write them at 0 for software upward compatibility.
26 AT75C221 Preliminary 6033A–INTAP–03/04
Peripheral Memory Map Figure 10 below gives the mapping of the peripherals integrated in the AT75C221.
Figure 10. Peripheral Memory Map
16K bytes
Peripheral Name Size
16K bytes
16K bytes
0
xFF00 4000
0xFF00 7FFF
16K bytes
Reserved
0
xFF00 8000
0xFF00 BFFF
SDRAMC SDRAM Controller
PIOA
0
xFF00 C000
0xFF00 3FFF
0xFF02 4000
0xFF02 FFFF
0xFF00 FFFF
TC0, TC1, TC2
0
xFF01 4000
0xFF01 7FFF
AIC
0
xFF03 0000
0xFF03 3FFF
MACA Ethernet MAC A
0
xFF03 4000
UART A Universal Asynchronous
Receiver Transmitter A
0
xFF01 8000
0xFF01 BFFF
UART B Universal Asynchronous
Receiver Transmitter B
0
xFF01 C000
0xFF01 FFFF
Reserved
0xFF03 C000
0xFFFF EFFF
SPI Serial Peripheral Interface
0
xFF02 0000
0xFF02 3FFF
0
xFF00 0000 SIAP
SMC
System Controller 16K bytes
Static Memory Controller 16K bytes
Parallel I/O Controller A 16K bytes
PIOB
0
xFF01 0000
0xFF01 3FFF
Parallel I/O Controller B 16K bytes
Timer Counter Channel 0, 1 and 2 16K bytes
16K bytesAdvanced Interrupt Controller
16K bytes
0xFF03 7FFF
MACB Ethernet MAC B
0
xFF03 8000 16K bytes
0xFF03 BFFF
AIC
0
xFFFF F000
0xFFFF FFFF
16K bytesAdvanced Interrupt Controller
AIC is
mapped
at both
addresse
s
27
AT75C221 Preliminary
6033A–INTAP–03/04
Peripheral Data Controller (PDC)
PDC Overview The A T75C221 fea tures a six-chan nel Peripheral Data Contr oller (PDC) dedicate d to
the tw o on-chip UARTs a nd the S PI. One P DC chan nel is connected to the r eceivin g
channel and one to the transmitting channel of each UART and of the SPI.
Each PDC channel operates as DMA (Direct Memory Access).
The User Interface of a PDC channel is integ ra ted i n the me mory spa ce of eac h per iph-
eral. It contains a 32-bit address pointer register and a 16-bit count register. When the
programmed number of bytes is transferred, an end-of-tr ansfer signal is sent to the
periphe ral a nd is vi sible in the p eripher al st atus regi ster. T his stat us bit might tr igge r an
interrupt.
PDC Channel Priority The transfer requests from the peripherals are treated in the order they happen.
When sev eral trans fer reque sts happ en in the sam e cycle, the followi ng priori ty order is
applied:
• the UART A receiver
• the UART A transmitter
• the UART B receiver
• the UART B transmitter
• the SPI receiver
• the SPI transmitter
28 AT75C221 Preliminary 6033A–INTAP–03/04
Boot Program The AT75C221 can boot in several ways as explained below. When the ARM7TDMI
processor is released from reset it basically attempts a fetch from address 0x00000000.
Depending on an hardware configuration, the memory mapping can be altered and thus
modify how the system boots.
Boot Mode When the master reset is released, the pin PA0 is latched. Its state defines how the sys-
tem boots. Wh en P A0 i s la tch ed at 1, the AT75C221 is said to be configured in exter na l
boot mode. T he initial state of the EBI m aps the 1-M byte address ran ge starting fro m
0x00000000 in the external device selected by NCE0. In this boot mode, NCE0 is
assumed to be connected to an external memory device containing the suitable boot
code.
When PA0 is latched at 0, the AT75C221 is said to be configured in internal boot mode.
The internal boot ROM normally located at base address 0xf9000000 is aliased at
addre ss 0x00 000000 . In this boot mod e, the ARM Proc essor e xecutes the firs t instru c-
tions out of the internal boot ROM.
The boot mode is reflected by the RM bit in register SIAP_M D. Reading RM at 0 indi-
cates that the boot ROM is aliased at base address 0x00000000, eventually overlapping
the memory layout defined by the SMC and the S DRAMC registers. Reading RM at 1
indicates that the boot ROM can be accessed only from base address 0xf9000000. Writ-
ing RM allows to select the mapping of the boot ROM under software control.
Hardware Connection of
the DataFlash The internal boot software provides the AT75C221 with the capability of booting from an
external serial DataFlash connected on the on-chip SPI interface as described above.
When the i nte rn al b oot so ftware i s use d i n conj unc ti on with a DataFlash, the l atte r must
be connected to the AT75C221 as shown below in Figure 11.
Figure 11. DataFlash Connection
Internal Boot Software The internal boot code goes through the following steps in sequence:
• The processor enters the supervisor mode and all the interrupts are masked.
• A branch is executed into the ROM alias based from 0xf9000000.
• The ROM alias based at 0x00000000 is removed by writing the RM bit at 1.
• The clock is programmed at the highest frequency achievable without using the on-
chip PLL (i.e. the frequency of the crystal divided by 2).
• The on-chip SPI interface is setup to prepare for communications with DataFlash.
• A bunch of data is downloaded from the DataFlash. This data is expected to contain
a formatted header describing the contents of the DataFlash.
• This header is analyzed to verify whether a DataFlash is actually present and
contains valid executable code.
C221
NPCS0/PA22
MISO
DataFlash
CS
SIMOSI
SPCK
SO
CK
29
AT75C221 Preliminary
6033A–INTAP–03/04
• If the DataFlash is there and contains valid executable code, this code is
downloaded into a location specified by the header, and an absolute branch to this
code is performed.
• If the DataFlash is missing, or if the header is not valid, an absolute branch to
address 0x00000000 is perf ormed. A suitable memory device should be mapped at
this address and contain the expected code.
DataFlash Header Details To ensure cor rect oper ation of the boo t out of a DataF lash, the Da taFlash must contai n
a valid header. This header contains several fields which define how the application
software residing further must be handled. The structure of the DataFlash header is
illustrated below in Table 7.
Note: 1. The field address is respective to the DataFlash space. 0x00 corresponds to the first
location of the DataFlash.
The MA GIC fie ld c ontai ns a predefi ned m agic numb er whic h al lows identif icati on of the
suitability of the DataFlash. The value of this field must be 0x0075C221 to allow the boot
routine to proceed. If another value is read, the boot code gives up the download and
branches to 0x0000 0000 where the real application code is expected.
The DSRC field contains the address where the code to be downloaded resides in
DataFla sh. This address is respec tive to the Data Flash ad dress s pace ( not the ARM
Process or addres s spa ce) and fol lows the non-line ar addr essin g schem e define d in the
documentation of the DataFlash. Note that all bits are not necessarily significant,
depending on the specific DataFlash device.
The DDS T field conta ins the desti nation addre ss where the do wnloaded c ode will be
copied. T his add ress is r especti ve to th e AR M Proces sor add ress spac e. Typi call y, this
address should point into some internal RAM.
The DSIZE field contains the number of bytes to be downloaded. This value is exclusive
of the header. It must be even.
The E NTRY fiel d cont ains the addres s where t he boot routin e must branch wh en the
downlo ad is comp lete. It i s the entry point of the newly dow nloade d softwa re. Altho ugh
this is not required, the ENTRY field equals the DDST field in most cases.
Reserved Resources The inte rnal boot cod e needs some res ources to ope rate correc tly, espec ially as it pro-
grams some on-chip peripherals. These must not be assumed to be in their reset state
when the control is given to the application code. The concerned peripherals are:
• the clock management system
• the SPI interface
• the PIO pin PA22
• the RM bit
Table 7. Header Structure
Field Addr ess Field Name Field Length
0x00 (1) MAGIC 4 bytes
0x04 DSRC 4 bytes
0x08 DDST 4 bytes
0x0c DSIZE 4 bytes
0x10 ENTRY 4 bytes
30 AT75C221 Preliminary 6033A–INTAP–03/04
The interna l boot code also us es some intern al RAM locations to store tempo rary data.
These reside in the first 64 bytes of RAM, i.e. from 0xFD00 FFC0 to 0xFD00 FFFF. The
DDST, DSIZE fields of the DataFlash header must not defi ne a memory area overlap-
ping the locations used by the internal boot routine. The ENTRY field must not point into
this area.
31
AT75C221 Preliminary
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Exte rnal Bus Interface (EBI)
The Exter nal Bus Inte rfac e (EB I) g ener a tes the sign al s whi c h co ntrol acce ss to ex ternal
memor ies or periphe ral devic es. It co ntains tw o contr ollers , the SDRA M Contro ller an d
the Static Memory Controller and manages the sharing of data and address busses
between both of these controllers.
Signal Multiplexing
Table 8. Signal Description and Multiplexing
Name Description Contr ol led b y SMC Contro lled by
SDRAMC
[D31:0] Data Bus [D31:0] [D31:0]
[A9:0] Address Lines 0 to 9 [A9:0] [A9:0]
A10 Address Lin e 10 A10
SDA10 SDRAM Controller Address Line 10 A10
[A12:11] Address Lin es 11 to 12 [A12:1 1] [A12:11]
[A18:13] Address Lines 13 to 18 [A18:1 3]
A19/BA0 Address Line 19 or Bank Address 0 A19 BA0
A20/BA1 Address Line 20 or Bank Address 1 A20 BA1
[A23:21] Address Lines 21 to 23 [A23:2 1]
SDCK SDRAM Clock SDCK
SDCS SDRAM Controller Chip Select SDCS
RAS SDRAM Row Signal RAS
CAS SDRAM Column Signal CAS
WE SDRAM Write Enable WE
DQM0-DQM3 SDRAM Data Mask Enable Signals DQM0-DQM3
NCE0-NCE3 Active low chip enable NCE0-NCE3
NWE0-NWE3 Active low byte select/write strobe signals NWE0-NWE3
NWR Active low write strobe signals NWR
NSOE Active low read enable signal NSOE
32 AT75C221 Preliminary 6033A–INTAP–03/04
SDRAM Controller (SDRAMC)
Description The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by provid-
ing the interface to an external 16-bit or 32-bit SDRAM device. The page size suppor ts
ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte
(8-bit), half-word (16-bit) and word (32-bit) accesses. The maximum addressable
SDRAM size is 256M bytes.
The SDRAM Cont roller s uppor ts a read or write burst length of one loc ation. It keeps
track of the active row in each bank, thus maximizing SDRAM performance, e.g., the
application may be placed in one bank and data in the other banks. So as to optimize
performance, it is advisab le to avoid accessing different rows in the same bank.
Block Diagram Figure 12. SDRAM Controller Block Diagram
33
AT75C221 Preliminary
6033A–INTAP–03/04
I/O Lines Description
Application Example
Hardware Interface Figure 13 below shows an example of an SDRAM device c onnection to the SDRAM
Controll er by us ing a 32-b it data bu s width . Figure 14 show s an ex ample of an S DRAM
device connection by using a 16-bit data bus width.
Figure 13. SDRAM Controller Connections to SDRAM Devices: 32-bit Data Bus Width
Table 9. I/O Line Description
Name Description Type Active Level
SDCK SDRAM Clock Output
SDCS SDRAM Controller Chip Select Output Low
BA[1:0] Bank Select Signals Output High
RAS Row Si gnal Output Low
CAS Column Signal Output Low
WE SDRAM Write Enable Output Low
DQM[3:0] Data Mask Enable Signals Output Low
A [12:11]
SDA10
A[9:0]
Address Bus Output
D[31:0] Data Bus I/O
SDRAM
Controller
D0-D31
A0-A9, SDA10, A11
RAS
CAS
SDCK
WE
DQM0
2M x 8
SDRAM
D0-D7
A0-A11
RAS
CAS
CLK
CKE CKE
WE
DQM
CS
BA0
BA1
DQM1
DQM2
DQM3
SDCS
D0-D7 D8-D15
A19/BA0
A20/BA1
A0-A11
BA0
BA1
2M x 8
SDRAM
D0-D7
RAS
CAS
CLK
WE
DQM
CS
BA0
BA1 BA0
BA1
2M x 8
SDRAM
D0-D7
RAS
CAS
CLK
WE
DQM
CS
BA0
BA1
D16-D23 D24-D31
BA0
BA1
2M x 8
SDRAM
D0-D7
RAS
CAS
CLK
WE
DQM
CS
BA0
BA1 BA0
BA1
DQM0 DQM1
DQM3
DQM2
WE
WE
WE
WE
A0-A11
VDD VDD
CKE
VDD CKE
VDD
A0-A11 A0-A11
A0-A11 A0-A11 A0-A11 A0-A11
34 AT75C221 Preliminary 6033A–INTAP–03/04
Figure 14. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width
Software Interface The SDRAM Contro ller’s fun ction is to mak e the SDRAM dev ice access pr otocol tran s-
parent to the use r. Tab le 10 to T able 14 il lustrat e t he SD RAM d evice memor y m appin g
therefor e seen by t he user in corre lation with th e devic e structur e. Various configura-
tions are illustrated.
32-bit Memory Data Bus Width
16-bit Memory Data Bus Width
SDRAM
Controller
D0-D31
A0-A9, SDA10, A11
RAS
CAS
SDCK
WE
DQM0
2M x 8
SDRAM
D0-D7
A0--A11
RAS
CAS
CLK
WE
DQM
CS
BA0
BA1
DQM1
SDCS
D0-D7 D8-D15
A19/BA0
A20/BA1
A0-A11
BA0
BA1
2M x 8
SDRAM
D0-D7
A0-A11
RAS
CAS
CLK
WE
DQM
CS
BA0
BA1
A0- A11
BA0
BA1
DQM0 DQM1
SDWE
SDWE
VDD CKE VDD CKE
A0-A11
Table 10. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bk[1:0] Row[10:0] Column[7:0] M[1:0]
Bk[1:0] Row[10:0] Column[8:0] M[1:0]
Table 11. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
2726252423222120191817161514131211109876543210
Bk[1:0] Row[11:0] Column[7:0] M[1:0]
Table 12. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bk[1:0] Row[10:0] Column[7:0] M0
Bk[1:0] Row[10:0] Column[8:0] M0
Bk[1:0] Row[10:0] Column[9:0] M0
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AT75C221 Preliminary
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SDRAM Device
Initialization The initialization sequence is generated by software. The SDRAM devices are initialized
by the following sequence:
1. A minimum pause of 200 µs is provided to precede any signal toggle.
2. An All Banks Precharge command is issued to the SDRAM devices.
3. Eight auto-refresh (CBR) cycles are provided.
4. A mode register set (MRS) cycle is issued to program the parameters of the
SDRAM devices, in particular CAS latency and burst length.
5. A Normal Mode command is provided, 3 clocks after tMRD is met.
6. Perform a dummy access in the SDRAM Memory Space to initialize the state
machine.
7. Write refresh rate into the count field in the SDRAMC Refresh Timer register.
(Refresh rate = delay between refresh cycles).
After these six steps, the SDRAM devices are fully functional.
The comm ands ( NOP, MR S, CBR, nor mal mod e) are g enerated b y prog ramming th e
command field in the SDRAMC Mode register.
Table 13. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
2726252423222120191817161514131211109876543210
Bk[1:0] Row[11:0] Column[7:0] M0
Bk[1:0] Row[11:0] Column[8:0] M0
Table 14. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
2726252423222120191817161514131211109876543210
Bk[1:0] Row[12:0] Column[7:0] M0
36 AT75C221 Preliminary 6033A–INTAP–03/04
Figure 15. SDRAM Device Initialization Sequence
tRP tRC tMRD
SDCK
A[9:0]
SDA10
A
[12:11]
SDCS
RAS
CAS
WE
NBS
Inputs Stable for
200 µsec Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command
37
AT75C221 Preliminary
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SDRAM Controller Writ e
Cycle The SDRAM Co ntr oller all ows bur s t ac ces s or s i ngl e a cces s . To initiate a burst access,
the SDRAM Controller uses the transfer type signal provided by the master requesting
the access. If the next access is a sequential write access, writing to the SDRAM device
is carried out. If the next access is a write-sequential access, but the current access is to
a boundar y page, or if the nex t access is in a nother row, th en the SDRAM Cont roller
generates a precharge command, activates the new row and initiates a write command.
To comply with SDRAM timing parameters, additional clock cycles are inserted between
prec harge/ active (tRP) commands and active/write (tRCD) commands. For a definition of
these timing parameters, refer to the “SDRAMC Configuration Register” on page 43.
This is described in Figure 16 below.
Figure 16. Write Burst, 32-bit SDRAM Access
SDCK
SDCS
RAS
CAS
A
[12:0]
D
[31:0]
t
RCD
= 3
Dna
WE
Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl
Row n col a col b col c col d col e col f col g col h col i col j col k col l
38 AT75C221 Preliminary 6033A–INTAP–03/04
SDRAM Controller Read
Cycle The SDRAM Co ntr oller all ows bur s t ac ces s or s i ngl e a cces s . To initiate a burst access,
the SDRAM Controller uses the transfer type signal provided by the master requesting
the access. If the next access is a sequential read access, reading to the SDRAM
device is carried out. If the next ac cess is a sequential read access , but the current
access is to a boundar y page, or if the next ac cess is in ano ther row, th en the SDRA M
Contro ller gene rate s a prec har ge co mman d, activ ates the new ro w and in itia tes a rea d
command. To comply with SDRAM timing parameters, an additional clock cycle is
inserted between the precharge/active (tRP) command and the active/read (tRCD) com-
mand, After a read command, additional wait states are generated to comply with cas
latenc y. The SDRAM Contr oller supports a cas latency of two . For definition of th ese
timing parameters, refer to “SDRAMC Configuration Register” on page 43. This is
described in Figure 17 below.
Figure 17. Read Burst, 32-bit SDRAM access
SDCK
SDCS
RAS
CAS
A[12:0]
D[31:0]
(Input)
Dna
WE
Dnb Dnc Dnd Dne Dnf
Row n col a col b col c col d col e col f
t
RCD
= 3 CAS = 2
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AT75C221 Preliminary
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Border M anag ement When the memory row boundary has been reached, an automatic page break is
inserted. In this case, the SDRAM controller generates a precharge command, activates
the new row and initiates a read or write command. To comply with SDRAM timing
parameters, an additional clock cycle is inserted between the precharge/active (tRP)
command and the active/read (tRCD) command. This is described in Figure 18 below.
Figure 18. Read Burst with Boundary Row Access
SDCK
SDCS
RAS
CAS
A
[12:0]
D
[31:0]
T
RP
= 3
WE
Row m
col a col a col b col c col d col e
Dna Dnb Dnc Dnd
T
RCD
= 3 CAS = 3
col b col c col d
Dma Dmb Dmc Dmd
Row n
Dme
40 AT75C221 Preliminary 6033A–INTAP–03/04
SDRAM Controller
Refresh Cycles An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are
generated internally by the SDRAM device and incremented after each auto-refresh
automa tically . The S DRAM Co ntrolle r gen erates th ese a uto-refres h co mmands period i-
cally. A timer is loaded with the value in the register SDRAMC_TR that indicates the
number of clock cycles between refresh cycles.
When the SDRAM Co ntroller initiate s a refresh of the SD RAM device , intern al memory
accesses are not delayed. However, if the ARM tries to access the SDRAM, it is hel d
until the refresh cycle has completed. See Figure 19 below.
Figure 19. Refresh Cycle Followed by a Read Access
SDCK
SDCS
RAS
CAS
A
[12:0]
D
[31:0]
(input)
WE
Dnb Dnc Dnd
col c col d
CAS = 2
Row m col a
Row n
Dma
t
RP
= 3
t
RC
= 8 t
RCD
= 3
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AT75C221 Preliminary
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SDRAM User Interface
Base Address: 0xFF00 8000
SDRAMC Mo de Register
Register Name: SDRAMC_MR
Access Type: Read/Write
Reset Value: 0x00000010
• MODE: SDRAMC Command Mode
This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
Table 15. SDRAM Controller Register Mapping
Offset Register Name Register Description Access Reset State
0x00 SDRAMC_MR SDRAMC Mode Register Read/Write 0x00000000
0x04 SDRAMC_TR SDRAMC Refresh Timer Register Read/Write 0x00000800
0x08 SDRAMC_CR SDRAMC Configuration Register Read/Write 0x0299C140
0x0C SDRAM_16BIT SDRAM 16-bit configuration Read/Write 0x00000001
0x10 SDRAMC_ADDR Base address for SDCS Read/Write 0x00000040
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––MODE
76543210
MODE – –
MODE Description
0 0 0 Normal mode. Any access to the SDRAM is decoded normally.
0 0 1 The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle.
0 1 0 The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
regardless of the cycle.
0 1 1 The SDRAM Controller issues a “Load Mode R egister” command when the SDRAM device is accessed
regardless of the cycle. The address offset with respect to the SDRAM device base address is used to program
the Mod e Re gister. Fo r insta nce , wh en thi s mo de is activ ate d, a n acces s to t he “SDRA M_Base + offs et” ad dress
genera tes a “Loa d Mode Regis ter” comma nd wit h the v alue “off se t” written to the SDRAM de vi ce Mod e Regi ster.
1 0 0 The SDRAM Controller issues a “Refresh” Command when the SDRAM device is accessed regardless of the
cycle. Prior to this, an “All Banks Precharge” comm and must be issued.
Others Reserved
42 AT75C221 Preliminary 6033A–INTAP–03/04
SDRAMC Refre sh Timer Re gister
Register Name: SDRAMC_TR
Access Type: Read/Write
Reset Value: 0x00000800
• COUNT: SDRAMC Refresh Timer Count
This 12-bi t field is lo aded int o a timer th at generates the refresh pu lse. Each time the refre sh pulse i s generate d, a refresh
burst is initiated . The value to be loade d depends on the SDRAMC clock frequency (MCK: Mast er Clock), the refresh rate
of the SDRAM device and the refresh burst length where 15.6 µs per row is a typical value for a burst of one length.
To refresh the SDRAM device even if the reset value is not equal to 0, this 12-bit field must be written. If this condition is not
satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – COUNT
76543210
COUNT
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SDRAMC Configuration Regist er
Register Name: SDRAMC_CR
Access Type: Read/Write
Reset Value: 0x0299C140
• NC: Number of Column Bits
Reset value is 8 column bits.
• NR: Number of Row Bits
Reset value is 11 row bits.
• NB: Number of Banks
Reset value is two banks.
• TWR: Write Recovery Delay
Reset value is two cycles.
This field defines the Write Recov ery Time in number of cycles. Number of cycles is between 2 and 15.
If TWR is less than or equal to 2, two clock periods are inserted by default.
31 30 29 28 27 26 25 24
–TRAS
23 22 21 20 19 18 17 16
TRAS TRCD TRP
15 14 13 12 11 10 9 8
TRP TRC TWR
76543210
TWR 1 0NB NR NC
NC Column Bits
008
019
1010
1111
NR Row Bits
00 11
01 12
10 13
11 Reserved
NB Number of Banks
02
14
44 AT75C221 Preliminary 6033A–INTAP–03/04
• TRC: Row Cycle Delay
Reset value is eight cycles.
This field defines the delay between a Ref re sh and an Activate Com mand in number of cycles. Number of cycles is
between 2 and 15.
If TRC is less than or equal to 2, two clock periods are inserted by default.
• TRP: Row Precharge Delay
Rese t value is three cycles.
This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles
is between 2 and 15.
If TRP is less than or equal to 2, two clock periods are inserted by default.
• TRCD: Row to Column Delay
Rese t value is three cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of
cycles is between 2 and 15.
If TRCD is less than or equal to 2, two clock periods are inserted by default.
• TRAS: Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of
cycles is between 2 and 15.
If TRAS is less than or equal to 2, two clock periods are inserted b y default.
SDRAMC Address Registe r
Register Name: SDRAMC_ADDR
Access Type: Read/Write
• SDCS_ADDR
This field defines the eight most significant bits of the base address of the SDRAMC .
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SDCS_ADDR
45
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Static Memory Controller (SMC)
The AT75C221 features a Static Memory Controller (SMC), that enables interfacing with
a wide rang e of external static m emory on perip heral devices, i ncluding Fla sh, ROM,
static RAM, and parallel peripherals.
The SMC provides a gl ueless memory i nterface to external memory using common
addres s, data bus and ded icate d contr ol signal s. The SMC is highly program mable and
has up to 24 bits of address bus, a 32- or 16-bit data bus and up to four chip select lines.
The SMC su p ports di ffere n t ac ce ss pr oto co ls al lowi ng si ngl e c lock - cycl e a cc esse s. Th e
SMC is prog rammed as an inter nal periphe ral that has a stand ard APB bus in terface
and a set of memory-mapped registers. It shares the external address and data buses
with the SDRAMC and any external bus master.
External Memory
Mapping The memory map associates the internal 32-bit address space with the external 24-bit
addres s bus. The mem ory map is defin ed by prog ramming the base addr ess and page
size of the external memories. Note that address bits A2 to A23 are significant for 32-bit
memories whereas address bits A1 to A23 are significant for 16-bit memories.
If the physical memory-m apped device is smaller than the programmed page size, it
wraps aroun d an d ap pear s to b e repeat ed wi thin the page . T he SMC cor rect ly han dles
any valid access to the memory device within the page.
In the event of an access request to an address outside any programmed page, an abort
signal is ge nerated by the i ntern al decode r. T wo type s of ab ort are poss ible: ins tructio n
prefetch abort and data abort. The corresponding exception vector addresses are
0x0000000C and 0x00000010. It is up to the system programmer to program the excep-
tion handling routine used in case of an abort.
Pin Description Table 16 below lists the pins used by the SMC to control external memories.
Data Bus Width A data bus width of 32 or 16 bits can be selected for each chip select. This option is con-
trolled by the DBW field in the Chi p Selec t Register (SMC_CSR) of the corresponding
chip select.
The AT75C221 boots up with a data bus as defined by the DBW32 pin. If tied high, Chip
Sele ct 0 is automati call y setup to b e 32-bit wid e. If ti ed low , the Chi p Sel ect 0 is confi g-
ured to be 16-bit wide.
The DBW bit in SMC_CSR resets accordingly to the level of DBW32.
Table 16. SMC Pin Description
FPDRAM Description Type
[A23:0] Address bus Output
[D31:0] Data bus I/O
NCE0-NCE3 Active low chip enable Output
NWE0-NWE3 Active low byte select/write strobe signals Output
NWR Active low write strobe signals Output
NSOE Active low read enable signal Output
46 AT75C221 Preliminary 6033A–INTAP–03/04
Byte Write or Byte Select
Mode Each chip select can be individually programmed to operate in Byte Write or Byte Select
Mode.
• The Byte Write Mode supports f our (32-bit b us) or two (16-bit bus) byte writes and a
single read signal.
• The Byte Select Mode selects the appropriate byte(s) using four (32-bit bus) or two
(16-bit bus) byte-select lines and separate read and write signals.
This option is contro lled by the BAT bit in the Chip Select Register (SMC_CSR 0 to
SMC_CSR3).
The Byte Write Mode is us ed to connect four 8-bit devices on a 32-bit bus or two 8-bit
devices on a 16-bit bus.
For a 32-bit bus:
• The NWE0 signal is used as the write enable signal for byte 0.
• The NWE1 signal is used as the write enable signal for byte 1.
• The NWE2 signal is used as the write enable signal for byte 2.
• The NWE3 signal is used as the write enable signal for byte 3.
• The NSOE signal enables memory reads to all memory blocks.
For a 16-bit bus:
• The NWE0 signal is used as the write enable signal for byte 0.
• The NWE1 signal is used as the write enable signal for byte 1.
• The NSOE signal enables memory reads to all memory blocks.
The Byte Select Mode is used to connect one 32-bit device or two 16-bit devices on a
32-bit data bus or one 16-bit device on a 16-bit data bus.
For a 32-bit bus:
• The NWE0 signal is used to select byte 0 for read and write operations.
• The NWE1 signal is used to select byte 1 for read and write operations.
• The NWE2 signal is used to select byte 2 for read and write operations.
• The NWE3 signal is used to select byte 3 for read and write operations.
• The NWR signal is used as the write enable signal for the memory block.
• The NSOE signal enables memory reads to the memory block.
For a 16-bit bus:
• The NWE0 signal is used to select byte 0 for read and write operations.
• The NWE1 signal is used to select byte 1 for read and write operations.
• The NWR signal is used as the write enable signal for the memory block.
• The NSOE signal enables memory reads to the memory block.
Read Protocols T he S MC p rovi des two a lte rn ati ve pr otoc ols fo r e xte rnal mem or y read ac ce ss ; stand ar d
and earl y rea d. The difference b etwee n th e two p rotoc ol s l ies i n the tim ing of th e NS OE
(read cycle) waveform.
The pro tocol is selected by the DRP fi eld in the Me mory C ontrol Re gister (S MC_MCR)
and is valid for all memory devices. Standard read protocol is the default protocol after
reset.
Standard Read Protocol Standard read protocol implements a read cycle in which NSOE and the write strobes
are similar. Both are active during the second half of the clock cycle. The first half of the
clock cycl e allows tim e to ensur e completi on of the pr eviou s access, as well as the out-
put of address and NCE before the read cycle begins.
47
AT75C221 Preliminary
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During a standard read protocol external memory access, the chip enable signal sNCE0
to NCE3 are set low and the address lines are valid at the beginning of the access ,
whereas NSOE goes low on ly i n the secon d hal f of t he mas ter clock c ycle to av oid bus
conflict. The write strobes are the same in both protocols. The write strobes always go
low in the second half of the master clock cycle.
Early Read Protocol Early rea d pr oto col pr ov id es mor e tim e for a read ac c es s from the me mor y by as s ertin g
NSOE at the beginning of the clock cycle. I n the case of successive read cycles in the
same mem ory, NSOE rema ins active con tinuously. Si nce a read cyc le normally l imits
the speed of operation of the external memory system, ear ly read protocol allows a
faster clock fr equency to be used. However, an extra wait state is required i n some
cases to avoid contention on the external bus.
In early read protocol, an early read wait state is automatically inserted when an exter-
nal writ e cycle is foll owed by a read c ycle to allow time fo r the wri te cycl e to end before
the subsequent read cycle begins. This wait state is generated in addition to any other
programme d wait s tates (i.e ., data fl oat wait). No wait sta te is ad ded w hen a read c ycle
is followed by a write cycle, between consecutive accesses of the same type or between
external and internal memory accesses.
Write Protocol During a write cycle, the data becomes valid after the falling edge of the write strobe sig-
nal and r emai ns vali d after the ris ing e dge of t he wri te strob e. The externa l writ e strob e
waveform on the approp ri ate write str o be pin is use d to co ntrol the out put data timing to
guarantee this operation.
Thus, it is necessary to avoid excessive loading of the write strobe pins, which could
delay the write signal too long and cause a contention with a subsequent read cycle in
standar d protoco l. In early re ad protoco l, the data ca n remain valid long er than in st an-
dard read protocol due to the additional wait cycle that follows a write access.
Wa it States The SMC can automatically insert wait states. The different types of wait states are:
• Standard wait states
• Data float wait states
• Chip select change wait states
• Early read wait states, as described in “Early Read Protocol” above.
Standard Wait States Each chip select can be programmed to insert one or more wait states during an access
on the corresponding device. This is done by setting the WSE field in the corresponding
SMC_CSR. The number of cycles to insert is programmed in the NWS field in the same
register.
When no wait state is programmed (WSE = 0), the NWE signal lasts only one-half cycle.
If at least one wait state is programmed, the NWE signal lasts an integer number of
cycles, accordingly to the number of wait states programmed.
Data Float Wait States Some memory devic es a re slow to rel ease the ex ternal b us. For s uch de vices it is nec-
essary t o add wait states (da ta float wa its) after a read acc ess before s tarting a wr ite
access or a read access to a different external memory.
The Data Float Output Time (TDF) for each external memory device is programmed in
the TDF field of the SMC_CSR register for the corresponding chip select. The value (0 -
7 clock cycles) indicates the number of data float waits to be inserted and represents the
time allowed for the data output to go to high impedance after the memory is disabled.
The SMC keeps track of the programmed external data float time even when it makes
interna l acce sses to ens ure th at the exte rnal memo ry sy stem is no t acces sed while it is
still busy.
48 AT75C221 Preliminary 6033A–INTAP–03/04
Internal memory accesses and consecutive accesses to the same external memo ry do
not insert added data float wait states.
When data float wa it states are being used, the SMC prevents the SDRAM Contr oller
from accessing the external data bus.
Chip Select Change Wait
States A chip select wait state is automatically inserted when consecutive accesses are made
to two dif ferent exte rnal memor ies (if no wait st ates hav e already been i nserted) . If any
wait states have already been inserted (e.g., data float wait), then none are added.
Signal Waveforms Figure 20 on page 49 shows a write to memory 0 followed by a write and a read to mem-
ory 1. SMC_CSR0 is programmed for one wait state with BAT = 0 and TDF = 0.
SMC_CSR1 i s progr ammed fo r zero wai t states with BA T = 1 and T DF = 0. Early Rea d
Protoc ol is enabl ed.
The write to memory 0 is a word access and therefore all four NWE strobes are active.
As BAT = 0, they are configured as write strobes and have the same timing as NWR. As
the access employs a single wait state, the write strobe pulse is one clock cycle long.
There is a chip select change wait state between the memory 0 write and the memory 1
write. The new address is output at the end of the memory 0 access, but the strobes are
delayed for one clock cycle.
The write to memory 1 is a half-word access to an odd half-word address and, therefore,
NWE2 and NWE3 are active. As BAT = 1, they are configured as byte select signals and
have the same timing as NCE. As the access has no internal wait states, the write
strobe pu lse is one- half cl ock cycle long. Data and addr ess are driven unti l the write
strobe rising edge is sensed at the AT75C221 pin to guarantee positive hold times.
There is an early read wait state between memory 1 write and memory 1 read to provide
time for th e AT7 5C22 1 to d is able the output d ata b efore th e me mor y is re ad. If the r ea d
was norma l mode, i.e., not ear ly, the NSOE strobe w ould not fall unt il the risi ng edge of
ACLK and no wait state would be inserted. If the write and early read were to different
memories, then the early read wait state is not required as a chip select wait state will be
implemented.
The read from memory 1 is a byte access to an address with a byte offset of 2 and
therefore only NWE2 is active.
49
AT75C221 Preliminary
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Figure 20. Write to Memory 0, Write and Read to Memory 1
Figure 21 on page 50 shows a write and a read to memory 0 followed by a read and a
write to mem ory 1. SMC_CSR0 is programm ed for zero wai t states with BA T = 0 a nd
DFT = 0. SMC_CSR1 i s programmed for zero wa it states with BAT = 1 and DFT = 1.
SMC_MCR is programmed for normal reads from all memories.
The write to memory 0 is a byte access and, therefore, only one NWE strobe is active.
As BAT = 0, they are configured as write strobes and have the same timing as NWR.
The mem or y 0 re ad i mm edi atel y fol low s th e wr it e as ea rly re ads are n ot c onf igu re d an d
an early read wait state is not requir ed. As early reads are no t configured, the read
strobe pulse is one-half clock cycle long.
There is a chip select change wait state between the memory 0 write and the memory 1
read. The n ew a ddr es s is ou tput at t he end of the me mory 0 a cces s but t he str ob es are
delayed for one clock cycle.
The write to memory 1 is a half-word access to an odd half-word address and, therefore,
NWE2 and NWE3 are active. As BAT = 1, they are configured as byte select signals and
have the same timing as NCE.
As DFT = 1 for memory 1, a wait sta te is imple mented between the read and write to
provide time for the memory to stop driving the data bus. DFT wait states are only imple-
mented at the end of read accesses.
ACLK
NCE0
NCE1
A
NWR
NSOE
NWE0
NWE1
NWE2
NWE3
D out
D in
Internal Wait State Chip Select Wait State Early Read Wait State
50 AT75C221 Preliminary 6033A–INTAP–03/04
The read from memory 1 is a byte access to an address with a byte offset of 2 and,
therefore, only NWE2 is active.
Figure 21. Write and Read to Memory 0, Read and Write to Memory 1
ACLK
NCE0
NCE1
A
NWR
NSOE
NWE0
NWE1
NWE2
NWE3
D out
D in
Chip Select Wait State Data Float Wait State
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AT75C221 Preliminary
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SMC User Interface The me mor y c ont ro l re gister (SMC _MCR ) is u se d to pr ogram the n umb er o f active c hip
select s and data read protocol. Fou r chip sele ct regist ers (SMC_CS R0 to SMC_CS R3)
are used to program the parameters for the individual external memories. Each
SMC_CSR must be programmed with a different base address, ev en for unused chip
selects.
The SMC_CSR register resets according to the DBW32 pin.
During the boot sequence , the Chip Select Reg isters must be pr ogrammed as required
depend ing on the de vices conn ected on the external b us. The chip s elect addr esses
that are programmed take effect immediately. Wait states also take effect immediately
when they are programmed to optimize boot program execution.
Table 17. SMC Register Mapping
Offset Register Name Register Description Access Reset Value
0x00 SMC_CSR0 Chip Select Register Read/Write 0x0000203D
0x0000203E
0x04 SMC_CSR1 Chip Select Register Read/Write 0x10000000
0x08 SMC_CSR2 Chip Select Register Read/Write 0x20000000
0x0C SMC_CSR3 Chip Select Register Read/Write 0x30000000
0x10 – Reserved ––
0x14 – Reserved ––
0x18 – Reserved ––
0x1C – Reserved ––
0x20 – Reserved ––
0x24 SMC_MCR Memory Control Register Read/ Write 0x0
52 AT75C221 Preliminary 6033A–INTAP–03/04
SMC Chip Select Register
Register Name: SMC_CSR0..SMC_CSR3
Access: Read/Write
• DBW: Data Bus Width
• NWS: Number of Wait States
• WSE: Wait State Enable
• MWS: Multiply Wait States
•PAGES: Page Size
31 30 29 28 27 26 25 24
BA
23 22 21 20 19 18 17 16
BA ––––
15 14 13 12 11 10 9 8
– – CSEN BAT TDF PAGES
76543210
PAGES MWS WSE NWS DBW
DBW Data Bus Width
0 0Reserved
0 116-bit external bus
1 032-bit external bus
1 1Reserved
NWS WSE Wait States Number
MWS = 0 MWS = 1
X X X 0 0 0
0 0 0 1 1 8
0 0 1 1 2 16
0 1 0 1 3 24
0 1 1 1 4 32
1 0 0 1 5 40
1 0 1 1 6 48
1 1 0 1 7 56
1 1 1 1 8 64
PAGES Page Size Base Address
0 01M byte BA20-BA31
0 14M bytes BA22-BA31
1 016M bytes BA24-BA31
1 1Reserved –
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AT75C221 Preliminary
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• TDF: Data Float Output Time
• BAT: Byte Access Mode
0 = By te Write Mode
1= Byte Select Mode
• CSEN: Chip Select Enable
0 = Chip Select is disabled
1 = Chip Select is enabled
• BA: Bas e Address
This fi eld contai ns the h igh-ord er bits o f t he ba se add ress. If the page si ze is lar ger th an 1 M byte, the n the unuse d bits of
the base address are ignored by the SMC decoder.
SMC Memor y Control Register
Register Name: SMC_MCR
Access Type: Read/Write
• DRP: Data Read Protocol
0 =Standard Read Mode
1 =Early Read Mode
TDF Cycles after Transfer
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––DRP––––
54 AT75C221 Preliminary 6033A–INTAP–03/04
Ethernet MAC (EMAC )
The AT75C221 features two identical Ethernet MACs which both feature the following:
• Compatible with IEEE Standard 802.3
• 10 and 100 Mbits per Second Data Throughput Capability
• Full- and Half-d upl ex Operation
• Media Independent Interface to the Physical Layer
• Register Interface to Address, Status and Control Registers
• DMA Interface
• Interrupt Generation to Signal Receive and Transmit Completion
• 28-byte Transmit and 28-byte Receive FIFOs
• Automatic Pad and CRC Generation on Transmitted Frames
• Address Checking Logic to Recognize Four 48-bit Addresses
• Supports Promiscuous Mode Where All Valid Frames are Copied to Memory
• Supports Physical Layer Management through MDIO Interface
The Ethe rnet MA C is the h ardwar e i mpl em enta tio n of th e MA C su b-lay er OSI r efe renc e
model between the physical layer (PHY ) and t he lo gical link layer (LLC). It cont rols the
data e xcha nge bet ween a host and a P HY la yer acco rding to Etherne t IE EE 8 02.3 da ta
frame format. The Ethernet MAC contains the required logic and transmit and receive
FIFOs for DMA m anagement . In a ddition, it is in terfaced th rough MD IO/MDC pin s for
PHY layer management.
The Ethernet MAC transfers data in media-independent interface (MII).
Block Diagram Figure 22. Block Diagram
Ethernet MAC
Interrupt Control
APB Bridge
ACLK
EMAC IRQ
Mx_TXCLK, Mx_RXCLK
Mx_TXEN, Mx_TXER
Mx_CRS, Mx_COL
Mx_RXER, Mx_RXDV
Mx_RXD[3:0]
Mx_TXD[3:0]
DMA
APB
MAC
ASB
Mx_MDC
Mx_MDIO
55
AT75C221 Preliminary
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MEDIA Independent Interface.
Transmit/Receive
Operation A standard IEEE 802.3 packet consists of the following fields: preamble, start of frame
delimiter (SFD), d estination addr ess (D A), source address (SA ), length, data (Logica l
Link Control Data) and frame check sequence CRC32 (FCS).
Note: 1. Frame Length between 64 bytes and 1518 bytes.
The packets are Manchester-encoded and -decoded and transferred serially using NRZ
data with a cl oc k. All fie lds are of fi x ed l eng th e xcep t for th e da ta f iel d. Th e MA C g ene r-
ates and appends the preamble, SFD and CRC fields during transmission.
The preamble and SFD fields are stripped during reception.
Preamble and Start of Frame
Delimiter (SFD) The preamble field is used to acquire bit synchronization with an incoming packet. When
transmitte d, each pa cket contai ns 62 bits o f altern ating 1, 0 preambl e. Some o f this pre-
amble is lost as the packet travels through the network. Byte alignment is performed
with the Start of Frame Delimiter (SFD) pattern that consists of two consecutive 1's.
Destination Address (DA) The destination address (DA) indicates the destination of the packet on the network and
is used to filter unwanted packets. There are three types of address formats: physical,
multi cast and br oadcast. T he physica l address is a un ique addre ss that co rrespon ds
only to a single node. All physical addresses have an MSB of 0.
Multica st a ddres s es b egi n wit h an MS B o f 1. The MA C fil ter s mul tic as t ad dr esse s us in g
a standard hashing algor ithm that maps all multicast addresses into a 6-bit value. This
6-bit value indexes a 64-bit array that filters the value. If the address consists of all ones,
it is a broadcast address, indicating that the packet is intended for all nodes.
Source Address (SA) The source address (SA) is the physical address of the node that sent the packet.
Source addresses cannot be multicast or broadcast addresses. This field is passed to
buffer memory.
Table 18. P in Conf igu ra tio n
MII Signal Signal Name Pin Name EMAC A Pin Name EMA C B
Transmit Clock ETXCK MA_TXCLK MB_TXCLK
Carrier Sense ECRS MA_CRS MB_CRS
Collision Detect ECOL MA_COL MB_COL
Receive Data Valid ERXDV MA_RXDV MB_RXDV
4-bit Receive Data ERX0-ERX3 MA_RXD[0:3] MB_RXD[0:3]
Receive Error ERXER MA_RXER MB_RXER
Receive Clock ERXCK MA_RXCLK MB_RXCLK
Transmit Enable ETXEN MA_TXEN MB_TXEN
4-bit Trans m it Data ETX0-ETX3 MA_TXD[ 0:3] MB_TXD[0 :3]
Transmit Error ETXER MA_TXER MB_TXER
Table 19. Packet Format
Preamble Frame(1)
Alternating 1s/0 s SFD DA SA Length/type LLC Data PAD FCS
Up to 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 4 bytes
56 AT75C221 Preliminary 6033A–INTAP–03/04
Length/Type If the value of this field is less than or equal to 1500, then the Length/Type field indicates
the number of by tes in the subse quen t LLC D ata fiel d. If th e va lu e of this field i s grea ter
than or equal to 1536, then the Length/Ty pe field indicates the nature of the MA C clie nt
protocol (protocol type).
LLC Data T he dat a fi el d con si sts o f a ny wher e from 46 to 1500 bytes . Mes sages longer th an 150 0
bytes need to be b rok en into m ultipl e pa cke ts. Messag es shor ter t han 46 byte s req uire
appending a pad to bring the data fiel d to the minimum length of 46 b ytes. If the da ta
field is padded, the number of valid data bytes is indicated in the length field.
Frame Check Sequence Field
(FCS) The Frame Ch eck S equ enc e ( FCS ) is a 32 -b it CR C fie ld, ca lc ul ated and app end ed to a
packet during transmission to allow detection of errors when a packet is received. Dur-
ing reception, error free packets result in a specific pattern in the CRC generator.
Packets with improper CRC will be rejected.
Frame Format Extensions The original Ethernet standards define the minimum frame size as 64 bytes and the
maximum as 1518 byte s. These numbers inc lude all bytes from the Desti nation MAC
Addres s fiel d thr ou gh the Fra me Che ck Se que nc e fie ld. The Pr ea mbl e an d Sta rt Fram e
Delimiter fields are not inclu ded when q uoting the s ize of a fr ame. The IEEE 802 .3ac
standard ex tended the maximum al lowable frame size to 1522 bytes to allow a VLAN
tag to be i nserted into the Et hernet fr ame forma t. The BIG bit defined in the ETH_ CFG
register processes packets with a VLAN tag.
The V LAN protoc ol p ermits inse rtio n of an i denti fier, or t ag, i nto t he E thern et fram e fo r-
mat t o iden ti fy th e VLAN to whi ch the fr ame belo ngs. It allo ws f rame s fr om st ati ons t o be
assig ned to log ical grou ps. This provides various benefits , such as easin g network
adminis tr ation, a ll owi ng fo rmati on o f wor k gr oups , e nhan ci ng netwo rk s ecur ity, an d pr o-
viding a means of limiting broadcast domains (refer to IEEE standard 802.1Q for
definiti on of the VL AN prot ocol). The 8 02.3ac st anda rd defin es only t he implem enta tion
details of the VLAN protocol that are specific to Ethernet.
If pres ent, the 4-by te VLAN tag is insert ed into the Ethern et frame betw een the So urce
MAC Addres s fie ld and the Len gth f ield. Th e fi rst 2 by tes of the VL AN tag consi st of th e
“802.1Q Tag Type” and are always set to a value of 0x8100. The 0x8100 v alue is a
reserved Length/Type field assignment that indicates the presence of the VLAN tag, and
signals that the traditional Length/Type field can be found at an of fset of four bytes fur-
ther into the frame. The last two bytes of the VLAN tag contain the following information.
• The first three bits are a User Priority Field that may be used to assign a priority
level to the Ethernet frame.
• The following one bit is a Canonical Format Indicator (CFI) used in Ethernet frames
to indicate the presence of a Routing Information Field (RIF).
• The last twelve bits are the VLAN Identifier (VID) that uniquely identifies the VLAN
to which the Ethernet frame belongs.
With the addition of VLAN tagging, the 802.3ac standard permits the maximum length of
an Ether net fra me to be extend ed from 15 18 byte s to 152 2 byte s. Ta ble 20 o n pa ge 57
illustr a tes the f ormat of an Ethernet fra me t hat h as bee n “ tag ged” wi th a VL AN i den tifi er
according to the IEEE 802.3ac standard.
57
AT75C221 Preliminary
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DMA Operations Frame data is transferred to and from the Ethernet MAC via the DMA interface. All trans-
fers are 32-b it words an d may be s ingle ac cesse s or bu rsts o f two, th ree o r four words.
Burst accesses do not cross 16-byte boundaries.
The DMA c ontro lle r per fo rms four typ es of ope ra tio ns on the AS B bus . I n o rd er of prior-
ity, these operations are receive buffer manager read, receive buffer manager write,
transmit data DMA read and receive data DMA write.
Transmitter Mode Transmit frame data needs to be stored in contiguous memory locations. It does not
need to be word-aligned.
The transmit address register is written with the address of the first byte to be
transmitted.
Transmi t is initi ated by w riting the number o f bytes to transfer (length) to the trans mit
control register.
The transmit channel then reads data from memory 32 bits at a time and places them in
the transmit FIFO.
The transmit bloc k starts frame transmission when thr ee words have been loaded into
the FIFO.
The tran sm it a ddres s r eg ist er mu st be wri tte n bef or e the tra n sm it control regi st er. Wh il e
a frame i s being transm itte d, it is p os si bl e t o s et up o ne othe r fr am e f or tran sm is si on by
writing new values to the transmit address and control registers. Reading the transmit
address register returns the address of the buffer currently being accessed by the trans-
mit FIFO.
Reading the transmit control register returns the total number of bytes to be transmitted.
The BNQ bi t in the Transmit St atus Register ind icates whethe r another buffer ca n b e
safely queued. An interrupt is generated whenever this bit is set.
Frame a sse mbly s tart s by a dding pream ble and t he s tart frame d elim iter. D ata is ta ken
from the transmit FIFO word-by-word. If necessary, padding is added to make the frame
length 60 bytes. The CRC is calculated as a 32-bit pol ynomial. This is inverted and
appended to the end of the frame, making the frame length a minimum of 64 bytes. The
CRC is not appended if the NCRC bit is set in the transmit control register.
In full-duplex mode, frames are transmitted immediately. Back-to-back frames are trans-
mitted at least 96 bit times apart to guarantee the inter-frame gap.
Table 20. Ethernet Frame with VLAN Tagging
Preamble 7 bytes
Start Frame Delimiter 1 byte
Dest. MAC Address 6 bytes
Source MAC Address 6 bytes
Length/Type = 802.1Q Tag Type 2 byte
Tag Control Information 2 bytes
Length / Ty pe 2 bytes
MAC Client Data 0 - n bytes
Pad 0 - p bytes
Frame Check Sequence 4 bytes
58 AT75C221 Preliminary 6033A–INTAP–03/04
In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-
assert and then starts transmission after the inter-frame gap of 96 bit-times.
If the collision signal is asserted during transmission, the transmitter transmits a jam
sequence of 32 bits taken from the data register and then retries transmission after the
backoff time has elapsed . An error i s indicated and a ny further attempts aborted if 16
attempts cause collisions.
If transmit DMA underruns, bad CRC is automatically appended using the same mecha-
nism as jam insertion. Underrun also causes TXER to be asserted.
Receiver Mode When a packet is received, it is checked for valid preamble, CRC, alignment, length and
address. If all these criteria are met, the packet is stored successfully in a receive buffer.
If at the end of reception the CRC is bad, then the received buffer is recovered. Eac h
received frame including CRC is written to a single receive buffer.
Receive buffer s are word-aligned and are capable of containing 1518 or 1522 bytes
(BIG = 1 in ETH_CFG) of data (the maximum length of an Ethernet frame).
The st art loc ation for ea ch rec eive d frame is s tored in m emory i n a l ist o f recei ve bu ffer
descriptor s at a locat ion pointed to by the receive buffer queue poin ter register. Each
entry in the li st consis ts of two w ords. The first word is the a ddress of t he receive d
buffer; the se co nd i s th e r ecei ve s ta tus . Tabl e 21 defi ne s an entry in the r ecei ve d bu ffer
descriptor list.
To receive frames, the buffer queue must be initialized by writing an appropriate
address to bits [31:2] in the first word of each l ist entry. Bit zero of word zero mus t be
written with zero.
After a frame is received, bit zero becomes set and the second word indicates what
caused the frame to be copied t o memory. T he start l ocation of the received bu ffer
descriptor li st should be written to the received buffer queue pointer regist er before
recei ve is enab led (by setting the rece ive ena ble bit in the netw ork cont rol reg ister) . As
soon as the received block s tarts writing received frame data to the receive FIFO, the
received buffer manager reads the first receive buffer location pointed to by the received
buffer queue pointer register. If the filter block is active, the frame s hould be copied to
memory; the receive data DMA operation starts writing data into the receive buffer. If an
error occurs , th e buffer is recovered . If the fra me is received without error, the queu e
entry is updated. The buffer pointer is rewritten to memory with its low-o rder bit set to
indicat e succ essfu l frame rece ption and a used buffer . The next word is written wit h the
length of the frame and how the destination address was recognized. Th e next receive
buffer location is then read from the following word or, if the current buffer pointer had its
wrap bi t set, the beg innin g of th e table . The maxi mum n umber of buffer poin ters be fore
a wrap bit is seen is 1024. If a wrap bit is not seen by then, a wrap bit is assumed in that
entry. The received buffer queue pointer register must be written with zero in its lower-
order bit positions to enable the wrap function to work correctly.
If bit zero is set when the receive buffer manager read s the location of the receive
buffer, then the buffer has already been used and cannot be used again until software
has processe d the frame and cl eared bit zero. In this case, the DMA block sets the
buffer un av ailabl e b it i n th e rec ei ved s tatu s register and tr i gge rs an in ter rupt. Th e fram e
is discarded and the queue entry is reread on reception of the next frame to see if the
buffer is now available. Each discarded frame increments a statistics register that is
cleared on being read. When there is network congestion, it is possible for the MAC to
be programmed to apply back pressure.
This is when half-d uplex mode collisions are forced on all received frames by transmit-
ting 64 bits of data (a default pattern).
59
AT75C221 Preliminary
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Reading the received buffer queue register returns the location of th e queue entry cur-
rently being accessed. The queue wraps around to the start after either 1024 entries
(i.e., 2048 words) or when the wrap bit is found to be set in bit 1 of the first word of an
entry.
Address Checking Whether or not a frame is stored dep ends on what is enabled in the netwo rk configura-
tion reg ister, the con tents of the spec ific address and hash registers and the frame
destinat ion ad dr ess. In this i mpl eme ntat ion o f th e M AC the fr am e source ad dres s is n ot
checked.
A frame is not copied to me mory if the MAC is transmitting in half-duplex mode at the
time a destination address is received.
The hash register is 64 bits long and takes up two locations in the memory map.
There are four 48-bit specific address registers, each taking up two memory locations.
The first location contains the first four bytes of the address; the second location con-
tains the last two bytes of the address stored in its least significant byte positions. The
addresses stored can be specific, group, local or universal.
Ethernet frames are transmitted a byte at a time, LSB first. The first bit (i.e., the LSB of
the first byte) of the destination address is the group/individual bit and is set one for mul-
ticast addresses and zero for unicast. This bit corresponds to bit 24 of the first word of
Table 21. Received Buffer Descriptor List
Bit Function
Word 0
31:2 Base address of receive buffer
1 Wrap bit. If this bit is set, the counter that is ORed with the received buffer queue
pointer register to give the pointe r to entries in this tab le is cleared a fter the b uff er is
used.
0 Ownership bit. 1 indicates software owns the pointer, 0 indicates that the DMA
owns the buffer. If this bit is not zero when the entry is read by the receiver, the
buffer unavailable bit is set in the received status register and the receiver goes
inactive.
Word 1
31 Global all ones broadcast address detected
30 Multicast hash match
29 Unicast hash match
28 Exter n al address
27 Unknown source address (reserved for future use)
26 Local address match (Specific address 1 match)
25 Local address match (Specific address 2 match)
24 Local address match (Specific address 3 match)
23 Local address match (Specific address 4 match)
22:11 Reserved; written to 0
10:0 Length of frame including FCS
60 AT75C221 Preliminary 6033A–INTAP–03/04
the speci fic add re ss re gi ste r. The MSB of the f irst byte of the de sti na tio n addr e ss corr e-
sponds to bit 31 of the specific address register.
The specif ic address registers are compared to the destination address of received
frames once they have been ac tiva ted. Ad dresses are dea ct ivated at rese t or whe n the
first byte [47:40] is written and activated or when the last byte [7:0] is written. If a receive
frame addr ess matches a n active ad dress, the loc al match sign al is set and the store
frame pulse signal is sent to the DMA block via the ACLK synchronization block.
A frame can also be copied if a unicast or multicast hash match occurs, it has the broad-
cast address of all ones, or the copy all frames bit in the network configuration register is
set.
The broadcast address of 0xFFFFFFFF is recognized if the no broadcast bit in the n et-
work configuration register is zero. This sets the broadcast match signal and triggers the
store frame signal.
The unicast hash enable and the multicast hash enable bits in the network configuration
register enab le the reception of hash matc hed frames. So all mul ticast frames can be
received by setting all bits in the hash register.
The CRC algorithm r educes the des tination address to a 6-bit index into a 64-bit hash
registe r.If the equival ent bit in the regi ster is set, the fra me is matched de pending on
whether the frame is mu lticas t or unicast and the approp riate matc h signal s are sent to
the DMA b lock . If th e cop y all fr ames bi t is set in the net work configur ation regist er, th e
store frame pulse is always sent to the DMA block as soon as any destination address is
received .
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AT75C221 Preliminary
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EMAC User Interface
MACA Memory Address: 0xFF034000
MACB Memory Address: 0xFF038000
Note: 1. For further details on the statistics registers, see Table 23, “Statistics Register Block,” on page 75.
Table 22. Ethernet MAC Register Mapping
Of fset Regi ster Name Register Description Read/Write Reset
0x00 ETH_CTL Network Control Register Read/Write 0x0
0x04 ETH_CFG Network Configuration Register Read/Write 0x800
0x08 ETH_SR Network Status Register Read-only 0x6
0x0C ETH_TAR Transmit Address Register Read/Write 0x0
0x10 ETH_TCR Transmit Control Register R ead/Write 0x0
0x14 ETH_TSR Transmit Status Register Read/Write 0x18
0x18 ETH_RBQP Receive Buff er Queue Pointer Read/Write 0x0
0x1C – Reserved Read-only 0x0
0x20 ETH_RSR Receive Statu s Regis te r Read/Write 0x0
0x24 ETH_ISR Interrupt Status Register Read/Write 0x0
0x28 ETH_IER Interrupt Enable Register Write-only –
0x2C ETH_IDR Interrupt Disable Regi ster Write-only –
0x30 ETH_IMR Interrupt Mask Register Read-only 0xFFF
0x34 ETH_MAN PHY Maintenance Register Read/Write 0x0
Statistics Registers(1)
0x40 ETH_FRA Frames Transmitted OK Register Read/Write 0x0
0x44 ETH_SCOL Single Collision Frame Register Read/Write 0x0
0x48 ETH_MCOL Multiple Collision Frame Register Read/Write 0x0
0x4C ETH_OK Frames Received OK Register Read/Write 0x0
0x50 ETH_SEQE Frame Ch eck Sequence Error Register Read/Write 0x0
0x54 ETH_ALE Alignment Error Re gister Read/Write 0x0
0x58 ETH_DTE Deferred Transmission Frame Register Read/Write 0x0
0x5C ETH_LCOL Late Coll isi on Register Read/Write 0x0
0x60 ETH_ECOL Excessive Collision Register Read/Write 0x0
0x64 ETH_CSE Carrier Sense Error Register Read/Write 0x0
0x68 ETH_TUE Transmi t Underrun Error Register Read/Write 0x0
0x6C ETH_CDE Code Error Register Read/Write 0x0
0x70 ETH_ELR Excessive Length Error Register Read/Write 0x0
0x74 ETH_RJB Receiv e Jabber Regis ter Read /Write 0x0
0x78 ETH_USF Undersize Frame Register Read/Write 0x0
0x7C ETH_SQEE SQE Test Error Register Read/Write 0x0
0x80 ETH_DRFC Discarded RX Frame Register Read/Write 0x0
Address Registers
0x 90 ET H_HSH Hash Address High [63:32] Read/Write 0x0
0x94 ETH_HSL Hash Address Low [31:0] Read/Write 0x0
0x 98 ET H_SA1L Specific Address 1 Low, First 4 Bytes Read/Wri te 0x0
0x9C E TH_SA1H S pecific Addr ess 1 High, La st 2 Bytes Read/Write 0x0
0xA0 ETH_SA2L Specific Address 2 Low, First 4 Bytes Read/Write 0x0
0xA4 ETH_SA2H Specific Addres s 2 High, Last 2 Bytes Read/Write 0x0
0xA8 ETH_SA3L Specific Address 3 Low, First 4 Bytes Read/Write 0x0
0xAC ETH_SA3H Specif ic Addr ess 3 High, La st 2 Bytes Read/Write 0x0
0xB0 ETH_SA4L Specific Address 4 Low, First 4 Bytes Read/Write 0x0
0xB4 ETH_SA4H Specific Addres s 4 High, Last 2 Bytes Read/Write 0x0
62 AT75C221 Preliminary 6033A–INTAP–03/04
EMAC Control Register
Register Name: ETH_CTL
Access Type: Read/Write
• LB: Loopback
. When set, loopback signal is at high level.
• LBL: Loopback Local
When set, connects ET X[3:0] to ERX[3:0], ET XEN to ERXDV, forces full duplex and dr ives ERXCK and ETXCK_REFCK
with ACK divided by 4.
• RE: Receive Enable
When set, enables the Ethernet MAC to receive data.
• TE: Transmit Enable
When set, enables the Ethernet transmitter to send data.
• MPE: Management Port Enable
Set to one to enable the management port. When zero, forces MDIO to high impedance state.
• CSR: Clear Statistics Registers
This bit is write-only. Writing a one clears the statistics registers.
• ISR: Increment Statistics Registers
This bit is write-only. Writing a one increments all the statistics registers by one for test purposes.
• WES: Write Enable for Statistics Registers
Setting this bit to one makes the statistics registers writable for functional test purposes.
• BP: Back Pressu re
If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (default
pattern).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––BP
76543210
WES ISR CSR MPE TE RE LBL LB
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EMAC Mode Register
Name: ETH_CFG
Access Type: Read/Write
• SPD : Speed
Set to 1 to indicate 100 Mbit/sec, 0 for 10 Mbit/sec. Has no other functional effect.
• FD: Full Duplex
If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting.
• BR: Bit Rate
• CAF: Copy All Frames
When set to 1, all valid frames are receiv ed.
• NBC: No Broadcast
When set to 1, frames addressed to the broadcast address of all ones are not received.
• MTI: Multicast Hash Enable
When set multica st frame s are re ceived when six b its of the C RC of t he dest inatio n addr ess p oint to a bit tha t is set i n the
hash regist e r.
• UNI: Unicast Hash Enable
When set, unicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the
hash regist e r.
• BIG: Receive 1522 Bytes
When set, the MAC receives up to 1522 bytes. Normally the MAC receives frames up to 1518 bytes in length.
This bit allows to receive extended Ethernet frame with “VLAN tag” (IEEE 802.3ac)
• EAE: External Address Match Enable
•CLK
The ARM clock is divi ded down to ge nerate MDC (th e clock for the MDIO). To c onfor m with IEEE standard 802.3 MDC
must not exceed 2.5 MHz. At reset this field is set to 10 so that ACK is divided by 32.
• RTY: Retry Test
When set, the time between frames is always one time slot. For test purposes only. Must be cleared for normal operation.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RTY CLK EAE BIG
76543210
UNI MTI NBC CAF – BR FD SPD
CLK MDC
00 ACK divided by 8
01 ACK divided by 16
10 ACK divided by 32
11 ACK divided by 64
64 AT75C221 Preliminary 6033A–INTAP–03/04
EMAC Status Register
Name: ETH_SR
Access Type: Read-only
•LINK
0 = LINK is at 0.
1 = LINK is at 1.
•MDIO
0 = MDIO pin not set.
1 = MDIO pin set.
•IDLE
0 = PHY logic is idle.
1 = PHY logic is running.
EMAC Transmit Address Register
Name: ETH_TAR
Access Type: Read/Write
• ADDRESS: Transmit Address Register
Written with the address of the frame to be transmitted, read as the base address of the buffer being accessed b y the tr ans-
mit FIFO. Note that if the two least significant bits are not zero, transmit starts at the byte indicated.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––IDLEMDIOLINK
31 30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
76543210
ADDRESS
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EMAC Transmit Control Register
Name: ETH_TCR
Access Type: Read/Write
• LEN: Transmit Frame Len gth
This registe r is wri tten to the number of bytes to be transmitte d excludi ng the four CRC bytes unless the no CRC bit is
asserted. Writing these bits to any non-zero value initiates a transmission. If the v alue is greater than 1514 (1518 if no CRC
is being generated), an oversize frame is transmitted. This field is buffered so that a new frame can be queued while the
previous frame is still being transmitted. Must always be written in address-then-length order. Reads as the total number of
bytes to be transmitted (i.e., this value does not change as the frame is transmitted.) F rame transmission does not start until
two 32- bit words have been loaded into the transmit FIFO. The length must be great enough to ensure two words are
loaded.
• NCRC: No CRC
If this bit is set, it is assumed that the CRC is included in the length being written in the low-order bits and the MA C does not
append CRC to th e transmitted frame. If the buffer is not a t l ea st 64 bytes long , a s hort frame is sent. This fie ld is buffered
so that a new frame can be queued while the previous frame is still being transmitted. Reads as the value of the frame cur-
rently being transmi tted .
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
NCRC – – – – LEN
76543210
LEN
66 AT75C221 Preliminary 6033A–INTAP–03/04
EMAC Transmit Status Registe r
Name: ETH_TSR
Access Type: Read/Write
• OVR: Ethernet Transmit Buffer Overrun
Software has written to the Tran sm it A ddres s Regi ste r (ETH_ TAR) or Transmi t Control Register (E TH_T CR) when bit BNQ
was not set. Cleared by writing a one to this bit.
• COL: Collision Occurred
Set by the assertion of a collision. Cleared by writing a one to this bit.
• RLE: Retry Limit Exceeded
Cleared by writing a one to this bit.
• IDLE: Transmitter Idle
Asserted when the transmitter has no frame to transmit. Cleared when a length is written to transmit frame length portion of
the Transmit Control register. This bit is read-only.
• BNQ: Ethernet Transmit Buffer not Queued
Software may write a new buff er address and length to the transmit DMA controller when set. Cleared by having one frame
ready to transmit and another in the process of being transmitted. This bit is read-only.
• COMP: Transmit Complete
Set when a frame has been transmitted. Cleared by writing a one to this bit.
• UND: Transmit Underrun
Set when transmit DMA was not able to read data from memory in time. If this happens, the transmitter forces bad CRC.
Cleared by writing a one to this bit.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– UND COMP BNQ IDLE RLE COL OVR
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EMAC Receiv e Buf fer Queue P o inter Re gist e r
Name: ETH_RBQP
Access Type: Read/Write
• ADDRESS: Receive Buffer Queue Pointer
Wri tten wi th the ad dress o f the sta rt of the re ceive queue, reads as a poin ter to t he curr ent buffe r bei ng use d. The re ceive
buffer is forced to word alignment.
EMAC Receive Status Register
Name: ETH_RSR
Access Type: Read/Write
• BNA: Buffer Not Available
An attem pt wa s made to get a new buffer and the poi nter indi cated that it was owned by the processo r. T he DMA rereads
the pointer each tim e a new frame star ts until a valid point er is found. This bit is set at ea ch attem pt that fai ls even if it has
not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit.
• REC: Frame Receive d
One or more frames have been received and placed in memory. Cleared by writing a one to this bit.
• OVR: RX Overrun
The DMA block was unable to store the receiv e frame to memory, either because the MAC ASB bus was not granted in time
or because an abort occurred. The buffer is recovered if this happens. Cleared by writing a one to this bit.
31 30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
76543210
ADDRESS
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––OVRRECBNA
68 AT75C221 Preliminary 6033A–INTAP–03/04
EMAC Interrupt Status Register
Name: ETH_ISR
Access Type: Read/Write
• DONE: Management Done
The PHY maintenance register has completed its operation. Cleared on read.
• RCOM: Receive Complete
A frame has been stored in memory. Cleared on read.
• RBNA: Receive Buffer Not Available
Cleared on read.
• TOVR: Transmit Buffer Overrun
Software has w ri tten to th e Transmit Addr ess R egiste r (ETH_TAR ) or Transm it Contr ol Regis ter (ETH_T CR) wh en BNQ of
the Transmit Status Register (ETH_TSR) was not set. Cleared on read.
• TUND: Transmit Buffer Underrun
Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted.
Cleared on read.
• RTRY: Retry Limit
Retry limit exceeded. Cleared on read.
• TBRE: Transmit Buffer Register Empty
Software may write a new buffer addres s and len gth to the tran smit DM A control ler. Clear ed by having one frame ready to
transmit and another in the process of being transmitted. Cleared on read.
• TCOM: Transmit Complete
Set when a frame has been transmitted. Cleared on read.
• TIDLE: Transmit Idle
Set when all frames have been transmitted. Cleared on read.
•LINK
Set when LINK pin changes value.
•ROVR: RX Overrun
Set when the RX overrun status bit is set. Cleared on read.
• ABT: Abor t
Set when the DMA generates an Abort. Cleared on read.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – ABT ROVR LINK TIDLE
76543210
TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE
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EMAC Interrupt Enable Register
Name: ETH_IER
Access Type: Write-only
• DONE: Management Done Interrupt Enab le
• RCOM: Receive Complete Interrupt Enable
• RBNA: Receive Buffer Not Available Interrupt Enable
• TOVR: Transmit Buffer Overrun Interrupt Enable
• TUND: Transmit Buffer Underrun Interrupt Enable
• RTRY: Retry Limit Interrupt Enable
• TBRE: Transmit Buffer Register Empty Interrupt Enable
• TCOM: Transmit Complete Interrupt Enable
• TIDLE: Transmit Idle Interrupt Enable
• LINK: LINK Interrupt Enable
• ROVR: RX Overrun Interrupt Enable
• ABT: Abort Interrupt Enable
0 =No effect.
1 =Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – ABT ROVR LINK TIDLE
76543210
TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE
70 AT75C221 Preliminary 6033A–INTAP–03/04
EMAC Interrupt Disable Register
Name: ETH_IDR
Access Type: Write-only
• DONE: Management Done Interrupt Disab le
• RCOM: Receive Complete Interrupt Disable
• RBNA: Receive Buffer Not Available Interrupt Disable
• TOVR: Transmit Buffer Overrun Interrupt Disable
• TUND: Transmit Buffer Underrun Interrupt Disable
• RTRY: Retry Limit Interrupt Disable
• TBRE: Transmit Buffer Register Empty Interrupt Disable
• TCOM: Transmit Complete Interrupt Disable
• TIDLE: Transmit Idle Interrupt Disable
• LINK: LINK Interrupt Disable
• ROVR: RX Overrun Inte rrupt Disable
• ABT: Abort Interrupt Disable
0 =No effect.
1 =Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – ABT ROVR LINK TIDLE
76543210
TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE
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EMAC Interrupt Mask Register
Name: ETH_IMR
Access Type: Read-only
• DONE: Management Done Interrupt Mask
• RCOM: Receive Complete Interrupt Mask
• RBNA: Receive Buffer Not Available Interrupt Mask
• TOVR: Transmit Buffer Overrun Interrupt Mask
• TUND: Transmit Buffer Underrun Interrupt Mask
• RTRY: Retry Limit Interrupt Mask
• TBRE: Transmit Buffer Register Empty Interrupt Mask
• TCOM: Transmit Complete Interrupt Mask
• TIDLE: Transmit Idle Interrupt Mask
• LINK: LINK Interrupt Mask
• ROVR: RX Overrun Inte rrupt Mask
• ABT: Abort Interrupt Mask
0 =The corresponding interrupt is enabled.
1 =The corresponding interrupt is not enabled.
Important Note: T he inte rr u pt i s dis abled when the c or res pond in g bi t is se t. This is no n- sta nda rd with other peripherals of
the product, as generally a mask bit set enables the interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – ABT ROVR LINK TIDLE
76543210
TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE
72 AT75C221 Preliminary 6033A–INTAP–03/04
EMAC PHY Maintenance Register
Name: ETH_MAN
Access Type: Read/Write
Wri ting to this reg ister s tar ts the sh ift re gister th at cont rols the ser ial conne ction to the PHY. On each s hift cyc le the MDIO
pin becomes equal to the MSB of the shift register and LSB of the shift register becomes equal to the value of the MDIO
pin. When the shifting is complete an interrupt is generated and the IDLE field is set in the Network Status register.
When read, gives current shifted value.
•DATA
For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read
from the PHY.
•CODE
Must be written to 10 in accordance with IEEE standard 802.3. Reads as written.
•REGA
Register address. Specifies the register in the PHY to access.
•PHYA
PHY address. Normally is 0.
•RW
Read/Write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame.
•HIGH
Must be written with 1 to make a valid PHY management frame. Conforms with IEEE standard 802.3.
•LOW
Must be written with 0 to make a valid PHY management frame. Conforms with IEEE standard 802.3.
31 30 29 28 27 26 25 24
LOW HIGH RW PHYA
23 22 21 20 19 18 17 16
PHYA REGA CODE
15 14 13 12 11 10 9 8
DATA
76543210
DATA
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AT75C221 Preliminary
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EMAC Hash Address High Regis ter
Register Name: ETH_HSH
Access Type: Read/Write
• ADDR
Hash address bits 63 to 32.
EMAC Hash Address Low Register
Register Name: ETH_HSL
Access Type: Read/Write
• ADDR
Hash address bits 31 to 0.
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR
74 AT75C221 Preliminary 6033A–INTAP–03/04
EMAC Specific Address (1, 2, 3 and 4) High Register
Register Name: ETH_SA1H,...ETH_SA4H
Access Type: Read/Write
• ADDR
Unicast addresses (1, 2, 3 and 4), Bits 47:32.
EMAC Specific Address (1, 2, 3 and 4) Low Register
Register Name: ETH_SA1L,...ETH_SA4L
Access Type: Read/Write
• ADDR
Unicast addresses (1, 2, 3 and 4), Bits 31:0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR
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AT75C221 Preliminary
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EMAC Statistics Register
Block Registers These r egist ers reset t o zer o on a r ead an d remai n at a ll o nes wh en the y co unt to their
maximum value. They should be read frequently enough to prevent loss of data.
The statistics register block contains the registers found in Table 22, “Ethernet MAC
Register Mapping,” on page 61.
Table 23. S tati st ics Regi st er Bloc k
Register Register Name Description
Frames Transmitted OK Register ETH_FRA A 24-bit register counting the number of frames successfully transmitted.
Single Collision Frame Register ETH_SCOL A 16-bit register counting the number of frames experiencing a single collision
before being transmitted and experiencing no carrier loss nor underrun.
Multiple Collision Frame Register ETH_MCOL A 16-bit register counting the number of frames experiencing between two and
fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no
underrun).
Frames Rece ived OK Register ETH_OK A 24-bit register counting the number of good frames received, i.e., address
reco gniz ed. A good fram e is of le ngth 6 4 to 1 518 b y tes a nd has no F CS , ali gnme nt
or code errors.
Frame Check Sequence Error
Register ETH_SEQE An 8-bit register counting address-recognized frames that are an integral number
of bytes long, that have bad CRC and that are 64 to 1518 bytes long.
Alignment Error Register ETH_ALE An 8-bit register counting frames that:
- are address-recognized,
- are not an integral number of bytes long,
- have bad CRC when their length is truncated to an integral number of byte s,
- are between 64 and 1518 bytes long.
Def e rred Transmissio n Fram e
Register ETH_D TE A 16-bit regist er counting th e num ber of fra mes e xperiencin g def erra l due to carrier
sense active on their first attempt at transmission (no underrun or collision).
Late Collision Reg ister ETH_LCO L A n 8-bit register c ounting the number o f frames t hat e xperience a coll ision after the
slot time (512 bits) has expired. No carrier loss or underrun. A late collision is
counted twice, i.e., both as a collision and a late collision.
Excessive Collision Register ETH_ECOL An 8-bit register counting the number of frames that failed to be transmitted
because they experienced 16 collisions (64 - 1518 bytes, no carrier loss or
underrun).
Carrier Sense Error Register ETH_CSE An 8-bit register counting the number of frames for which carrier sense was not
detected and that were maintained in half-duplex mode one slot time (512 bits)
after the start of transmission (no excessive collision).
Transmit Underrun Error Register ETH_TUE An 8-bit register counting the number of frames not transmitted du e to a transmit
DMA underrun. If this register is incremented, then no other register is
incremented.
Code Error Register ETH_CDE An 8-bit register counting the number of frames that are address-recognized, had
RXER asserted during reception. If this counter is incremented, then no other
counters are incremented.
Excessive Length Error Register ETH_ELR An 8-bit register counting the number of frames received exceeding 1518 bytes in
length but that do not have either a CRC error, an alignment error or a c o de error.
Receive Jabber Register ETH_RJB An 8-bit register counting the number of frames received ex ceeding 1518 bytes in
length and having either a CRC error, an alignment error or a code error.
Undersize Frame Register ETH_USF An 8-bit register counting the number of frames received less that are than 64
bytes in length but that do not have either a CRC error, an alignment error or a
code error.
SQE Test Error Register ETH_SQEE An 8- bi t re gi ste r c ou nting the number of frames where pi n ECO L w as not as s erted
within a slot time of pin ETXEN being deasserted.
Discarded RX Frame Register ETH_DRFC This 16-bit counter is incremented every time an address-recognized frame is
received but cannot be copied to memory because the receive buffer is available.
76 AT75C221 Preliminary 6033A–INTAP–03/04
Advanced Interrupt Controller (AIC)
The AT75C221 integrates the Atmel advanced interrupt controller (AIC).
The interrup t controller is connected to the fast interrupt request ( nFIQ) and the stan-
dard i nterrupt reques t (NIRQ) inp uts of the AR M7TDMI proces sor. The p rocessor ’s
nFIQ line c an onl y be as serted by th e exter nal fa st inte rrupt r equest input ( FIQ). The
nIRQ line can b e asserted b y the interrupts gene rated by the on-chip periphe rals and
the two external interrupt request lines, IRQ0 to IRQ1.
An 8-le vel priorit y encoder allo ws the user to defin e the priority be tween the diff erent
interrupt sourc es. Internal sources are programmed to be level-sens itive or edge-trig-
gered. Ex ternal so urces can be progr amm ed to be posi tive- or neg ative- edge tr iggere d
or high- or low-level sensitive.
Figure 23. Advanced Interrupt Controller Block Diagram
Control
Logic
Memorization
Memorization Prioritization
Controller NIRQ
Manager
NFIQ
Manager
FIQ Source
Advanced Peripheral Bus
(APB)
ARM7TDMI
Core
NFIQ
NIRQ
Internal Interrupt Sources
External Interrupt Sources
Table 24. Interrupt Sources
Interrupt Source Interrupt Name Interrupt Description
0 FIQ Fast Interrupt (LOWP)
1--
2 SWI Software Interrupt
3 UARTA UART A Interrupt
4 TC0 Timer Channel 0 Interrupt
5 TC1 Timer Channel 1 Interrupt
6 TC2 Timer Channel 2 Interrupt
7 PIOA PIO A Interrupt
8 MACA MAC A Interrupt
9 SPI Serial Peripheral Interface
10 IRQ0 External Interrupt
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Priority Controller The nIRQ line is controlled by an 8-level priority encoder. Each source has a program-
mable priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest.
When the AIC receives more than one unmasked interrupt at a time, the interrupt with
the highes t priority is ser viced fi rst. If both i nterrupts have equ al priority, the i nterrupt
with the lowest interrupt source number is serviced first.
The current priority level is defined as the priority level of the current interrupt at the time
the register AIC_IVR is read (the interrupt which wil l be serviced). In the case when a
higher priority unmasked interrupt occurs while an interrupt already exists, there are two
possible outcomes depending on whether the AIC_IVR has been read.
1. If the nIRQ line has been asserted but the AIC_IVR has no t been read , then the
processor will read the new higher priority interrupt handler number in the
AIC_IVR re gis te r and the curr en t inter r upt level is update d.
2. If the process or has alrea dy rea d the AI C_IVR, then the nIRQ line is reas serted.
When the processor has authorized nested interrupts to occur and reads the
AIC_IVR a gai n, i t r ead s th e new, higher prior ity in terrupt han dle r a ddres s. At th e
same time the current priority value is pushed onto a first-in last-out stack and
the current priority is updated to the higher priority.
When the End of Interrupt Command Register (AIC_EOICR) is written, the current inter-
rupt level is updated with the current interrupt level from the stack (if any). Hence, at the
end of a higher priority interrupt, the AIC returns to the previous state corresponding to
the preceding lower priority interrupt which had been interrupted.
Interrupt Handling The interrupt handler must r ead the AIC_IVR as soon as possible. This deasserts the
nIRQ request to the processor and clears the interrupt in case it is programmed to be
edge-triggered. This permits the AIC to assert the nIRQ line again when a higher priority
unmasked interrupt occurs.
At the end of the interrupt service routine, the End of Interrupt Command Register
(AIC_EOICR) must be written. This allows pending interrupts to be serviced.
Interrupt Masking Each interrupt sou rce, includi ng FIQ, can be enabled o r disable d using the c ommand
regi sters AIC _IECR an d AIC_I DCR. Th e interru pt mask c an be rea d in the read only
register AIC_IMR. A disabled interrupt does not affect the servicing of other interrupts.
Interrupt Clearing and Setting All interrupt sources which are programmed to be edge-triggered (including FIQ) can be
individually set or cleared by respectively writing to the registers AIC_ISCR and
AIC_ICCR. This function of the interrupt controller is available for auto-test or software
debug purpo se s.
11 IRQ1 External Interrupt
12 OAKA OAK Semaphore Interrupt
13 MACB MAC B Interrupt
14 UARTB UART B Interrupt
15 PIOB PIO B Interrupt
16 - 31 Re served
Table 24. Interrupt Sources (Continued)
Interrupt Source Interrupt Name Interrupt Description
78 AT75C221 Preliminary 6033A–INTAP–03/04
Standard Interrupt
Sequence It is assumed that:
• The advanced interrupt controller has been programmed, AIC_SVR registers are
loaded with corresponding interrupt service routine addresses and interrupts are
enabled.
When nIRQ is asserted and if the I bit of CPSR is 0, the sequence is as follows:
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is
loaded in the IRQ link register (R14_IRQ) and the Program Counter (R15) is
loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM
core adjusts R14_IRQ, decrementing it by 4.
2. The ARM core enters IRQ mode if it is not already.
3. When the instruction at 0x18 is executed, the Program Counter is loaded with
the value read in the AIC_IVR. Reading the AIC_IVR has the following effects:
Sets the current interrupt to be the pending one with the highest priority. The current
leve l is the priori ty lev el of the curren t inter r upt.
De-asserts the nIRQ line on the processor (even if vectoring is not used, AIC_IVR
must be read in order to de-assert nIRQ).
Automatically clears the interrupt if it has been programmed to be edge-triggered.
Pushes the current level on to the stack.
Returns the AIC_ SV R corr esponding to the curren t interr upt.
4. The previous step establishes a connection to the corresponding ISR. This
begins by saving the link register (R14_IRQ) and the SPSR (SPSR_IRQ). Note
that the link register must be decremented by 4 when it is saved if it is to be
restored directly into the Program Counter at the end of the interrupt.
5. Further interrupts can then be unmasked by clearing the I bit in the CPSR, allow-
ing re-assertion of the nIRQ to be taken into account by the core. This can occur
if an interrupt with a higher priority than the current one occurs.
6. The inte rru pt handler then pr oceeds as requi red, saving the regis ters which are
used and restoring them at the end. During this phase, an interrupt of priority
higher than the current le vel will restart the sequence from step 1. Note that if the
interr u pt i s p ro grammed to be leve l- se ns iti ve, the source of the inter rupt must b e
cleared during this phase.
7. The I bit in the CPSR must be set in order to mask interrupts before exiting to
ensure that the interrupt is completed in an orderly manner.
8. The service routine should then connect to the common exit routine.
9. The End Of Interru pt Command Re gister (AIC_E OICR) must be wr itten in order
to indicate to the AIC that the current interrupt is finished. This causes the cur-
rent level to be popped fro m the stack, restor in g the previous cur rent level if one
exists. If another interr upt w ith lower or equ al priority tha n the ol d c urre nt l evel is
pending, the nIRQ lin e is re-a ss ert ed but the interrupt seque nc e doe s no t im me-
diately start because the I bit is set in the core.
10. T he SP S R (SPS R_IRQ ) is resto re d. Fina ll y, the saved value of the Lin k Reg ister
is res tor ed di rectl y in to the PC. This ha s the effect of r etu rnin g from the interr upt
to the ste p previously executed, o f loading th e CPSR with the s tored SPSR an d
of masking or unmasking the interrupts depending on the state saved in the
SPSR (the previous st ate of the ARM core).
Note: The I bit in the SPSR is significant. If it is set, it indicates that the ARM core was just
about to mask IRQ interrupts when the mask instruction was interrupted. Hence, when
the SPSR is restored, the mask instruction is comp leted (IRQ is masked).
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AT75C221 Preliminary
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Fast Interrupt The external FIQ line is the only source which can raise a fast interrupt request to the
processor. Therefore it has no priority controller. It can be programmed to be positive- or
negative-edge triggered or high- or low-level sensitive in the AIC_SMR0 register.
The fast interrupt handler address can be stored in the AIC_SVR0 register. The value
written into this register is available by reading the AIC_FVR register when an FIQ inter-
rupt is raised. By storing the following instruction at address 0x0000001C, the processor
will lo ad the prog ram count er with the interrupt handler ad dress sto red in the AI C_FVR
register.
LDR PC, [PC, #-&F20]
Alternatively, the interrupt handler can be stored starting from address 0x0000001C as
described in the ARM7TDMI datasheet.
Fas t Interrupt Sequence It is assumed that:
• The advanced interrupt controller has been programmed, AIC_SVR[0] is loaded
with the fast interrupt service routine address and the fast interrupt is enabled.
• Nested fast interrupts are not needed by the user.
When nFIQ is asserted, if the F bit of CPSR is 0, the sequence is:
1. The CPSR is stored in SPSR_fiq, the current value of the Program Counter is
loaded in the FIQ link register (R14_FIQ) and the Program Counter (R15) is
loaded with 0x1C. In the foll owing cycl e, during fetch at ad dress 0x20, the AR M
core adjusts R14_FIQ, decrementing it by 4.
2. The ARM core enters FIQ mode.
3. When the in stru ction load ed at address 0x1C is executed , the Program Counter
is loaded wi th the va lue read in AIC_F VR. Reading the AIC_F VR has the effect
of clearing the fast interrupt (source 0 connected to the FIQ line) if it has been
programmed to be edge-triggered. In this case only, it de-asser ts the nFIQ line
on the processor.
4. The previous step establishes a connection to the corresponding interrupt ser-
vice routine. It is not necessary to save the Link Register (R14_FIQ) and the
SPSR (SPSR_FIQ) if nested fast interrupts are not needed.
5. The interrupt handler can then proceed as required. It is not necessary to save
regis ters R8 to R1 3 becaus e FIQ mode has its own dedicated registe rs and the
user R8 to R13 are banked. The other registers, R0 to R7, must be saved before
being used and restored at the end (before the next step). Note that if the fast
interrupt is programmed to be le vel- sensitive, the source of the interrupt must be
cleared during this phase in order to de-assert the nFIQ line.
6. Finally, the Link R egister (R14_FIQ ) is re sto r ed int o the PC aft er decre men tin g it
by 4 (e.g., with instruction SUB PC, LR, #4). This has the effect of returning from
the interrupt to the step previously ex ecuted, of loading the CPSR with the SPSR
and of maskin g or unmas king the fas t interr upt dep ending on the state s aved i n
the SPSR.
Note: The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was just
about to mask FIQ interrupts when the mask instruction was interrupted. Hence, when
the SPSR is restored, the interrupted instruction is completed (FIQ is masked).
Software Interrupt Any interrupt source of the AIC can be a software interrupt. It must be programmed to
be edge-triggered in order to set or clear it by writing to the AIC_ISCR and AIC_ICCR.
This is totally independent of the SWI instruction of the ARM7TDMI processor.
80 AT75C221 Preliminary 6033A–INTAP–03/04
Spurious Interrupt A spurious interrupt is a signal of very short duration on one of the interrupt input lines. A
spur ious inter rupt also ar ises when an interrupt is trigger ed and maske d in the sam e
cycle.
Spurious Interrupt Sequence A spurious interrupt is handled by the following sequence of actions.
1. When an interrupt is active, the AIC asserts the nIRQ (or nFIQ) line and the
ARM7TDMI enters IRQ (or FIQ) mode. At this moment, if the interrupt source
disappears, the nIRQ (or nFIQ) line is de-asserted but the ARM7TDMI continues
with the interrupt handler.
2. If the IRQ Vecto r Register (AIC_IV R) is read when the nIR Q is not as serted, th e
AIC_IVR is read with the contents of the Spurious Interrupt Vector Register.
3. If the FIQ Vector Re giste r (A IC_F VR ) is read when the nF IQ i s n ot a sserted, the
AIC_FVR is read with the contents of the Spurious Interrupt Vector Register.
4. The Spur ious ISR must w rite an End o f Interr upt c ommand as a minimum , how-
ever, it is sufficient to write to the End of Interrupt Command Register
(AIC_EO ICR). Until the AIC_EOICR wr ite is r eceived by the interr upt controll er,
the nIRQ (or nFIQ) line is not re-asserted.
5. This causes the ARM7TDMI to jump into the Spurious Interrupt Routine.
6. During a spurious ISR, the AIC_ISR reads 0.
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AIC User Interface
Base Address: 0xFF030000 with double mapping at address 0xFFFF F000
Note: 1. The reset value of this register depends on the level of the external IRQ lines. All other sources are cleared at reset.
Table 1. AIC Register Mapping
Offset Register Register Name Ac cess Reset State
0x000
0x004
–
0x07C
Source Mode Register 0
Source Mode Register 1
–
Source Mode Register 31
AIC_SMR0
AIC_SMR1
–
AIC_SMR31
Read/Write
Read/Write
–
Read/Write
0
0
–
0
0x080
0x084
–
0xFC0
Source Vector Register 0
Source Vector Register 1
–
Source Vector Register 31
AIC_SVR0
AIC_SVR1
–
AIC_SVR31
Read/Write
Read/Write
–
Read/Write
0
0
–
0
0x100
0x104
0x108
0x10C
IRQ Vector Register
FIQ Vector Register
Interrupt Status Register
Interrupt Pending Register
AIC_IVR
AIC_FVR
AIC_ISR
AIC_IPR
Read-only
Read-only
Read-only
Read-only
0
0
0
(1)
0x110
0x114
0x118
0x11C
Interrupt Mask Register
Core Interrupt Status Register
Reserved
Reserved
AIC_IMR
AIC_CISR
–
–
Read-only
Read-only
–
–
0
0
–
–
0x120
0x124
0x128
0x12C
Interrupt Enable Command Register
Interrupt Disable Command Register
Interrupt Clear Command Register
Interrupt Set Command Register
AIC_IECR
AIC_IDCR
AIC_ICCR
AIC_ISCR
Write-only
Write-only
Write-only
Write-only
–
–
–
–
0x130 End-of-in terrupt Command Register AI C_EOICR Write-only –
0x1 34 Spuri ous Interrupt Vector Register AIC_SPU Read/Write 0
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AIC Source Mode Register
Register Name: AIC_SMR0...AIC_SMR31
Access Type: Read/Write
•PRIOR: Priority Level
Programs the priority level for all sources except source 0 (FIQ).
The priority level can be between 0 (lowest) and 7 (highest).
The priority level is not used for the FIQ in the SMR0.
• SRCTYPE: Interrupt Source Type
Programs the input to be positive- or negative-edge triggered or positive- or negative-level sensitive.
The active level or edge is not programmable for the internal sources.
AIC Source Vector Registers
Register Name: AIC_SVR0...AIC_SVR31
Access Type: Read/Write
•Vector
In these registers, the user may store the addresses of the corresponding handler for each interrupt source.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– SRCTYPE – – PRIOR
SRCTYPE Internal Sources External Sources
00 Level-sensitive Low-l evel sensitive
01 Edge-triggered Negative-edge triggered
10 Level-sen sitive High-level sensitive
11 Edge-triggered Positive-edge triggered
31 30 29 28 27 26 25 24
Vector
23 22 21 20 19 18 17 16
Vector
15 14 13 12 11 10 9 8
Vector
76543210
Vector
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AIC Interrupt Vector Registers
Register Name: AIC_IVR
Access Type: Read-only
Reset Value: 0
•IRQV
The IRQ Vector Reg ister co ntains the vector programmed by the user i n the Sourc e Vector Re gister c orresp onding to th e
current interrupt. The SVR Register (1 to 31) is indexed by the current interrupt number when the IVR register is read.
When there is no interrupt, the IRQ registe r reads 0.
AIC FIQ Vector Register
Register Name: AIC_FVR
Access Type: Read-only
Reset Value: 0
•FIQ
The vector register contains the vector programmed by the user in SVR Register 0 which corresponds to FIQ.
31 30 29 28 27 26 25 24
IRQV
23 22 21 20 19 18 17 16
IRQV
15 14 13 12 11 10 9 8
IRQV
76543210
IRQV
31 30 29 28 27 26 25 24
FIQV
23 22 21 20 19 18 17 16
FIQV
15 14 13 12 11 10 9 8
FIQV
76543210
FIQV
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AIC Interrupt Status Register
Register Name: AIC_ISR
Access Type: Read-only
•IRQID
The interrupt status register returns the current interrupt source register.
AIC Interrupt Pending Register
Register Name: AIC_IPR
Access Type: Read-only
• Interrupt Pending
0 = Corresponding interrupt is not pending.
1 = Corresponding interrupt is pending.
AIC Interrupt Mask Register
Register Name: AIC_IMR
Access Type: Read-only
• Interrupt Mask
0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––– IRQID
31 30 29 28 27 26 25 24
00000000
23 22 21 20 19 18 17 16
00000000
15 14 13 12 11 10 9 8
PIOB UARTB MACB OAKA IRQ1 IRQ0 SPI MACA
76543210
PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ
31 30 29 28 27 26 25 24
00000000
23 22 21 20 19 18 17 16
00000000
15 14 13 12 11 10 9 8
PIOB UARTB MACB OAKA IRQ1(1) IRQ0 SPI MACA
76543210
PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ
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AIC Core Interrupt Status Register
Register Name: AIC_CISR
Access Type: Read-only
• nFIQ: nFIQ Status
0 = nFIQ line inactive.
1 = nFIQ line active.
• NIRQ: nIRQ Status
0 = nIRQ line inactive.
1 = nIRQ line active.
AIC Interrupt Enable Command Register
Register Name: AIC_IECR
Access Type: Write-only
• Interrupt Ena ble
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––NIRQnFIQ
31 30 29 28 27 26 25 24
00000000
23 22 21 20 19 18 17 16
00000000
15 14 13 12 11 10 9 8
PIOB UARTB MACB OAKA IRQ1 IRQ0 SPI MACA
76543210
PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ
86 AT75C221 Preliminary 6033A–INTAP–03/04
AIC Interrupt Disable Command Register
Register Name: AIC_IDCR
Access Type: Write-only
• Interrupt Disa ble
0 = No effect.
1 = Disables the corresponding interrupt.
AIC Interrupt Clear Command Register
Register Name: AIC_ICCR
Access Type: Write-only
• Interrupt Clea r
0 = No effect.
1 = Clears the corresponding interrupt.
31 30 29 28 27 26 25 24
00000000
23 22 21 20 19 18 17 16
00000000
15 14 13 12 11 10 9 8
PIOB UARTB MACB OAKA IRQ1 IRQ0 SPI MACA
76543210
PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ
31 30 29 28 27 26 25 24
00000000
23 22 21 20 19 18 17 16
00000000
15 14 13 12 11 10 9 8
PIOB UARTB MACB OAKA IRQ1 IRQ0 SPI MACA
76543210
PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ
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AIC Interrupt Set Command Register
Register Name: AIC_ISCR
Access Type: Write-only
• Interrupt Set
0 = No effect.
1 = Sets the corresponding interrupt.
AIC End of Interrupt Command Register
Register Name: AIC_EOICR
Access Type: Write-only
The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
Any val ue can be written as it is only necessar y to make a write to this register location to si gnal the end of interrupt
treatment.
31 30 29 28 27 26 25 24
00000000
23 22 21 20 19 18 17 16
00000000
15 14 13 12 11 10 9 8
PIOB UARTB MACB OAKA IRQ1 IRQ0 SPI MACA
76543210
PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––––
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AIC Spurious Interrupt V ector Register
Register Name: AIC_SPU
Access Type: Read/Write
•SIQV
This register contains the 32-bit address of an interrupt routine which is used to treat cases of spurious interrupts.
The programmed address is read in the AIC_IVR if it is read when the nIRQ line is not asserted.
The programmed address is read in the AIC_FVR if it is read when the nFIQ line is not asserted.
31 30 29 28 27 26 25 24
SIQV
23 22 21 20 19 18 17 16
SIQV
15 14 13 12 11 10 9 8
SIQV
76543210
SIQV
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Parallel I/O Controller (PIO)
The AT75 C221 integ rates two P IO controller s, PIOA and PIOB. PIOA control s 32 I/O
lines an d PIOB cont rols 16 FI/O lin es. Each I/O li ne can be progr ammed as an in put or
an output and can genrate an interrupt on level change.
These pins are used for several functions:
• External I/O for Internal Peripherals
• Keypad Controller Function
• General Purpose I/O
Output Selection T he user can enable each individual I/O s ignal as an output with the PIO_OER and
PIO_ODR registers. The output status of the I/O signals can be read in the PIO_OSR
regist er. The direc tion def ined has an effect on ly if the pi n is configu red to be c ontrolle d
by the PIO controller.
I/O Levels Each pin can be configured to be driven high or low. The level is defined in four different
ways, according to the following conditions:
• If a pin is controlled by the PIO controller and is defined as an output, the level is
programmed using the PIO_SODR and PIO_CODR registers. In this case, the
programmed v alue can be read in the PIO_ODSR register.
• If a pin is controlled by the PIO controller and is not defined as an output, the lev el is
determined by the external circuit.
• If a pin is not controlled by the PIO controller, the state of the pin is defined by the
peripheral.
In all cases, the level on the pin can be read in the register PIO_PDSR.
Interrupts Each parallel I/O c an be programmed to generate an interrupt when a level change
occurs. This is controlled by the PIO_IER and PIO_IDR registers which enable/disable
the I/O interrupt by setting/clearing the corresponding bit in PIO_IMR. When a change in
level occu rs, the corresponding bit in PIO_IS R is set dependi ng on whether the pin is
used as a PIO or a periphera l, and whethe r it is define d as input or outpu t. If the corre-
sponding interrupt in PIO_IMR is enabled, the PIO interrupt is asserted.
When PIO_ISR is read, the register is automatically cleared.
90 AT75C221 Preliminary 6033A–INTAP–03/04
I/O Line Control
Figure 24. I/O Line Block Diagram
Pad
PIO_OSR
1
0
1
0
PIO_PSR
PIO_ODSR
0
1
PIO_PSR
Event
Detection
PIO_PDSR
PIO_ISR
PIO_IMR
Peripheral
Output
Enable
Peripheral
Output
Peripheral
Input
PIOIRQ
Pad Output Enable
Pad Output
Pad Input
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Parallel I/O Controller (PIO) User Interface
Each in di vidual I/O is as s oc ia ted with a bit pos i tion i n th e p aral lel I/O u se r in ter face regist er s. Eac h of th es e registers is 32
bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read as zero.
Notes: 1. The reset value of this register depends on the level of the external pins at reset.
2. This reg ister is cleared at res et. However, the first read of the regi ste r ca n g ive a value no t eq ual to z e ro if any ch an ges have
occurred on any pins between the reset and the read.
Table 25. PIO Controller Memory Map
Offset Register Name Description Access Rese t Value
0x00 PIO_PER PIO E nable Register Write- only –
0x04 PIO_PDR PIO Disable R egister Write-only –
0x08 PIO_PSR PIO Status Register Read-only –
0x0C – Reserved – –
0x10 PIO_OER Output E nable Register W rite-only –
0x14 PIO_ ODR Output Disable Register Write-only –
0x18 PIO_OSR Output Status Register Read-only 0x0
0x1C – Reserved – –
0x20 – Reserved – –
0x24 – Reserved – –
0x28 – Reserved – 0x0
0x2C – Reserved – –
0x30 PIO_SODR Set Ou tput Data Register Write-onl y –
0x34 PIO_CODR Clear Output Data R egister Write-only –
0x38 PIO_ODSR Output Data Status Register Read-only 0x0
0x3C PIO_PDSR(1) Pin Data Status Re gister Read-only See Note 1
0x40 PIO_IER Interrupt Enable Register Write-only –
0x44 PIO_IDR Interrupt Disable Register Write-only –
0x48 PIO_IMR Interrupt Ma sk Register Read-only –
0x4C PIO_ISR(2) Interrupt Status Register Read-only See Note 2
92 AT75C221 Preliminary 6033A–INTAP–03/04
PIO Enable Register
Register Name: PIO_PER
Access Type: Write-only
This register is used to enable individual pins to be controlled by the PIO controller instead of the assoc iated peripheral.
When the PIO is enabled, the associated peripheral (if any) is held at logic zero.
1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
0 = No effect.
PIO Di sable Regi ster
Register Name: PIO_PDR
Access Type: Write-only
This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral func-
tion is enabled on the corresponding pin.
1 = Disables PIO control (enables peripheral control) on the corresponding pin.
0 = No effect.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
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PIO Status Regi ster
Register Name: PIO_PSR
Access Type: Read-only
This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or
disabled.
1 = PIO is active on the corresponding line (peripheral is inactive).
0 = PIO is inactive on the corresponding line (peripheral is activ e).
PIO Output Enable Register
Register Name: PIO_OER
Access Type: Write-only
This register is used to enable PIO output drivers. If the pin is driven by a peripheral, there is no effect on the pin but the
information is stored. The register is programmed as follows:
1 = Enables the PIO output on the corresponding pin.
0 = No effect.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
94 AT75C221 Preliminary 6033A–INTAP–03/04
PIO Output Disable Register
Register Name: PIO_ODR
Access Type: Write-only
This register is used to disable PIO output drivers. If the pin is driven by the peripheral, there is no effect on the pin, but the
information is stored. The register is programmed as follows:
1 = Disables the PIO output on the corresponding pin.
0 = No effect.
PIO Output Status Register
Register Name: PIO_OSR
Access Type: Read-only
This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The
defined v alue is effectiv e only if the pin is controlled by the PIO. The register reads as follows:
1 = The corresponding PIO is output on this line.
0 = The corresponding PIO is input on this line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
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PIO Set Output Data Register
Register Name: PIO_SODR
Access Type: Write-only
This regi st er is us ed to se t PIO ou tput data . It affects the p in o nly if the co rr esponding PI O output line is e nabled and if the
pin is controlled by the PIO. Otherwise, the information is stored.
1 = PIO output data on the corresponding pin is set.
0 = No effect.
PIO Clear Output Data Re gister
Register Name: PIO_CODR
Access Type: Write-only
This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the
pin is controlled by the PIO. Otherwise, the information is stored.
1 = PIO output data on the corresponding pin is cleared.
0 = No effect.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
96 AT75C221 Preliminary 6033A–INTAP–03/04
PIO Output Data Status Register
Register Name: PIO_ODSR
Access Type: Read-only
This regi ster sh ows the output data status whi ch is pro grammed in PIO_SO DR or PIO_ CODR. T he defin ed value is effec-
tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output.
1 = The output data for the corresponding line is programmed to 1.
0 = The output data for the corresponding line is programmed to 0.
PIO Pin Data Status Register
Register Name: PIO_PDSR
Access Type: Read-only
This register shows the state of the physical pin of the chip . The pin values are always valid, regardless of whether the pins
are enabled as PIO, peripheral, input or output. The register reads as follows:
1 = The corresponding pin is at logic 1.
0 = The corresponding pin is at logic 0.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
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PIO Interrupt Enable Register
Register Name: PIO_IER
Access Type: Write-only
This register is used to enable PIO interrupts on the corresponding pin. It has an effect whether PIO is enabled or not.
1 = Enables an interrupt when a change of logic level is detected on the corresponding pin.
0 = No effect.
PIO Interrupt Disable Register
Register Name: PIO_IDR
Access Type: Write-only
This register is used to disable PIO interrupts on the corresponding pin. It has an effect whether the PIO is enabled or not.
1 = Disables the interrupt on the corresponding pin. Logic level changes are still detected.
0 = No effect.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
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PIO Interrupt Mask Register
Register Name: PIO_IMR
Access Type: Read-only
This regi ster shows wh ich pi ns have interr upts e nabled. It is up dated whe n inte rr upts are en abled or disabled by writ ing to
PIO_IER or PIO_IDR.
1 = Interrupt is enabled on the corresponding pin.
0 = Interrupt is not enabled on the corresponding pin.
PIO Interrupt Status Register
Register Name: PIO_ISR
Access Type: Read-only
This register indicates for each pin when a logic value change has been detected (rising or falling edge). This is valid
whether the PIO is selected for the pin or not and whether the pin is an input or an output.
The register is reset to zero following a read and at reset.
1 = At least one input change has been detected on the corresponding pin since the register was last read.
0 = No input change has been detected on the corresponding pin since the register was last read.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
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Univer s al As ynchro nous Receive r Transmitter (UART)
The AT75C221 provides two iden tical full-du plex Universal As ynchronous Recei ver
Transm itters, UART A and UART B. These periph erals sit on t he A PB bus but are also
connected to the ASB bus (and hence external memory) via a dedicated PDC.
The main features are:
• Programmable Baud Rate Generator
• P arity, Framing and Overrun Error Detection
• Line Break Generation and Detection
• Automatic Echo, Local Loopback and Remote Loopback Channel Modes
• Interrupt Generation
• Two Dedicated Peripheral Data Controller Channels
• 6-, 7- and 8-bit Character Length
• Modem Control Signals
Block Diagram
Figure 25. UART Block Diagram
Peripheral Data Controller
Receive
Channel Transmit
Channel
Control Logic
Interrupt Control
Baud Rate Generator
Receiver
Transmitter
Peripheral
Bridge
ARM
ASB
APB
U
ART Interrupt
ACLK
ACLK/8
RXD
TXD
SCK
UART
Baud Rate Clock
PIO
Modem Control
NRT
S
NCT
S
NRI
NDS
R
NDT
R
NDC
D
100 AT75C221 Preliminary 6033A–INTAP–03/04
Pin Description
Each UART channel has external signals as defined in Table 26.
Baud Rate Generator The baud rate generator provides the bit period clock (the baud rate clock) to both the
receiver and the transmitter.
The baud rate gen erator can selec t between external an d internal clock sources. The
external clock source is SCK. The internal clock sources can be either the ARM Clock
(ACLK) or the ARM Clock divided by 8 (ACLK/8).
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer
than the system clock (ACLK) period. The external clock frequency must be at least 2.5
times lower than the system clock.
The selected clock is divided by 16 times the value (CD) written in US_BRGR (Baud
Rate Generator Register). If US_BRGR is set to 0, the baud rate clock is disabled.
Table 26. UART Pins
Signal Name Descript ion Type
SCK UART Serial Clock. Can be configured as input or output. See US_MR I/O
TXD Transmit Serial Data Output
RXD Receive Serial Data Input
NRTS Request to Send Output
NCTS Clear to Send Input
NDTR Data Terminal Ready Output
NDSR Data Set Ready Input
NDCD Da ta Ca rrier Detect Input
NRI Ring Indicator Input
Baud Rate =S elect ed Clock
16 x CD
Table 27. Clock Generator Table with Crystal Frequency of 16 MHz
Required Baud Rate
(bps) CD Actual CD Actual Baud Rate (bps) Error (bps) % Error
9600 260.42 260 9615.385 15,38 0.16
19200 130.21 130 19230.77 30.77 0.16
38400 65.10 65 38461.54 61.54 0.16
57600 43.41 43 58139.53 539.53 0.94
115200 21.70 22 113636.40 -1163.64 -1.36
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Figure 26. Baud Rate Generator
Receiver Opera t ions The UART detects the start of a received character by sampling the RXD signal until it
detects a valid star t bit. A low l evel (s pace) on RX D is inte rpreted as a valid start bit if it
is detected for more than seven cycles of the sampling clock, which is 16 times the baud
rate. Hence, a space which is longer than 7/16 of the bit period is detected as a valid
start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver con-
tinues to wait for a valid start bit.
When a va lid start bit has bee n det ected, th e receiv er s ample s the RXD at the theore ti-
cal mid-point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock
(1-bit period) so the sampling point is eight cycles (0.5-bit periods) afte r the start of the
bit. The firs t samplin g point is there fore 24 cycles (1.5-bit peri ods) after th e falling edg e
of the s tart bi t was de tected. Eac h subse quent bi t is samp led 16 c ycles (1- bit per iod)
after the previou s one.
Figure 27. Start Bit Detection
Figure 28. Character Reception
Receiver Ready When a complete character is received, it is transferred to the US_RHR and the RXRDY
status bit in US_CSR is set. If US_RHR has not been read since the last transfer, the
OVRE status bit in US_C SR is set.
0
1
ACLK
ACLK/8
CLK 16-bit Counter
0
Baud Rate
Clock
CD
CD
OUT
Divide
by 16
0
1
>1
USCLKS [0]
16 x Baud
R
ate Clock
RXD
True Start
Detection D0
Sampling
D0 D1 D2 D3 D4 D5 D6 D7
RXD
True Start Detection
Sampling Parity Bit Stop B
it
E
xample: 8-bit, parity enabled 1 stop
1-bit
period
0.5-bit
periods
102 AT75C221 Preliminary 6033A–INTAP–03/04
Parity Error Each time a character is received, the receiver calculates the parity of the received data
bits in a ccordanc e with the fiel d PAR in US_MR . It the n compares the r esult with the
received parity bit. If different, the parity error bit PARE in US_CSR is set.
Framing Error If a character is received with a stop bit at low level and with at least one data bit at high
level, a framing error is generated. This sets FRAME in US_CSR.
Time-out This function allows an idle condition on the RXD line to be detected. The maximum
delay for which the UART should wait for a new character to arrive while the RXD line is
inactive (high level) is programmed in US_RTOR. When this register is set to 0, no time-
out is detected. Otherwise, the receiver waits for a first character and then initializes a
counter which is decremented at each bit period and reloaded at each byte reception.
When th e counte r reach es 0, the TI MEOUT bi t in US_CS R is set. The user can restar t
the wait for a first character with the STTTO (Start Time-out) bit in US_CR.
Calcula tio n of time-out dur ati on :
Transmitter Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first,
on the falling edge of the serial clock.
The number of data bits is selected in the CHRL field in US_MR.
The parity bit is set according to the PAR field in US_MR.
The number of stop bits is selected in the NBSTOP field in US_MR.
When a character is written to US_THR, it is transferred to the Shift Register as soon as
it is empty. When the transfer occurs, the TXRDY bit in US_CSR is set until a new char-
acter is writt en to US_TH R. If the T rans mi t S hift Register an d US _THR ar e both em pty,
the TXEMPTY bit in US_CSR is set.
Figure 29. Character Transmission
Time-guard The time-guard function allows the transmitter to insert an idle state on the TXD line
between two characters. The duration of the idle state is programmed in US_TTGR.
When thi s regi st er i s se t to zero, no ti me-gu ar d is ge nerated. Other wi se , t he trans mi tter
holds a high level on TXD after each transmitted byte during the number of bit periods
programmed in US_TTGR.
Channel Modes The UART can be programmed to operate in three different test modes using the field
CHMODE in US_MR.
Duration Value 4
×Bit Period
×
=
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Example: 8-bit, parity enabled 1 stop
Baud Rate
Clock
Idle state duration
between two characters =Time-guard
value xBit
period
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Automatic echo mode all ows bit-by-b it re-tra nsmission. W hen a bi t is rec eived on th e
RXD line, it is sent to the TXD line. Programming the transmitter has no effect.
Local loopback mode allows the transmitted characters to be received. TXD and RXD
pins are not us ed and the out put of the tra ns mit ter is inter na ll y conn ect ed to the inpu t of
the rec eiver. The RXD pin level ha s no eff ect and the TXD pi n is h eld high, as in idl e
state.
Remote loopback mode directly connects the RXD pin to the TXD pin. The transmitter
and the receiver are disabled and have no effect. This mode allows bit-by-bit re-
transmission.
Figure 30. Channel Modes
Peripheral Data
Controller Each UART channel is closely connected to a corresponding peripheral data controller
channel. One is dedicated to the receiver, the other is dedicated to the transmitter.
The PDC channel is programmed using US_TPR and US_TCR for the transmitter and
US_RP R and US_R CR for the re ceiver. Th e status of the PDC is given in U S_CSR by
the ENDTX bit for the transmitter and by the ENDRX bit for the receiver.
The poi nter r egis ter s U S_TP R and US_RPR ar e u se d to sto re the a ddr ess of th e tr an s-
mit or receive buffers. The counter registers US_TCR and US_RCR are used to store
the size of these buffers.
The recei ver data trans fer is tr iggered by the RXRDY bit and the transmitt er data tran s-
fer is triggered by TXRDY. When a transfer is performed, the counter is decreme nted
and the pointer is incremented. When the counter reaches 0, the status bit is set
Receiver
Transmitter Disabled
RX
D
TXD
Receiver
Transmitter Disabled
RX
D
TXD
VDD
Disabled
Receiver
Transmitter Disabled
RX
D
TXD
Disabled
Automatic Echo
Local Loopback
R
emote Loopback VDD
104 AT75C221 Preliminary 6033A–INTAP–03/04
(ENDRX for the receiver, ENDTX for the transmitter in US_CSR) and can be pro-
grammed to generate an interrupt. Transfers are then disabled until a new non-zero
counter value is programmed.
Modem Control and
Status Signals
NCTS: Clear to Send When low, this indicates that the modem or data set is ready to exchange data. The
NCTS signal is a modem status input; its conditions can be tested by the CPU reading
bit 4 (CTS) of the Modem Status Reg ister. Bit 4 is the co mplemen t of the NCTS signal .
Bit 0 (DCTS) of the Modem Status Register indicates whether the NCTS input has
changed state since the previous read of the Modem Status Register. NCTS has no
effect on the transmitter.
NDCD: Data Carrier Detect When lo w, this indica tes that the data carri er has been detected by the mode m or data
set. The NDCD signal is a modem status input; its condition can be tested by the CPU
reading bit 7 (DCD) of the Modem Status Register. Bit 7 is the complement of the NDCD
signal. Bit 3 (DDCD) of the Modem Status Register indicates whether the NDCD input
pin has changed since the previous reading of the Modem Status Register. NDCD has
no effect on the receive r.
NDSR: Data Set Ready When low, thi s in forms th e modem or d ata se t that th e UART is rea dy to co mmunic ate.
The NDSR signal is a modem status input; its condition can be tested by the CPU read-
ing bit 5 (DSR) of the Modem Status Register. Bit 5 is the complement of the NDSR
signal. Bit 1 (DDSR of the Modem Status Register) indicates whether the NDSR input
has changed state since the previous read of the Modem Status Register.
NDTR: Data Terminal Ready When low , this infor ms th e modem or data set tha t th e UART i s ready to co mmunic ate.
The NDTR output signal can be set to active low by programming bit 0 (DTR) of the
Modem Co ntrol Register to a high level. A master reset operation sets this signal to its
inactive (high) state. Loop mode operation holds this signal in its inactive state.
NRI: Ring Indicator When low, this indicates that a telephone ringing signal has been received by the
modem or data set. The NRI sign al is a modem sta tus inpu t; its con dition can be teste d
by the CPU readi ng bit 6 (RI) of the Modem Status Reg ister. Bit 6 is the comple ment of
the N RI signal. Bit 2 (TERI) of the Modem St atus Regi ster indi cates whether th e NRI
input signal has changed from a low to a high state since the previous read of the
Modem Status Register.
NRTS: Request to Send When low, this informs the modem or data set that the UART is ready to exchange data.
The NRTS output signal can be set to an active low by programming bit 1 (RTS) of the
Modem Co ntrol Register. A master reset operation sets this signal to its inactive (high)
state.
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AT75C221 Preliminary
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Universal Asynchronous Receiver/Transmitter (UART) User Interface
Table 28. UART Memory Map
Offset Register Name Description Access Reset Value
0x00 US_CR Control Register Write-only –
0x04 US_MR M ode Registe r Re ad/Write 0
0x08 US_IER Interrupt Enable Register W rite-only –
0x 0C US_I DR Interrupt Disable Register Write-only –
0x10 US_IMR Interrupt Mask Register Read-only 0
0x14 US_CSR Channel Status Register Read-only 0x18
0x18 US_RHR Receiver Holding Register Read-only 0
0x1C US_THR Transmitter Holding Register Write-only –
0x20 US_BR GR Baud Rate Generator Register Read/Write 0
0x24 US_RTOR Receiver Time-out Register Read/Write 0
0x28 US_T TGR Transmi tter Time-guard Register Read/Wri te 0
0x2C – Reserved – –
0x30 US_RPR Receive Pointer Register Read/Write 0
0x34 US_RCR Receive Counter Register Read/Write 0
0x38 US_TPR Transmit Pointer Regi ster Read/Write 0
0x3C US_TCR Transmit Counter Register Read/Write 0
0x40 US_MC Modem Contro l Regis ter Write-o nly –
0x44 US_MS Mode m Statu s Regis te r Read-only
106 AT75C221 Preliminary 6033A–INTAP–03/04
UART Control Register
Name: US_CR
Access Type: Write-only
• RSTRX: Reset Receiver
0 = No effect.
1 = The receiver logic is reset.
• RSTTX: Reset Transmitter
0 = No effect.
1 = The transmitter logic is reset.
• RXEN: Receiver Enable
0 = No effect.
1 = The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable
0 = No effect.
1 = Th e receiver is disabled.
• TXEN: Transmitter Enable
0 = No effect.
1 = The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0 = No effect.
1 = The transmitter is disabled.
• RSTSTA: Reset Status Bits
0 = No effect.
1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – RSTSTA
7 6 5 4 3 2 1 0
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
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UART Mode Register
Name: US_MR
Access Type: Read/Write
• USCLKS: Clock Selection
• CHRL: Character Length
• PAR: Parity Type
• NBSTOP: Number of Stop Bits
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
CHMODE NBSTOP PAR –
7 6 5 4 3 2 1 0
CHRL USCLKS – – – –
USCLKS Selected Clock
00ACLK
01ACLK/8
1 X External (SCK)
CHRL Character Length
00Five bits
01Six bits
1 0 Seven bits
1 1 Eight bits
PAR Parity Type
000Even parity
0 0 1 Odd parity
0 1 0 Parity forc ed to 0 (space)
0 1 1 Parity forc ed to 1 (mark)
10xNo parity
NBSTOP
00 1 stop bit
01 1.5 stop bits
10 2 stop bits
11 Reserved
108 AT75C221 Preliminary 6033A–INTAP–03/04
• CHMODE: Channel Mode
CHMODE Mode Description
0 0 Normal Mode
The UART channel operates as an Rx/Tx UART.
0 1 Automatic Echo
Receiver data input is connected to TXD pin.
1 0 Local Loopback
Transm itter output si gnal is conn ected to receiv er
input signal.
1 1 Remote Loopback
RXD pin is internally connected to TXD pin.
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UART Interrupt Enable Register
Name: US_IER
Access Type: Write-only
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• ENDRX: Enable End of Receive Transfer Interrupt
• ENDTX: Enable End of Transmit Transfer Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• DMSI: Delta Modem Interrupt
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – DMSI TXEMPTY –
7 6 5 4 3 2 1 0
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
110 AT75C221 Preliminary 6033A–INTAP–03/04
UART Interrupt Disable Regist er
Name: US_IDR
Access Type: Write-only
• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Disable End of Receive Transfer Interrupt
• ENDTX: Disable End of Transmit Transfer Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• DMSI: Disable Delta Modem Interrupt
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – DMSI TXEMPTY –
7 6 5 4 3 2 1 0
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
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UART Interrupt Mask Register
Name: US_IMR
Access Type: Read-only
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• ENDRX: End of Receive Transfer Interrupt Mask
• ENDTX: End of Transmit Transfer Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• DMSI: Delta Modem Status Indication Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – DMSI TXEMPTY –
7 6 5 4 3 2 1 0
PARE FRAME OVRE ENDTX ENDRX RXBRK –RXRDY
112 AT75C221 Preliminary 6033A–INTAP–03/04
UART Channel Status Register
Name: US_CSR
Access Type: Read-only
• RXRDY: Receiver Ready
0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled.
1 = At least one complete character has been received and the US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0 = US_THR contains a character waiting to be transferred to the Transmit Shift Register.
1 = US_THR is empty and there is no break request pending TSR availability.
Equal to zero when the UART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one.
• ENDRX: End-of-receive Transfer
0 = The end-of-transfer signal from the PDC channel dedicated to the receiver is inactive.
1 = The end-of-transfer signal from the PDC channel dedicated to the receiver is activ e.
• ENDTX: End-of-transmit Transfer
0 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is inactive.
1 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is active.
• OVRE: Overrun Error
0 = No byte has been transferred from the Receiv e Shift Register to the US_RHR when RxRDY was asserted since the last
reset status bits command.
1 = At leas t one byte has bee n transferred from the Receive Shift Register to the US_RHR when RxRDY was asser ted
since the last reset status bits command.
• FRAME: Framing Error
0 = No stop bit has been detected low since the last reset status bits command.
1 = At least one stop bit has been detected low since the last reset status bits command.
• PARE: Parity Error
1 = At least one parity bit has been detected false ( or a parity bit high in multi-drop mode) since the last reset status bit”
command.
0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bits command.
• TXEMPTY: Transmitter Empty
0 = There are characters in either US_THR or the Transmit Shift Register or a break is being transmitted.
1 = There are no characters in US_THR and the Transmit Shift Register and break is not active.
Equal to zero when the UART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one.
• DMSI: Delta Modem Status Indication Interrupt
0 = No effect.
1 = There has been a change in the modem status delta bits since the last reset status bits command.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – DMSI TXEMPTY –
7 6 5 4 3 2 1 0
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
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UART Receiver Holding Register
Name: US_RHR
Access Type: Read-only
• RXCHR: Received Character
Last character received if RXRDY is set. When number of data bits is less than eight, the bits are right-aligned.
UART Transmitter Holding Register
Name: US_THR
Access Type: Write-only
• TXCHR: Character to be Transmitted
Nex t character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than eight,
the bits are right-aligned.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
RXCHR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
TXCHR
114 AT75C221 Preliminary 6033A–INTAP–03/04
UART Baud Rate Generator Register
Name: US_BRGR
Access Type: Read/Write
• CD: Clock Divisor
This register has no effect if synchronous mode is selected with an external clock.
UART Receive Pointer Register
Name: US_RPR
Access Type: Read/Write
• RXPTR: Receive Pointer
RXPTR must be loaded with the address of the receive buffer.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
CD
7 6 5 4 3 2 1 0
CD
CD Effect
0 Disables clock
1 Clock divisor bypass
2 to 65535 Baud rate = Selected clock/(16 x CD)
31 30 29 28 27 26 25 24
RXPTR
23 22 21 20 19 18 17 16
RXPTR
15 14 13 12 11 10 9 8
RXPTR
7 6 5 4 3 2 1 0
RXPTR
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UART Receive Counter Register
Name: US_RCR
Access Type: Read/Write
Reset Value: 0x0
• RXCTR: Receive Co unter
RXCTR must be loaded with the size of the receive buffer.
0 =Stop peripheral data transfer dedicated to the receiver.
1 - 65535: Start peripheral data transfer if RXRDY is active.
UART Transmit Pointer Register
Name: US_TPR
Access Type: Read/Write
Reset Value: 0x0
• TXPTR: Transmit Pointer
TXPTR must be loaded with the address of the transmit buffer.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
RXCTR
7 6 5 4 3 2 1 0
RXCTR
31 30 29 28 27 26 25 24
TXPTR
23 22 21 20 19 18 17 16
TXPTR
15 14 13 12 11 10 9 8
TXPTR
7 6 5 4 3 2 1 0
TXPTR
116 AT75C221 Preliminary 6033A–INTAP–03/04
UART Transmit Counter Register
Name: US_TCR
Access Type: Read/Write
Reset Value: 0x0
• TXCTR: Transmit Counter
TXCTR must be loaded with the size of the transmit buff er.
0 =Stop peripheral data transfer dedicated to the transmitter.
1 - 65535: Start peripheral data transfer if TXRDY is active.
Modem Control Register
Register Name: US_MC
Access Type: Write-only
Reset Value: Undefined
This register controls the interf ace with the modem or data set (or a peripheral de vice emulating a modem). The contents of
the Control Register are indicated below.
• DTR: Data Terminal Ready
This bit controls the NDTR output. When bit 0 is set to a logic 1, the NDTR output is forced to a logic 0.
When bit 0 is reset to a logic 0, the NDTR output is forced to a logic 1.
The NDTR o utpu t of the UART can be a ppl ie d to an EI A i nvert ing line dr i ver to obtai n p r oper p ol arity inp ut a t th e s ucce ed-
ing modem or data set.
• RTS: Request to Send
This bit controls the NRTS output. Bit 1 aff ects the NRTS output in a manner identical to that described above for bit 0.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
TXCTR
7 6 5 4 3 2 1 0
TXCTR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – – RTS DTR
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Modem Status Register
Register Name: US_MS
Access Type: Read-only
This register provides the current state of the control lines from the modem (or peripheral device) to the CPU. In addition to
this current-state information, four bits of the Modem Status Register provide change infor mation. These bits are set to a
logic 1 whenever a control input from the modem changes state. They are reset to logic 0 whenever the CPU reads the
Modem Status Register.
• DCTS: Delta Clear to Send
Bit 0 indicates that the NCTS input to the chip has changed state since the last time it was read by the CPU.
• DDSR: Delta Data Set Ready
Bit 1 indicates that the NDSR input to the chip has changed state since the last time it was read by the CPU.
• TERI: Trailing Edge Ring Indicator
Bit 2 indicates that the NRI input to the chip has changed from a low to a high state.
• DDCD: Delta Data Carrier Detect
Bit 3 indicates that the NDCD input has changed state.
Note that when ever bi t 0, 1, 2, or 3 is s et to log ic 1, a modem stat us int err upt is g enerated. T his is ref lected in the m odem
status register.
• CTS: Clear to Send
This bit is the complement of the Clear to Send (NCTS) input.
• DSR: Data Set Ready
This bit is the complement of the Data Set Ready (NDSR) input.
• RI: Ring Indicator
This bit is the complement of the Ring Indicator (NRI) input.
• DCD: Data Carrier Detect
This bit is the complement of the Data Carrier Detect (NDCD) input.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
DCD RI DSR CTS DDCD TERI DDSR DCTS
118 AT75C221 Preliminary 6033A–INTAP–03/04
Timer/Count er (TC) The AT75C221 features a timer/counter block that includes three identical 16-bit
timer/counter channels. Each channel can be independently programmed to perform a
wide range of functions including frequency measurement, event counting, interval mea-
surement, pulse generation, delay timing and pulse-width modulation.
Each timer/coun ter channel has three exter nal cloc k inputs , five i nternal cl ock in puts,
and two multi-purpose input/output signals that can be configured by the user. Each
channel drives an inter nal interru pt signal that ca n be progra mmed to generate proces-
sor interrupts via the AIC.
The timer/counter block has two global registers which act upon all three TC channels.
The Bloc k Control Reg ister all ows the three c hannels to be started s imultaneo usly wit h
the same instruction. The Block Mode Register defines the external clock inputs for
each timer/counter channel, allowing them to be chained.
Block Diagram
Figure 31. Timer/Counter Block Diagram
Timer/Counter
Channel 0
Timer/Counter
Channel 1
Timer/Counter
Channel 2
SYNC
Parallel I/O
Controller
TC1XC1S
TC0XC0S
TC2XC2S
INT
INT
INT
TIOA0
TIOA1
TIOA2
TIOB0
TIOB1
TIOB2
XC0
XC1
XC2
XC0
XC1
XC2
XC0
XC1
XC2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TIOA1
TIOA2
TIOA0
TIOA2
TIOA0
TIOA1
Advanced
Interrupt
Controller
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Timer/Counter Block
TIOA
TIOB
TIOA
TIOB
TIOA
TIOB
SYNC
SYNC
ACLK/2
ACLK/8
ACLK/32
ACLK/128
ACLK/1024
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AT75C221 Preliminary
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Signal Name Description
Note: After a hardware reset, the timer/counter block pins are controlled by the PIO controller. They must be configured to be con-
trolled by the peripheral before being used.
Description The three timer/counter channels are independent and identical in operation.
Counter Each timer/counter channel is organized around a 16-bit counter. The value of the
counter is incremented at ea ch positive edge of the s elected clock. When the counter
has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the
COVFS bit in TC_SR (Status Register) is set.
The current value of the counter is accessible in real time by reading TC_CV. The
counter can be reset by a trigger. In this case, the counter v alue passes to 0x 0000 on
the next valid edge of the selected clock.
Clock Selection At block lev el, inpu t clock si gnals of each ch annel c an either be co nne cted to the exter-
nal inputs TCLK0, TC LK1 or TCLK2, or be connected to the configurable I/O signals
TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode).
Each channel can independently select an internal or external clock source for its
counter:
• Internal clock signals: ACLK/2, ACLK/8, ACLK/32,
ACLK/128, ACLK/1024
• External clock signals: XC0, XC1 or XC2
The se lecte d clo ck can be i nverted wit h the C LKI bi t in TC _CMR (Chan nel Mo de). T his
allows counting on the opposite edges of the clock.
Table 29. Timer Counter Signal Description
Channel Signal Description Type
XC0, XC1, XC2 External clock inputs I
TIOA Capture mode: General-purpose input
Waveform mode: General-purpose output I
O
TIOB Capture mode: General-purpose input
Waveform mode: General-purpose input/output I
O
INT Interrupt signal output O
SYNC Synchronization input signal I
Block S ignal
TCLK0, TCLK1, TCLK2 External clock inputs I
TIO A0 TIO A signal for Channel 0 I/O
TIO B0 TIOB signal for Channel 0 I/O
TIO A1 TIO A signal for Channel 1 I/O
TIO B1 TIOB signal for Channel 1 I/O
TIO A2 TIO A signal for Channel 2 I/O
TIO B2 TIOB signal for Channel 2 I/O
120 AT75C221 Preliminary 6033A–INTAP–03/04
The burst func tion allow s the clock to be validated when an externa l signal is hig h. The
BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
Note : In al l ca ses, if a n externa l cl ock i s us ed , t h e dura t io n of ea ch o f i t s levels must be lo n ge r
than the system clock (ACLK) period. The external clock frequency must be at least 2.5
times lower than the system clock (ACLK).
Figure 32. Clock Selection
Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/dis-
abled and started/stopped.
1. The cl ock can b e enabled or d isabled by the us er with the CLKEN and the CL K-
DIS commands in the Control Register. In capture mode, it can be disabled by an
RB load e v ent if LDBDIS is set to 1 in TC_CMR. In wav eform mode, it can be dis-
abled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When
disabled, the start or the stop ac tio ns have no effect: onl y a CLK EN comm and in
the Control Register can re-enable the clock. When the clock is enabled, the
CLKSTA bit is set in the Status Register.
2. The clock can also be star ted or stopped: a trigger (software, synchro, exter nal
or compare) always starts the clock. The clock can be stopped by an RB load
event in capture mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in
waveform mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands
have an effect only if the clock is enab led.
Timer/Counter Operating
Modes Each timer/counter channel can operate independently in two different modes:
1. Capture mode allows measurement on signals
2. Waveform mode allows wave generation
The timer/counter operating mode is programmed with the WAVE bit in the TC Mode
Register. In capture mode, TIOA and TIOB are configured as inputs. In waveform mode,
TIOA is always configured to be an output and TIOB is an output if it is not selected to
be the external trig ger.
ACLK/2
ACLK/8
ACLK/32
ACLK/128
ACLK/1024
XC0
XC1
XC2
CLKS
CLKI
BURST
1
Selecte
d
Clock
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Figure 33. Clock Control
Trigger A trigger resets the c ounter and starts the counter clock. Three types of triggers are
common to both modes, and a fourth external trigger is available to each mode.
The following triggers are common to both modes:
1. Software trigger: Each channel has a software trigger, available by setting
SWTRG in TC_CCR.
2. SYNC: Eac h channel has a synch ronization s ignal, SYNC. When as ser ted, this
signa l has the s ame effect as a software tr igger. T he SYNC si gnals of all chan-
nels a re as s erted s imult ane ous ly by wr iti ng TC_B CR ( Block Con trol) wi th SYNC
set.
3. Compare RC trigger: RC is implemented in each channel and can provide a trig-
ger when the counter value matches the RC value if CPCTRG is set in TC_CMR.
The timer/counter channel can also be configured to have an external trigger. In capture
mode, the external trigger signal can be selected between TIOA and TIOB. In waveform
mode, an external event can be programmed on one of the following signals: TIOB,
XC0, XC 1 or XC 2. This exte rnal e vent can th en be pr ogram med to pe rform a trig ger by
setting ENET RG in TC_CMR .
If an exter nal tri gger is used, the d urati on of the pulse s mus t be lon ger than t he sy stem
clock (ACLK) period in order to be detected.
Whatever the trigger used, it will be taken into account at the following active edge of the
selecte d c loc k. Thi s m ean s th at th e co unter value may no t re ad ze ro j us t afte r a trigg er ,
especially when a low-frequency signal is selected as the clock.
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
Stop
Event Disab
le
Even
t
Counter
Clock
S
elected
Clock Trigger
122 AT75C221 Preliminary 6033A–INTAP–03/04
Capture Operating Mode This mode is e ntered by clearing the W AVE parameter in TC_CM R (Channel Mo de
Register). Captur e mode allows the TC Ch annel to perform m easurements such as
pulse t iming , fre quency, peri od, du ty c ycle an d pha se on TIOA and T IOB s ignal s whic h
are inputs.
Figure 34 shows the configuration of the TC Chan nel when programmed in cap ture
mode.
Capture Registers A and B
(RA and RB) Regi sters A and B are used as cap ture registers; thus, they can be loaded with the
counter value when a programmable event occurs on the TIOA signal.
The param eter LDRA in TC_CMR defi nes the TI OA edge for the loadin g of Register A,
and the parameter LDRB defines the TIOA edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded
since the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loadi ng RA or RB befor e the read o f the las t value loaded sets the O verrun Error Fl ag
(LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten.
Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an
external trigger can be defined.
Bit ABETRG in TC_CMR selects input signal TIO A or TIOB as an external trigger.
Param eter E TRGED G d efine s the e dge (ris ing, fallin g or b oth ) dete cted to g enerate an
external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
Status Regist er The following bits in the status register are significant in capture operating mode.
• CPCS: RC Compare Status
There has been an RC Com pare match at least once since the last read of the
status.
• COVFS: Counter Overflow Status
The counter has attempted to count past $FFFF since the last read of the status.
• LOVRS: Load Overrun Status
RA or RB has been loaded at least twice without any read of the corresponding reg-
ister since the last read of the status.
• LDRAS: Load RA Status
RA has been loaded at least once without any read since the last read of the status.
• LDRBS: Load RB Status
RB has been loaded at least once without any read since the last read of the status.
• ETRGS: External Trigger Status
An exter nal trigger on TIOA or TI OB has b een detected s ince the last read of th e
status.
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AT75C221 Preliminary
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Figure 34. Capture Mode
Waveform Operating
Mode This mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode
Register).
Wavefo rm operati ng mode al lows the TC ch annel to ge nerate 1 or 2 PW M signa ls with
the same frequency and independently programmable duty cycles, or to generate differ-
ent types of one-shot or repetitive pulses.
In this mode, TIOA is configured as output and TIOB is defined as output if it is not used
as an external event (EEVT parameter in TC_CMR).
Figure 35 on page 126 shows the configuration of the TC channel when programmed in
waveform operating mode.
Compare Register A, B and C
(RA, RB, and RC) In waveform operating mode, RA, RB and RC are all used as compare registers.
RA Compare is used to control the TIOA output. RB Compare is used to control the
TIOB (if configured as output). RC Compare can be programmed to control TIOA and/or
TIOB outputs.
RC Compare can also stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or dis-
able the counter clock (CPCDIS = 1 in TC_CMR).
ACLK/2
ACLK/8
ACLK/32
ACLK/128
ACLK/1024
XC0
XC1
XC2
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
BURST
TIOB
Register C
Capture
Register A Capture
Register B Compare RC =
16-bit Counter
ABETRG
SWTRG
ETRGEDG CPCTRG
TC_IMR
Trig
LDRBS
LDRAS
ETRGS
TC_SR
LOVRS
COVFS
SYNC
1
MTIOB
TIOA
MTIOA
LDRA
LDBSTOP
If RA is not loaded
or RB is loaded If RA is loaded
LDBDIS
CPCS
INT
Edge
Detector
Edge
Detector
LDRB
Edge
Detector
CLK OVF
RESET
Timer/Counter Channel
124 AT75C221 Preliminary 6033A–INTAP–03/04
As in ca pture mode, RC Compare can also generate a tr igg er i f CP CTRG = 1 . A trig ger
resets the counter so RC can control the period of PWM waveforms.
Extern al Ev ent/ Trigg er
Conditions An external event can be programmed to be detected on one of the clock sources (XC0,
XC1, XC2) or TIOB. The external event selected can then be used as a trigger.
The parameter EEVT in TC_CMR selects the external trigger. The parameter EEVT-
EDG def ine s the tr igger edge for eac h of th e p ossible exte rnal tr igger s (risi ng, fa lling or
both). If EEVTEDG is cleared (none), no external event is defined.
If TIOB i s define d as an external event si gnal (E EVT = 0 ), TIOB is no long er used as
output and the TC channel can only generate a waveform on TIOA.
When an ex terna l ev en t is defined , it c an be us ed as a trigge r b y setti ng bit ENE TR G in
TC_CMR.
As in capture mode, the SYNC signal, the software trigger and the RC compare trigger
are also available as triggers.
Output Controller The output controller defines the output level changes on TIO A and TIOB following an
event. TIOB control is used only if TIOB is defined as output (not as an external event).
The following eve nts control TIOA and TIOB: software tr igger, external event and RC
compare. RA compare controls TIOA and RB compare controls TIOB. Each of these
events can be programmed to set, clear or toggle the output as defined in the corre-
sponding parameter in TC_CMR.
Table 30 and Table 31 show which parameter in TC_CMR is used to define the effect of
each event.
If two or more events occur at the same time, the priority level is defined as follows:
1. Software trigger
2. External even t
3. RC compare
4. RA or RB compare
Table 30. TIOA Events
Parameter TIOA Event
ASWTRG Software trigger
AEEVT External event
ACPC RC compare
ACPA RA compare
Table 31. TIOB Events
Parameter TIOB E vent
BSWTRG Softw are trigger
BEEVT External event
BCPC RC c ompare
BCPB RB compare
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Status The following bits in the status register are significant in waveform mode:
• CPAS: RA Compare Status
There has been a RA Compare match at least once since the last read of the status
• CPBS: RB Compare Status
There has been a RB Compare match at least once since the last read of the status
• CPCS: RC Compare Status
There has been a RC Compare match at least once since the last read of the status
• COVFS: Coun ter Overflow
Counter has attempted to count past $FFFF since the last read of the status
• ETRGS: External Trigger
External trigger has been detected since the last read of the status
126 AT75C221 Preliminary 6033A–INTAP–03/04
Figure 35. Waveform Mode
ACLK/2
ACLK/8
ACLK/32
ACLK/128
ACLK/1024
XC0
XC1
XC2
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
CPCDIS
BURST
TIOB
Register A Register B Register C
Compare RA = Compare RB = Compare RC =
CPCSTOP
16-bit Counter
EEVT
EEVTEDG
SYNC
SWTRG
ENETRG
CPCTRG
TC_IMR
Trig
ACPC
ACPA
AEEVT
ASWTRG
BCPC
BCPB
BEEVT
BSWTRG
TIOA
MTIOA
TIOB
MTIOB
CPAS
COVFS
ETRGS
TC_SR
CPCS
CPBS
CLK OVF
RESET
Output Controller
Output Controller
INT
1
Edge
Detector
Timer/Counter Channel
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AT75C221 Preliminary
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Timer/Counter (TC) User Interface
TC_BCR ( Block Control Regis ter) and TC_ BMR (Blo ck Mode Regis ter) contr ol the whole TC block. TC chann els are con-
trolled b y the registers listed in Table 33. The offset of each of the channel registers in Table 33 is in relation to the offset of
the corresponding channel as specified in Table 32.
Note: 1. Read only if WAVE = 0.
Table 32. TC Global Memory Map
Offset Register Name Channel/Register Access Re set Value
0x00 TC Channel 0 See Table 33
0x40 TC Channel 1 See Table 33
0x80 TC Channel 2 See Table 33
0xC0 TC_BCR TC Block Control Register Write-only –
0xC4 TC_BMR TC Block Mode Register Read/Write 0
Table 33. TC Channel Memory Map
Offset Register Name Description Access Rese t Value
0x00 TC_CCR Channel Cont rol Re gister Write-only –
0x04 TC_CMR Channel Mode Regist er Read/Writ e 0
0x08 Reserved –
0x0C Reserved –
0x10 TC_CVR Count er Value Register Read/Write 0
0x14 TC_RA Register A Read/Write(1) 0
0x18 TC_RB Register B Read/Write(1) 0
0x1C TC_RC Register C Read/Write 0
0x20 TC_SR Status Register Read-only –
0x24 TC_IER Interrupt Enable Register Write-only –
0x28 TC_IDR Inter rupt Disa ble Register Write-only –
0x2C TC_IMR Interrupt Ma sk Register Read-only 0
128 AT75C221 Preliminary 6033A–INTAP–03/04
TC Block Control Register
Register Name: TC_BCR
Access Type: Write-only
• SYNC: Synchro Command
0 = No effect.
1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – – – SYNC
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TC Block Mode Register
Register Name: TC_BMR
Access Type: Read/Write
• TC0XC0S: External Clock Signal 0 Selection
• TC1XC1S: External Clock Signal 1 Selection
• TC2XC2S: External Clock Signal 2 Selection
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – TC2XC2S TC1XC1S TC0XC0S
TC0XC0S Signal Connected to XC0
00TCLK0
01None
10TIOA1
11TIOA2
TC1XC1S Signal Connected to XC1
00TCLK1
0 1 none
10TIOA0
11TIOA2
TC2XC2S Signal Connected to XC2
00TCLK2
0 1 none
10TIOA0
11TIOA1
130 AT75C221 Preliminary 6033A–INTAP–03/04
TC Channel Control Register
Register Name: TC_CCR
Access Type: Write-only
• CLKEN: Counter Clock Enable Command
0 = No effect.
1 = Enables the clock if CLKDIS is not 1.
• CLKDIS: Counter Clock Disable Command
0 = No effect.
1 = Disables the clock.
• SWTRG: Software Trigger Command
0 = No effect.
1 = A software trigger is performed: the counter is reset and clock is started.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – SWTRG CLKDIS CLKEN
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TC Channel Mode Register: Capture Mode
Register Name: TC_CMR
Access Type: Read/Write
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• LDBSTOP: Counter Clock Stopped with RB Loading
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
• LDBDIS: Counter Clock Disable with RB Loading
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disab led when RB loading occurs.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG – – – ABETRG ETRGEDG
7 6 5 4 3 2 1 0
LDBDIS LDBSTOP BURST CLKI TCCLKS
TCCLKS Clock Selected
000ACLK/2
001ACLK/8
010ACLK/32
0 1 1 ACLK/128
1 0 0 ACLK/1024
101XC0
110XC1
111XC2
BURST
0 0 The clock is not gated by an external signal.
0 1 XC0 is ANDed with the sel ec ted clock.
1 0 XC1 is ANDed with the sel ec ted clock.
1 1 XC2 is ANDed with the sel ec ted clock.
132 AT75C221 Preliminary 6033A–INTAP–03/04
• ETRGEDG: External Trigger Edge Selection
• ABETRG: TIOA or TIOB External Trigger Selection
0 = TIOB is used as an external trigger.
1 = TIOA is used as an external trigger.
• CPCTRG: RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and starts the counter clock.
•WAVE
0 = Capture mode is enabled.
1 = Capture mode is disabled (waveform mode is enabled).
• LDRA: RA Loading Selection
• LDRB: RB Loading Selection
ETRGEDG Edge
0 0 None
0 1 Rising edge
1 0 Falling edge
1 1 Each edge
LDRA Edge
0 0 None
0 1 Rising edge of TIOA
1 0 Falling edge of TIOA
1 1 Each edge of TIOA
LDRB Edge
00None
0 1 Rising edge of TIOA
1 0 Falling edge of TIOA
1 1 Each edge of TIOA
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TC Channel Mode Register: Waveform Mode
Register Name: TC_CMR
Access Type: Read/Write
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• CPCSTOP: Counter Clock Stopped with RC Compare
0 = Counter clock is not stopped when counter reaches RC.
1 = Counter clock is stopped when counter reaches RC.
• CPCDIS: Counter Clock Disable with RC Compare
0 = Counter clock is not disabled when counter reaches RC.
1 = Counter clock is disabled when counter reaches RC.
31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE CPCTRG –ENETRG EEVT EEVTEDG
7 6 5 4 3 2 1 0
CPCDIS CPCSTOP BURST CLKI TCCLKS
TCCLKS Clock Selected
000ACLK/2
001ACLK/8
010ACLK/32
0 1 1 ACLK/128
1 0 0 ACLK/1024
101XC0
110XC1
111XC2
BURST
0 0 The clock is not gated by an external signal.
0 1 XC0 is ANDed with the sel ec ted clock.
1 0 XC1 is ANDed with the sel ec ted clock.
1 1 XC2 is ANDed with the sel ec ted clock.
134 AT75C221 Preliminary 6033A–INTAP–03/04
• EEVTE DG : Exte rn al Eve n t Edge Select io n
• EEVT: External Event Selection
Note: If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.
• ENETRG: Exte rnal Eve nt Trigger Enable
0 = The external event ha s no effect on the coun ter and its cl ock. In this cas e, the select ed external event only cont rols the
TIOA output.
1 = The external event resets the counter and starts the counter clock.
• CPCTRG: RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and starts the counter clock.
•WAVE
0 = Waveform mode is disabled (Capture mode is enabled).
1 = Wavef orm mode is enabled.
• ACPA: RA Compare Effect on TIOA
• ACPC: RC Compare Effect on TIOA
EEVTEDG Edge
00None
0 1 Rising edge
1 0 Falling edge
1 1 Each edge
EEVT Signal Selected as
External Event TIOB
Direction
0 0 TIOB Input(1)
0 1 XC0 Output
1 0 XC1 Output
1 1 XC2 Output
ACPA Effect
0 0 None
01Set
10Clear
11Toggle
ACPC Effect
00None
01Set
1 0 Clear
1 1 Toggle
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• AEE VT: External Event Effect on TIOA
• ASWTRG: Software Trigger Effect on TIOA
• BCPB: RB Compare Effect on TIOB
• BCPC: RC Compare Effect on TIOB
• BEE VT: External Event Effect on TIOB
AEEVT Effect
00None
01Set
10Clear
11Toggle
ASWTRG Effect
00None
01Set
10Clear
11Toggle
BCPB Effect
00None
01Set
10Clear
11Toggle
BCPC Effect
00None
01Set
10Clear
1 1 Toggle
BEEVT Effect
00None
01Set
10Clear
1 1 Toggle
136 AT75C221 Preliminary 6033A–INTAP–03/04
• BSWTRG: Software Trigger Effect on TIOB
TC Counter Value Register
Register Name: TC_CVR
Access Type: Read-only
• CV: Counter Value
CV contains the counter value in real-time.
BSWTRG Effect
00None
01Set
1 0 Clear
1 1 Toggle
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
CV
7 6 5 4 3 2 1 0
CV
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TC Register A
Register Name: TC_RA
Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1
• RA: Register A
RA contains the Register A value in real-time.
TC Register B
Register Name: TC_RB
Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1
• RB: Register B
RB contains the Register B value in real-time.
TC Register C
Register Name: TC_RC
Access Type: Read/Write
• RC: Register C
RC contains the Register C value in real-time.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
RA
7 6 5 4 3 2 1 0
RA
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
RB
7 6 5 4 3 2 1 0
RB
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
RC
7 6 5 4 3 2 1 0
RC
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TC Status Register
Register Name: TC_SR
Access Type: Read-only
• COVFS: Counter Overflow Status
0 = No counter ov erflow has occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
• LOVRS: Load Overrun Status
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-
tus Register if WAVE = 0.
• CPAS: RA Compare Status
0 = RA compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA compare has occurred since the last read of the Status Register if WAVE = 1.
• CPBS: RB Compare Status
0 = RB compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB compare has occurred since the last read of the Status Register if WAVE = 1.
• CPCS: RC Compare Status
0 = RC compare has not occur red since the last read of the Status Register.
1 = RC compare has occurred since the last read of the Status Register.
• LDRAS: RA Loading Status
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
• LDRBS: RB Loading Status
0 = RB load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB load has occurred since the last read of the Status Register if WAVE = 0.
• ETRGS: External Trigger Status
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.
• CLKSTA: Clock Enabling Status
0 = Clock is disabled.
1 = Clock is enabled.
• MTIOA: TIOA Mirror
0 = TIOA is low. If WAVE = 0, then TIOA pin is low. If WAVE = 1, then TIOA is driven low.
1 = TIOA is high. If WAVE = 0, then TIOA pin is high. If WAVE = 1, then TIOA is driven high.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
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• MTIOB: TIOB Mirr or
0 = TIOB is low. If WAVE = 0, then TIOB pin is low. If WAVE = 1, then TIOB is driven low.
1 = TIOB is high. If WAVE = 0, then TIOB pin is high. If WAVE = 1, then TIOB is driven high.
TC Interrupt Enable Register
Register Name: TC_IER
Access Type: Write-only
• COVFS: Counter Overflow
• LOVRS: Load Overrun
• CPAS: RA Compare
• CPBS: RB Compare
• CPCS: RC Compare
• LDRAS: RA Loading
• LDRBS: RB Loading
• ETRGS: External Trigger
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
140 AT75C221 Preliminary 6033A–INTAP–03/04
TC Interrupt Disable Register
Register Name: TC_IDR
Access Type: Write-only
• COVFS: Counter Overflow
• LOVRS: Load Overrun
• CPAS: RA Compare
• CPBS: RB Compare
• CPCS: RC Compare
• LDRAS: RA Loading
• LDRBS: RB Loading
• ETRGS: External Trigger
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
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TC Interrupt Mask Register
Register Name: TC_IMR
Access Type: Read-only
• COVFS: Counter Overflow
• LOVRS: Load Overrun
• CPAS: RA Compare
• CPBS: RB Compare
• CPCS: RC Compare
• LDRAS: RA Loading
• LDRBS: RB Loading
• ETRGS: External Trigger
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
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Serial Per ipheral Interface (SPI)
The AT75C221 embeds a Serial Peripheral Interface featuring:
• Four Chip Selects with External Decoder Support Allowing Communication with Up
to 15 Peripherals
• Serial Memories, such as DataFlash and 3-wire EEPROMS
• Serial Peripherals, such as ADCS, DACS, LCD Controllers, CAN Controllers And
Sensors
• External Co-processors
• Master or Slave Serial Peripheral Bus Interface
• 8- to 16-bit Programmable Data Length Per Chip Select
• Programmable Phase and Polarity Per Chip Select
• Programmab le Transf er Dela ys Between Consecutiv e Transf ers and Between Clock
and Data Per Chip Select
• Programmable Delay Between Consecutive Transfers
• Selectable Mode Fault Detection
• Connection to PDC Channel Capabilities Optimizes Data Transfers
• One Channel for the Receiver, One Channel for the Transmitter
Overview The S erial Periph eral Interface ( SPI) circuit is a synchr onous serial data link th at pro-
vides communication with external devices in Master or Slave Mode. It also allows
communication between processors if an external processor is connected to the system.
The Se rial P eriph er al Int erfac e i s a sh ift regi ste r tha t s eria lly tr ansmi ts da ta b its to ot her
SPIs. During a data transfer, one SPI system acts as the “master”' that controls the data
flow, while the other system acts as the “slave'' that has data shifted into and out of it by
the master. Different CPUs can take turn being masters (Multiple Master Protocol ver-
sus Si ngl e Mas ter P r otocol , where one CPU is a lwa ys th e m as ter while al l of t he others
are al ways sl aves ), and one mast er may simu ltaneo usly s hift da ta into mult iple sl aves.
However, only one slave may drive its output to write data back to the master at any
given time.
A slave device i s selected when the master as serts its NSS signal. If mul tiple slave
devices exist, the master generates a separate slave select signal for each slave
(NPCS).
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line supplies the output data from the master
shifted into the input(s) of the slave(s).
Master In Sla ve Out (MISO ): This data line s uppl ies the outpu t data from a sla ve to th e
input of th e m aster. T here ma y be n o m ore than o ne sl ave tran sm itting dat a du ring any
particula r trans fer .
Seri al Clock (SPCK ): This control line i s drive n by the master an d regu lates the flow of
the data bits. The maste r may transmit data a t a var iety of baud rates; the SPCK line
cycles once for each bit that is transmitted.
Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
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Block Diagram
Figure 36. Block Diagram
SPI Interface
Interrupt Control
PIO
PDC
APB Bridge
ACK
SPI Interrupt
SPCK
MISO
MOSI
NPCS0/NS
S
NPCS1
NPCS2
ACK/32
NPCS3
ASB
APB
144 AT75C221 Preliminary 6033A–INTAP–03/04
Connections
Figure 37. Application Block Diagram: Single Master/Multiple Slave Implementation
Pin Name List
Master Mode Operations When configured in Master Mode, the Serial Peripheral Interface controls data transfers
to and fr om the slav e(s) con necte d to the S PI bus. T he SPI drives th e chip select (s) to
the sla ve(s) an d the seria l clock (SPCK). After ena bling the S PI, a data tr ansfer be gins
when the core writes to the SPI_TDR (Transmit Data Register).
Transmit and Receive buffers maintain the data flow at a constant rate with a reduced
requirement for high-priority interrupt servicing. When new data is available in the
Table 34. I/O Lines Description
Pin Name Pin Description Type Mode Comments
MISO Master In Slave Out I/O Maste r
Slave Serial data input to SPI
Serial data output from SPI
MOSI Master Out Slave In I/O Master
Slave Serial data ou tput from SPI
Serial data input to SPI
SPCK Serial Clock I/O Master
Slave Clock output from SPI
Clock input to SPI
NPCS1-NPCS3 Peripheral Chip Selects Input Master Select peripherals
NPCS0/NSS Peripheral Chip Select/Slave
Select I/O Master
Master
Slave
Output: Selects peripheral
Input: low causes mode fault
Input: chip select for SPI
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
MISO
MOSI
NSS
Slave 0
SPCK
MISO
MOSI
NSS
Slave 1
SPCK
MISO
MOSI
NSS
Slave 2
NC
NPCS3
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SPI_TDR, the SPI continues to transfer data. If the SPI_RDR (Receive Data Register)
has not been read before new data is received, the Overrun Error (OVRES) flag is set.
Note: As long as this flag is set, no data is loaded in the SPI_RDR. The user has to read the
status register to clear it.
The delay between the activation of the chip select and the start of the data transfer
(DLYBS), as well as the delay between each data transfer (DLYBCT), can be pro-
grammed for each of the four external chip selects. All data transfer characteristics,
including the two timing values, are programmed in registers SPI_CSR0 to SPI_CSR3
(Chip Select Registers).
In Master Mode, the peripheral selection can be defined in two different ways:
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
Figure 41 and Figure 42 show the operation of the SPI in Master Mode. For details con-
cerning the flag and c ontrol bits in these diagrams, see “SPI Chip Select Regis ter” on
page 160.
Fixed Peripheral Select This mode is used for transferring memory blocks without the ex tr a overhead in the
transmit data register to determine the peripheral.
Fixed Peripheral Select is activated by s etting bit PS to zero in SPI_MR (Mode Regis-
ter). The peripheral is defined by the PCS field in SPI_MR.
This option is only available when the SPI is programmed in Master Mode.
Variable Peripheral Select Variable Peripheral Select is activated by setting the PS bit to one. The PCS field in
SPI_TDR is used to select the destination peripheral. The data transfer characteristics
are changed when the selected peripheral changes, depending on the associated chip
select register.
The PCS field in the SPI_MR has no effect.
This option is available only when the SPI is programmed in Master Mode.
Chip Selects The Chi p Select lin es are driv en by the SPI only if it is pr ogramm ed in Master Mo de.
These lines are used to select the destination peripheral. The PCSDEC field in SPI_MR
(Mode Register) selects one to four peripherals (PCSDEC = 0) or up to 15 per ipherals
(PCSDEC = 1).
If Variab le P er ipher al Sel ect is act iv e, the chi p se le ct s ign als ar e de fin ed for eac h tran s-
fer in the PCS field in SPI_ TDR. Chip sele ct signals c an thus be defin ed indepen dently
for each transfer.
If Fixed Peripheral Select is active, Chip Select signals are defined for all transfers by
the field PCS in SPI_MR. If a transfer with a new peripheral is necessary, the software
must wait until the current transfer is completed, then change the value of PCS in
SPI_MR before writing new data in SPI_TDR.
The value on the NPCS pins at the end of each tra nsfer can be read in the SPI_RDR
(Receive Data Register).
By default, all NPCS signals are high (equal to one) before and after each transfer.
Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is
driven by an external master on the NPCS[0]/NSS signal.
146 AT75C221 Preliminary 6033A–INTAP–03/04
When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is
read and the SPI is disabled until re-enabled by bit SPIEN in the SPI_CR (Control
Register).
By default, Mode Fault Detection is enabled. It is disabled by setting the MODFDIS bit in
the SPI Mode Register.
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Master Mode Flow Diagram
Figure 38. Master Mode Flow Diagram
SPI Enable
TDRE
PS
1
0
0
1
1
1
0
Same peripheral
New peripheral
NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD)
TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer
RDRF = 1
TDRE
PS
NPCS = 0xF
Delay DLYBCS
SPI_TDR(PCS)
NPCS = 0xF
Delay DLYBCS
NPCS = SPI_TDR(PCS)
Fixed peripheral
Variable peripheral
Fixed peripheral
Variable peripheral
Delay DLYBCT
0
148 AT75C221 Preliminary 6033A–INTAP–03/04
Master Mode Block Diagram
Figure 39. Master Mode Block Diagram
S
P
I
E
N
S
Serializer
SPI_MR(DIV32)
ACK
ACK/32
SPCK Clock Generator
SPI_CSRx[15:0]
S
R
Q
SPI_MR(PS)
PCS
SPI_RDR
MISO
S
PI_MR(PCS)
SPIDIS SPIEN
SPI_MR(MSTR) SPI_SR
MOSI
NPCS3
NPCS2
NPCS1
NPCS0
LSB MSB
SPCK
SPI
Master
Clock
RD
PCS
SPI_TDR TD
M
O
D
F
T
D
R
E
R
D
R
F
O
V
R
E
0
1
SPI_IER
SPI_IDR
SPI_IMR
SPI Interrupt
0
1
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SPI Slave Mode In Slave Mode, the SPI waits for NSS to go active low before receiving the serial clock
from an external master.
In Slave Mode, CPOL , NCPHA and BITS fields of SPI_C SR0 ar e used to define the
transfer characteristics. The other Chip Select Registers are not used in Slave Mode.
Figure 40. Slave Mode Block Diagram
Data Transfers F our mo des are us ed for data tr ansf ers. The se mode s cor respon d to comb inatio ns of a
pair of para meters called c lo ck pol ar it y ( CP OL ) and c lock phas e ( CP HA) tha t dete r min e
the edges of the clock signal on which the data are driven and sampled. Each of the two
parameters has two possible states, resulting in four po ssible combinations that are
inco mpatible with one anothe r. Thus a maste r/slave pa ir must use the s ame parame ter
S
R
Q
T
D
R
E
R
D
R
F
O
V
R
E
S
P
I
E
N
S
Serializer
SPCK
SPIDIS SPIEN
SPI_IER
SPI_IDR
SPI_IMR
SPI_SR
MISO
LSB MSB
NSS
MOSI
SPI_RDR
RD
SPI_TDR
TD
SPI Interrupt
150 AT75C221 Preliminary 6033A–INTAP–03/04
pair va lues to com munica te. If multipl e slaves ar e used and fixe d in diff erent config ura-
tions, the master must reconfigure itself each time it needs to communicate with a
different slave.
Table 35 shows the four modes and corresponding parameter settings.
Figure 41 and Figure 42 show examples of data transfers.
Figure 41. SPI Transfer Format (NCPHA = 1, 8 bits per transfer
Table 35. SPI Bus Protocol Mode
SPI Mode CPOL CPHA
000
101
210
311
SPCK
(CPOL=0)
SPCK
(CPOL=1)
1234567
MOSI
(from master)
MISO
(from slave)
NSS (to slave)
S
PCK cycle (for reference) 8
MSB
MSB
LSB
LSB
6
6
6
5
5
4
4
3
3
2
2
1
1*
* Not defined, but normally MSB of previous character received.
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Figure 42. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
Clock Generation In Master Mode, the SPI Master Clock is either CLOCK or FDIV, as defined by the
DIV32 field of SPI_MR. The SPI baud rate clock is generated by dividing the SPI Master
Clock by a valu e between 4 and 510. The divi sor is defined in the SCBR fiel d in each
Chip Select Regi ster. The transfer speed ca n thus be defined independen tly for each
chip select signal.
CPOL and NCPHA in the Chip Select Registers define the clock/data relationship
between master and slave devices. CPOL defines the inactive value of the SPCK.
NCPHA defines which edge causes data to change and which edge causes data to be
captured.
In Slave Mode, the input clock low and high pulse duration must be longer than two sys-
tem clock (CLOCK) periods.
SPCK
(CPOL=0)
SPCK
(CPOL=1)
1234567
MOSI
(from master)
MISO
(from slave)
NSS (to slave)
S
PCK cycle (for reference) 8
MSB
MSB
LSB
LSB
6
6
6
5
5
4
4
3
3
2
2
1
1
* Not defined but normally LSB of previous character transmitted.
*
152 AT75C221 Preliminary 6033A–INTAP–03/04
Serial Peripheral Interface (SPI) User Interface
Table 36. S PI Memor y Map
Offset Register Register Name Access Reset
0x00 Cont rol Regi ster SPI_CR Write-only ---
0x04 Mode R egi ste r SPI_MR Read/Write 0x0
0x08 Receive Data Register SPI_RDR Read-only 0x0
0x0C Transmit Data Register SPI_TDR Write-only ---
0x10 Status R egi ste r SPI_SR Read-only 0x000000F0
0x14 Interrupt Enable Register SPI_IER Write-only ---
0x18 Interrupt Disable Register SPI_IDR Write-only ---
0x1C Interrupt Mask Register SPI_IMR Read-only 0x0
0x20 Receive Pointer Register SPI_RPR Read/Write 0x0
0x24 Receive Counter Register SPI_RCR Read/Write 0x0
0x28 Transmit Pointer Register SPI_TPR Read/Write 0x0
0x2C Transmit Counter Register SPI_TCR Read/Write 0x0
0x30 Chip Select Register 0 SPI_CSR0 Read/Write 0x0
0x34 Chip Select Register 1 SPI_CSR1 Read/Write 0x0
0x38 Chip Select Register 2 SPI_CSR2 Read/Write 0x0
0x3C Chip Select Register 3 SPI_CSR3 Read/Write 0x0
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SPI Control Register
Name: SPI_CR
Access Type: Write-only
• SPIEN: SPI Enable
0 = No effect.
1 = Enables the SPI to transfer and receive data.
• SPIDIS: SPI Disable
0 = No effect.
1 = Disables the SPI.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabl ed.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled
• SWRST: SPI Software Reset
0 = No effect.
1 = Resets the SPI. A software-triggered hardware reset of the SPI interface is performed.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST – – – – – SPIDIS SPIEN
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SPI Mode Register
Name: SPI_MR
Access Type: Read/Write
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder.
The Chip Select Registers define the characteristics of the 16 chip selects according to the f ollowing rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 15*.
*Note: The 16th state corresponds to a state in which all chip selects are inactive . This allows a different clock configuration
to be defined by each chip select register.
• DIV32: Clock Selection
0 = SPI Master Clock equals ACK.
1 = SPI Master Clock equals ACK/32.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• LLB: Local Loopback Enable
0 = Local loopback path disabled
1 = Local loopback path enabled
LLB controls the local loopback on the data serializer for testing in Master Mode only.
31 30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
– – – – PCS
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
LLB – – MODFDIS DIV32 PCSDEC PS MSTR
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• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactiv e to the activation of another NPCS. The DLYBCS time guarantees non-over-
lapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six SPI Master Clock periods will be inserted by default.
Otherwise, the following equation determines the delay:
NPCS_to_SCK_Delay = DLYBCS * SPI_Master_Clock_period
156 AT75C221 Preliminary 6033A–INTAP–03/04
SPI Receive Data Register
Name: SPI_RDR
Access Type: Read-only
• RD: Receive Data
Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
• PCS: Peripheral Chip Select
In Master Mode only, these bits indi cate the value on the NPCS pins at the end of a transfer. O therwise, thes e bits read
zero.
SPI Transmit Data Register
Name: SPI_TDR
Access Type: Write-only
• TD: Transmit Data
Data to be transmitted by the SPI is stored in this register. Information to be transmitted must be written to the transmit data
register in a right-justified f ormat.
PCS: Peripheral Chip Select
This field is only used if Variable Peripheral Select is active (PS = 1).
If PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – PCS
15 14 13 12 11 10 9 8
RD
7 6 5 4 3 2 1 0
RD
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – PCS
15 14 13 12 11 10 9 8
TD
7 6 5 4 3 2 1 0
TD
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SPI Status Register
Name: SPI_SR
Access Type: Read-only
• RDRF: Receive Data Register Full
0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has bee n transferred from the ser i ali zer to SPI_RDR si nce the l ast read
of SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer
0 =
The Receive Counter Register has not reached 0 since the last write in SPI_RCR.
1 =
The Receive Counter Register has r eached 0 since the last write in SPI_RCR.
• ENDTX: End of TX buffer
0 =
The Transmit Counter Register has not reached 0 since the last writ e in SPI_TCR.
1 =
The Transmit Counter Register has reached 0 since the last writ e in SPI_TCR.
• SPIENS: SPI Enable Status
0 = SPI is disabled.
1 = SPI is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––SPIENS
15 14 13 12 11 10 9 8
––––––––
76543210
– – ENDTX ENDRX OVRES MODF TDRE RDRF
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SPI Interrupt Enable Register
Name: SPI_IER
Access Type: Write-only
• RDRF: Receive Data Register Full Interrupt Enable
• TDRE: SPI Transmit Data Register Empty Interrupt Enable
• MODF: Mode Fault Error Interrupt Enable
• OVRES: Overrun Error Inter rupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
SPI Interrupt Disable Register
Name: SPI_IDR
Access Type: Write-only
• RDRF: Receive Data Register Full Interrupt Disable
• TDRE: SPI Transmit Data Register Empty Interrupt Disable
• MODF: Mode Fault Error Interrupt Disable
• OVRES: Overrun Error Interrupt Disabl e
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – ENDTX ENDRX OVRES MODF TDRE RDRF
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – ENDTX ENDRX OVRES MODF TDRE RDRF
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SPI Interrupt Mask Register
Name: SPI_IMR
Access Type: Read-only
• RDRF: Receive Data Register Full Interrupt Mask
• TDRE: SPI Transmit Data Register Empty Interrupt Mask
• MODF: Mode Fault Error Interrupt Mask
• OVRES: Overrun Error Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – ENDTX ENDRX OVRES MODF TDRE RDRF
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SPI Chip Select Register
Name: SPI_CSR0... SPI_CSR3
Access Type: Read/Write
• CPOL: Clock Polarity
0 = The inactive state value of SCK is logic level zero.
1 = The inactive state value of SCK is logic level one.
CPOL is used to determine the inactive state v alue of the serial clock (SCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SCK and captured on the following edge of SCK.
1 = Data is captured on the leading edge of SCK and changed on the following edge of SCK.
NCPHA deter mines which edge of S CK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS – – NCPHA CPOL
BITS[3:0] Bit s Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
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• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI I nterface u ses a modulus co unter to derive the SPCK baud rate from the SPI Master Clock
(selected between CLOCK and FDIV). The Baud rate is selected b y writing a value from 2 to 255 in the field SCBR. The f ol-
lowing equation dete rmin es the SP CK baud rate:
SPCK Baudrat e = SPI_Master_Clock / (2 * SCBR )
Giving SCBR a value of zero or one disables the baud rate generator. SPCK is dis abled and as sumes its inactive state
value. No serial transfers may occur. At reset, baud rate is disabled.
• DLYBS: Delay Before SCK
This field defines the delay from NPCS valid to the first valid SCK transition.
When DLYBS equals zero, the NPCS valid to SCK transition is 1/2 the SCK clock period.
Otherwise, the following equation determines the delay:
NPCS_to_SCK_Delay = DLYBS * SPI_Master_Clock_period
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, a delay of four SPI Master Clock periods are inserted.
Otherwise, the following equation determines the delay:
Delay_After_Transfer = 32 * DLYBCT * SPI_Master_Clock_period.
162 AT75C221 Preliminary 6033A–INTAP–03/04
SPI Recei ve Pointer Registe r
Register Name: SPI_RPR
Access Type: Read/Write
• RXPTR: Receive Pointer
RXPTR must be loaded with the address of the receive buffer.
SPI Receive Counter Register
Register Name: SPI_RCR
Access Type: Read/Write
• RXCTR: Rece ive Counter Regist er
RXCTR must be loaded with the size of the receive buffer.
0 = Stops peripheral data transfer
1 - 65535 = Start peripheral data transfer if RDRF is active.
31 30 29 28 27 26 25 24
RXPTR
23 22 21 20 19 18 17 16
RXPTR
15 14 13 12 11 10 9 8
RXPTR
7 6 5 4 3 2 1 0
RXPTR
31 30 29 28 27 26 25 24
-- -- -- -- -- -- -- --
23 22 21 20 19 18 17 16
-- -- -- -- -- -- -- --
15 14 13 12 11 10 9 8
RXCTR
7 6 5 4 3 2 1 0
RXCTR
163
AT75C221 Preliminary
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SPI Transmit Pointer Register
Register Name: SP_TPR
Access Type: Read/Write
• TXPTR: Transmit Pointer R egister
TXPTR must be loaded with the address of the transmit buffer.
SPI Transmit Counter Register
Register Name: SP_TCR
Access Type: Read/Write
• TXCTR: Transmit Counter Register
TXCTR must be loaded with the size of the receive buffer.
0 = Stops peripheral data transfer
1 - 65535 = Start peripheral data transfer if TDRE is active.
31 30 29 28 27 26 25 24
TXPTR
23 22 21 20 19 18 17 16
TXPTR
15 14 13 12 11 10 9 8
TXPTR
7 6 5 4 3 2 1 0
TXPTR
31 30 29 28 27 26 25 24
-- -- -- -- -- -- -- --
23 22 21 20 19 18 17 16
-- -- -- -- -- -- -- --
15 14 13 12 11 10 9 8
TXCTR
7 6 5 4 3 2 1 0
TXCTR
164 AT75C221 Preliminary 6033A–INTAP–03/04
Mechanical Characteristics and Packag ing
BGA Packaging Information
Figure 43. AT75C221 BGA Package
For BGA package data, see Table 37 on page 165,
∅b
165
AT75C221 Preliminary
6033A–INTAP–03/04
BGA Package Data .
Table 37. Dimensions (mm)
Symbol Min Nom Max
A1 0.50 0.60 0.70
0.60 0.75 0.90
aaa 0.30
bbb 0.25
ccc 0.35
ddd 0.30
eee 0.15
A 1.92 2.13 2.34
B 0.28 0.32 0.38
D/E 26.8 27.0 27.2
D1/E1 24.0 24.7
e1.27
f8.05
∅
b
166 AT75C221 Preliminary 6033A–INTAP–03/04
PQFP Packaging Information
Figure 44. PQ FP Pac k age Drawing
For package data, see Table 38, Table 39 and Table 40 on page 167.
CC1
167
AT75C221 Preliminary
6033A–INTAP–03/04
PQFP Package Da ta
Table 38. Dimensions (mm)
Symbol Min Nom Max
c 0.11 0.23
c1 0.11 0.15 0.19
L 0.65 0.88 1.03
L1 1.60 REF
R2 0.13 0.3
R1 0.13
S0.4
Tolerances of Form and Position
aaa 0.25
ccc 0.10
Table 39. Dimensions specific to PQFP Package (mm)
A A1 A2 b b1 D D1 E E1 e ddd
Max Min Min Nom Max Min Max Min Nom Max BSC BSC BSC BSC BSC BSC
4.10 0.25 3.20 3.40 3.60 0.17 0.27 0.17 0.20 0.23 31.20 28.00 31.20 28.00 0.50 0.10
Table 40. 208-lead PQFP Package Electrical Characteristics
Body
Size
R (mΩ)C
s (pF) Cm (pF) Ls (nH) Lm (nH)
MinMaxMinMaxMinMaxMinMaxMinMax
28 x 28 53 71 1.4 1.7 0.56 0.73 6.7 8.4 3.9 5.1
168 AT75C221 Preliminary 6033A–INTAP–03/04
Document Details
Title AT75C221
Literature Number 6033
Revision History
Version A Publication Date: 03/04
i
AT75C221
6033A–INTAP–03/04
Table of Contents Features............. .. ........ ................ ................................. .. ................ ........ .......... 1
Description............ ................................................. .. ........ ................................ 1
Block Diagram ................ ......................................................... ................ ........ 2
Typical Application ........................ .................. .................. .......................... .... 3
Pinout ...................... ............. ............. ............ ...... ............. ............ ............. ....... 3
208-lead PQFP Package Pinout ..................................................................... 4
Mechanical Overview of the 208-lead PQFP Package .................................... 5
256-ball BGA Package Pinout ......................................................................... 6
Mechanical Overview of the 256-ball BGA Package........................................ 8
Peripheral Mult iplexing on PIO Lines............... .............. ............... ............... . 9
PIO Controller A Multiplexing ........................................................................ 10
PIO Controller B Multiplexing ........................................................................ 11
Signal Descript ion ............ ............. .................. ..... .. .. ............. ..... .. ........ ........ 12
Power Supplies.................... ............. ................ ............. ................................ 15
System Controller.......................................................................................... 15
Test................................................................................................................ 15
Reset Controll er ............. ...... ...... ....................................... ....... ...... ....... ...... ... 15
Clock Generator............................................................................................. 16
Chip ID ........................................................................................................... 16
System Controller User Interface.................................................................... 17
SIAP-E Mode Register................................................................................... 18
SIAP-E ID Register ........................................................................................ 19
SIAP-E Clock Status Register........................................................................ 19
Memory Controller (MC)................................................................................ 20
Architecture.................................................................................................... 20
Memory Map.................................................................................................. 21
ARM ASB Arbitration...................................................................................... 22
MAC ASB Arbitration...................................................................................... 22
ASB-ASB Bridge Arbitration........................................................................... 22
Boot Mode...................................................................................................... 23
Endianness .................................................................................................... 23
OakA Program RAM ...................................................................................... 23
Dual-Port Mailbox........................................................................................... 24
ii AT75C221 6033A–INTAP–03/04
Peripherals....... ............ .......................... ...... ............ .......................... ......... ... 25
Peripher al Regi ster s....................................... ...... ....... ...... ....... ...... ....... ...... ... 25
Peripher al Mem ory Map....... ...... ....... ...... ....... ...... ....... ...... ....... ...... ................ 26
Peripheral Data Cont roller (PDC).................... ..... .. ...................... ................ 27
PDC Overview................................................................................................ 27
PDC Channel Priority..................................................................................... 27
Boot P ro g r a m............................. .. .. ................................................................ 28
Boot Mode...................................................................................................... 28
Hardware Connection of the DataFlash......................................................... 28
Internal Boot Software.................................................................................... 28
DataFlash Header Details.............................................................................. 29
Reserved Resources...................................................................................... 29
External Bus Interface (EBI) ........ .. ................ .. ..... ........ ................ ........ ........ 31
Signal Mul tip lexi ng ........ ...... ...... ....... ...... ....... ................... ....... ...... ....... ...... ... 31
SDRAM Controller (SDRAMC).................... ....... .. ....... .. .. ....... .. .. ......... .......... 32
Description ..................................................................................................... 32
Block Diagram................................................................................................ 32
I/O Lines Description ..................................................................................... 33
Application Example....................................................................................... 33
SDRAM Device Initialization .......................................................................... 35
SDRAM Controller Write Cycle ...................................................................... 37
SDRAM Controller Read Cycle...................................................................... 38
Border Management ...................................................................................... 39
SDRAM Controller Refresh Cycles ................................................................ 40
SDRAM User Interface...................................................................................... 41
SDRAMC Mode Register............................................................................... 41
SDRAMC Refresh Timer Register ................................................................. 42
SDRAMC Configuration Register................................................................... 43
SDRAMC Address Register........................................................................... 44
Static Memory Controller (SMC) .................................................................. 45
External Memory Mapping ............................................................................. 45
Pin Description............................................................................................... 45
Data Bus Width .............................................................................................. 45
Byte Write or Byte Select Mode ..................................................................... 46
Read Protocols............................................................................................... 46
Write Protocol................................................................................................. 47
Wait States.............. ....... ...................................... ....... ...... ....... ...... ....... ...... ... 47
Signal Wav ef orms... ....... ...... ...... ....... ................... ....... ...... ....... ...... ....... ...... ... 48
iii
AT75C221
6033A–INTAP–03/04
SMC User Interface........................................................................................... 51
SMC Chip Select Register ............................................................................. 52
SMC Memory Control Register ...................................................................... 53
Ethernet MA C (E MAC)................................................................................... 54
Block Diagram................................................................................................ 54
MEDIA Independent Interface. ...................................................................... 55
Transmit/Receive Operation .......................................................................... 55
DMA Operations............................................................................................. 57
Address Chec king... ....... ...... ...... .................... ...... ....... ...... ....... ...... ....... ...... ... 59
EMAC User Interface ........................................................................................ 61
EMAC Control Register.................................................................................. 62
EMAC Mode Register .................................................................................... 63
EMAC Status Register ................................................................................... 64
EMAC Transmit Address Register................................................................. 64
EMAC Transmit Control Register................................................................... 65
EMAC Transmit Status Register .................................................................... 66
EMAC Receive Buffer Queue Pointer Register.............................................. 67
EMAC Receive Status Register ..................................................................... 67
EMAC Interrupt Status Register..................................................................... 68
EMAC Interrupt Enable Register.................................................................... 69
EMAC Interrupt Disable Register................................................................... 70
EMAC Interrupt Mask Register ...................................................................... 71
EMAC PHY Maintenance Register ................................................................ 72
EMAC Hash Address High Register .............................................................. 73
EMAC Hash Address Low Register ............................................................... 73
EMAC Specific Address (1, 2, 3 and 4) High Register................................... 74
EMAC Specific Address (1, 2, 3 and 4) Low Register.................................... 74
EMAC Statistics Register Block Registers..................................................... 75
Advanced Interrupt Controller (AIC)......................... ............................. ...... 76
Priority Controller ........................................................................................... 77
Interrupt Handling........................................................................................... 77
Standard Interrupt Sequence......................................................................... 78
Fast Interrupt.................................................................................................. 79
Software Interrupt........................................................................................... 79
Spurious Interrupt........................................................................................... 80
AIC User Interface............................................................................................. 81
AIC Source Mode Register ............................................................................ 82
AIC Interrupt Vector Registers ....................................................................... 83
AIC FIQ Vector Register ................................................................................ 83
AIC Interrupt Status Register ......................................................................... 84
AIC Interrupt Mask Register........................................................................... 84
AIC Core Interrupt Status Register ................................................................ 85
AIC Interrupt Enable Command Register....................................................... 85
iv AT75C221 6033A–INTAP–03/04
AIC Interrupt Disable Command Register...................................................... 86
AIC Interrupt Clear Command Register ......................................................... 86
AIC Interrupt Set Command Register ............................................................ 87
AIC End of Interrupt Command Register ....................................................... 87
AIC Spurious Interrupt Vector Register.......................................................... 88
Parallel I/O C o n tr o ll e r (P I O ) .... .. .................................................................... 89
Output Selection............................................................................................. 89
I/O Levels....................................................................................................... 89
Interrupts........................................................................................................ 89
I/O Line Control.............................................................................................. 90
Parallel I/O Controller (PIO) User Interface .................................................... 91
PIO Enable Register ...................................................................................... 92
PIO Disable Register...................................................................................... 92
PIO Status Register ....................................................................................... 93
PIO Output Enable Register........................................................................... 93
PIO Output Disab le Regist er................... ....... ...... ....... ................... ....... ...... ... 94
PIO Output Status Register............................................................................ 94
PIO Set Output Data Register........................................................................ 95
PIO Clear Output Data Register..................................................................... 95
PIO Output Data Status Register................................................................... 96
PIO Pin Data Status Register......................................................................... 96
PIO Interrupt Enable Register........................................................................ 97
PIO Interrupt Disable Register ....................................................................... 97
PIO Interrupt Mask Register........................................................................... 98
PIO Interrupt Status Register......................................................................... 98
Universal Asynchronous Receiver Transmitter (UART)......... .............. ..... 99
Block Diagram................................................................................................ 99
Pin Description............................................................................................. 100
Baud Rate Generat or..... ...... ...... ....... ................... ....... ...... ....... ...... ....... ...... . 100
Receiver Operati ons ...... ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... .............. 101
Transmitter................................................................................................... 102
Channel Modes............................................................................................ 102
Peripheral Data Controller............................................................................ 103
Modem Control and Status Signals.............................................................. 104
Universal Asynchronous Receiver/Transmitter (UART) User Interface .... 105
UART Control Register ................................................................................ 106
UART Mode Register................................................................................... 107
UART Interrupt Enable Register .................................................................. 109
UART Interrupt Disable Register.................................................................. 110
UART Interrupt Mask Register..................................................................... 111
UART Channel Status Register ................................................................... 112
UART Receiver Holding Register................................................................. 113
UART Transmitter Holding Register............................................................. 113
v
AT75C221
6033A–INTAP–03/04
UART Baud Rate Generator Register.......................................................... 114
UART Receive Pointer Register................................................................... 114
UART Receive Counter Register................................................................. 115
UART Transmit Pointer Register.................................................................. 115
UART Transmit Counter Register................................................................ 116
Modem Control Register.............................................................................. 116
Modem Status Register................................................................................ 117
Timer/Counter (TC)...... ................................... .................... .. .................... ... 118
Block Diagram.............................................................................................. 118
Signal Name Description.............................................................................. 119
Description ................................................................................................... 119
Capture Operating Mode.............................................................................. 122
Waveform Operating Mode.......................................................................... 123
Timer/Counter (TC) User Interface................................................................ 127
TC Block Control Register............................................................................ 128
TC Block Mode Register .............................................................................. 129
TC Channel Control Register....................................................................... 130
TC Channel Mode Register: Capture Mode................................................. 131
TC Channel Mode Register: Waveform Mode ............................................. 133
TC Counter Value Register.......................................................................... 136
TC Register A............................................................................................... 137
TC Register B............................................................................................... 137
TC Register C .............................................................................................. 137
TC Status Register....................................................................................... 138
TC Interrupt Enable Register ....................................................................... 139
TC Interrupt Disable Register....................................................................... 140
TC Interrupt Mask Register.......................................................................... 141
Serial Peripheral Interface (SPI)............. .. ................ .. ..... .. ...................... .. . 142
Overview ...................................................................................................... 142
Block Diagram.............................................................................................. 143
Connections................................................................................................. 144
Pin Name List .............................................................................................. 144
Master Mode Operations.............................................................................. 144
SPI Slave Mode ........................................................................................... 149
Data Transfers ............................................................................................. 149
Clock Generation ......................................................................................... 151
Serial Peripheral Interface (SPI) User Interface ........................................... 152
SPI Control Register .................................................................................... 153
SPI Mode Register....................................................................................... 154
SPI Receive Data Register .......................................................................... 156
SPI Transmit Data Register ......................................................................... 156
SPI Status Register...................................................................................... 157
SPI Interrupt Enable Register ...................................................................... 158
vi AT75C221 6033A–INTAP–03/04
SPI Interrupt Disable Register...................................................................... 158
SPI Interrupt Mask Register......................................................................... 159
SPI Chip Select Register.............................................................................. 160
SPI Receive Pointer Register....................................................................... 162
SPI Receive Counter Register ..................................................................... 162
SPI Transmit Pointer Register...................................................................... 163
SPI Transmit Counter Register .................................................................... 163
Mechanical Characteristics and Packaging................................................. 164
BGA Packaging Information......................................................................... 164
BGA Package Data...................................................................................... 165
PQFP Packaging Information....................................................................... 166
PQFP Package Data.................................................................................... 167
Document Details ........................................................................................... 168
Revision History ........................................................................................... 168
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