Circuit Systems, Inc. 1CS9176-03 Low Skew Output Buffer General Description The 1CS9176-03 is designed specifically to support the tight timing requirements of high-performance microprocessors and chip sets. Because the jitter of the device is limited to +250ps, the [CS9176-03 is ideal for clocking Pentium systems. The 10 high drive (40mA), low-skew (+250ps) outputs make the 1CS9176-03 a perfect fit for PCI clocking requirements. The 1CS9176-03 has 10 outputs synchronized in phase and frequency to an input clock. The internal phase locked loop (PLL) acts either as a 1X clock multiplier or a 1/2X clock multiplier depending on the state of the input contro! pins TO and T1. With metal mask options, any type of ratio between the input clock and output clock can be achieved, including 2X. The PLL maintains the phase and frequency relationship be- tween the input clock and the outputs by externally feeding back FBOUT to FBIN. Any change in the input will be tracked by all 10 outputs. However, the change at the outputs will happen smoothly so no glitches will be present on any driven input. The PLL circuitry matches rising edges of the input clock and the output clock. Since the input to FBIN skew is guaran- teed to +500ps, the part acts as a zero delay buffer. The ICS9176-03 has a total of eleven outputs. Of these, FBOUT is dedicated as the feedback into the PLL and another, Q/2, has an output frequency half that of the remaining nine. These nine outputs can either be running at the same speed as the input, or at half the frequency of the input. With Q/2 as the feedback to FBIN, the nine Q outputs will be running at twice the input frequency in the normal divide-by-1 mode. In this case, the output can go to 120 MHz with a 60 MHz input clock. The maximum rise and fall time of an output is 14ns and each is TTL-compatible with a 40mA symmetric drive. The [CS9176-03 is fabricated using CMOS technology which results in much lower power consumption and cost compared with the gallium arsenide based 1086E. The typical operating current for the 1CS9176-03 is 60mA versus 115mA for the GA1086E. Features e 3.3 or 5.0 volt supply operation +500ps skew (max) between input and outputs @ +250ps skew (max) between outputs 10symmetric, TLL-compatible outputs e = =28-pin PLCC surface mount package e = High drive, 40mA outputs Power-down option Output frequency range 20 MHz to 120 MHz Input frequency range 20 MHz to 100 MHz Ideal for PCI bus applications Selection Table fom | T | DESCRIPTION | ; 0 | 0. 'Power-down | 1 Test Mode (PLL Off CLK=outputs) | 0 [Normal (PLL. On) _ | 1 [Divide by2Mode Block Diagram FBOUT Q1 Q2 CLK Q3 Q4 Q5 6 Q7 Qa Qg Qi2 DIVIDE LOGIC TO 11 CONTROL LOGIC Pentium is a trademark of tntel Corporation. ICS9176-03RevA120195 D-611CS9176-03 Pin Configuration z a B, 38998 Gun = 1 28 & a7 os 43 2 Voo To vod VDD | 4 25 l= GND voo JJ as GND 5 & 24 = a5 of : So BE BS our ENO (pin?) vp 8 = 2 as FBOUT a CLK 4 9 & 20 a2 ag Q6 T1 | 10 19 GND vod 79)) FBIN = 11 18 Fe VDD TO =| 12 17 ai VDD y 13 16" FBOUT Q/2 "1 14 15 fF" GND 28-Pin PLCC 28-Pin SOIC J-10 J-7 Pin Descriptions [ PINNUMBER | PINNAME TYPE DESCRIPTION 1 GND - GROUND. _. Se 2 'Qs Output Output clock 8. _ 3 Qo Output Output clock 9. - _ 4 VDD - jPower supply. _ . _ 5 :GND. - GROUND. - - 6 | NC No Connect. _ 7 NC, of INo Connect. _ _ 8 ___|VDD Pr - Power supply. a a CLK _t Input Input for reference clock. __ oe . 10 - Tl Input T! selects normal operation, power-down, or test mode. _ Jl | FBIN Input FEEDBACK INPUT from output FBOUT. 2. TO _ Input TO selects normal operation, power-down, or test mode. 13. VDD - Power Supply. __ - 14, |Q/2 Output Half-clock output. _ 15. GND wo tn. . .. |GROUND. coe _ _16 FBOUT | .., Output __ |. FEEDBACK OUTPUT to input FBIN. 17 Ql | ..., Output Output clock 1. - 18 VDD | - Power Supply. . 19 |GND |. - |GROUND. 20. iQ2 ; Output __ Output clock 2. 21 :Q3. | Output _| Output clock 3. _22 ,YDD . - Power supply. 23 \Q4_ _ _Qutput____ [Output clock 4. 24 Q5 : Output Output clock 5. _ 25 GND | -_ GROUND. 2 VDD - [Power Supply. 27 6 _ Output Output clock 6, _ 8 QT. nn Output Output clock 7 D-62ICS9176-03 Timing Diagrams INPUT CLOCK oo LI LI LI Le es Timing in Divide by 1 Mode INPUT CLOCK | | | | | LJ ao Li J LJ Timing in Divide by 2 Mode INPUT CLOCK Q1-Q9 on | J e_- Wt we Timing in Eliminate by Test Mode Note: In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is transparent. Damage to the device may occur if an output is shorted or forced to ground or VDD. INPUT CLOCK Q1 - Q9 Q/2 Timing in Power-down Mode D-63ICS9176-03 Absolute Maximum Ratings VDD referenced toGND ...............-.05-5. 7V Operating Temperature under bias............... 0C to +70C Storage Temperature... 0.0.0.0... 0 2.00.0 eee eee -65C to +150C Voltage on I/O pins referenced toGND........... GND -0.5V to VDD +0.5V Power Dissipation. .... 00.0.0. 2c eee eee 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics 3.3 Volt DC Characteristics Vpp = +3.3Vt5%, Ta=0C to 70C unless otherwise stated PARAMETER | SYMBOL | TESTCONDITIONS , MIN | TYP = MAX UNITS | Input Low Voltage : VIL Vpp=3.3V - | _ 0.8 v I Input High Voltage Vin | Vpp=3.3V 20 | - | oywe Input Current | ot |MinsOV, 5V ee | LA | Output Low Voltage | Vo. | @IoL=14mA - | 0.25 0.4 Vv | Output Low Current = Jon. @ VoL =0.8V | 3 0a | - | mA | Output High Voltage , VOH | @lon=-38mA ; 2.4 - - | v Output High Current | lon =, @Von=2.0V - | -59 , Al mA | 5.0 Volt DC Characteristics Vpp = +5V45%, Ta=0C to 70C unless otherwise stated _ | PARAMETER SYMBOL | TESTCONDITIONS MIN | TYP | MAX | UNITS | Input Low Voltage Vi 'Vpp=5V - | - 0.8 v | | Input High Voltage VIH Vop=5V 2.0 - - fo ov t Input Current ; I Vin=0V, 3Vv_ | 5 - 5 | pA Output Low Voltage VOL :@loL=l4mA - 0.25 0.4 Vv | Output Low Current = | Tok, @ VoL =0.8V | 33 | 42 - mA Output High Voltage == Von_| @lon=-38mA 2400 - | - | Vv | ' Output High Current lou | @Voue2.0v - -59 -41 . mA D-64ICS9176-03 AC Characteristics (3.3 volt supply) | PARAMETER | SYMBOL | TESTCONDITIONS | MIN | TYP = MAX | UNITS | Input Clock Pulse Width* CLKw | Vdd=4.5V, fcLKk=100 MHz 2.5 | - 75 ns f * : | Output Rise time, 0.8 to | ty | 1SpF load - | (07 1 | ons | 20Ve Po | | | | ! Rise time, 20% to 80% tr | 15pF load - Ls 2 | ns Vpp* ; / ; / 7 ; ; - | ; | . Output Fall time, 2.0V to tf So load | - 0.7 1 : ns 0.8V* 1 i i : Fall time, 80% 10 20% | te _. 15pF load ; - ar 2 | ns | Vpp* - ; | | : Output Duty cycle* | di | 15pF load 1 45 | 495155 | % Jitter, 1 sigma* : Tis - - 60 | - . ps Jitter, absolute | Tabs 1. 250 | 100 250 | ps Input Frequency _ 7 fi [ ; 20 / | 100, MHz Output Frequency | fo | 20 - 120; MHz |(Q outputs) oo. oe oe | |. FBIN to IN skew | tskewl Note 1, 3. Input rise ume | -500 250 0 ps '<3ns | Skew between any 2 out- | tskew2 ~([Note 1, 3. -250 | 50 | 250 ps puts at same frequency | | | Skew between any 1 out- 3 | ns | ke Notes: 1. All skew specifications are measured with a 50Q transmission line, load terminated with 50Q to 1.4V. 2. Duty cycle measured at 1.4V. 3. Skew measured at 1.4V on rising edges. Loading must be equal on outputs. * Guaranteed by design and characterization. Not subject to 100% test. D-65ICS9176-03 AC Characteristics (5.0 volt supply) "PARAMETER. SYMBOL [ TESTCONDITIONS | MIN i TYP. | MAX | UNITS. Input Clock Pulse Width* ! CLKw | Vdd=4.5V, fcLK=100 MHz | 2.5 . - | 75 ns Output Rise time, 0.8 to, tr ISpF load - 0.7 1 ns 2.0V" | | - Rise time, 20% to 80% tr I5pF load | - 1.5 2 | ns Vpp* . . | : | Output Fall time, 2.0V to , tr 15pF load | - | 0.7 | l ns 0.8V* | : i | Fall time, 80% to 20% tr ISpF load / - | 1.2 2 ' ns Output Duty cycle* dr |1SpF load 45 49/51! 355 | % Jitter, | sigma* | Tis , | - 60 | - : ps | Jitter, absolute* Tabs -250 | +100 250 | ps Input Frequency | fi : 20 | - 100 MHz Output Frequency fo 20 - | 120 MHz (Q outputs) | | FBIN to IN skew | tskewi Note 1, 3. Input rise time | -500 250 | 0 ps ; i<3ns | | : | Skew between any 2 out- | tskew2 Note 1, 3. | -250 | 50 250 ps |puts at same frequency | | | | | Skew between any | out- | | | 3 ns | | put and Q/2 aa _ ft | _ | Notes: 1. All skew specifications are measured with a 502. transmission line, load terminated with 50Q to 1.4V. 2. Duty cycle measured at 1.4V. 3. Skew measured at |.4V on rising edges. Loading must be equal on outputs. * Guaranteed by design and characterization. Not subject to 100% test. D-661CS9176-03 Applications FBOUT is normally connected to FBIN to facilitate input to output skew control. However, there is no requirement that the external feedback connection be a direct hardwire from an output pin to the FBIN pin. As long as the signal at FBIN is derived directly from the FBOUT pin and maintains its fre- quency, additional delays can be accommodated. The clock phase of the outputs (rising edge) will be adjusted so that the phase of FBIN and the input clock will be the same. See Figure | for an example. FBIN ICS9176 66 MHz 33 MHz 66 MHz Figure 1 In Figure !, the propagation delay through the divide-by-2 circuit is eliminated. The internal phase-locked loop will adjust the output clock on the ICS9176-03 to ensure zero phase delay between the FBIN and CLK signals, as a result, the rising edge at the output of the divide by two circuit will be aligned with the rising edge of the 66 MHz input clock. This type of configuration can be used to eliminate propagation delay as long as the signal at FBIN is continuous and is not gated or conditional. Ordering Information ICS9176Q-03 or ICS9176M-01 Example: ICS XXXX M -PPP Package Type Q=PLCC, M=SOIC Prefix ICS, AV=Standard Device The 1CS9176-03 is also ideal for clocking multi-processor systems. The 10 outputs can be used to synchronize the opera- tion of CPU cache and memory banks operating at different speeds, Figure 2 depicts a 2-CPU system in which processors and associated peripherals are operating at 66 MHz. Each of the nine outputs operating at 66 MHz are fully utilized to drive the appropriate CPU, cache and memory control logic. The 33 MHz. output is used to synchronize the operation of the slower memory bank to the restart of the system. FBOUT Qi Q2 Q3 Q4 Qs Q6 Q7 Q8 Qs SYSTEM CLOCK MEMORY CONTROL LOGIC GND VDD SLOW MEMORY CONTROL LOGIC (33 MHz) Figure 2 Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) D-67