2010 Microchip Technology Inc. DS39583C-page 1
PIC18FXX20
1.0 DEVICE OVERVIEW
This document includes the programming
specifications for the following devices:
• PIC18F6520
• PIC18F6620
• PIC18F6720
• PIC18F8520
• PIC18F8620
• PIC18F8720
2.0 PROGRAMMING OVERVIEW
OF THE PIC18FXX 20
PIC18FXX2 0 devi ces c an be pro gramm ed usi ng eith er
the high voltage In-Circuit Serial ProgrammingTM
(ICSPTM) method, or the low voltage ICSP method.
Both of these c an be d one with the de vi ce in the us ers ’
system. The low voltage ICSP method is slightly
different than the high voltage method, and these
differences are noted where applicable. This
programming specification applies to PIC18FXX20
devices in all package types.
2.1 Hardware Requirements
In high voltage ICSP mode, the PIC18FXX20 requires
two programmable power supplies: one for VDD and
one for MCLR/VPP. Both supplies should have a
minimum resolution of 0.25V. Refer to Section 6.0 for
additional hardware parameters.
2.1.1 LOW VOLTAGE ICSP
PROGRAMMING
In low voltage ICSP mode, the PIC18FXX20 can be
programmed using a VDD source in the operating
range. This only means that MCLR/VPP does not have
to be brought to a different voltage, but can instead be
left at the normal operating voltage. Refer to
Section 6.0 for additional hardware parameters.
2.2 Pin Diagrams
The pin diagrams for the PIC18FXX20 family are
shown in Figure 2-1. The pin descriptions of these
diagram s do not represent the co mplete functio nality of
the devic e typ es . Users shou ld ref er to the ap prop riate
device data sheet for complete pin descriptions.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXX20
Pin Name During Programming
Pin Name Pin Type Pin Description
MCLR/VPP/RA5 VPP P Program mi ng Enab le
VDD(2) VDD P Power Supply
VSS(2) VSS P Ground
AVDD AVDD P Analog Power Supply
AVSS AVSS P Analog Ground
RB5 PGM I Low Voltage ICSP™ Input when LVP Configuration bit equals ‘1’ (1)
RB6 SCLK I Serial Clock
RB7 SDATA I/O Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: See Section 5.3 for more detail.
2: All power supply and ground must be connected.
Flash Micr ocontr oller Programming Specification
PIC18FXX20
DS39583C-page 2 2010 Microchip Technology Inc.
FIGURE 2-1: PIC18FXX20 FAMILY PIN DIAGRAMS
Note: Not all multiplexed pin definitions are shown. Refer to the appropriate data sheet for complete pin descriptions.
PIC18F6620
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
RE2
RE3
RE4
RE5
RE6
RE7
RD0
VDD
VSS
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE1
RE0
RG0
RG1
RG2
RG3
MCLR/VPP
RG4
VSS
VDD
RF7
RF6
RF4
RF3
RF2
RB0
RB1
RB2
RB3
RB4
RB5
RB6
VSS
OSC2/RA6
OSC1
VDD
RB7
RC4
RC3
RC2
RF0
RF1
AVDD
AVSS
RA3
RA2
RA1
RA0
VSS
VDD
RA4
RA5
RC1
RC0
RC7
RC6
RC5
15
16
31
40
39
27 28 29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 59
64 63 62 61
PIC18F6720
RF5
PIC18F8620
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
4039
64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32
RE2
RE3
RE4
RE5
RE6
RE7
RD0
VDD
VSS
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE1
RE0
RG0
RG1
RG2
RG3
MCLR/VPP
RG4
VSS
VDD
RF7
RF6
RF5
RF4
RF3
RF2
RB0
RB1
RB2
RB3
RB4
RB5
RB6
VSS
OSC2/RA6
OSC1
VDD
RB7
RC4
RC3
RC2
RF0
RF1
AVDD
AVSS
RA3
RA2
RA1
RA0
VSS
VDD
RA4
RA5
RC1
RC7
RC6
RC5
RJ0
RJ1
RH1
RH0
1
2
RH2
RH3
17
18
RH7
RH6
RH5
RH4
RJ5
RJ4
37
RJ7
RJ6
50
49
RJ2
RJ3
19
20
33 34 35 36 38
58
57
56
55
54
53
52
51
60
59
68 67 66 6572 71 70 69
74 73
78 77 76 75
79
80
PIC18F8720
RC0
64L TQFP
80L TQFP
PIC18F6520
PIC18F8520
2010 Microchip Technology Inc. DS39583C-page 3
PIC18FXX20
2.3 Memory Map
The code memory space extends from 0000h to
1FFFFh (128 Kbytes) in eight 16-Kbyte blocks.
Addresses 0000h through 01FFh, however, define a
“Boot Block” region that is treated separately from
Block 1. All of these blocks define code protection
boundaries within the code memory space.
In contra st, code memory panels are defined in 8-Kbyte
boundaries. Panels are discussed in greater detail in
Section 3.2.
TABLE 2-2: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-2: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FXX20 DEVICES
Device Code Memory Size (Bytes)
PIC18F6520 000000h - 007FFFh (32K)
PIC18F8520
PIC18F6620 000000h - 00FFFFh (64K)
PIC18F8620
PIC18F6720 000000h - 01FFFFh (128K)
PIC18F8720
000000h
1FFFFFh
3FFFFFh
01FFFFh
Note: Sizes of memory areas not to scale.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE / DEVICE
32 Kbytes
(PIC18FX520) Address
Range 64 Kbytes
(PIC18FX620) 128 Kbytes
(PIC18FX720) Address
Range
Boot Block 000000h
0007FFh Boot Block Boot Block 000000h
0001FFh
Block 0 000800h
001FFFh Block 0 Block 0 000200h
003FFFh
Block 1 002000h
003FFFh Block 1 Block 1 004000h
007FFFh
Block 2 004000h
005FFFh Block 2 Block 2 008000h
00BFFFh
Block 3 006000h
007FFFh Block 3 Block 3 00C000h
00FFFFh
Unimplemented
Read ‘0’s
008000h
Unimplemented
Read ‘0’s
Block 4 010000h
013FFFh
Block 5 014000h
017FFFh
Block 6 018000h
01BFFFh
1FFFFFh Block 7 01C000h
01FFFFh
PIC18FXX20
DS39583C-page 4 2010 Microchip Technology Inc.
In addition to the code memory space, there are three
blocks in the configuration and ID space that are
accessible to the user through Table Reads and Table
Writes. Their locations in the memory map are shown
in Figure 2-3.
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h thro ugh 200007h. The ID locations
read out normally , even after code protection is applied.
Locations 300000h through 30000Dh are reserved for
the Confi guratio n bits . These bi t s select va riou s device
options, and are described in Section 5.0. These
Configuration bits read out normally, even after code
protection.
Locatio ns 3FFFF Eh and 3FFF FFh are res erved fo r the
Device ID bits. These bits may be used by the
programmer to identify what device type is being
programmed, and are described in Section 5 .0. These
Device ID bits read out normally, even after code
protection.
2.3.1 M EMORY ADDR ESS POINTER
Memory in the addres s space 000000 0h to 3FFFFFh is
addressed via the Table Pointer, which is comprised of
three pointe r regis ters :
• TBLPTRU, at RAM address 0FF8h
• TBLPTRH, at RAM address 0FF7h
• TBLPTRL, at RAM address 0FF6h
The 4-bit command, ‘0000’ (C ore In struct ion), is used
to load the Table Pointer prior to using many Read or
Write operations.
FIGURE 2-3: CONFIGURATION AND ID LOCATIONS FOR PIC18FXX20 DEVICES
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]
ID Location 1 200000h
ID Location 2 200001h
ID Location 3 200002h
ID Location 4 200003h
ID Location 5 200004h
ID Location 6 200005h
ID Location 7 200006h
ID Location 8 200007h
CONFIG1L 300000h
CONFIG1H 300001h
CONFIG2L 300002h
CONFIG2H 300003h
CONFIG3L 300004h
CONFIG3H 300005h
CONFIG4L 300006h
CONFIG4H 300007h
CONFIG5L 300008h
CONFIG5H 300009h
CONFIG6L 30000Ah
CONFIG6H 30000Bh
CONFIG7L 30000Ch
CONFIG7H 30000Dh
Device ID1 3FFFFE h
Device ID2 3FFFFFh
Note: Sizes of memory areas are not to scale.
000000h
1FFFFFh
3FFFFFh
01FFFFh Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
2FFFFFh
2010 Microchip Technology Inc. DS39583C-page 5
PIC18FXX20
2.4 High Level Overview of the
Programming Process
Figure 2-4 shows the high level overview of the
programming process. First, a bulk erase is performed.
Next, the Code Memory, ID Locations, and Data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the Configuration bits are then
programmed and verified.
2.5 Entering High Voltage ICSP
Program/Verify Mode
The hig h volt age ICSP Prog ram/Veri fy mode is entere d
by holding SCLK and SDATA low and then raising
MCLR/VPP to VIHH (high voltage). Once in this mode,
the Code Memory, Data EEPROM, ID Locations, and
Configuration bits can be accessed and pro grammed in
serial fashion.
The sequence that enters the device into the
Program/Verify mode pl aces all unuse d I/Os in the high
impedance state.
2.5.1 ENTERING LOW VOLTAGE ICSP
PROGRAM/VERIFY MODE
When the LVP confi gura tio n b it i s ‘ 1’ (s ee Sec tio n 5.3),
the low voltage ICSP mode is enabled. Low voltage
ICSP Progra m/V erify mod e is entered b y holding SCLK
and SDATA low, p lacing a logic high on PG M, and then
raising MCLR/VPP to VIH. In this mode, the RB5/PGM
pin is dedicated to the programming function and
ceases to be a general purpose I/O pin.
The sequence that enters the device into the
Program/Verify mode, places all unused I/Os in the
high impedance state.
FIGURE 2-5: ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
FIGURE 2-4: HIGH LEVEL
PROGRAMMING FLOW
FIGURE 2-6: ENTERING LOW
VOLTAGE PROGRAM/
VERIFY MODE
MCLR/VPP
P12
SDATA
SDATA = Input
SCLK
VDD
D110
P13
P1
Start
Program Memory
Program IDs
Program Data
Verify Program
Veri fy IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Perform Bulk
Erase
MCLR/VPP
P12
SDATA
SDATA = Input
SCLK
PGM
P15
VDD
VIH
VIH
PIC18FXX20
DS39583C-page 6 2010 Microchip Technology Inc.
2.6 Serial Program/Verify Operation
The SCLK pin is used as a clock input pin and the
SDATA pin is used for enterin g comm and bit s an d dat a
input/output during serial operation. Commands and
data are transmitted on the rising edge of SCLK,
latched on the falling edge of SCLK, and are Least
Significant bit (LSb) first.
2.6.1 4-BIT COMMANDS
All instructions are 20-bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
command, SCLK is cycled four times. The commands
needed for programming and verification are shown in
Table 2-3.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data, or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Figure 2-4. The 4-bit
command is shown MSb first. The command operand,
or “Data Payload”, is shown <MSB><LSB>. Figure 2-7
demonstrates how to serially present a 20-bit
command/operand to the device.
2.6.2 CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to setup
register s as ap propria te for use with oth er comm ands.
TABLE 2-3: COMMANDS FOR
PROGRAMMING
TABLE 2-4: SAMPLE COMMAND
SEQUENCE
FIGURE 2-7: TABLE WRITE, POST-INCREMENT TIMING (1101)
Description 4-Bit
Command
Core Instruction
(Shift in16-bit instruction) 0000
Shift out TABLAT register 0010
Table Read 1000
Table Read, post-inc rem en t 1001
Table Read, post-dec rem en t 1010
Table Read, pre-in cre men t 1011
Table Write 1100
Table Write, post-increment by 2 1101
Table Write, pos t-de cre me nt by 2 1110
Table Write, start programming 1111
4-Bit
Command Data
Payload Core Instruction
1101 3C 40 Table Write,
post-increment by 2
1234
SCLK P5
SDATA
SDATA = Input
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-bit Command
1011
1234
nnnn
P3
P2 P2A
000000 010001111 0
04C3
P4
4-bit Command 16- bit Data Payload
P2B
2010 Microchip Technology Inc. DS39583C-page 7
PIC18FXX20
3.0 DEVICE PROGRAMMING
3.1 High Voltage ICSP Bulk Erase
Erasing Code or Data EEPROM is accomplished by
writing an “erase option” to address 3C0004h. Code
memory may be erased portions at a time, or the user
may era se th e entir e devi ce in one a ction . “Bulk Erase”
operations will also clear any code protect settings
associated with the memory block erased. Erase
options are detailed in Table 3-1.
TABLE 3-1: BULK ERASE OPTIONS
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th SC LK after t he NOP command), s erial executio n
will cease until the erase completes (parameter P11).
During this time, SCLK may continue to toggle, but
SDATA must be held low.
The code s equence to er ase the entire devic e is shown
in Figure 3-1 and the flowchart is shown in Figure 3-2.
FIGURE 3-1: BULK ERASE COMMAND
SEQUENCE
FIGURE 3-2: BULK ERASE FLOW
FIGURE 3-3: BULK ERASE TIMING
Description Data
Chip Erase 80h
Erase Data EEPROM 81h
Erase Boot Block 83h
Erase Block 1 88h
Erase Block 2 89h
Erase Block 3 8Ah
Erase Block 4 8Bh
Erase Block 5 8Ch
Erase Block 6 8Dh
Erase Block 7 8Eh
Erase Block 8 8Fh
Note: A bulk erase is the only way to reprogram
code protect bits from an on-state to an
off-state.
Non-code protect bits are not returned to
default s ettings by a bulk eras e. These bit s
should be programmed to ones, as out-
lined in Section 3.6, "Configuration Bits
Programming".
4-Bit
Command Data
Payload Core Instruction
0000
0000
0000
0000
0000
0000
1100
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
00 80
00 00
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 80h TO 3C0004h to
eras e enti re de vice .
NOP
Hold SDATA low until
erase completes.
Start
Done
Write 80h
To Erase
Entire Device
Load Address
Poi n te r to
3C0004h
Delay P11+P10
Time
n
1234 121516 123
SCLK
P5 P5A
SDATA
SDATA = Input
00011
P11
P10
Erase Time
00 0 000 0 0
12
00
4
0
12 1516
P5
123
P5A
4
0000
n
4-bit Command 4-bit Command 4-b it Command
16-bit
Data Payload
16-bit
Data Payload 16-bit
Data Payload
PIC18FXX20
DS39583C-page 8 2010 Microchip Technology Inc.
3.1.1 LOW VOLTAGE ICSP BULK ERASE
When using low voltage ICSP, the part must be
supplied by the voltage specified in parameter #D111,
if a bulk erase is to be executed. All other bulk erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the bulk erase
limit, refer to the erase methodology described in
Sections 3.1.2 and 3.2.2.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the bulk erase
limit, follow the methodology described in Section 3.3
and write ones to the array.
3.1.2 ICSP MULTI-PANEL SINGLE ROW
ERASE
Irrespective of whether high or low voltage ICSP is
used, it is possible to erase single row (64 bytes of
data) in all panel s at once. For example, in the case of
a 64-Kbyte device (8 panels), 512 bytes through 64
bytes i n e ach panel c an be eras ed simult a ne ous ly du r-
ing each era se sequ ence. In this case, the offs et of the
erase within each panel is the same (see Figure 3-6).
Multi-panel single row erase is enabled by appropri-
ately configuring the Programming Control register
located at 3C 000 6h.
The multi-panel single row erase duration is externally
timed and is controlled by SCLK. After a “Start Pro-
grammin g” co mm an d is issue d (4-bi t, ‘1111’), a NOP is
issued, where the 4th SCLK is held high for the
duration of the programming time, P9.
After SC LK is bro ugh t lo w, the programming seq ue nce
is terminated. SCLK must be held low for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to program a PIC18FXX20 device
is shown in Table 3-2. The flowchart shown in
Figure 3-4 depicts the logic necessary to completely
erase a PIC18FXX20 device. The timing diagram that
details the “Start Programming” command, and
parameters P9 and P10 is shown in Figure 3-7.
Note: The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
2010 Microchip Technology Inc. DS39583C-page 9
PIC18FXX20
TABLE 3-2: ERASE CODE MEMORY CODE SEQUENCE
FIGURE 3-4: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW
4-Bit
Command Data Payload Core Instruction
St ep 1: Direc t access to config memory.
0000
0000
0000
8E A6
8C A6
86 A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
BSF EECON1, WREN
St ep 2: Configure device for multi-panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 40
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 40h to 3C0006h to enable multi-panel erase.
St ep 3: Direct access to code memory and enable erase.
0000
0000
0000
0000
0000
0000
8E A6
9C A6
88 A6
6A F8
6A F7
6A F6
BSF EECON1, EEPGD
BCF EECON1, CFGS
BSF EECON1, FREE
CLRF TBLPTRU
CLRF TBLPTRH
CLRF TBLPTRL
Step 4: Erase single row of all panels at an offset.
1111
0000
<DummyLSB>
<DummyMSB>
00 00
Write 2 dummy bytes and start programming.
NOP - hold SCLK high for time P9.
Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased.
Done
Start
Delay P9 + P10
Time for Erase
to occur
All
Panels
Done?
No
Yes
Addr = 0
Configure
Device for
Multi-Panel Erase
Addr = Addr + 64
Start Erase Sequence
and hold SCLK High
Until Done
PIC18FXX20
DS39583C-page 10 2010 Microchip Technology Inc.
3.2 Code Memory Programming
Programming code memory is accomplished by first
loading dat a int o the appro priate wr ite bu ffe rs an d then
initiating a programming sequence. Each panel in the
code memory space (see Figure 2-2) has an 8-byte
deep w rite buffer that must be load ed pri or to init iat ing
a write sequence. The actual memory write sequence
takes the contents of these buffers and programs the
associated EEPROM code memory.
Typically, all of the program buffers are written in
paral lel (Multi-Panel W rite mode). In othe r words, in the
case of a 128-Kbyte device (16 panels with an 8-byte
buffer per panel), 128 bytes will be simultaneously
programmed during each programming sequence. In
this cas e, the of fset of t he write with in each p anel is the
same (see Figure 3-5). Multi-Panel Write mode is
enabled by ap prop riately confi guri ng the Programming
Control register located at 3C0006h.
The programming duration is externally timed and is
controlled by SCLK. After a “Start Programming”
command is issued (4-bit command, ‘1111’), a NOP is
issued, where the 4th SCLK is held high for the
duration of the programming time, P9.
Aft er SCLK i s b roug ht l ow, the programm ing se que nc e
is terminated. SCLK must be held low for the time
specified by parameter P10 to allow high voltage
discharge of the memory array.
The code sequence to program a PIC18FXX20 device
is shown in Figure 3-3. The flowchart shown in
Figure 3-6 depicts the logic necessary to completely
write a PIC18FXX20 device. The timing diagram that
details the “Start Programming” command, and
parameters P9 and P10, is shown in Figure 3-7.
Note: The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
2010 Microchip Technology Inc. DS39583C-page 11
PIC18FXX20
FIGURE 3-5: ERASE AND WRITE BOUNDARIES
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLP T R<2 1:13 > = 0
Offset = TBLPTR<12:6>
Panel 1
Erase Region
(64 bytes)
8-byte Write Buffer
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = 1
Offset = TBLPTR<12:6>
Panel 2
Erase Region
(64 bytes)
8-byte W rite Buffer
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = 2
Offset = TBLPTR<12:6>
Panel 3
Erase Region
(64 bytes)
8-byte Write Buffer
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = (n – 1)
Offset = TBLPTR<12:6>
Panel n
Erase Region
(64 bytes)
8-byte Write Buffer
Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.
PIC18FXX20
DS39583C-page 12 2010 Microchip Technology Inc.
TABLE 3-3: WRITE CODE MEMORY CODE SEQUENCE
4-Bit
Command Data Payload Core Instruction
St ep 1: Direct access to config memory.
0000
0000
0000
8E A6
8C A6
86 A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
BSF EECON1, WREN
St ep 2: Configure device for multi-panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 40
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 40h to 3C0006h to enable multi-panel writes.
St ep 3: Direct access to code memory.
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 4: Load write buffer for Panel 1.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1100
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes
St ep 5: Repeat for Panel 2.
Step 6: Repeat for all but the last panel (N – 1).
Step 7: Load write buffer for last panel.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold SCLK high for time P9
To continue writing data, repeat steps 2 through 5, where the Address Pointer is incremented by 8 in each panel at each iteration of
the loop.
2010 Microchip Technology Inc. DS39583C-page 13
PIC18FXX20
FIGURE 3-6: PROGRAM CODE MEMORY FLOW
FIGURE 3-7: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)
Start Write Sequence
All
Locations
Done?
No
Done
Start
Yes
Delay P9+P10 Time
for Wr i te to O c cu r
Load 8 Bytes
to Panel N Write
Buffer at <Addr>
All
Panel Buffers
Written?
No
Yes
and Hold SCLK
High Until Done
N = 1
LoopCount = 0
Configure
Device for
Multi-Panel Writes
N = 1
LoopCount =
LoopCount + 1
N = N + 1
Panel Base Address =
(N – 1) x 2000h
Addr = Panel Base Address
+ (8 x LoopCount)
1234 12 1516 123 4
SCLK
P5A
SDATA
SDATA = Input
n
1111
34 65
P9
P10
Programming Time
nnn nn n n 0 0
12
000
16-bit
Data Payload
0
3
0
P5
4-bit Command 16-bit Data Payload 4-bit Command
PIC18FXX20
DS39583C-page 14 2010 Microchip Technology Inc.
3.2.1 SINGLE PANEL PROGRAMMING
The programming example presented in Section 3.2
utilizes multi-panel programming. This technique
greatly decreases the tot al amount of time necessary to
completely program a device and is the recommended
method of com pl etel y prog ram mi ng a devi ce .
There may be situations, however, where it is
advantageous to limit writes to a single panel. In such
cases, the user only needs to disable the multi-panel
write feature of the device by appropriately configuring
the programming control register located at 3C0006h.
The single panel that will be written will automatically
be enabled based on the value of the Table Pointer.
3.2.2 MODIFYING CODE MEMORY
All of the programming examples up to this point have
assum ed tha t the dev ic e has bee n bulk er ased prior to
programming (see Section 3.1). It may be the case,
however, that the user wishes to modify only a section
of an already programmed device.
The minim um am ount of dat a that c an be wri tten to the
device is 8 bytes. This is accomplished by placing the
device i n Single Pan el Wr ite m ode (s ee Sec ti on 3.2.1),
loading the 8-byte write buffer for the panel, and then
initiating a write sequence. In this case, however, it is
assumed that the address space to be written already
has data in it (i.e., it is not blank).
The minimum amount of code memory that may be
erased at a given time is 64 bytes. Again, the device
must be placed in Single Panel Write mode. The
EECON1 register must then be used to erase the
64-byte t arg et sp a ce prio r to writing the data.
When using the EECON1 register to act on
code memory, the EEPGD bit must be set
(EECON1<7> = 1) and the CFGS bit mu st be cleared
(EECON1<6> = 0). The WREN bit must be set
(EECON1<2> = 1) to enable writes of any sort (e.g.,
erases), and this must be done prior to initiating a
write sequence. The FREE bit must be set
(EECON1<4> = 1) in order to erase the program
space being pointed to by the Table Pointer. The
erase sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is strongly recommended that
the WREN bit be set on ly when abs ol utely n ec e ss ary.
To help prevent inadvertent writes when using the
EECON1 re gister , EECON2 is used to “ena ble” the WR
bit. This register must be sequentially loaded with 55h
and then AAh, immediately prior to asserting the WR bit
in order for the write to occur.
The erase will begin on the falling edge of the 4th
SCLK, af ter the WR bit is set. Afte r the erase sequence
terminates, SCLK must still be held low for the time
specified by parameter #P10 to allow high voltage
discharge of the memory array.
Note: Even though multi-panel writes are dis-
abled, t he user mu st still fil l the 8-byte w rite
buffe r for the given panel.
2010 Microchip Technology Inc. DS39583C-page 15
PIC18FXX20
TABLE 3-4: MODIFYING CODE MEMORY
4-Bit
Command Data Payload Core Instruction
St ep 1: Direct access to config memory.
0000
0000 8E A6
8C A6 BSF EECON1, EEPGD
BSF EECON1, CFGS
St ep 2: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes.
St ep 3: Direct access to code memory.
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
St ep 4: Set the Table Pointer for the block to be erased.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 5: Enable memory writes and set up an erase.
0000
0000 84 A6
88 A6 BSF EECON1, WREN
BSF EECON1, FREE
Step 6: Perform required sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 55h
MOVWF EECON2
MOVLW 0AAh
MOVWF EECON2
Step 7: Initiate erase.
0000
0000 82 A6
00 00 BSF EECON1, WR
NOP
Step 8: Wait for P11+P10 and then disable writes.
0000 94 A6 BCF EECON1, WREN
Step 9: Load write buffer for panel. The correct panel will be selected based on the Table Pointer.
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold SCLK high for time P9
To continue writing data, repeat step 8, where the Address Pointer is incremented by 8 at each iteration of the loop.
PIC18FXX20
DS39583C-page 16 2010 Microchip Technology Inc.
3.3 Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
Address Poin ter (register p air EEADR:EEADRH) and a
data latch (EEDATA). Data EEPROM is written by
loading EEADR:EEADRH with the desired memory
location, EEDATA with the data to be written, and
initiating a memory write by appropriately configuring
the EECON1 and EECON2 registers. A byte write
automatically erases the location and writes the new
data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EEC ON1< 2> = 1) to enable writes of any sort,
and this must be done prior to initiating a write
sequen ce. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongl y recom me nde d
that the WREN bit be set only when absolutely
necessary.
To help prevent inadvertent writes when using the
EECON1 re gister , EECON2 i s used to “enable ” the WR
bit. This register must be sequentially loaded with 55h
and then AAh, immediately pri or to asserting the WR bit
in order for the write to occur.
The write begins on the falling edge of the 4th SCLK
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, SCLK
must still be held low for the time specified by
parameter P10 to allow high voltage discharge of the
memory array.
FIGURE 3-8: PROGRAM DAT A FL OW
FIGURE 3-9: DATA EEPROM WRITE TIMING
Start
St ar t Write
Set Data
Done
No
Yes
Done
?
Enable Write
Unlock Sequence
55h - EECON2
AAh - EECON2
Sequence
Set Address
WR bit
Clear ? No
Yes
n
SCLK
SDATA
SDATA = Input
0000
BSF EECON1, WR
4-bit Command
1234 121516
P5 P5A
P10 12
n
Poll WR bit, Repeat Until Clear
16-bit Data
Payload
1234 121516 123
P5 P5A
41 2 15 16
P5 P5A
0000
MOVF EECON1, W, 0
4-bit Command
0000
4-bit Command Shift Out Data
MOVWF TABLAT
SCLK
SDATA
(see below)
(see Figure 4-6)
SDATA = Input SDATA = Output
Poll WR bit
2010 Microchip Technology Inc. DS39583C-page 17
PIC18FXX20
TABLE 3-5: PROGRAMMING DATA MEMORY
4-Bit
Command Data Payload Core Instruction
St ep 1: Direct access to data EEPROM.
0000
0000 9E A6
9C A6 BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0000
0000
0E <Addr>
6E A9
OE <AddrH>
6E AA
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
Step 3: Load the data to be written.
0000
0000 0E <Data>
6E A8 MOVLW <Data>
MOVWF EEDATA
Step 4: Enable memory writes.
0000 84 A6 BSF EECON1, WREN
Step 5: Perform required sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 0X55
MOVWF EECON2
MOVLW 0XAA
MOVWF EECON2
Step 6: Initiate write.
0000 82 A6 BSF EECON1, WR
Step 7: Poll WR bit, repeat until the bit is clear.
0000
0000
0010
50 A6
6E F5
<LSB><MSB>
MOVF EECON1, W, 0
MOVWF TABLAT
Shift out data(1)
Step 8: Disable writes.
0000 94 A6 BCF EECON1, WREN
Repeat steps 2 through 8 to write more data.
Note 1: See Figure 4-4 for details on Shift Out Data timing.
PIC18FXX20
DS39583C-page 18 2010 Microchip Technology Inc.
3.4 ID Location Programming
The ID Locations are programmed much like the code
memory, except that multi-panel writes must be
disabled. The single panel that will be written will
automatically be enabled, based on the value of the
Table Pointer. The ID registers are mapped in
address es 20 0000h throug h 2000 07h. T hese locat ions
read out normal ly, even af ter code protection.
Figure 3-6 demonstrates the code sequence required
to write the ID locations.
TABLE 3-6: WRITE ID SEQUENCE
In order to modify the ID locations, refer to the
methodology described in Section 3.2.2, “Modifying
Code Mem ory ”. As with co de m em ory, the ID locations
must be erased before modified.
Note: Even though multi-panel writes are dis-
abled, the user must stil l fill the 8-byte dat a
buffer for the panel.
4-Bit
Command Data Payload Core Instruction
St ep 1: Direct access to config memory.
0000
0000 8E A6
8C A6 BSF EECON1, EEPGD
BSF EECON1, CFGS
St ep 2: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes.
St ep 3: Direct access to code memory.
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 4: Load write buffer. Panel will be automatically determined by address.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold SCLK high for time P9
2010 Microchip Technology Inc. DS39583C-page 19
PIC18FXX20
3.5 Boot Block Programming
The Boot Block segment is programmed in exactly the
same manner as the ID locations (see Section 3.4).
Multi-panel writes must be disabled so that only
address es in the rang e 000 0h to 01 FFh wil l be wr itte n.
The code sequence detailed in Figure 3-6 should be
used, ex cept t hat the addres s dat a use d in “Step 2” will
be in the range 000000h to 0001FFh.
3.6 Configuration Bit s Programming
Unlike code memory, the configuration bits are
programmed a byte at a time. The “Table Write, Begin
Programming” 4-bit command (1111) is use d, bu t onl y
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses,
and the MSB will be written to odd addresses. The
code sequence to program two consecutive
configuration locations is shown in Figure 3-7.
TABLE 3-7: SET ADDRESS POINTER TO CONFIGURATION LOCATION
FIGURE 3-10: CONFIGURATION PROGRAMMING FLOW
4-Bit
Command Data Payload Core Instruction
St ep 1: Direct access to config memory.
0000
0000 8E A6
8C A6 BSF EECON1, EEPGD
BSF EECON1, CFGS
St ep 2: Position the program counter(1).
0000
0000 EF 00
F8 00 GOTO 100000h
Step 3(2): Set Table Pointer for config byte to be written. Write even/odd addresses.
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
INCF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
Note 1: If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
code protection logic may prevent further table write. To avoid this situation, move the program counter outside the code
protection area (e.g., GOTO 100000h).
2: Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration
bits. Always write all the configuration bits before enabling the write protection for configuration bits.
Load Even
Configuration
Start
Program Program
MSB
Done
Delay P9 Time
for Writ e
Delay P9 Time
for Wr i te
LSB
Load Odd
Configuration
Address Address
Done
Start
PIC18FXX20
DS39583C-page 20 2010 Microchip Technology Inc.
4.0 READING THE DEVICE
4.1 Read Code Memory, ID Locations,
and Configurati on Bits
Code memory is accessed one byte at a time via the
4-bit command, ‘1001’ (Table Read, post-increment).
The co ntents of memory p ointed to by the Table Pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the
Table Lat c h and then seriall y output on SDATA.
The 4-bit command is shifted in LSb first. The Table
Read is executed during the next 8 clocks, then shifted
out on S DATA during t he last 8 cloc ks, LSb t o MSb. A
delay of P6 must be introduced after the falling edge of
the 8th SCLK of the operand to allow SDATA to
transition from an input to an output. During this time,
SCLK must be held low (see Figure 4-1). This operation
also increments the Table Pointer by one, pointing to the
next byte in code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFF h a ddre ss s pace, s o i t a ls o a ppl ie s
to the reading of the ID and Configuration registers.
TABLE 4-1: READ CODE MEMORY SEQUENCE
FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
4-Bit
Command Data Payload Core Instruction
Step 1: Set Table Pointer.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 2: Read memory into Table Latch and then shift out on SDATA, LSb to MSb.
1001 00 00 TBLRD *+
1234
SCLK
P5
SDATA
SDATA = Input
Shift Data Out
P6
SDATA = Output
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-bit Command
1001
SDATA = Input
LSb MSb
123456
1234
nnnn
P14
2010 Microchip Technology Inc. DS39583C-page 21
PIC18FXX20
4.2 Verify Code Memory and ID
locations
The veri fy step invo lves read ing back the code memo ry
space and comparing against the copy held in the
programmer’s buffer. Memory reads occur a single byte
at a time, so two bytes must be read to compare
against the word in the programmer’s buffer. Refer to
Section 4.1 for implementation details of reading code
memory.
The Table Pointer must be manually set to 200000h
(base address of the ID locations), once the code
memory has been verified. The post-increment feature
of the Table Read 4-bit command may not be used to
increment the Table Pointer beyond the code memory
space. In a 32-Kbyte device, for example, a
post-increment read of address 7FFFh will wrap the
Table Pointer back to 0000h, rather than point to
unimplemented address 8000h.
FIGURE 4-2: VERI FY CODE MEMORY FLOW
Read Low Byte
Read High byte
Does
Word = Expect
Data? Failure,
Report
Error
All
Code Memory
Verified?
No
Yes
No
Set Pointer = 0
Start
Set Pointer = 200000h
Yes
Read Low Byte
Read High byte
Does
Word = Expect
Data? Failure,
Report
Error
All
ID Locations
Verified?
No
Yes
Done
Yes
No
PIC18FXX20
DS39583C-page 22 2010 Microchip Technology Inc.
4.3 Verify Configuration Bits
A configuration address may be read and output on
SDATA via the 4-bit command, ‘1001’. Configuration
data is read and written in a byte-wise fashion, so it is
not nec essary t o merg e two by tes into a word p rior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.1 for implementation details of reading
configu r ati on data.
4.4 Read Data EEPROM Memory
Data EEPROM is accessed one byte at a time via an
Address Poin ter (register p air EEADR:EEADRH) and a
data latch (EEDAT A). Data EEPROM is read by loadin g
EEADR:EEADRH with the desired memory location
and initiating a memory read by appropriately
configuring the EECON1 register. The data will be
loaded i nto EEDA TA, where it m ay be serially ou tput on
SDATA via the 4-bit command, ‘0010’ (S hift Ou t Data
Holding register). A delay of P6 must be introduced
after the falling edge of the 8th SC LK of the operan d to
allow SDATA to transition from an input to an output.
During this time, SCLK must be held low (see
Figure 4-4).
The command sequence to read a single byte of data
is shown in Figure 4-2.
FIGURE 4-3: READ DATA EEPR OM
FLOW
Start
Set
Address
Read
Byte
Done
No
Yes
Done
?
Mov e to TAB L AT
Shif t Ou t Da ta
2010 Microchip Technology Inc. DS39583C-page 23
PIC18FXX20
TABLE 4-2: READ DATA EEPROM MEMORY
FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TIMING (0010)
4-Bit
Command Data Payload Core Instruction
St ep 1: Direct access to data EEPROM.
0000
0000 9E A6
9C A6 BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0000
0000
0E <Addr>
6E A9
OE <AddrH>
6E AA
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
Step 3: Initiate a memory read.
0000 80 A6 BSF EECON1, RD
Step 4: Load data into the Serial Data Holding register.
0000
0000
0010
50 A8
6E F5
<LSB><MSB>
MOVF EEDATA, W, 0
MOVWF TABLAT
Shift Out Data(1)
Note 1: The <LSB> is undefined. The <MSB> is the data.
1234
SCLK
P5
SDATA
SDATA = Input
Shift Data Out
P6
SDATA = Output
5678 1234
P5A
91011 13 15161412
Fetch Next 4-bit Command
0100
SDATA = Input
LSb MSb
123456
1234
nnnn
P14
PIC18FXX20
DS39583C-page 24 2010 Microchip Technology Inc.
4.5 Verify Data EEPROM
A data EEPROM add res s may b e re ad via a se qu enc e
of core instructions (4-bit command, ‘0000’) and then
output on SDATA via the 4-bit command, ‘0010’ (Shift
Out Data Holding register). The result may then be
immediately compared to the appropriate data in the
programmer’s memory for verification. Refer to
Section 4.4 for implementation details of reading data
EEPROM.
4.6 Blank Check
The term “Blank Chec k” me ans to verify that the device
has no p ro gr amm ed m em ory ce l ls. A ll m e mo rie s mu st
be verified: Code Memory, Data EEPROM, ID
Locations, and Configuration bits. The Device ID
registers (3FFFFEh:3FFFFFh) should be ignored.
A “blank” o r “erased” memory cell will re ad as a ‘1’. So,
“Blank Checking” a device merely means to verify that
all bytes read as FFh, except the Configuration bits.
Unused (reserved) Configuration bits will read ‘0’
(programmed). Refer to Table 5-2 for blank
configuration expect data for the various PIC18FXX20
devices.
Given that “Blank Checking” is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.4 and Sect ion 4.2 for implem ent ation d eta ils.
FIGURE 4-5: BLANK CHECK FLOW
Yes
No
Start
Blank Check Device
Is
Device
Blank? Continue
Abort
2010 Microchip Technology Inc. DS39583C-page 25
PIC18FXX20
5.0 CONFIGURATION WORD
The PIC18FXX20 devices have several configuration
words. These bits can be set or cleared to select
various device configurations. All other memory areas
should be programmed and verified prior to setting
configuration words. These bits may be read out
normally, even after read or code protection.
5.1 ID Locations
A user may sto re ide ntif ic atio n inf orm atio n (ID) in eight
ID locations mapped in 200000h:200007h. It is
recommended that the Most Significant nibble of each
ID be 0Fh. In doing so, if the user code inadvertently
tries to execute from the ID space, the ID data will
execute as NOP.
5.2 Device ID W ord
The device ID word for the PIC18FXX20 is located at
3FFFFEh:3FFFFFh. These bits may be used by the
programmer to identify what device type is being
progra mmed an d re ad out normal ly, even a fter code or
read protect ion .
5.3 Low Volt age Programming (LVP)
Bit
The LVP bit in Configuration register, CONFIG4L,
enables low voltage ICSP programming. The LVP bit
defaults to a ‘1’ from the factory.
If Low V ol tage Program ming mode is no t used, the L V P
bit can be pro grammed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be
programmed by entering the high voltage ICSP mode,
where M CLR/VPP is raised to VIHH. Once the LVP bit is
programmed to a ‘0’, only the high voltage ICSP mode
is available and only the high voltage ICSP mode can
be used to program the device.
TABLE 5-1: DEVICE ID VALUES
Note 1: The normal ICSP mode is always avail-
able, regardless of the state of the LVP
bit, by applying VIHH to the MCLR/VPP
pin.
2: While in low voltage ICSP mode, the RB5
pin can no longer be used as a general
purpose I/O.
Device Device ID Value
DEVID2 DEVID1
PIC18F6520 0Bh 001x xxxx
PIC18F6620 06h 011x xxxx
PIC18F6720 06h 001x xxxx
PIC18F8520 0Bh 000x xxxx
PIC18F8620 06h 010x xxxx
PIC18F8720 06h 000x xxxx
Note: The ‘x’s in DEVID1 contain the device revision code.
PIC18FXX20
DS39583C-page 26 2010 Microchip Technology Inc.
TABLE 5-2: PIC18FXX20 CONFIGURATION BITS AND DEVICE IDS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/
Unprogrammed
Value
300001h CONFIG1H —— OSCSEN —— FOSC2 FOSC1 FOSC0 0010 0111
300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN 0000 1111
300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN 0000 1111
300004h(1) CONFIG3L WAIT — — — — —PM1PM01000 0011
300005h CONFIG3H — — — — — —T1OSCMX
(3) CCP2MX 0000 0001
300006h CONFIG4L DEBUG — — — —LVP —STVREN1000 0101
300008h CONFIG5L CP7(2) CP6(2) CP5(2) CP4(2) CP3 CP2 CP1 CP0 1111 1111
300009h CONFIG5H CPD CPB — — — — — — 1100 0000
30000Ah CONFIG6L WRT7(2) WRT6(2) WRT5(2) WRT4(2) WRT3 WRT2 WRT1 WRT0 1111 1111
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 1110 0000
30000Ch CONFIG7L EBTR7(2) EBTR6(2) EBTR5(2) EBTR4(2) EBTR3 EBTR2 EBTR1 EBTR0 1111 1111
30000Dh CONFIG7H —EBTRB — — — — — — 0100 0000
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18F6X20 devices; maintain this bit set.
2: Unimplemented in PIC18FX620 and PIC18FX520 devices; maintain this bit set.
3: PIC18F8520/8620 devices only.
2010 Microchip Technology Inc. DS39583C-page 27
PIC18FXX20
TABLE 5-3: PIC18FXX20 CONFIGURATION BIT DESCRIPTIONS
Bit Name Configuration
Words Description
OSCEN CONFIG1H Low Power System Clo ck Opti on (Timer1) Enable bit
1 = Disabled
0 = Timer1 oscillator system clock option enabled
FOSC2:FOSC0 CONFIG1H Oscillator Selection bits
111 = RC oscillator w/ OSC2 configured as RA6
110 = HS oscillator w/ PLL enabled
101 = EC oscillator w/ OSC2 configured as RA6
100 = RC oscillator w/ OSC2 configured as “divide by 4 clock output”
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
BORV1:BORV0 CONFIG2L Brown-out Reset Voltage bits
11 =V
BOR set to 2.0V
10 =V
BOR set to 2.7V
01 =V
BOR set to 4.2V
00 =V
BOR set to 4.5V
BOREN CONFIG2L Brown-out Reset Enable bit
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
PWRTEN CONFIG2L Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTPS2:WDTPS0 CONFIG2H Watchdog Timer Postscaler Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
WDTEN CONFIG2H Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
WAIT(1) CONFIG3L External Bus Data Wait Enable bit
1 = Wait selections unavailable
0 = Wait selections determined by WAIT1:WAIT0 bits of MEMCOM
register
PM1:PM0(1) CONFIG3L Processor Mode Select bits
11 = Microcontroller mode
10 = Microprocessor mode
01 = Microprocessor with Boot Block mode
00 = Extended Microcontroller mode
Note 1: Unimplemented in PIC18F6X 20 (64-pin) de vices; maintain this bit set.
2: Unimplement ed in PIC18FX620 devic es; maintain this bit set.
3: PIC18F8 520 /86 20 dev ic es only.
PIC18FXX20
DS39583C-page 28 2010 Microchip Technology Inc.
T1OSCMX(3) CONFIG3H Timer1 Oscillat or MUX bit
1 = Legacy Timer1 oscillator selected
0 = Low power Timer1 oscillator selected
CCP2MX CONFIG3H CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
DEBUG CONFIG4L Background Debugger Enable bit
1 = Background debugger disabled
0 = Background debugger enabled
LVP CONFIG4L Low Voltage Programming Enable bit
1 = Low voltage programming enabled
0 = Low voltage programming disabled
STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit
1 = Stack overflow/underflow will cause RESET
0 = Stack overflow/underflow will not cause RESET
CP0 CONFIG5L Code Protection bits (Block 0)
1 = Code memory not code protected
0 = Code memory code protected
CP1 CONFIG5L Code Protection bits (Block 1)
1 = Code memory not code protected
0 = Code memory code protected
CP2 CONFIG5L Code Protection bits (Block 2)
1 = Code memory not code protected
0 = Code memory code protected
CP3 CONFIG5L Code Protection bits (Block 3)
1 = Code memory not code protected
0 = Code memory code protected
CP4(2) CONFIG5L Code Protection bits (Bl ock 4 )
1 = Code memory not code protected
0 = Code memory code protected
CP5(2) CONFIG5L Code Protection bits (Bl ock 5 )
1 = Code memory not code protected
0 = Code memory code protected
CP6(2) CONFIG5L Code Protection bits (Bl ock 6 )
1 = Code memory not code protected
0 = Code memory code protected
CP7(2) CONFIG5L Code Protection bits (Bl ock 7 )
1 = Code memory not code protected
0 = Code memory code protected
TABLE 5-3: PIC18FXX20 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Unimplemented in PIC18F6X 20 (64-pin) de vices; maintain this bit set.
2: Unimplement ed in PIC18FX620 devic es; maintain this bit set.
3: PIC18F8 520 /86 20 dev ic es only.
2010 Microchip Technology Inc. DS39583C-page 29
PIC18FXX20
CPD CONFIG5H Code Protection bits (Data EEPROM)
1 = Data EEPROM not code protected
0 = Data EEPROM code protected
CPB CONFIG5H Code Protection bits (Boot Block)
1 = Boot block not code protected
0 = Boot block code protected
WRT0 CONFIG6L Table Write Protection bit (Block 0)
1 = Code memory not write protected
0 = Code memory write protected
WRT1 CONFIG6L Table Write Protection bit (Block 1)
1 = Code memory not write protected
0 = Code memory write protected
WRT2 CONFIG6L Table Write Protection bit (Block 2)
1 = Code memory not write protected
0 = Code memory write protected
WRT3 CONFIG6L Table Write Protection bit (Block 3)
1 = Code memory not write protected
0 = Code memory write protected
WRT4(2) CONFIG6L Table Write Protection bit (Block 4)
1 = Code memory not write protected
0 = Code memory write protected
WRT5(2) CONFIG6L Table Write Protection bit (Block 5)
1 = Code memory not write protected
0 = Code memory write protected
WRT6(2) CONFIG6L Table Write Protection bit (Block 6)
1 = Code memory not write protected
0 = Code memory write protected
WRT7(2) CONFIG6L Table Write Protection bit (Block 7)
1 = Code memory not write protected
0 = Code memory write protected
WRTD CONFIG6H Table Write Protection bit (Data EEPROM)
1 = Data EEPROM not write protected
0 = Data EEPROM write protected
WRTB CONFIG6H Table Write Protection bit (Boot Block)
1 = Boot block not write protected
0 = Boot block write protected
WRTC CONFIG6H Table Write Protection bit (Configuration registers)
1 = Configuration registers not write protected
0 = Configuration registers write protected
TABLE 5-3: PIC18FXX20 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Unimplemented in PIC18F6X 20 (64-pin) de vices; maintain this bit set.
2: Unimplement ed in PIC18FX620 devic es; maintain this bit set.
3: PIC18F8 520 /86 20 dev ic es only.
PIC18FXX20
DS39583C-page 30 2010 Microchip Technology Inc.
EBTR0 CONFIG7L Table R ead Protecti on bit (Block 0)
1 = Code memory not protected from table reads executed in other
blocks
0 = Code memory protected from table reads executed in other blocks
EBTR1 CONFIG7L Table R ead Protecti on bit (Block 1)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR2 CONFIG7L Table R ead Protecti on bit (Block 2)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR3 CONFIG7L Table R ead Protecti on bit (Block 3)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR4(2) CONFI G7L Table Read Prote c tion bit (Block 4)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR5(2) CONFI G7L Table Read Prote c tion bit (Block 5)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR6(2) CONFI G7L Table Read Prote c tion bit (Block 6)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTR7(2) CONFI G7L Table Read Prote c tion bit (Block 7)
1 = Code memory not protected from Table Reads executed in other
blocks
0 = Code memory protected from Table Reads executed in other blocks
EBTRB CONFIG7H Table Read Protection bit (Boot Block)
1 = Boot block not protected from Table Reads executed in other blocks
0 = Boot block protected from Table Reads executed in other blocks
DEV10:DEV3 DEVID2 Device ID bits
These bits are used with the DEV2:DEV0 bits in the DEVID1 register to
identify part number.
DEV2:DEV0 DEVID1 Device ID bits
These bits are used with the DEV10:DEV3 bits in the DEVID2 register to
identify part number.
REV4:REV0 DEVID1 These bits are used to indicate the revision of the device.
TABLE 5-3: PIC18FXX20 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Unimplemented in PIC18F6X 20 (64-pin) de vices; maintain this bit set.
2: Unimplement ed in PIC18FX620 devic es; maintain this bit set.
3: PIC18F8 520 /86 20 dev ic es only.
2010 Microchip Technology Inc. DS39583C-page 31
PIC18FXX20
5.4 Embedding Configuration Word
Info rmatio n in th e H EX Fi le
To allow portability of code, a PIC18FXX20
prog r am mer is r e qui r ed to r e ad th e c o nf i gur a ti on w ord
locations from the HEX file. If configuration word
informa tion is not prese nt in the HEX file, then a sim ple
warning message should be issued. Similarly, while
saving a HEX file, all configuration word information
must be included. An option to not include the
configu ration word informatio n may be provided. Whe n
embedding configuration word information in the HEX
file, it should start at address 300000h.
Microchip Technology Inc. feels strongly that this
featur e is imp orta nt for th e bene fit of t he end cu stome r.
5.5 Checksum Comput ation
The check s um is cal cu lat ed by sum mi ng the foll owing:
• The contents of all code memo ry locations
• The configuration word, appropriately masked
• ID locations
The Least Significant 16-bits of this sum are the
checksum.
Table 5-4 (pages 32 through 37) describes how to
calculate the checksum for each device.
Note 1: The checksum calculation differs depend-
ing on the code protect setting. Since the
code memory locations read out differ-
ently, depending on the code protect set-
ting, the table describes how to
manipulate the actual code memory val-
ues to simulate the values that would be
read from a protected device. When cal-
culatin g a chec ksum by readi ng a dev ice,
the entire code memory can simply be
read and summed. The configuration
word and ID locations can always be
read.
PIC18FXX20
DS39583C-page 32 2010 Microchip Technology Inc.
TABLE 5-4: CHECKSUM COMPUTATION
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
PIC18F6520
None SUM(0000:07FF)+SUM(0800:1FFF)+SUM(2000:3FFF)+
SUM(4000:5 FFF) +SUM(6 000 :7FFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0002)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
(CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)
05A8 04FE
Boot
Block SUM(0800:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+
SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+
(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+
(CFGW3H & 0002)+(CFGW4L & 0085)+(CFGW4H & 0000)+
(CFGW5L & 00FF)+(CFGW5H & 00C0)+(CFGW6L & 00FF)+
(CFGW6H & 00E0)+(CFGW7L & 00FF)+(CFGW7H & 0040)+
SUM(IDs)
077F 734
Boot/
Block1/
Block2
SUM(4000:5 FFF) +SUM(6 000 :7FFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0002)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
(CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)+SUM(IDs)
857C 8531
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0002)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)
480 048A
Legend: Item Description
CFGW = Conf igur ation Word
SUM[a:b] = Sum of location s, a to b inc lusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND
2010 Microchip Technology Inc. DS39583C-page 33
PIC18FXX20
PIC18F6620
None SUM(0000:01FF)+SUM(0200:3FFF)+SUM(4000:7FFF)+
SUM(8000:BF FF)+S UM(C00 0:F FFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+
(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+
(CFGW7H & 0040)
02D8 022E
Boot
Block SUM(0200:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+
SUM(C000:FFFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+
(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+
(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H & 0000)+
(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+
(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+
SUM(IDs)
04AF 455
Boot/
Block1/
Block2
SUM(8000:BF FF)+S UM(C00 0:F FFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+
(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+
(CFGW7H & 0040)+SUM(IDs)
82AC 8252
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+
(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+
(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)
02A0 029B
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CFGW = Conf igur ation Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND
PIC18FXX20
DS39583C-page 34 2010 Microchip Technology Inc.
PIC18F6720
None SUM(0000:01FF)+SUM(0200:3FFF)+SUM(4000:7FFF)+
SUM(8000:BFFF)+SUM(C000:FFFF)+SUM(10000:13FFF)+
SUM(14000:17FFF)+SUM(18000:1BFFF)+SUM(1C000:1FFFF)+
(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)
05A8 04FE
Boot
Block SUM(0200:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+
SUM(C000:FFFF)+SUM(10000:13FFF)+SUM(14000:17FFF)+
SUM(18000:1BFFF)+SUM(1C000:1FFFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
(CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)+SUM(IDs)
077F 0734
Boot/
Block1/
Block2
SUM(8000:BFFF)+SUM(C000:FFFF)+SUM(10000:13FFF)+
SUM(14000:17FFF)+SUM(18000:1BFFF)+SUM(1C000:1FFFF)+
(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)
857C 8531
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)
480 048A
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CFGW = Conf igur ation Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND
2010 Microchip Technology Inc. DS39583C-page 35
PIC18FXX20
PIC18F8520
None SUM(0000:07FF)+SUM(0800:1FFF)+SUM(2000:3FFF)+
SUM(4000:5 FFF) +SUM(6 000 :7FFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0002)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
(CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)
05AA 500
Boot
Block SUM(0800:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+
SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+
(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+
(CFGW3H & 0002)+(CFGW4L & 0085)+(CFGW4H & 0000)+
(CFGW5L & 00FF)+(CFGW5H & 00C0)+(CFGW6L & 00FF)+
(CFGW6H & 00E0)+(CFGW7L & 00FF)+(CFGW7H & 0040)+
SUM(IDs)
783 071A
Boot/
Block1/
Block2
SUM(4000:5 FFF) +SUM(6 000 :7FFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0000)+(CFGW3H & 0002)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
(CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)+SUM(IDs)
8580 8517
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0002)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)
484 470
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CFGW = Conf igur ation Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND
PIC18FXX20
DS39583C-page 36 2010 Microchip Technology Inc.
PIC18F8620
None SUM(0000:01FF)+SUM(0200:3FFF)+SUM(4000:7FFF)+
SUM(8000:BFFF)+SUM(C000:FFFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0083)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+
(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+
(CFGW7H & 0040)
035B 02B1
Boot
Block SUM(0200:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+
SUM(C000:FFFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+
(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L & 0083)+
(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H & 0000)+
(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+
(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+
SUM(IDs)
052E 04D4
Boot/
Block1/
Block2
SUM(8000:BFFF)+SUM(C000:FFFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0083)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+
(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+
(CFGW7H & 0040)+SUM(IDs)
832B 82D1
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0083)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+
(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+
(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)
031F 031A
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CFGW = Conf igur ation Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND
2010 Microchip Technology Inc. DS39583C-page 37
PIC18FXX20
5.6 Embedding Data EEPROM
Info rmatio n In th e H EX Fi le
To allow portability of code, a PIC18FXX20
programmer is required to read the data EEPROM
information from the HEX file. If data EEPROM
info rmatio n is not present , a simpl e warnin g messa ge
should be issued. Sim ila rly, when saving a HEX file , al l
data EEPROM inform ation must be inc luded. An optio n
to not include the data EEPROM information may be
provide d. When embeddi ng data EEPROM information
in the HEX file, it should start at address F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.
PIC18F8720
None SUM(0000:01FF)+SUM(0200:3FFF)+SUM(4000:7FFF)+
SUM(8000:BFFF)+SUM(C000:FFFF)+SUM(10000:13FFF)+
SUM(14000:17FFF)+SUM(18000:1BFFF)+SUM(1C000:1FFFF)+
(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0083)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)
062B 581
Boot
Block SUM(0200:3FFF)+SUM(4000:7FFF)+SUM(8000:BFFF)+
SUM(C000:FFFF)+SUM(10000:13FFF)+SUM(14000:17FFF)+
SUM(18000:1BFFF)+SUM(1C000:1FFFF)+(CFGW1L & 0000)+
(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+
(CFGW3L & 0083)+(CFGW3H & 0001)+(CFGW4L & 0085)+
(CFGW4H & 0000)+(CFGW5L & 00FF)+(CFGW5H & 00C0)+
(CFGW6L & 00FF)+(CFGW6H & 00E0)+(CFGW7L & 00FF)+
(CFGW7H & 0040)+SUM(IDs)
07FE 07A4
Boot/
Block1/
Block2
SUM(8000:BFFF)+SUM(C000:FFFF)+SUM(10000:13FFF)+
SUM(14000:17FFF)+SUM(18000:1BFFF)+SUM(1C000:1FFFF)+
(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0083)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)
85FB 85A1
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+
(CFGW2H & 000F)+(CFGW3L & 0083)+(CFGW3H & 0001)+
(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L & 00FF)+
(CFGW5H & 00C0)+(CFGW6L & 00FF)+(CFGW6H & 00E0)+
(CFGW7L & 00FF)+(CFGW7H & 0040)+SUM(IDs)
04FF 04FA
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CFGW = Conf igur ation Word
SUM[a:b] = Sum of locations, a to b inclusive
SUM_ID = Byte-wise sum of lower four bits of all customer ID locations
+ = Addition
& = Bit-wise AND
PIC18FXX20
DS39583C-page 38 2010 Microchip Technology Inc.
6.0 AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Note 1: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program
executions to oc cur. The maxim um tr ansition t ime is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/P LL, and XT modes only)
+ 2 ms (for HS/ PLL mode onl y) + 1. 5 s (for EC mode only )
where TCY is the Instruction Cycle Time, TPWRT is the Power-up Timer Period, and TOSC is the Oscillator Period.
For specific values, refer to the Electrical Characteristics section of the Device Data Sheet for the particular device.
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
No. Sym Characteristic Min Max Units Conditions
D110 VIHH Hi gh Vol tage Programm ing Voltage on
MCLR/VPP 9.00 13.25 V
D110A VIHL Low Voltage Programming Voltage on
MCLR/VPP 2.00 5.50 V
D111 VDD Supply Vo ltage Dur i ng Prog ra m m i ng 2.00 5.50 V Norm al pro gr am m i ng
4.50 5.50 V Bulk er ase oper atio ns
D112 IPP Programming Current on MCLR/VPP —300A
D113 IDDP Supply Current Dur i ng Pr ogrammin g — 10 mA
D031 VIL Input Lo w Voltage VSS 0.2 VDD V
D041 VIH Inp ut High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA @ 4.5V
D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA @ 4.5V
D012 CIO Capacitive Loading on I/O pin (SDATA) — 50 pF To meet AC s p ecifications
P1 TRMCLR/VPP Rise Time to enter
Program/ Verif y m ode —1.0s(N ote 1)
P2 Tsclk Serial Clock (SCLK) Period 100 — ns
P2A TsclkL Serial Clock (SCLK) Low Time 40 — ns
P2B TsclkH Serial Clock (SCLK) High Time 40 — ns
P3 Tset1 Input Data Setup T ime to Serial Clock 15 — ns
P4 Thld1 Input Data Hold Time from SCLK 15 — ns
P5 Tdly1 Delay between 4-bit Command and
Comma nd O perand 40 — ns
P5A Tdly1a Delay between 4-bit Command
Opera nd and next 4-b it C om m and 40 — ns
P6 Tdly2 Delay between Last SCLK of
Com ma nd Byte to First SCL K of Read
of Data Word
20 — ns
P9 Tdly5 SCLK High Time
(minimum programming time ) 1—ms
P10 Tdly6 SCLK Lo w Time af ter Programming
(high voltage di scharg e tim e) 5—s
P11 Tdly7 Delay to allow Self-Timed Data Write or
Bulk Erase to occur 10 — ms
P11A Tdrwt Data Write Polling Time 4 — m s
P12 Thld2 Input Data Hold Time from MCLR/VPP 2—s
P13 Tset2 VDD Setup Time to MCLR/VPP 100 — ns
P14 Tvalid Data Ou t Valid from SCLK 10 — ns
P15 Tset3 PGM Setup Time to MCLR/VPP 2—s
2010 Microchip Technology Inc. DS39583C-page 39
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by updates . I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In - Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLA B Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its f amily of products is one of the most secure famili es of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39583C-page 40 2010 Microchip Technology Inc.
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