Ultrafast, SiGe, Open-Collector
HVDS Clock/Data Buffer
ADCLK914
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
FEATURES FEATURES
7.5 GHz operating frequency 7.5 GHz operating frequency
160 ps propagation delay 160 ps propagation delay
100 ps output rise/fall 100 ps output rise/fall
110 fs random jitter 110 fs random jitter
On-chip input terminations On-chip input terminations
Extended industrial temperature range: −40°C to +125°C Extended industrial temperature range: −40°C to +125°C
3.3 V power supply (VCC − VEE) 3.3 V power supply (VCC − VEE)
APPLICATIONS APPLICATIONS
Clock and data signal restoration Clock and data signal restoration
High speed converter clocking High speed converter clocking
Broadband communications Broadband communications
Cellular infrastructure Cellular infrastructure
High speed line receivers High speed line receivers
ATE and high performance instrumentation ATE and high performance instrumentation
Level shifting Level shifting
Threshold detection Threshold detection
FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM
D
D
Q
V
CC
V
EE
V
T
Q
D
D
Q
V
CC
V
EE
V
T
Q
V
REF
06561-001
50Ω50Ω50Ω50Ω
ADCLK914
Figure 1.
GENERAL DESCRIPTION
The ADCLK914 is an ultrafast clock/data buffer fabricated on
the Analog Devices, Inc., proprietary, complementary bipolar
(XFCB-3) silicon-germanium (SiGe) process. The ADCLK914
features high voltage differential signaling (HVDS) outputs
suitable for driving the latest Analog Devices high speed digital-
to-analog converters (DACs). The ADCLK914 has a single,
differential open-collector output.
The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps
propagation delay and adds only 110 fs random jitter (RJ).
The input has a center tapped, 100 Ω, on-chip termination
resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS
(ac-coupled only). A VREF pin is available for biasing ac-coupled
inputs.
The HVDS output stage is designed to directly drive 1.9 V each
side into 50 Ω terminated to VCC for a total differential output
swing of 3.8 V.
The ADCLK914 is available in a 16-lead LFCSP. It is specified
for operation over the extended industrial temperature range of
−40°C to +125°C.
ADCLK914
Rev. A | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ..............................................7
Applications Information .................................................................9
Power/Ground Layout and Bypassing ........................................9
HVDS Output Stage ......................................................................9
Interfacing to High Speed DACs .................................................9
Optimizing High Speed Performance ........................................9
Random Jitter .................................................................................9
Typical Application Circuits ..................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
10/08—Rev. 0 to Rev. A
Changes to Input Low Voltage Parameter, Table 1 ....................... 3
Changes to Output High Voltage Parameter, Table 1 ................ 3
Changes to Output Low Voltage Parameter, Table 1 .................. 3
Output Differential Range Parameter, Table 1 ............................ 3
Changes to Absolute Maximum Ratings Section ........................ 5
7/08—Revision 0: Initial Version
ADCLK914
Rev. A | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 3.3 V, VEE = 0 V, TA = −40°C to +125°C. All outputs terminated through 50 Ω to VCC, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input High Voltage VIH V
EE + 1.65 VCC V
Input Low Voltage VIL V
EE V
CC − 0.2 V
Input Differential Range VID 0.2 3.4 V p-p
TA = −40°C to +85°C
(±1.7 V between input pins)
0.2 2.8 V p-p
TA = 85°C to 125°C
(±1.4 V between input pins)
Input Capacitance CIN 0.4 pF
Input Resistance 50 Ω
Differential Mode 100 Ω
Common Mode 50 kΩ Open termination
Input Bias Current 20 µA
DC OUTPUT CHARACTERISTICS
Output High Voltage VOH V
CC − 0.55 VCC − 0.40 VCC − 0.25 V
Output Low Voltage VOL V
CC − 2.75 VCC − 2.35 VCC − 1.9 V
Output Differential Range VOD 1.54 1.95 2.22 V
Reference Voltage VREF
Output Voltage (VCC + 1)/2 V −500 A to +500 A
Output Resistance 250 Ω
AC PERFORMANCE
Operating Frequency 7.5 GHz
>1.1 V differential output swing,
VCC = 3.3 V ± 10%
Propagation Delay tPD 127 158 202 ps
VCC = 3.3 V ± 10%,VICM = VREF,
VID = 1.6 V p-p
Propagation Delay Temperature
Coefficient
140 fs/°C
Propagation Delay Skew (Device
to Device)
65 ps VID = 1.6 V p-p
Output Rise Time tR 100 125 ps 20%/80%
Output Fall Time tF 80 95 ps 80%/20%
Wideband Random Jitter1RJ 110 fs rms VID = 1.6 V p-p, 6 V/ns, VICM = 1.85 V
Additive Phase Noise
622.08 MHz −132 dBc/Hz @10 Hz offset
−143 dBc/Hz @100 Hz offset
−151 dBc/Hz @1 kHz offset
−156 dBc/Hz @10 kHz offset
−157 dBc/Hz @100 kHz offset
−156 dBc/Hz >1 MHz offset
245.76 MHz −133 dBc/Hz @10 Hz offset
−143 dBc/Hz @100 Hz offset
−153 dBc/Hz @1 kHz offset
−158 dBc/Hz @10 kHz offset
−159 dBc/Hz @100 kHz offset
−158 dBc/Hz >1 MHz offset
ADCLK914
Rev. A | Page 4 of 12
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
122.88 MHz −150 dBc/Hz @10 Hz offset
−156 dBc/Hz @100 Hz offset
−160 dBc/Hz @1 kHz offset
−161 dBc/Hz @10 kHz offset
−161 dBc/Hz @100 kHz offset
−160 dBc/Hz >1 MHz offset
POWER SUPPLY
Supply Voltage Requirement VCC 2.97 3.63 V
Power Supply Current
Negative Supply Current IVEE 66 111 150 mA Includes output current
Positive Supply Current IVCC 34 55 73 mA
Power Supply Rejection2PSRVCC 13 ps/V VCC = 3.3 V ± 10%
Output Swing Supply Rejection3 −15 dB VCC = 3.3 V ± 10%
1 Calculated from SNR of ADC method. See Figure 8 for rms jitter vs. input slew rate.
2 Change in tPD per change in VCC.
3 Change in output swing per change in VCC.
ADCLK914
Rev. A | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage (VCC to GND) 6.0 V
Input Voltage −0.5 V to VCC + 0.5 V
Maximum Output Voltage VCC + 0.5 V
Minimum Output Voltage VEE − 0.5 V
Input Termination ±2 V
Voltage Reference VCC − VEE
Operating Temperature Range, Ambient −40°C to +125°C
Operating Temperature, Junction 150°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL PERFORMANCE
The ADCLK914 is specified for a case temperature (TCASE). To
ensure that TCASE is not exceeded, use an airflow source.
To determine the junction temperature on the application PCB
TJ = TCASE + (ΨJT × PD)
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the customer at
top center of package.
ΨJT is determined by the values listed in Table 3.
PD is the power dissipation.
Value s of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order
approximation of TJ by the equation
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
Values of θJB are provided for package comparison and PCB
design considerations.
Table 3. Thermal Parameters for ADCLK914 16-Lead LFCSP
Symbol Description1 Value Units
θJA Junction-to-ambient thermal
resistance, 0.0 meters per sec air
flow per JEDEC JESD51-2 (still air)
78.4 °C/W
θJMA Junction-to-ambient thermal
resistance, 1.0 meter per sec air flow
per JEDEC JESD51-6 (moving air)
68.5 °C/W
θJMA Junction-to-ambient thermal
resistance, 2.5 m/s air flow per
JEDEC JESD51-6 (moving air)
61.4 °C/W
θJB Junction-to-board thermal
resistance, 1.0 meter per sec air flow
per JEDEC JESD51-8 (moving air)
48.8 °C/W
θJC Junction-to-case thermal resistance
(die-to-heatsink) per MIL-Std 883,
Method 1012.1
1.5 °C/W
ΨJT Junction-to-top-of-package
characterization parameter, 0
meters per sec air flow per JEDEC
JESD51-2 (still air)
2.0 °C/W
1 Descriptions based on using a 2s2p test board.
ESD CAUTION
ADCLK914
Rev. A | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NC = NO CONNECT
1D
2D
3NC
4NC
11
12
10
9
5
NC
6
NC
7
V
EE
8
V
CC
15 V
REF
16 V
T
14 V
EE
13 V
CC
ADCLK914
TOP VIEW
(Not to Scale)
06561-002
Q
Q
NC
NC
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 D Noninverting Input.
2 D Inverting Input.
3, 4, 5, 6, 9, 10 NC No Connect. No physical connection to the die.
7, 14 VEE Negative Supply Voltage.
8, 13 VCC Positive Supply Voltage.
11 Q Inverting Output.
12 Q Noninverting Output.
15 VREF Reference Voltage. Reference voltage for biasing ac-coupled inputs.
16 VT Center Tap. Center tap of 100 Ω input resistor.
Heat Sink/
Exposed Pad
NC No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit.
It can be left floating for optimal electrical isolation between the package handle and the substrate of the
die. It can also be soldered to ground on the application board if improved thermal and/or mechanical
stability is needed. Exposed metal at the corners of the package is connected to this back surface. Allow
sufficient clearance for vias and other components.
ADCLK914
Rev. A | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0 V, TA = 25°C. All outputs terminated through 50 to VCC, unless otherwise noted.
06561-003
Q
Q
250mV/DI
V
62.5ps/DIV
Figure 3. Output Waveform at 1 GHz, VCC = 3.3 V
–
120
–130
–140
–150
–160
–170
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
06561-004
Figure 4. Phase Noise at 122.88 MHz
–
120
–130
–140
–150
–160
–170
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
06561-005
Figure 5. Phase Noise at 245.76 MHz
06561-006
Q
Q
250mV/DI
V
100ps/DIV
Figure 6. Output Waveform at 1 GHz, VCC = 3.3 V
–
120
–130
–140
–150
–160
–170
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
06561-007
Figure 7. Phase Noise at 622.08 MHz
350
0
012345678
INPUT SLEW RATE (V/ns)
RMS JITTER (fs)
06561-008
300
250
200
150
100
50
T
A
= 25°C
Figure 8. RMS Jitter vs. Input Slew Rate
ADCLK914
Rev. A | Page 8 of 12
3.80
3.75
3.70
3.65
3.60
3.55
3.50
2.97 3.13 3.30 3.46 3.63
POWER SUPPLY VOLTAGE (V)
DIFFERENTIAL OUTPUT SWING (V)
06561-009
Figure 9. Differential Output Swing vs. Power Supply Voltage
115
114
113
112
111
110
109
108
107
106
105
2.97 3.13 3.30 3.46 3.63
POWER SUPPLY VOLTAGE (V)
POWER SUPPLY CURRENT (mA)
06561-010
Figure 10. Power Supply Current vs. Power Supply Voltage
200
180
160
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5
INPUT COMMON MODE (V)
PROPAGATION DELAY (ps)
06561-011
Figure 11. Propagation Delay vs. VICM; VID = 1.6 V p-p
162
160
158
156
154
152
150
148
146
0.4 0.8 1.2 1.6 2.0
INPUT DIFFERENTIAL (V p-p)
PROPAGATION DELAY (ps)
06561-012
Figure 12. Propagation Delay vs. VID; VICM = 2.15 V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5
FREQUENCY (GHz)
DIFFERENTIAL OUTPUT SWING (V)
06561-013
Figure 13. Toggle Rate, Differential Output Swing vs. Frequency
ADCLK914
Rev. A | Page 9 of 12
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCLK914 buffer is designed for very high speed applica-
tions. Consequently, high speed design techniques must be used
to achieve the specified performance. It is critically important to
use low impedance supply planes for both the negative supply
(VEE) and the positive supply (VCC) planes as part of a multilayer
board. Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
It is also important to adequately bypass the input and output
supplies. Place a 1 µF electrolytic bypass capacitor within several
inches of each power supply pin to ground. In addition, place
multiple high quality 0.001 µF bypass capacitors as close as
possible to each VEE and VCC supply pin and connect these cap-
acitors to the GND plane with redundant vias. Carefully select
high frequency bypass capacitors for minimum inductance and
ESR. To maximize the effectiveness of the bypass capacitors at
high frequencies, strictly avoid parasitic layout inductance.
Slew currents may also appear at the VDD and VSS pins of the
device being driven by the ADCLK914.
HVDS OUTPUT STAGE
The ADCLK914 has been developed to provide a bipolar interface
to any CMOS device that requires extremely low jitter, high
amplitude clocks. It is intended to be placed as close as possible
to the receiving device and allows the rest of the clock distribu-
tion to run at standard CML or PECL levels.
Interconnects must be short and very carefully designed
because the single terminated design provides much less
margin for error than lower voltage, double terminated
transmission techniques.
06561-015
VEE
Q
Q
40mA
VEE
7mA
VEE
7mA
Figure 14. Simplified Schematic Diagram
of the ADCLK914 HVDS Output Stage
INTERFACING TO HIGH SPEED DACs
The ADCLK914 is designed to drive high amplitude, low jitter
clock signals into high speed, multi-GSPS DACs. The ADCLK914
should be placed as close as possible to the clock input of the
DAC so that the high slew rate and high amplitude clock signal
that these devices require do not cause routing difficulties,
generate EMI, or become degraded by dielectric and other
losses. The ADCLK914, in turn, may be driven directly by
standard or low swing PECL, CML, CMOS, or LVTTL sources,
or by LVDS with simple ac coupling, as illustrated in Figure 15
through Figure 19.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed circuit, proper design and layout tech-
niques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power, and ground
impedances, as well as other layout issues, can severely limit
performance and can cause oscillation. Discontinuities along
input and output transmission lines can also severely limit the
specified jitter performance by reducing the effective input
slew rate.
Input and output matching have a significant impact on
performance. The ADCLK914 buffer provides internal 50 Ω
termination resistors for both D and D inputs. The return side
can be connected to the reference pin provided or to a current
sink at VCC − 2 V for use with differential PECL, or to VCC for
direct coupled CML. The VREF pin should be left floating any
time that it is not used to minimize power consumption.
Note that the ADCLK914 VREF source is current-limited to resist
damage from momentary shorts to VEE or VCC and from capacitor
charging currents; for this reason, the VREF source cannot be
used as a PECL termination supply.
Carefully bypass the termination potential using ceramic capa-
citors to prevent undesired aberrations on the input signal due
to parasitic inductance in the termination return path. If the
inputs are directly coupled to a source, care must be taken to
ensure that the pins remain within the rated input differential
and common-mode ranges.
If the return is floated, the device exhibits 100 Ω cross-term-
ination, but the source must then control the common-mode
voltage and supply the input bias currents.
ESD/clamp diodes between the input pins prevent the appli-
cation of excessive offsets to the input transistors. ESD diodes
are not optimized for best ac performance. If a clamp is needed,
it is recommended that appropriate external diodes be used.
RANDOM JITTER
The ADCLK914 buffer has been specifically designed to
minimize random jitter over a wide input range. Provided
that sufficient voltage swing is present, random jitter is affected
most by the slew rate of the input signal. Whenever possible,
clamp excessively large input signals with fast Schottky diodes
because attenuators reduce the slew rate. Input signal runs of
more than a few centimeters should be over low loss dielectrics
or cables with good high frequency characteristics.
ADCLK914
Rev. A | Page 10 of 12
TYPICAL APPLICATION CIRCUITS
V
REF
V
CC
V
T
D
D
CONNECT V
T
TO V
CC
.
06561-017
Figure 15. Interfacing to CML Inputs
V
REF
V
T
D
D
NOTES
1. PLACING A BYPASS CAPACITOR
FROM V
T
TO GROUND CAN IMPROVE
THE NOISE PERFORMANCE.
CONNECT V
T
TO V
REF
.
06561-019
Figure 16. AC Coupling Differential Signals
V
EE
40mA
V
EE
7mA
V
EE
7mA
Q
Q
V
CC
06561-021
Figure 17. Interfacing to High Speed DAC
V
REF
V
CC
– 2V
V
T
D
D
CONNECT V
T
TO V
CC
– 2V.
06561-018
Figure 18. Interfacing to ECL Inputs
V
REF
V
T
D
D
CONNECT V
T
, V
REF
, AND D. PLACE A BYPASS
CAPACITOR FROM V
T
TO GROUND.
ALTERNATIVELY, V
T
, V
REF
, AND D CAN BE
CONNECTED, GIVING A CLEANER LAYOUT AND
A 180º PHASE SHIFT.
06561-020
Figure 19. Interfacing to AC-Coupled, Single-Ended Inputs
ADCLK914
Rev. A | Page 11 of 12
*COMPLIANT
TO
JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1
INDICATOR
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
3.00
BSC SQ
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
BOTTOM VIEW
071708-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 20. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADCLK914BCPZ-WP1−40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-3
ADCLK914BCPZ-R71 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-3
ADCLK914BCPZ-R21 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-3
ADCLK914/PCBZ1 Evaluation Board
1 Z = RoHS Compliant Part.
ADCLK914
Rev. A | Page 12 of 12
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06561-0-10/08(A)
