SyncMOS
F29C51001T/F29C51001B
3
F29C51001T/F29C51001B V1.0 May 1999
Functional Block Diagram
Capacitance
(1,2)
NOTE:
1. Capacitance is sampled and not 100% tested.
2. T
A
= 25
°
C, V
CC
= 5V
±
10%, f = 1 MHz.
Latch Up Characteristics
(1)
NOTE:
1. Includes all pins except V
CC
. Test conditions: V
CC
= 5V, one pin at a time.
AC Test Load
Symbol Parameter Test mSetup Typ. Max. Units
C
IN
Input Capacitance V
IN
= 0 6 8 pF
C
OUT
Output Capacitance V
OUT
= 0 8 12 pF
C
IN2
Control Pin Capacitance V
IN
= 0 8 10 pF
Parameter Min. Max. Unit
Input Voltage with Respect to GND on A
9
, OE -1 +13 V
Input Voltage with Respect to GND on I/O, address or control pins -1 V
CC
+ 1 V
V
CC
Current -100 +100 mA
Address buffer & latchesA0–A16
51001-05
I/O Buffer & Data Latches
I/O0–I/O7
Y-Decoder
1,048,576 Bit
Memory Cell Array
X-Decoder
Control Logic
CE
OE
WE
51001-06
IN3064 or Equivalent
IN3064
or Equivalent 2.7 kΩ
6.2 kΩ
+5.0 V
IN3064 or Equivalent
IN3064 or Equivalent
CL = 100 pF
Device Under
Test
4
SyncMOS
F29C51001T/F29C51001B
F29C51001T/F29C51001B V1.0 May 1999
Absolute Maximum Ratings
(1)
NOTE:
1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. No more than one output maybe shorted at a time and not exceeding one second long.
DC Electrical Characteristics
(over the commercial operating range)
Symbol Parameter Commercial Extended Unit
V
IN
Input Voltage (input or I/O pins) -2 to +7 -2 to +7 V
V
IN
Input Voltage (A
9
pin, OE) -2 to +13 -2 to +13 V
V
CC
Power Supply Voltage -0.5 to +5.5 -0.5 to +5.5 V
T
STG
Storage Temerpature (Plastic) -65 to +125 -65 to +150
°
C
T
OPR
Operating Temperature 0 to +70 -40 to + 125
°
C
I
OUT
Short Circuit Current
(2)
200 (Max.) 200 (Max.) mA
Parameter
Name Parameter Test Conditions Min. Max. Unit
V
IL
Input LOW Voltage V
CC
= V
CC
Min. — 0.8 V
V
IH
Input HIGH Voltage V
CC
= V
CC
Max. 2 — V
I
IL
Input Leakage Current V
IN
= GND to V
CC
, V
CC
= V
CC
Max. —
±
1
µ
A
I
OL
Output Leakage Current V
OUT
= GND to V
CC
, V
CC
= V
CC
Max. —
±
1
µ
A
V
OL
Output LOW Voltage V
CC
= V
CC
Min., I
OL
= 2.1mA — 0.4 V
V
OH
Output HIGH Voltage V
CC
= V
CC
Min, I
OH
= -400
µ
A 2.4 — V
I
CC1
Read Current CE = OE = V
IL
, WE = V
IH
, all I/Os open,
Address input = V
IL
/V
IH
, at f = 1/t
RC
Min.,
V
CC
= V
CC
Max.
— 40 mA
I
CC2
Program Current CE = WE = VIL, OE = V
IH
, V
CC
= V
CC
Max. — 50 mA
I
SB
TTL Standby Current CE = OE = WE = V
IH
, VCC = VCC Max. — 2 mA
ISB1 CMOS Standby Current CE = OE = WE = VCC – 0.3V, VCC = VCC Max. — 100 µA
VHDevice ID Voltage for A9CE = OE = VIL, WE = VIH 11.5 12.5 V
IHDevice ID Current for A9CE = OE = VIL, WE = VIH, A9 = VH Max. — 50 µA
SyncMOS
F29C51001T/F29C51001B
5
F29C51001T/F29C51001B V1.0 May 1999
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Program (Erase/Program) Cycle
Parameter
Name Parameter
-45 -70 -90
UnitMin. Max. Min. Max. Min. Max.
tRC Read Cycle Time 45 — 70 — 90 — ns
tAA Address Access Time — 45 — 70 — 90 ns
tACS Chip Enable Access Time — 45 — 70 — 90 ns
tOE Output Enable Access Time — 25 — 35 — 45 ns
tCLZ CE Low to Output Active 0 — 0 — 0 — ns
tOLZ OE Low to Output Active 0 — 0 — 0 — ns
tDF Output Enable or Chip Disable to Output
in High Z 0 15 0 20 0 30 ns
tOH Output Hold from Address Change 0 — 0 — 0 — ns
Parameter
Name Parameter
-45 -70 -90
UnitMin.Typ.Max.Min.Typ.Max.Min.Typ.Max.
tWC Program Cycle Time 45 — — 70 — — 90 — — ns
tAS Address Setup Time 0 — — 0 — — 0 — — ns
tAH Address Hold Time 35 — — 45 — — 45 — — ns
tCS CE Setup Time 0 — — 0 — — 0 — — ns
tCH CE Hold Time 0 — — 0 — — 0 — — ns
tOES OE Setup Time 0 — — 0 — — 0 — — ns
tOEH OE High Hold Time 0 — — 0 — — 0 — — ns
tWP WE Pulse Width 25 — — 35 — — 45 — — ns
tWPH WE Pulse Width High 20 — — 35 — — 38 — — ns
tDS Data Setup Time 20 — — 25 — — 30 — — ns
tDH Data Hold Time 0 — — 0 — — 0 — — ns
tWHWH1 Programming Cycle — — 20 — — 20 — — 20 µs
tWHWH2 Sector Erase Cycle — — 10 — — 10 — — 10 ms
tWHWH3 Chip Erase Cycle — 500 — — 500 — — 500 — ms
6
SyncMOS
F29C51001T/F29C51001B
F29C51001T/F29C51001B V1.0 May 1999
Waveforms of Read Cycle
Waveforms of WE Controlled-Program Cycle
NOTES:
1. I/O7: The output is the complement of the data written to the device.
2. PA: The address of the memory location to be programmed.
3. PD: The data at the byte address to be programmed.
tRC
tAA
tCE
tOE
tCLZ tOH
tAA
tOLZ
tDF
ADDRESS
CE
OE
WE
I/O VALID DATA OUT VALID DATA OUT HIGH-Z
51001-07
HIGH-Z
tWC tAS
PA5555H
tWHWH1
tWPH
tCS
tRC
tAH
tDStDH
tWP
tOES
tDF
tOH
tOE
DOUTI/O7(1)
PD(3)
A0H
51001-08
ADDRESS
CE
OE
WE
I/O
3rd bus cycle
PA(2)
tCH
SyncMOS
F29C51001T/F29C51001B
7
F29C51001T/F29C51001B V1.0 May 1999
Waveforms of CE Controlled-Program Cycle
Waveforms of Erase Cycle
(1)
NOTES:
1. PA: The address of the memory location to be programmed.
2. PD: The data at the byte address to be programmed.
3. SA: The sector address for Sector Erase. Address = don’t care for Chip Erase.
tWC
tAS
tWHWH1
tWPH
tOES
tRC
tAH
tDStDH
tWP
tDF
tOH
tOE
DOUTI/O7
PD(2)
A0H
51001-09
ADDRESS 5555H PA PA(1)
WE
OE
CE
I/O
tWC tAS
tWPH
ADDRESS
CE
OE
WE
I/O
5555H 5555H 5555H2AAAH 2AAAH SA
AAH 55H 80H AAH 55H 30H
10H for
Chip Erase
51001-10
tAH
tWP
tDS tDH
tCS
8
SyncMOS
F29C51001T/F29C51001B
F29C51001T/F29C51001B V1.0 May 1999
Waveforms of DATA Polling Cycle
Waveforms of Toggle Bit Cycle
tOEH
tCE
tWHWH1 tOH
tDF
tCH
CE
OE
WE
I/O7I/O7I/O7
VALID DATA OUT
HIGH-Z
tOE
51001-11
I/O0-I/O6
I/O0-I/O6INVALID
VALID DATA OUT
HIGH-Z
51001-12
CE
WE
OE
tOEH
I/O6
9
F29C51001T/F29C51001B V1.0 May 1999
SyncMOS
F29C51001T/F29C51001B
Functional Description
The F29C51001T/F29C51001B consists of 256
equally-sized sectors of 512 bytes each. The 8 KB
lockable Boot Block is intended for storage of the
system BIOS boot code. The boot code is the first
piece of code executed each time the system is
powered on or rebooted.
The F29C51001 is available in two versions: the
F29C51001T with the Boot Block address starting
from 1E000H to 1FFFFH, and the F29C51001B
with the Boot Block address starting from 00000H
to 1FFFFH.
Read Cycle
A read cycle is performed by holding both CE
and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).
Output Disable
Returning OE or CE HIGH, whichever occurs first
will terminate the read operation and place the l/O
pins in the HIGH-Z state.
Standby
The device will enter standby mode when the CE
signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE signal.
Byte Program Cycle
The F29C51001T/F29C51001B is programmed
on a byte-by-byte basis. The byte program
operation is initiated by using a specific four-bus-
cycle sequence: two unlock program cycles, a
program setup command and program data
program cycles (see Table 2).
During the byte program cycle, addresses are
latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte program
cycle can be CE controlled or WE controlled.
Sector Erase Cycle
The F29C51001T/F29C51001B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. Sector erase operation
is initiated by using a specific six-bus-cycle
sequence: Two unlock program cycles, a setup
command, two additional unlock program cycles,
and the sector erase command (see Table 2). A
sector must be first erased before it can be
reprogrammed. While in the internal erase mode,
the device ignores any program attempt into the
device. The internal erase completion can be
determined via DATA polling or toggle bit.
The F29C51001T/F29C51001B is shipped with
pre-erased sectors (all bits = 1).
8KB Boot Block
512
512
512
512
512
512
•
•
•
512
512 8KB Boot Block
F29C51001T F29C51001B
1FFFFH
1E000H
00000H
01FFFH
51001-13
00000H
8KB Boot Block = 16 Sectors
•
•
•
Table 1. Operation Modes Decoding
Decoding Mode CE OE WE A0A1A9I/O
Read VIL VIL VIH A0A1A9READ
Byte Write VIL VIH VIL A0A1A9PD
Standby VIH X X X X X HIGH-Z
Autoselect Device ID VIL VIL VIH VIH VIL VHCODE
Autoselect Manufacture ID VIL VIL VIH VIL VIL VHCODE
Enabling Boot Block Protection Lock VIL VHVIL X X VHX
10
SyncMOS
F29C51001T/F29C51001B
F29C51001T/F29C51001B V1.0 May 1999
NOTES:
1. X = Don’t Care, VIH = HIGH, VIL = LOW. VH = 12.5V Max.
2. PD: The data at the byte address to be programmed.
Table 2. Command Codes
NOTES:
1. Top Boot Sector
2. Bottom Boot Sector
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
Disabling Boot Block Protection Lock VHVHVIL X X VHX
Output Disable VIL VIH VIH X X X HIGH-Z
Command
Sequence
First Bus
Program Cycle Second Bus
Program Cycle Third Bus
Program Cycle Fourth Bus
Program Cycle Fifth Bus
Program Cycle Six Bus
Program Cycle
Address Data Address Data Address Data Address Data Address Data Address Data
Read XXXXH F0H
Read 5555H AAH 2AAAH 55H 5555H F0H RA RD
Autoselect 5555H AAH 2AAAH 55H 5555H 90H 00H 40H
01H 01H(1)
A1H(2)
Byte
Program 5555H AAH 2AAAH 55H 5555H A0H PA PD(4)
Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Sector Erase5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H PA(3) 30H
Decoding Mode CE OE WE A0A1A9I/O
Chip Erase Cycle
The F29C51001T/F29C51001B features a chip-
erase operation. The chip erase operation is
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The chip erase operation is performed
sequentially, one sector at a time. When the
automated on chip erase algorithm is requested
with the chip erase command sequence, the device
automatically programs and verifies the entire
memory array for an all zero pattern prior to erasure
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
Program Cycle Status Detection
There are two methods for determining the state
of the F29C51001T/F29C51001B during a
program (erase/program) cycle: DATA Polling
(I/O7) and Toggle Bit (I/O6).
DATA Polling (I/O
7
)
The F29C51001T/F29C51001B features DATA
polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
complement of the loaded data on I/O7. Once the
program cycle is completed, I/O7 will show true
data, and the device is then ready for the next
cycle.
Toggle Bit (I/O
6
)
The F29C51001T/F29C51001B also features
another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O6 toggling between 1 and 0. Once the program is
completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.
11
F29C51001T/F29C51001B V1.0 May 1999
SyncMOS
F29C51001T/F29C51001B
Boot Block Protection
The F29C51001T/F29C51001B features
hardware Boot Block Protection. The boot block
sector protection is enabled when high voltage
(12.5V) is applied to OE and A9 pins with CE pin
LOW and WE pin lOW. The sector protection is
desabled when high voltage is applied to OE, CE
and A9 pins with WE pin LOW. Other pins can be
HIGH or LOW. This is shown in table 1.
Autoselect
The F29C51001T/F29C51001B features an
Autoselect mode to identify
the Boot Block
(protected/unprotected), the Device (Top/Bottom),
and the manufacturer ID.
To get to the Autoselect mode, a high voltage
(VH) must be applied to the A9 pin. Once the A9
signal is returned to LOW or HIGH, the device will
return to the previous mode.
Boot Block Protection Status
In Autoselect mode, performing a read at
address 3CXX2H or address 0CXX2H will indicate
if the Top Boot Block sector or the Bottom Boot
Block sector is locked out. If the data is 01H, the
Top/Bottom Boot Block is protected. If the data is
00H, the Top/Bottom Boot Block is unprotected.
(see Table 3.)
Device ID
In Autoselect mode, performing a read at
address XXXXH will determine whether the device
is a Top Boot Block device or a Bottom Boot Block
device. If the data is 01H, the device is a Top Boot
Block. If the data is A1H, the device is a Bottom
Boot Block device (see Table 3).
In addition, the device ID can also be read via the
command register when the device is erased or
programmed in a system without applying high
voltage to the A9 pin. When A0 is HIGH, the device
ID is presented at the outputs.
Manufacturer ID
In Autoselect mode, performing a read at
address. XXXX0H will determine the manufacturer
ID. 40H is the manufacturer code for SyncMOS
Flash.
In addition the manufacturer ID can also be read
via the command register when the device is
erased or programmed in a system without
applying high voltage to the A9 pin. when A0 is
LOW, the manufacturer ID is presented at the
outputs.
Hardware Data Protection
V
CC
Sense Protection:
the program operation is
inhibited when VCC is less than 2.5V.
Noise Protection:
a CE or WE pulse of less than
5ns will not initiate a program cycle.
Program Inhibit Protection:
holding any one of
OE LOW, CE HIGH or WE HIGH inhibits a program
cycle.
Table 3. Autoselect Decoding
NOTE:
1. X = Don’t Care, VIH = HIGH, VIL = LOW.
Decoding Mode Boot Block
Address
Data I/O0–I/O7
A0A1A2–A13 A14–A16
Boot Block Protection Top VIL VIH X VIH 01H: protected
Bottom VIL VIH X VIL 00H: unprotected
Device ID Top VIH VIL X X 01H
Bottom A1H
Manufacture ID VIL VIL X X 40H
12
SyncMOS
F29C51001T/F29C51001B
F29C51001T/F29C51001B V1.0 May 1999
Byte Program Algorithm Chip/Sector Erase Algorithm
Write Program
Command Sequence
Add/Data
5555H/AAH
2AAAH/55H
5555H/A0H
Four Bus
Cycle
Sequence
PA/PD
DATA Polling (I/O7)
or Toggle Bit (I/O6)
Programming
Completed
Verify Byte?
Yes
No
Write Erase
Command Sequence
Add/Data
5555H/AAH
2AAAH/55H
5555H/80H
Six Bus
Cycle
Sequence
5555H/AAH
2AAAH/55H
5555H/10H (Chip Erase)
PA/30H (Sector Erase
DATA Polling or Toggle Bit
Successfully Completed
Erase Complete
51001-14
SyncMOS
F29C51001T/F29C51001B
13
F29C51001T/F29C51001B V1.0 May 1999
DATA Polling Algorithm Toggle Bit Algorithm
NOTE:
1. PBA: The byte address to be programmed.
Read I/O7
Address = PBA(1)
Program
Done
Program
Done
I/O7 = Data
No
Yes
Read I/O6
No
Yes I/O6 Toggle
Read I/O6
51002-17
14
SyncMOS
F29C51001T/F29C51001B
F29C51001T/F29C51001B V1.0 May 1999
Package Diagrams
32-pin Plastic DIP
32-pin PLCC
15° MAX
0.545/0.555
INDEX-1
.047 +.012
– 0
0.210 MAX
0.120 MIN
0.010 MIN
.600 TYP
1.660 MAX.
.050 MAX
.100
TYP
.032 +.012
– 0
.018 +.006
– .002
.010 +.004
– .0004
INDEX-2
EJECTOR MARK
.420 ± .003 3° - 6° 3° - 6°
3° - 6°
.017
30°
.136 ± .003
.110 .046 ± .003
.025
.050 TYP
.450 ± .003
.490 ± .005
.045X45°
.590 ± .005
.550 ± .003
201918 17161514
21
22
23
24
25
26
27
28
29 303132 1 2 3 4
13
12
11
10
9
8
7
6
5
SyncMOS
F29C51001T/F29C51001B
15
F29C51001T/F29C51001B V1.0 May 1999
32-pin TSOP-I
0.032 TYP. 0.020 SBC
0.003 MAX
0.020 MAX.
0.024 ± 0.004
SEATING
PLANE
0.010
See Detail “A”
Detail “A”
0.724 TYP. (0.728 MAX.)
0.787 ± 0.008
0.009 ± 0.002
0.315 TYP.
(0.319 MAX.)
0.035 ± 0.002
0.047 MAX.
0.005 MIN.
0.007 MAX.
Units in inches
SyncMOS Technology Inc.
Sales Office :
No. 1, Creation Rd. 1,
Science-Based Industrial Park,
Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5792926
Fax : 886-3-5792953
Note 1 : publication date : May 1999. Rev. A
Note 2 : all data and specification are subject to change without notice.
F29C51001T/F29C51001B V1.0 May 199916
