M45PE80 8 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability and a 75 MHz SPI bus interface Features SPI bus compatible serial interface 75 MHz clock rate (maximum) 2.7 V to 3.6 V single supply voltage VFQFPN8 (MP) 6 x 5 mm (MLP8) 8 Mbit of Page-Erasable Flash memory Page size: 256 bytes: - Page Write in 11 ms (typical) - Page Program in 0.8 ms (typical) - Page Erase in 10 ms (typical) Sector Erase (64 Kbytes) SO8W (MW) 208 mils width SO8N (MN) 150 mils width Hardware Write protection of the bottom sector (64 Kbytes) Electronic signature - JEDEC standard two-byte signature (4014h) Unique ID code (UID) with 16 bytes read only, available upon customer request only on T9HX process technology parts QFN8L (MS) MLP8 6 x 5 mm Deep Power-down mode 1 A (typical) More than 100 000 Write cycles More than 20 years' data retention Packages - RoHS compliant December 2008 Rev 11 1/48 www.numonyx.com 1 Contents M45PE80 Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Active Power, Stand-by Power and Deep Power-Down modes . . . . . . . . 13 4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4.1 2/48 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 M45PE80 Contents 6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 22 6.7 Page Write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.9 Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.10 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.12 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3/48 List of tables M45PE80 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. 4/48 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power-Up timing and VWI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 AC characteristics (33 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC characteristics (50 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AC characteristics (75 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Timings after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VFQFPN8 (MLP8)8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, mechanical data. . . . . . . . 42 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 QFN8L (MLP8) 8-lead dual flat package no lead, 6 x 5 mm package mechanical data. . . 44 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 M45PE80 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 20 Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 21 Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 22 Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Page Write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Page Erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Release from Deep Power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 30 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Write Protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, package outline . . . . . . . . 42 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 43 QFN8L (MLP8) 8-lead, dual flat package no lead, 6 x 5 mm, package outline . . . . . . . . . 44 5/48 Summary description 1 M45PE80 Summary description The M45PE80 is a 8 Mbit (1 Mbit x 8 bit) Serial Paged Flash Memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle. The memory is organized as 16 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or 1 048 576 bytes. The memory can be erased a page at a time, using the Page Erase instruction, or a sector at a time, using the Sector Erase instruction. In order to meet environmental requirements, Numonyx offers the M45PE80 in RoHS compliant packages, which are also Lead-free. Figure 1. Logic diagram VCC D Q C S M45PE80 W Reset VSS AI06810B Table 1. Signal names Signal name 6/48 Function Direction C Serial Clock Input D Serial Data Input Input Q Serial Data Output Output S Chip Select Input W Write Protect Input Reset Reset Input VCC Supply Voltage VSS Ground M45PE80 Summary description Figure 2. VFQFPN and SO connections M45PE80 D C Reset S 1 2 3 4 8 7 6 5 Q VSS VCC W AI06811B 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1. 7/48 Signal description 2 Signal description 2.1 Serial Data Output (Q) M45PE80 This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial Data Input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). 2.3 Serial Clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). 2.4 Chip Select (S) When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. 2.5 Reset (Reset) The Reset (Reset) input provides a hardware reset for the memory. When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the device enters the Reset mode. In this mode, the output Q is high impedance: If an internal operation (Write, Erase or Program cycle) is in progress when Reset (Reset) is driven Low, the device enters the Reset mode and any on-going Write, Program or Erase cycle is aborted. The addressed data may be lost. 2.6 Write Protect (W) This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is connected to VSS, causing the first 256 pages of memory to become read-only by protecting them from write, program and erase operations. When Write Protect (W) is connected to VCC, the first 256 pages of memory behave like the other pages of memory. 8/48 M45PE80 2.7 Signal description VCC supply voltage VCC is the supply voltage. 2.8 VSS ground VSS is the reference for the VCC supply voltage. 9/48 SPI modes 3 M45PE80 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data: Figure 3. C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Bus master and memory devices on the SPI bus VSS VCC R SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C Q D SPI Bus Master SPI Memory Device R CS3 VCC C Q D VSS C Q D VCC VSS SPI Memory Device R VSS SPI Memory Device R CS2 CS1 S W HOLD S W HOLD S W HOLD AI12836b 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure that the M45PE80 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). The typical value of R is 100 k, assuming that the time constant R*Cp (Cp = parasitic capacitance of the bus line) is shorter than the time during which the Bus Master leaves the SPI bus in high impedance. 10/48 M45PE80 SPI modes Example: Cp = 50 pF, that is R*Cp = 5 s <=> the application must ensure that the Bus Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 s. Figure 4. SPI modes supported CPOL CPHA 0 0 C 1 1 C D Q MSB MSB AI01438B 11/48 Operating features 4 Operating features 4.1 Sharing the overhead of modifying data M45PE80 To write or program one (or more) data bytes, two instructions are required: Write Enable (WREN), which is one byte, and a Page Write (PW) or Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal cycle (of duration tPW or tPP). To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to 256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, provided that they lie in consecutive addresses on the same page of memory. 4.2 An easy way to modify data The Page Write (PW) instruction provides a convenient way of modifying data (up to 256 contiguous bytes at a time), and simply requires the start address, and the new data in the instruction sequence. The Page Write (PW) instruction is entered by driving Chip Select (S) Low, and then transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte, and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data bytes are written to the data buffer, starting at the address given in the third address byte (A7-A0). When Chip Select (S) is driven High, the Write cycle starts. The remaining, unchanged, bytes of the data buffer are automatically loaded with the values of the corresponding bytes of the addressed memory page. The addressed memory page then automatically put into an Erase cycle. Finally, the addressed memory page is programmed with the contents of the data buffer. All of this buffer management is handled internally, and is transparent to the user. The user is given the facility of being able to alter the contents of the memory on a byte-by-byte basis. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few bytes (see Page Write (PW), Table 13: AC characteristics (50 MHz operation), and Table 14.: AC characteristics (75 MHz operation)). 12/48 M45PE80 4.3 Operating features A fast way to modify data The Page Program (PP) instruction provides a fast way of modifying data up to 256 contiguous bytes at a time, provided that it involves only resetting bits to 0 that had previously been set to 1. The following are times this use case might occur: The designer is programming the device for the first time; The designer knows that the page has already been erased by an earlier Page Erase (PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available; The designer knows that the change involves only resetting bits to 0 that are still set to 1. When this method is possible, it has the additional advantage of minimizing the number of unnecessary erase operations, and the extra stress incurred by each page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Page Program (PP), Table 13: AC characteristics (50 MHz operation), and Table 14.: AC characteristics (75 MHz operation)). 4.4 Polling during a Write, Program or Erase cycle A further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (tPW, tPP, tPE, or tSE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous cycle is complete. 4.5 Reset An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition protection is provided by driving Reset (Reset) Low during the Power-on process, and only driving it High when VCC has reached the correct voltage level, VCC(min). 4.6 Active Power, Stand-by Power and Deep Power-Down modes When Chip Select (S) is Low, the device is enabled, and in the Active Power mode. When Chip Select (S) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write). The device then goes in to the Stand-by Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode) is executed. While in the Deep Power-down mode, the device ignores all Write, Program and Erase instructions (see Deep Power-down (DP)). This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. 13/48 Operating features 4.7 M45PE80 Status Register The Status Register contains two status bits that can be read by the Read Status Register (RDSR) instruction. See Section 6.4: Read Status Register (RDSR) for a detailed description of the Status Register bits. 4.8 Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M45PE80 boasts the following data protection mechanisms: 14/48 Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - Power-up - Reset (RESET) driven Low - Write Disable (WRDI) instruction completion - Page Write (PW) instruction completion - Page Program (PP) instruction completion - Page Erase (PE) instruction completion - Sector Erase (SE) instruction completion The Hardware Protected mode is entered when Write Protect (W) is driven Low, causing the first 256 pages of memory to become read-only. When Write Protect (W) is driven High, the first 256 pages of memory behave like the other pages of memory The Reset (Reset) signal can be driven Low to protect the contents of the memory during any critical time, not just during Power-up and Power-down. In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions while the device is not in active use. M45PE80 5 Memory organization Memory organization The memory is organized as: 4096 pages (256 bytes each). 1 048 576 bytes (8 bits each) 16 sectors (512 Kbits, 65536 bytes each) Each page can be individually: programmed (bits are programmed from 1 to 0) erased (bits are erased from 0 to 1) written (bits are changed to either 0 or 1) The device is Page or Sector Erasable (bits are erased from 0 to 1). Table 2. Memory organization Sector Address range 15 F0000h FFFFFh 14 E0000h EFFFFh 13 D0000h DFFFFh 12 C0000h CFFFFh 11 B0000h BFFFFh 10 A0000h AFFFFh 9 90000h 9FFFFh 8 80000h 8FFFFh 7 70000h 7FFFFh 6 60000h 6FFFFh 5 50000h 5FFFFh 4 40000h 4FFFFh 3 30000h 3FFFFh 2 20000h 2FFFFh 1 10000h 1FFFFh 0 00000h 0FFFFh 15/48 Memory organization Figure 5. M45PE80 Block diagram Reset W High Voltage Generator Control Logic S C D I/O Shift Register Q Address Register and Counter Status Register 256 Byte Data Buffer Y Decoder FFFFFh 10000h First 256 Pages can be made read-only 00000h 000FFh 256 Bytes (Page Size) X Decoder AI06812 16/48 M45PE80 6 Instructions Instructions All instructions, addresses, and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 3. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read) or Read Status Register (RDSR) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Write (PW), Page Program (PP), Page Erase (PE), Sector Erase (SE), Write Enable (WREN), Write Disable (WRDI), Deep Power-down (DP) or Release from Deep Power-down (RDP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle are ignored, and the internal Write cycle, Program cycle or Erase cycle continues unaffected. Table 3. Instruction set Instruction Description One-byte instruction code Address Dummy bytes bytes Data bytes WREN Write Enable 0000 0110 06h 0 0 0 WRDI Write Disable 0000 0100 04h 0 0 0 RDID Read Identification 1001 1111 9Fh 0 0 1 to 3 RDSR Read Status Register 0000 0101 05h 0 0 1 to READ Read Data Bytes 0000 0011 03h 3 0 1 to Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to PW Page Write 0000 1010 0Ah 3 0 1 to 256 PP Page Program 0000 0010 02h 3 0 1 to 256 PE Page Erase 1101 1011 DBh 3 0 0 SE Sector Erase 1101 1000 D8h 3 0 0 DP Deep Power-down 1011 1001 B9h 0 0 0 RDP Release from Deep Power-down 1010 1011 ABh 0 0 0 FAST_READ 17/48 Instructions 6.1 M45PE80 Write Enable (WREN) The Write Enable (WREN) instruction (Figure 6) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page Program (PP), Page Erase (PE), and Sector Erase (SE) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 6. Write Enable (WREN) instruction sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI02281E 6.2 Write Disable (WRDI) The Write Disable (WRDI) instruction (Figure 7) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions: Power-up Write Disable (WRDI) instruction completion Page Write (PW) instruction completion Page Program (PP) instruction completion Page Erase (PE) instruction completion Sector Erase (SE) instruction completion Figure 7. Write Disable (WRDI) instruction sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI03750D 18/48 M45PE80 6.3 Instructions Read Identification (RDID) The Read Identification (RDID) instruction allows the device identification data to be read as explained here, with the data values shown in Table 4.: Read Identification (RDID) data-out sequence. Manufacturer identification (1 byte): Numonyx value assigned by JEDEC. Device identification (2 bytes): assigned by the device manufacturer. - The first byte indicates the memory type. - The second byte indicates the memory capacity of the device. Unique ID code (UID) (17 bytes): available upon customer request.(1) - The first byte contains the length of the data that is contained in the UID. - The remaining 16 bytes are available upon customer request and contain the optional Customized Factory Data (CFD) content. The CFD bytes are read-only and can be programmed with customer data upon customer demand. If a customer does not make a request, the device is shipped with all CFD bytes programmed to zero (00h). Any Read Identification (RDID) instruction performed while an Erase or Program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 1-byte instruction code for the instruction is shifted in. After this the 20-bytes stored in memory are shifted out on Serial Data output (Q), including the 3-bytes of manufacturer and device identification information, the 1-byte CFD length, and the 16 bytes of CFD content. Each bit of these 20-bytes is shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 8: Read Identification (RDID) instruction sequence and data-out sequence. The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 4. Read Identification (RDID) data-out sequence Manufacturer Identification 20h Device Identification UID Memory Type Memory Capacity CFD length CFD content 40h 14h 10h 16 bytes 1. UID available on T9HX process technology parts. 19/48 Instructions M45PE80 Figure 8. Read Identification (RDID) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 18 28 29 30 31 C Instruction D Manufacturer Identification Device Identification High Impedance Q 15 14 13 3 2 1 0 MSB MSB AI06809 6.4 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 9. The status bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.4.2 WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write, Program or Erase instruction is accepted. Table 5. Status Register Format b7 0 b0 0 0 0 0 0 (1) WEL 1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is automatically set and reset by the internal logic of the device). 20/48 WIP(1) M45PE80 Instructions Figure 9. Read Status Register (RDSR) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Status Register Out Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB AI02031E 6.5 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents at that address is shifted out on Serial Data Output (Q), each bit being shifted out at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 21/48 Instructions M45PE80 Figure 10. Read Data Bytes (READ) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 24-Bit Address 23 22 21 D 3 2 1 0 MSB Data Out 1 High Impedance Q 7 6 5 4 3 2 Data Out 2 1 0 7 MSB AI03748D 1. Address bits A23 to A20 are Don't Care. 6.6 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 11. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 22/48 M45PE80 Instructions Figure 11. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 C Instruction 24 BIT ADDRESS 23 22 21 D 3 2 1 0 High Impedance Q S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte D 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 Q 7 6 5 4 MSB 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB AI04006 1. Address bits A23 to A20 are Don't Care. 6.7 Page Write (PW) The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Write (PW) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). The rest of the page remains unchanged if no power failure occurs and the device is not reset during the write cycle. The Page Write (PW) instruction performs a page erase cycle even if only one byte is updated. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are written from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 12. 23/48 Instructions M45PE80 If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be written correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly written at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few bytes (see Table 13: AC characteristics (50 MHz operation) and Table 14.: AC characteristics (75 MHz operation)). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Write (PW) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Write cycle (whose duration is tPW) is initiated. While the Page Write cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Write cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Write (PW) instruction applied to a page that is Hardware Protected is not executed. Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Page Write (PW) instruction sequence S 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 C Instruction 24-Bit Address 23 22 21 D 3 2 Data Byte 1 1 0 7 6 5 4 3 2 0 1 MSB MSB S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 D 7 6 MSB 5 4 3 2 Data Byte 3 1 0 7 MSB 6 5 4 3 2 Data Byte n 1 0 7 6 5 4 3 2 1 0 MSB AI04045 1. Address bits A23 to A20 are Don't Care 2. 1 n 256 24/48 M45PE80 6.8 Instructions Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are programmed from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 13. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Table 13: AC characteristics (50 MHz operation) and Table 14.: AC characteristics (75 MHz operation)). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page that is Hardware Protected is not executed. Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 25/48 Instructions M45PE80 Figure 13. Page Program (PP) instruction sequence S 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 C Instruction 24-Bit Address 23 22 21 D 3 2 Data Byte 1 1 0 7 6 5 4 3 2 0 1 MSB MSB S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 D 7 6 MSB 5 4 3 2 Data Byte 3 1 0 7 MSB 6 5 4 3 2 Data Byte n 1 0 7 6 5 4 3 2 1 0 MSB AI04044 1. Address bits A23 to A20 are Don't Care 2. 1 n 256 26/48 M45PE80 6.9 Instructions Page Erase (PE) The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data Input (D). Any address inside the Page is a valid address for the Page Erase (PE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Page Erase (PE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Erase cycle (whose duration is tPE) is initiated. While the Page Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Page Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Erase (PE) instruction applied to a page that is Hardware Protected is not executed. Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 14. Page Erase (PE) instruction sequence S 0 1 2 3 4 5 6 7 8 9 29 30 31 C Instruction D 24 Bit Address 23 22 2 1 0 MSB AI04046 1. Address bits A23 to A20 are Don't Care. 27/48 Instructions 6.10 M45PE80 Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data Input (D). Any address inside the Sector (see Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a sector that contains a page that is Hardware Protected is not executed. Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 15. Sector Erase (SE) instruction sequence S 0 1 2 3 4 5 6 7 8 9 29 30 31 C Instruction D 24 Bit Address 23 22 2 1 0 MSB AI03751D 1. Address bits A23 to A20 are Don't Care. 28/48 M45PE80 6.11 Instructions Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode (if there is no internal cycle currently in progress). But this mode is not the Deep Powerdown mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified in Table 11). To exit from Deep Power-down mode, the Release from Deep Power-down (RDP) instruction must be issued. No other instruction must be issued while the device is in this mode. The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 16. Deep Power-down (DP) instruction sequence S 0 1 2 3 4 5 6 7 tDP C Instruction D Stand-by Mode Deep Power-down Mode AI03753D 29/48 Instructions 6.12 M45PE80 Release from Deep Power-down (RDP) To exit from Deep Power-down mode, the Release from Deep Power-down (RDP) instruction must be issued. No other instruction must be issued while the device is in this mode. The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the instruction to be rejected, and not executed. After Chip Select (S) has been driven High, followed by a delay, t RDP, the device is put in the Standby mode. Chip Select (S) must remain High at least until this period is over. The device waits to be selected, so that it can receive, decode and execute instructions. Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Release from Deep Power-down (RDP) instruction sequence S 0 1 2 3 4 5 6 7 tRDP C Instruction D High Impedance Q Deep Power-down Mode Stand-by Mode AI06807 30/48 M45PE80 7 Power-up and Power-down Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC(min) at Power-up, and then for a further delay of tVSL VSS at Power-down A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the POR threshold value, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program (PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write, Program or Erase instructions should be sent until the later of: tPUW after VCC passed the VWI threshold tVSL after VCC passed the VCC(min) level These values are specified in Table 6. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration of the Power-up and Power-down phases. At Power-up, the device is in the following state: The device is in the Standby mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. The Write In Progress (WIP) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 100 nF). At Power-down, when VCC drops from the operating voltage, to below the POR threshold value, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.) 31/48 Power-up and Power-down M45PE80 Figure 18. Power-up timing VCC VCC(max) Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed VCC(min) tVSL Reset State of the Device Read Access allowed Device fully accessible VWI tPUW time AI04009C Table 6. Power-Up timing and VWI threshold Symbol tVSL (1) tPUW(1) VWI (1) Parameter Min. Unit VCC(min) to S low 30 Time delay before the first Write, Program or Erase instruction 1 10 ms 1.5 2.5 V Write inhibit voltage 1. These parameters are characterized only, over the temperature range -40C to +85C. 32/48 Max. s M45PE80 8 Initial delivery state Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). All usable Status Register bits are 0. 9 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 7. Absolute maximum ratings Symbol TSTG TLEAD Parameter Storage temperature Min. Max. Unit -65 150 C Lead temperature during soldering See (1) C VIO Input and output voltage (with respect to Ground) -0.6 VCC + 0.6 V VCC Supply voltage -0.6 4.0 V -2000 2000 V VESD Electrostatic Discharge Voltage (Human Body Model)(2) 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx RoHS complian 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ) 33/48 DC and AC parameters 10 M45PE80 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8. Operating conditions Symbol Min. Max. Unit Supply voltage 2.7 3.6 V TA Ambient operating temperature -40 85 C Table 9. AC measurement conditions Min. Max. Unit VCC Parameter Symbol CL Parameter Load capacitance 30 Input rise and fall times pF 5 ns Input pulse voltages 0.2VCC to 0.8VCC V Input and output timing reference voltages 0.3VCC to 0.7VCC V 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 19. AC measurement I/O waveform Input Levels Input and Output Timing Reference Levels 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI00825B Table 10. Symbol COUT CIN Capacitance(1) Parameter Output capacitance (Q) Input capacitance (other pins) Test Condition Max. Unit VOUT = 0 V 8 pF VIN = 0 V 6 pF 1. Sampled only, not 100% tested, at TA=25 C and a frequency of 33 MHz. 34/48 Min. M45PE80 Table 11. Symbol DC and AC parameters DC characteristics Parameter Test condition (in addition to those in Table 8) Min. Max. Unit ILI Input leakage current 2 A ILO Output leakage current 2 A ICC1 Standby current (Standby and Reset modes) S = VCC, VIN = VSS or VCC 50 A ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 10 A C = 0.1VCC / 0.9.VCC at 33 MHz, Q = open 4 C = 0.1VCC / 0.9.VCC at 75 MHz, Q = open 12 ICC3 Operating current (FAST_READ) mA ICC4 Operating current (PW) S = VCC 15 mA ICC5 Operating current (SE) S = VCC 15 mA VIL Input low voltage - 0.5 0.3VCC V VIH Input high voltage 0.7VCC VCC+0.4 V VOL Output low voltage IOL = 1.6 mA 0.4 V VOH Output high voltage IOH = -100 A VCC-0.2 V 35/48 DC and AC parameters Table 12. M45PE80 AC characteristics (33 MHz operation) Test conditions specified in Table 8 and Table 9 Symbol Alt. Parameter Min. fC fC Clock frequency for the following instructions: FAST_READ, PW, PP, PE, SE, DP, RDID, RDP, WREN, WRDI, RDSR Clock frequency for READ instructions fR Max. Unit D.C. 33 MHz D.C. 20 MHz (1) tCLH Clock High time 13 ns (1) tCLL Clock Low time 13 ns 0.03 V/ns S active setup time (relative to C) 10 ns S not active hold time (relative to C) 10 ns tCH tCL Typ. Clock slew rate tSLCH tCSS tCHSL (2) (peak to peak) tDVCH tDSU Data In setup time 3 ns tCHDX tDH Data In hold time 5 ns tCHSH S active hold time (relative to C) 5 ns tSHCH S not active setup time (relative to C) 5 ns 200 ns tSHSL tCSH S deselect time tSHQZ(2) tDIS Output Disable time 12 ns tCLQV tV Clock Low to Output Valid 12 ns tCLQX tHO Output hold time 0 ns tTHSL Top Sector Lock setup time 50 ns tSHTL Top Sector Lock hold time 100 ns tDP (2) S to Deep Power-down 3 s S High to Standby Power mode 30 s 25 ms 0.4+ n*0.8/256 5 ms tRDP (2) Page Write cycle time (256 bytes) tPW(3) Page Write cycle time (n bytes) Page Program cycle time (256 bytes) tPP (3) Page Program cycle time (n bytes) 11 10.2+ n*0.8/256 1.2 tPE Page Erase cycle time 10 20 ms tSE Sector Erase cycle time 1 5 s 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) 36/48 M45PE80 Table 13. DC and AC parameters AC characteristics (50 MHz operation) Test conditions specified in Table 8 and Table 9 Symbol Alt. Parameter Min. fC fC Clock frequency for the following instructions: FAST_READ, PW, PP, PE, SE, DP, RDP, WREN, WRDI, RDSR, RDID Clock frequency for READ instructions fR tCH(1) tCL(1) Max. Unit D.C. 50 MHz D.C. 33 MHz tCLH Clock High time 9 ns tCLL Clock Low time 9 ns 0.1 V/ns S active setup time (relative to C) 5 ns S not active hold time (relative to C) 5 ns Clock slew rate tSLCH Typ. tCSS tCHSL (2) (peak to peak) tDVCH tDSU Data in setup time 2 ns tCHDX tDH Data in hold time 5 ns tCHSH S active hold time (relative to C) 5 ns tSHCH S not active setup time (relative to C) 5 ns 100 ns tSHSL tSHQZ (2) tCSH S deselect time tDIS Output disable time 8 ns Clock Low to Output Valid 8 ns tCLQV tV tCLQX tHO Output hold time 0 ns tWHSL Write Protect setup time 50 ns tSHWL Write Protect hold time 100 ns tDP(2) tRDP(2) tRLRH(2) S to Deep Power-down 3 s S High to Standby mode 30 s tRST Reset pulse width 10 s tRHSL tREC Reset recovery time 3 s tSHRH Chip should have been deselected before Reset is de-asserted 10 ns tPW(3) Page Write cycle time (256 bytes) 11 23 ms Page Program cycle time (256 bytes) 0.8 3 ms tPP(3) Page Program cycle time (n bytes) int(n/8) x 0.025 tPE Page Erase cycle time 10 20 ms tSE Sector Erase cycle time 1 5 s 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. n = number of bytes to program. int(A) corresponds to the upper integer part of A. Examples: int(1/8) = 1, int(16/8) = 2, int(17/8) = 3. 37/48 DC and AC parameters Table 14. M45PE80 AC characteristics (75 MHz operation) Test conditions specified in Table 8 and Table 9 Symbol Alt. Parameter Min. fC fC Clock frequency for the following instructions: FAST_READ, RDLR, PW, PP, WRLR, PE, SE, SSE, DP, RDP, WREN, WRDI, RDSR, WRCR Clock frequency for READ instructions fR tCH(1) tCL(1) Max. Unit D.C. 75 MHz D.C. 33 MHz tCLH Clock High time 6 ns tCLL Clock Low time 6 ns 0.1 V/ns S active setup time (relative to C) 5 ns S not active hold time (relative to C) 5 ns Clock slew rate tSLCH Typ. tCSS tCHSL (2)(2) (peak to peak) tDVCH tDSU Data in setup time 2 ns tCHDX tDH Data in hold time 5 ns tCHSH S active hold time (relative to C) 5 ns tSHCH S not active setup time (relative to C) 5 ns 100 ns tSHSL tSHQZ (2) tCSH S deselect time tDIS Output disable time tCLQV tV tCLQX tHO Clock Low to Output Valid under 30 pF / 10 pF 8 ns 8/6 ns Output hold time 0 ns tWHSL (3) Write Protect setup time 20 ns tSHWL (3) Write Protect hold time 100 ns tDP(2) tRDP(2) tW tPW (4) tPP(4) S to Deep Power-down 3 s S High to Standby mode 30 s Write status register cycle time 3 15 s Page Write cycle time (256 bytes) 11 23 ms Page Program cycle time (256 bytes) 0.8 3 ms Page Program cycle time (n bytes) int(n/8) x 0.025 (5) tPE Page Erase cycle time 10 20 ms tSE Sector Erase cycle time 1 5 s 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 4. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes (1 . n . 256). 5. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16. 38/48 M45PE80 DC and AC parameters Figure 20. Serial input timing tSHSL S tCHSL tSLCH tCHSH tSHCH C tDVCH tCHCL tCHDX tCLCH LSB IN MSB IN D High Impedance Q AI01447C Figure 21. Write Protect setup and hold timing W tSHWL tWHSL S C D High Impedance Q AI07439 Figure 22. Output timing S tCH C tCLQV tCLQX tCLQV tCL tSHQZ tCLQX LSB OUT Q tQLQH tQHQL D ADDR.LSB IN AI01449e 39/48 DC and AC parameters Table 15. M45PE80 Reset conditions Test conditions specified in Table 8 and Table 9 Symbol Alt. Parameter tRLRH(1) tRST Reset Pulse Width 10 s Chip should have been Chip Select High to deselected before Reset is Reset High de-asserted 10 ns tSHRH Conditions Min. Typ. Max. Unit 1. Value guaranteed by characterization, not 100% tested in production. Table 16. Timings after a Reset Low pulse(1) Test conditions specified in Table 8 and Table 9 Symbol tRHSL Alt. Conditions: Reset pulse occurred Parameter Reset tREC Recovery time Min. Typ. Max. Unit While decoding an instruction(2): WREN, WRDI, RDID, RDSR, READ, Fast_Read, PW, PP, PE, SE, DP, RDP 30 s Under completion of an Erase or Program cycle of a PW, PP, PE, SE operation 300 s Device deselected (S High) and in Standby mode 0 s 1. All the values are guaranteed by characterization, and not 100% tested in production. 2. S remains Low while Reset is Low. Figure 23. Reset ac waveforms S tSHRH Reset tRHSL tRLRH AI06808 40/48 M45PE80 Package mechanical Figure 24. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package outline A D aaa C A R1 D1 E1 E2 e bbb E M C A B B 2x b 0.10 C B aaa C B 11 Package mechanical 0.10 C A D2 L A2 ddd A C A1 A3 70-ME 1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 17. VFQFPN8 (MLP8)8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package mechanical data millimeters inches Symbol A Typ Min Max Typ Min Max 0.85 0.80 1.00 0.0335 0.0315 0.0394 0.00 0.05 0.0000 0.0020 0.0138 0.0189 0.1260 0.1417 A1 A2 0.65 0.0256 A3 0.20 0.0079 b 0.40 D 6.00 0.2362 D1 5.75 0.2264 D2 3.40 E 5.00 0.1969 E1 4.75 0.1870 E2 4.00 3.80 4.30 0.1575 0.1496 0.1693 e 1.27 - - 0.0500 - - R1 0.10 0.00 0.0039 0.0000 L 0.60 0.50 0.0236 0.0197 0.35 3.20 0.48 3.60 0.75 0.0157 0.1339 0.0295 12 12 aaa 0.15 0.0059 bbb 0.10 0.0039 ddd 0.05 0.0020 41/48 Package mechanical M45PE80 Figure 25. SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, package outline A2 A c b CP e D N E E1 1 A1 k L 6L_ME 1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 18. SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, mechanical data millimeters inches Symbol Typ Min A Typ Min 2.50 Max 0.098 A1 0.00 0.25 0.000 0.010 A2 1.51 2.00 0.059 0.079 b 0.40 0.35 0.51 0.016 0.014 0.020 c 0.20 0.10 0.35 0.008 0.004 0.014 CP 0.10 0.004 D 6.05 0.238 E 5.02 6.22 0.198 0.245 E1 7.62 8.89 0.300 0.350 - - k 0 L 0.50 N 8 e 42/48 Max 1.27 0.050 - - 10 0 10 0.80 0.020 8 0.031 M45PE80 Package mechanical Figure 26. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline h x 45 A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 19. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data millimeters inches Symbol Typ Min A Max Typ Min 1.75 Max 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.25 0.004 0.010 0.049 0.10 0.004 D 4.90 4.80 5.00 0.193 0.189 0.197 E 6.00 5.80 6.20 0.236 0.228 0.244 E1 3.90 3.80 4.00 0.154 0.150 0.157 e 1.27 - - 0.050 - - h 0.25 0.50 0.010 0.020 k 0 8 0 8 L 0.40 1.27 0.016 0.050 L1 1.04 0.041 43/48 Package mechanical M45PE80 Figure 27. QFN8L (MLP8) 8-lead, dual flat package no lead, 6 x 5 mm, package outline E E2 0PIN 1 ID OPTION L D D2 b e A E2/2 A3 A1 0.08 5X_ME 1. Drawing is not to scale. Table 20. QFN8L (MLP8) 8-lead dual flat package no lead, 6 x 5 mm package mechanical data millimeters inches Symbol 44/48 Typ Min Max Typ Min Max A 0.90 0.80 1.00 0.035 0.031 0.039 A1 0.02 0.00 0.05 0.001 0.000 0.002 A3 0.20 b 0.40 0.014 0.019 D 6.00 D2 3.00 0.110 0.126 E 5.00 E2 3.00 0.110 0.126 e 1.27 L 0.60 0.020 0.030 0.008 0.35 0.48 0.016 0.236 2.80 3.20 0.118 0.197 2.80 3.20 0.118 0.050 0.50 0.75 0.024 M45PE80 12 Part numbering Part numbering Table 21. Ordering information scheme Example: M45PE80 - V MP 6 T G Device Type M45PE = Page-Erasable Serial Flash Memory Device Function 80 = 8 Mbit (1 Mbit x 8) Operating Voltage V = VCC = 2.7 to 3.6V Package MW = SO8W (208 mils width) MP = VFQFPN8 6 x 5 mm (MLP8) MN = SO8N (150 mils width) MS = QFN 8L 6 x 5 mm, pitch1.2 mm Device Grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow Option blank = Standard Packing T = Tape & Reel Packing Plating Technology P or G = RoHS compliant For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 45/48 Reference 13 M45PE80 Reference 14 AN1995: Serial Flash Memory Device Marking. Revision history Table 22. Document revision history Date Version 10-Feb-2003 1.0 Document written 02-Apr-2003 1.1 VFQFPN8 (MLP) package added 08-Apr-2003 1.2 Document promoted to Product Preview 05-May-2003 1.3 Document promoted to Preliminary Data 04-Jun-2003 1.4 Description corrected of entering Hardware Protected mode (W must be driven, and cannot be left unconnected). Document Revision History for 05-May-2003 corrected. 26-Nov-2003 2.0 VIO(min) extended to -0.6V, and tPP(typ) improved to 1.2ms. Table of contents, SO16 package, warning about exposed paddle on MLP8, and Pb-free options added. Change of naming for VDFPN8 package. Document promoted to full datasheet 23-Jan-2004 3.0 SO16 pin-out corrected 28-May-2004 4.0 Soldering temperature information clarified for RoHS compliant devices. Device Grade clarified 5.0 SO16 wide package replaced by SO8 wide package. Active Power, Stand-by Power and Deep Power-Down modes, Read Identification (RDID), Deep Power-down (DP), and Release from Deep Power-down (RDP) descriptions updated. Table 21: Ordering information scheme updated. Figure 22: Output timing updated. 6.0 Added Table 12: AC characteristics (33 MHz operation). An easy way to modify data, A fast way to modify data, Page Write (PW) and Page Program (PP) sections updated to explain optimal use of Page Write and Page Program instructions. Updated ICC3 values in Table 11: DC characteristics. Updated Table 21: Ordering information scheme RoHS information added. 7 X process technology added (see Section 2.5: Reset (Reset), Table 14: Reset timings for U process technology devices and Table 15: Reset timings for X process technology devices). MLP package renamed as VFQFPN8, MLP silhouette modified on page 1. TLEAD removed from Table 7: Absolute maximum ratings. Table 5: Status Register Format moved from Section 4.7: Status Register to Section 6.4: Read Status Register (RDSR). Blank option removed under Plating Technology in Table 21: Ordering information scheme. 10-May-2005 4-Oct-2005 14-Feb-2006 46/48 Changes M45PE80 Revision history Table 22. Document revision history Date Version Changes 15-Dec-2006 8 50 MHz frequency added, Table 13: AC characteristics (50 MHz operation) added. Small text changes. Section 2.5: Reset (Reset) updated. VCC supply voltage and VSS ground descriptions added. Figure 3: Bus master and memory devices on the SPI bus modified and explanatory text added. Behavior of WIP bit specified at Power-up in Section 7: Power-up and Power-down. VIO max modified and TLEAD added in Table 7: Absolute maximum ratings. Table 15: Reset conditions and Table 16: Timings after a Reset Low pulse updated. SO8N package added (T9HX technology only), SO8W and VFQFPN8 package specifications updated (see Section 11: Package mechanical). 10-Dec-2007 9 Applied Numonyx branding. 11-Nov-2008 10 Added frequency up to 75 MHz frequency, including Table 14.: AC characteristics (75 MHz operation); Added new package, including Figure 27.: QFN8L (MLP8) 8-lead, dual flat package no lead, 6 x 5 mm, package outline and Table 20.: QFN8L (MLP8) 8-lead dual flat package no lead, 6 x 5 mm package mechanical data; Added UID/CFD protection. 12-Dec-2008 11 Added the "UID columns" to Table 4.: Read Identification (RDID) data-out sequence. 47/48 M45PE80 Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2008, Numonyx, B.V., All Rights Reserved. 48/48